Etching method of combined patterns

Abstract

The application relates to an etching method of a combined pattern, applied to a semiconductor device, the semiconductor device comprising a substrate and a conductive layer, a dielectric layer, a mask layer and a photoresist layer which are sequentially stacked along a vertical direction of the substrate, the conductive layer comprising a plurality of metal electrodes, the combined pattern comprising at least one groove and at least one via, the method comprising: etching the semiconductor device at a target etching gas pressure; inputting a target proportion of a main etching gas and an inert gas to reduce the etching speed difference between each groove or via in the combined pattern, so that each groove or via in the combined pattern exposes at least one metal electrode. At least by means of the etching gas pressure and the input of the target proportion of the main etching gas and the inert gas, the etching rate between the combined patterns is balanced, the great load at the groove and / or the via formed by etching is avoided, and the influence on the key electrical data of the semiconductor device is also avoided.

Description

Technical Field

[0001] This application relates to the field of semiconductor device etching technology, and in particular to an etching method for combined patterns. Background Technology

[0002] With the advancement of semiconductor manufacturing technology, the etching of semiconductors requires a combination of trench and via patterns, which are usually combined in the same layer or across multiple layers to form complex circuit structures.

[0003] In related technologies, when etching combined patterns, the etching of trenches is usually the main focus. The combined pattern of trenches and through holes is etched by the etching process of large patterns such as trenches, and the combined pattern is formed by sufficient over-etching.

[0004] However, using a combined pattern etching method that primarily involves trench etching can easily result in extremely high loads at the trenches and vias formed by the etching process. The presence of these extremely high loads makes it impossible for conventional stop layer film deposition to cover them, which can severely affect the critical electrical data of semiconductor devices. Summary of the Invention

[0005] Based on this, it is necessary to provide an etching method for combined patterns to address the above-mentioned technical problems. This method can at least reduce the etching rate difference between each pattern in the combined pattern by controlling the etching gas pressure, and further balance the etching rate between the combined patterns by inputting a target ratio of main etching gas and inert gas. This avoids excessive load at the trenches and vias formed by etching, and also avoids the impact on the critical electrical data of semiconductor devices.

[0006] In a first aspect, this application provides an etching method for a composite pattern, applied in a semiconductor device, the semiconductor device including a substrate and a conductive layer, a dielectric layer, a mask layer and a photoresist layer sequentially stacked on the substrate along a direction perpendicular to the substrate, the conductive layer including a plurality of metal electrodes, the composite pattern including at least one trench and at least one via; wherein, the method includes: etching the semiconductor device at a target etching gas pressure; inputting a target ratio of main etching gas and inert gas to reduce the etching rate difference between each trench or via in the composite pattern, so that each trench or via in the composite pattern exposes at least one metal electrode.

[0007] In the etching method of the combined pattern described in the above embodiment, by controlling the etching gas pressure, reducing the plasma concentration and the intensity of bombarding the hard mask, the etching rate of the trenches in the combined pattern can be reduced, so that the etching rates of the trenches and vias in the combined pattern can reach a preliminary balance. On this basis, by adding an inert gas as a protective gas, the change of the electrical properties of the material by the main etching gas during the etching process can be prevented, thereby reducing etching-induced damage.

[0008] In one embodiment, the method further includes etching the semiconductor device at a target voltage such that the difference in etching load ratio between different locations in the semiconductor device is within a target range.

[0009] In the etching method for the combined pattern described in the above embodiments, by controlling the etching voltage, it is possible to promote the uniform distribution of plasma without affecting the formation of the combined pattern as much as possible, thereby reducing the difference in etching load ratio between different locations of the semiconductor device.

[0010] In one embodiment, the target etching pressure is determined by the following steps: obtaining the etching rate of the combined patterns under different etching pressures; and determining the etching pressure at which the etching rates of the combined patterns are closest as the target etching pressure.

[0011] In the etching method of the combined pattern in the above embodiment, by obtaining the etching rate of the combined pattern under different etching gas pressures, the etching gas pressure at which the etching rates of the trenches and vias in the combined pattern reach equilibrium is taken as the target etching gas pressure, so that when the semiconductor is etched at the target etching gas pressure, the etching rates of the trenches and vias in the combined pattern reach equilibrium.

[0012] In one embodiment, the semiconductor device further includes a bottom anti-reflective coating located between the photoresist layer and the mask layer; wherein, the target ratio of the main etching gas and the inert gas is determined by the following steps: when removing the bottom anti-reflective coating, the etching rate difference between the combined patterns is obtained when the main etching gas and the inert gas have different input ratios; the input ratio between the main etching gas and the inert gas that minimizes the etching rate difference between the combined patterns is determined as the target ratio of the main etching gas and the inert gas.

[0013] In the etching method for the combined pattern described in the above embodiment, when removing the bottom anti-reflective coating, the etching gas ratio at which the etching rates of the trenches and vias in the combined pattern reach equilibrium is determined as the target ratio of the main etching gas and the inert gas. This ensures that when the main etching gas and the inert gas at the target ratio are used to remove the bottom anti-reflective coating, the etching rates of the trenches and vias in the combined pattern reach equilibrium.

[0014] In one embodiment, the main etching gas is hydrogen and the inert gas is nitrogen.

[0015] In the etching method of the combined pattern described in the above embodiments, hydrogen is used as the main etching gas, which can suppress the volatilization of polymer during the etching process, thereby reducing the reaction rate and inhibiting the etching rate of silicon. This greatly increases the selectivity of silicon dioxide to silicon and balances the etching rate difference between trenches and vias in the combined pattern. Nitrogen is used as an inert gas, which can prevent hydrogen atoms generated during the etching process from changing the electrical properties of the material, thereby reducing etching-induced damage and achieving the effect of reducing critical dimensions.

[0016] In one embodiment, the target ratio between the main etching gas and the inert gas is between 1 and 1 / 2.

[0017] In the etching method for combined patterns described in the above embodiments, by limiting the target ratio between the main etching gas and the inert gas, when etching the combined pattern, the addition of a gas that can suppress the volatilization of the polymer, reduce the reaction rate, and suppress the etching rate of silicon greatly increases the selectivity of silicon dioxide to silicon, balances the difference in etching rate between trenches and vias in the combined pattern, and also prevents the main etching gas generated during the etching process from changing the electrical properties of the material, thereby reducing etching-induced damage and achieving the effect of reducing critical dimensions.

[0018] In one embodiment, the target etching pressure is 30mT-90mT.

[0019] In the etching method of the combined pattern in the above embodiment, by limiting the target etching gas pressure, the plasma concentration is reduced and the intensity of bombarding the hard mask is slowed down when etching the combined pattern, thereby slowing down the etching rate of the trenches in the combined pattern, so that the etching rates of the trenches and vias in the combined pattern are balanced.

[0020] In one embodiment, the target voltage is 150V-300V.

[0021] In the etching method for combined patterns described in the above embodiments, by limiting the target voltage, the difference in etching load ratio between different locations in the semiconductor device can be reduced. Without affecting the combined pattern load, limiting the target voltage as an aid further promotes the uniform distribution of plasma.

[0022] In one embodiment, the method further includes etching the target low-frequency power semiconductor device to reduce the etching rate difference between each pattern in the combined pattern.

[0023] In the combined pattern etching method of the above embodiments, when etching the semiconductor device with the target etching gas pressure, the target low-frequency power is added to further reduce the plasma concentration and slow down the intensity of bombarding the hard mask, so that the etching rate of the trenches and vias in the combined pattern can be further balanced.

[0024] In one embodiment, the target low-frequency power is 0W-200W.

[0025] In the etching method for the combined pattern described above, by reducing the low-frequency power for etching the combined pattern, the concentration of plasma and the intensity of bombardment of the hard mask during etching are reduced, thereby further weakening the etching rate of the trenches in the combined pattern.

[0026] The above-mentioned etching method for combined patterns reduces the etching rate difference between each pattern in the combined pattern by controlling the etching gas pressure, and further balances the etching rate between the combined patterns by inputting the target ratio of main etching gas and inert gas, thus avoiding the occurrence of large loads at the trenches and vias formed by etching, and also avoiding the impact on the key electrical data of semiconductor devices. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a flowchart illustrating an etching method for a combined pattern in one embodiment;

[0029] Figure 2 This is a flowchart illustrating the etching method for combined patterns in another embodiment;

[0030] Figure 3 This is a comparative schematic diagram of combined pattern etching in one embodiment;

[0031] Figure 4 This is a structural block diagram of an etching apparatus for combining patterns in one embodiment;

[0032] Figure 5 This is an internal structural diagram of a computer device in one embodiment.

[0033] Reference numerals and explanations: 10, First pattern; 20, Second pattern; 30, Third pattern; 40, Fourth pattern; 50, Polymer; 60, Substrate; 70, Dielectric layer; 80, Mask layer; 90, Photoresist layer; 11, Metal layer; 100, Target etching gas pressure control module; 200, Reactive gas control module. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0035] Please refer to Figure 1 In one exemplary embodiment, a method for etching combined patterns is provided, including the following steps S101 to S102. Wherein:

[0036] Step S101: Etch the semiconductor device with the target etching pressure.

[0037] Step S102: Input the target ratio of main etching gas and inert gas to reduce the etching rate difference between each pattern in the combined pattern.

[0038] It's important to note that in semiconductor etching, pattern loading refers to the effect of the density or arrangement of patterns on the wafer surface on the etching reaction rate during the etching process. Pattern loading affects the density distribution of the etchable regions. For example, on a wafer surface, if there are a large number of open areas (unprotected areas) and fewer patterned areas (such as areas covered by metal or photoresist), the reaction rate and etching rate of these areas may differ. Pattern loading typically refers to the ratio between patterned areas (areas covered by photoresist or other materials) and unpatterned areas (exposed material areas). A denser pattern results in more reaction areas, which may lead to faster or slower etching rates in certain areas, especially when the etching gas concentration is uneven or the physical and chemical reaction conditions are inconsistent, making the difference in etching rate more pronounced.

[0039] In particular, when the morphology and size of the combined patterns differ greatly, the amount of polymer generated by the etching of the lower dielectric layer and extracted from the different combined patterns varies greatly. Furthermore, the etching rate of combined patterns with large size differences also differs significantly. As a result, a large load is formed between the trenches and vias.

[0040] Furthermore, during the etching of composite patterns, extremely high etching loads easily occur at the trenches and vias within the composite pattern. Simultaneously, extremely high loads also exist between different etching locations (e.g., the center and edge of the semiconductor device). This superposition of dual loads creates a situation that is difficult to eliminate. The presence of such extremely high loads prevents the conventional stop layer film from being covered, resulting in over-etching at the trenches and under-etching of the vias, severely impacting subsequent critical electrical data such as Rc. Existing solutions focus on etching the trenches of the composite pattern, using a single trench etching process to etch the composite pattern. This approach prioritizes sufficient over-etching to open the vias within the composite pattern, provided there is sufficient plasma for large-pattern etching. However, different patterns exhibit significantly different selectivity to the same etching gas and etching pressure. Therefore, simply increasing over-etching may accelerate the etching of easily extractable polymer trench patterns, while small via patterns may even be under-etched, further increasing the load.

[0041] This application reduces the etching rate of trenches in the combined pattern by controlling the etching gas pressure, lowering the plasma concentration and the intensity of bombardment of the hard mask, thus achieving a preliminary balance between the etching rates of trenches and vias in the combined pattern. Furthermore, when removing the bottom anti-reflective coating, the addition of an inert gas as a protective gas can prevent the main etching gas from altering the electrical properties of the material during the etching process, thereby reducing etching-induced damage.

[0042] Here, this application first considers the improvement of the most difficult-to-balance etching load between the trenches and vias in the combined pattern, which enables the etching of semiconductor devices with a target etching gas pressure and the etching load of the semiconductor device when the target ratio of main etching gas and inert gas is input during the removal of the bottom anti-reflective coating to meet the process requirements.

[0043] Specifically, the target etching pressure can be determined by the following steps: obtaining the etching rate of the combined patterns under different etching pressures; and determining the etching pressure at which the etching rates of the combined patterns are closest as the target etching pressure.

[0044] In the etching method of the combined pattern in the above embodiment, by obtaining the etching rate of the combined pattern under different etching gas pressures, the etching gas pressure at which the etching rates of the trenches and vias in the combined pattern reach equilibrium is taken as the target etching gas pressure, so that when the semiconductor is etched at the target etching gas pressure, the etching rates of the trenches and vias in the combined pattern reach equilibrium.

[0045] Specifically, the target etching pressure is between 30mT and 90mT.

[0046] As an example, the target etching pressure can be 30mT, 40mT, 50mT, 60mT, 80mT, 90mT, etc.

[0047] In the etching method of the combined pattern in the above embodiment, by limiting the target etching gas pressure, the plasma concentration is reduced and the intensity of bombarding the hard mask is slowed down when etching the combined pattern, thereby slowing down the etching rate of the trenches in the combined pattern, so that the etching rates of the trenches and vias in the combined pattern are balanced.

[0048] Specifically, the target ratio of main etching gas and inert gas can be determined through the following steps: when removing the bottom anti-reflective coating, obtain the etching rate difference between the combined patterns when the main etching gas and inert gas have different input ratios; determine the target ratio of main etching gas and inert gas by taking the input ratio between the main etching gas and inert gas that minimizes the etching rate difference between the combined patterns.

[0049] The semiconductor device also includes a bottom anti-reflective coating, which is located between the photoresist layer and the mask layer.

[0050] The main etching gas is hydrogen, and the inert gas is nitrogen.

[0051] Here, hydrogen is used as the main etching gas, which can suppress the volatilization of polymer during the etching process, thus reducing the reaction rate and inhibiting the etching rate of silicon. This greatly increases the selectivity of silicon dioxide for silicon and balances the etching rate difference between trenches and vias in the combined pattern. Nitrogen is used as an inert gas, which can prevent hydrogen atoms generated during the etching process from changing the electrical properties of the material, thereby reducing etching-induced damage and achieving the effect of reducing critical dimensions.

[0052] Specifically, the target ratio between the main etching gas and the inert gas is between 1 and 1 / 2.

[0053] As an example, the target ratio between the main etching gas and the inert gas is 1, 3 / 4, 4 / 5, 1 / 2, etc.

[0054] Here, based on the determination of the target etching gas pressure, when removing the bottom anti-reflective coating (BARC), this application uses hydrogen as the main etching gas to suppress polymer volatilization, thereby reducing the reaction rate and inhibiting the etching rate of silicon. This greatly increases the selectivity of silicon dioxide to silicon, balances the etching rate difference between trenches and vias, and uses nitrogen as a protective gas to prevent hydrogen atoms generated during the etching process from altering the electrical properties of the material, thereby reducing etching-induced damage and achieving the effect of reducing critical dimensions.

[0055] Experiments have shown that when using hydrogen as the main etching gas and nitrogen as the inert gas, a certain ratio range must be maintained. After multiple adjustments, it was found that a hydrogen to nitrogen ratio of 1:1 has a good trend, and adjusting the hydrogen to nitrogen ratio to 1:2 provides better control over critical dimensions.

[0056] In the above-mentioned etching method for combined patterns, the etching rate difference between each pattern in the combined pattern is reduced by controlling the etching gas pressure, and the etching rate between the combined patterns is further balanced by inputting the target ratio of main etching gas and inert gas, so as to avoid the occurrence of large loads at the trenches and vias formed by etching, and also to avoid the impact on the key electrical data of semiconductor devices.

[0057] It should be noted that when etching combined patterns, not only is pattern loading very easy to occur, but also extremely high loading can easily occur between different locations, such as W / C loading, W / E loading, etc.

[0058] Here, W / C loading refers to the loading of the pattern located at the center of the semiconductor device during etching; W / E loading refers to the loading of the pattern located at the edge of the semiconductor device during etching. Reducing the pattern loading of the combined pattern, while also reducing the loading between different locations, is crucial for improving the electrical properties of the semiconductor device.

[0059] This application improves the etching load, which is the most difficult pair to balance between trenches and vias in the combined pattern, by adjusting the etching pressure and etching gas. However, it is still necessary to improve the etching load at different locations of the semiconductor device.

[0060] For example, please refer to Figure 2 In one exemplary embodiment, an etching method for combined patterns is provided, including the following step S201. Wherein:

[0061] S201, at the target voltage, etch the semiconductor device so that the difference in etching load ratio between different locations in the semiconductor device is within the target range.

[0062] In this way, by controlling the etching voltage, it is possible to promote the uniform distribution of plasma without affecting the formation of the combined pattern as much as possible, thereby reducing the difference in etching load ratio between different locations of the semiconductor device.

[0063] Here, without affecting the combined pattern load, this application improves the most difficult-to-balance etching load between trenches and vias in the combined pattern by reducing the voltage as an aid. By adjusting the voltage, the etching load of patterns at different positions is balanced, so that the plasma is more evenly distributed on the surface of the entire semiconductor device, eliminating the double superimposed etching load.

[0064] Specifically, the target voltage is 150V-300V.

[0065] As an example, the target voltage can be 150V, 180V, 200V, 250V, 300V, etc.

[0066] It should be noted that the target voltage range of this application is significantly smaller than the etching voltage under normal etching conditions. By limiting the voltage and reducing the voltage intervention, this application enables the plasma to be more evenly distributed across the entire wafer surface, which can improve the loading of W / C and W / E, thereby eliminating the double-overlapping combined pattern loading and loading at different locations.

[0067] In some embodiments, the method further includes etching the target low-frequency power semiconductor device to reduce the etching rate difference between each pattern in the combined pattern.

[0068] Specifically, the target low-frequency power is 0W-200W.

[0069] As an example, the target low-frequency power can be 0W, 50W, 150W, 180W, 200W, etc.

[0070] Here, the target low-frequency power of this application is significantly lower than the normal low-frequency power. By reducing the etching gas pressure and lowering the low-frequency power, the concentration of plasma and the intensity of bombardment of the hard mask can be reduced, which can weaken the effect of excessively fast trench pattern etching rate.

[0071] Furthermore, reducing low-frequency power can also extend the lifespan of components within the cavity.

[0072] For example, please refer to Figure 3 In one exemplary embodiment, a comparative schematic diagram of combined pattern etching is provided. Wherein, Figure 3 Figure a in the diagram shows a schematic diagram of the structure obtained by etching the combined pattern using existing technology. Figure 3 Figure b in the figure is a schematic diagram of the structure obtained by etching the combined patterns in this application. The first pattern 10 is a groove, the second pattern 20 is a groove, the third pattern 30 is a through hole, and the fourth pattern 40 is a groove.

[0073] The etching method for the combined pattern proposed in this application is applied to a semiconductor device. The semiconductor device includes a substrate 60 and a conductive layer 11, a dielectric layer 70, a mask layer 80 and a photoresist layer 90 sequentially stacked on the substrate along the direction perpendicular to the substrate. The conductive layer 11 includes a plurality of metal electrodes, and the combined pattern includes at least one trench and at least one via.

[0074] For example, the dielectric layer can be an oxide layer, a dielectric layer, a combination of an oxide layer and a dielectric layer, etc., wherein the oxide layer can be silicon dioxide (SiO2), etc., and the dielectric layer can be TEOS (tetraethoxysilane), BPSG (Boro-phospho-silicate glass), BD (low-K material), SIN (silicon nitride), SION (silicon oxynitride), etc.

[0075] like Figure 3 As shown in Figure a, when etching semiconductor devices using existing techniques, the etching rate for trenches is much higher than that for vias. Furthermore, existing techniques often involve over-etching the trenches to increase via etching, accelerating the etching of easily removable polymer trench patterns. Small via patterns may even be under-etched, further increasing the load. Specifically, the first pattern 10, the second pattern 20, and the fourth pattern 40 contain relatively little polymer, while the third pattern 30 has severe polymer buildup. This means that even with over-etching of the first, second, and fourth patterns 10, the third pattern 30 still cannot reach the etching position.

[0076] Please refer to Figure 3 Figure b illustrates that when etching a semiconductor device using a target gas pressure and removing the bottom anti-reflective coating, with a target ratio of main etching gas (hydrogen) and inert gas (nitrogen) input, the polymers in the first pattern 10, second pattern 20, third pattern 30, and fourth pattern 40 are relatively uniform. Hydrogen suppresses the evaporation rate of the polymer in the trench pattern. Under the action of the target gas pressure, the etching rates of the trenches and vias in the combined pattern reach a certain balance, reducing the etching rate of the trenches and increasing the etching rate of the vias. This ensures that when the trenches reach their target positions, the vias can also reach their target positions, reducing the load. At the same time, the addition of inert gas as a protective gas can prevent the main etching gas from changing the electrical properties of the material during the etching process, thereby reducing etching-induced damage.

[0077] In the process of combined pattern etching, this application first needs to consider improving the pattern loading between trenches and vias. By reducing the etching gas pressure, decreasing the low-frequency power, and lowering the plasma concentration and the intensity of bombardment of the hard mask, the impact of excessively fast trench pattern etching rate on pattern loading can be weakened. Second, when removing the bottom anti-reflective coating, the etching rate between combined patterns is balanced by inputting the target ratio of main etching gas and inert gas. The addition of hydrogen can suppress polymer volatilization, reduce the reaction rate, suppress the silicon etching rate, and greatly increase the silicon selectivity ratio of silicon dioxide to silicon, further balancing the rate difference between trench and via etching. After improving the pattern loading, the voltage should be slightly adjusted without affecting the pattern loading, so as to weaken the voltage as an auxiliary and promote the uniform distribution of plasma.

[0078] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0079] Based on the same inventive concept, this application also provides an etching control device for combining patterns to implement the etching method for combining patterns described above. The solution provided by this device is similar to the solution described in the above method. Therefore, the specific limitations of one or more embodiments of the etching control device for combining patterns provided below can be found in the limitations of the etching control method for combining patterns described above, and will not be repeated here.

[0080] Please refer to Figure 4In one exemplary embodiment, an etching control device for a combined pattern is provided, applied in a semiconductor device. The semiconductor device includes a substrate and a conductive layer, a dielectric layer, a mask layer, and a photoresist layer sequentially stacked on the substrate along a direction perpendicular to the substrate. The conductive layer includes a plurality of metal electrodes. The combined pattern includes at least one trench and at least one via. The etching control device for the combined pattern includes a target etching gas pressure control module 100 and a reactive gas control module 200. The target etching gas pressure control module 100 is used to etch the semiconductor device at a target etching gas pressure. The reactive gas control module 200 is used to input a target ratio of main etching gas and inert gas when removing the bottom anti-reflective coating to reduce the etching rate difference between each pattern in the combined pattern.

[0081] Each module in the above-mentioned combined pattern etching control device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the operations corresponding to each module.

[0082] In an exemplary embodiment, a computer device is provided, which may be a terminal. The computer device includes a processor, memory, an input / output interface, a communication interface, a display unit, and an input device. The processor, memory, and input / output interface are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interface. The processor of the computer device provides computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The input / output interface of the computer device is used for exchanging information between the processor and external devices. The communication interface of the computer device is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, Near Field Communication (NFC), or other technologies. When the computer program is executed by the processor, it implements an etching control method for combined patterns. The display unit of the computer device is used to form a visually visible image and may be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the computer device, or external keyboards, touchpads, or mice, etc.

[0083] Those skilled in the art will understand that Figure 4 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0084] In one exemplary embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to perform the following steps:

[0085] The semiconductor device is etched using the target etching pressure;

[0086] Input the target ratio of main etching gas and inert gas to reduce the etching rate difference between each trench or via in the composite pattern, so that each trench or via in the composite pattern exposes at least one metal electrode.

[0087] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, the computer program performing the following steps when executed by a processor:

[0088] The semiconductor device is etched using the target etching pressure;

[0089] Input the target ratio of main etching gas and inert gas to reduce the etching rate difference between each trench or via in the composite pattern, so that each trench or via in the composite pattern exposes at least one metal electrode.

[0090] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, performs the following steps:

[0091] The semiconductor device is etched using the target etching pressure;

[0092] Input the target ratio of main etching gas and inert gas to reduce the etching rate difference between each trench or via in the composite pattern, so that each trench or via in the composite pattern exposes at least one metal electrode.

[0093] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0094] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0095] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for etching combined patterns, characterized in that, The semiconductor device is used in semiconductor devices, which include a substrate and a conductive layer, a dielectric layer, a mask layer and a photoresist layer stacked sequentially on the substrate along a direction perpendicular to the substrate. The conductive layer includes a plurality of metal electrodes and the combined pattern includes at least one trench and at least one via. The method includes: The semiconductor device is etched using the target etching pressure; Input the target ratio of main etching gas and inert gas to reduce the etching rate difference between each trench or via in the composite pattern, so that each trench or via in the composite pattern exposes at least one metal electrode. The semiconductor device further includes a bottom anti-reflective coating, which is located between the photoresist layer and the mask layer; The target ratio of the main etching gas to the inert gas is determined through the following steps: When removing the bottom anti-reflective coating, the etching rate difference between the combined patterns is obtained when the main etching gas and the inert gas are used in different input ratios; The input ratio between the main etching gas and the inert gas, which minimizes the difference in etching rate between combined patterns, is determined as the target ratio between the main etching gas and the inert gas. The target ratio between the main etching gas and the inert gas is between 1 and 1 / 2; The target etching pressure is 30mT-90mT.

2. The method according to claim 1, characterized in that, The method further includes: At the target voltage, the semiconductor device is etched such that the difference in the etching load ratio between different locations in the semiconductor device is within the target range.

3. The method according to claim 1, characterized in that, Determine the target etching pressure using the following steps: Obtain the etching rate of the combined pattern under different etching gas pressures; The etching pressure at which the etching rates of the combined patterns are closest is determined as the target etching pressure.

4. The method according to claim 1, characterized in that, The main etching gas includes hydrogen, and the inert gas includes nitrogen.

5. The method according to claim 2, characterized in that, The target voltage is 150V-300V.

6. The method according to claim 1, characterized in that, The method further includes: Etching of semiconductor devices with target low-frequency power reduces the etching rate difference between each pattern in the combined pattern.

7. The method according to claim 6, characterized in that, The target low-frequency power is 0W-200W.

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