Five-surface encapsulation structure, device and encapsulation process thereof

Abstract

The technology comprises the following steps: chip packaging: a chip is packaged in a packaging body A, the surface of an adhesive layer A on the back surface of the chip is flush with the packaging body A and is exposed, a circuit layer and a conductive column are electroplated on the front surface of the chip, and the surface of the conductive column is flush with the packaging body A and is exposed; enclosing wall electroplating: providing a substrate, electroplating a metal frame on the substrate, and enabling the top surface of the metal frame to be flush with the exposed conductive columns; mounting and packaging: the packaging body A is mounted on the substrate in the middle of the enclosing wall through an adhesive layer A, the enclosing wall is filled with a packaging material, the top surface is solidified and ground until the conductive columns and the metal frame are flush with the top surface of the packaging whole body and exposed, a packaging body B is formed, and the packaging body A and the packaging body B form the packaging whole body; the packaging semi-finished product structure is firstly formed, so that the production efficiency is greatly improved, and the process is simplified; and the enclosing walls and the metal surfaces form a five-surface packaging structure for packaging the whole body, so that the electromagnetic shielding effect is enhanced, and the sealing performance is good.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip packaging, and in particular relates to a five-sided encapsulation packaging structure, a device and a packaging process thereof. Background Art

[0002] The purpose of integrated circuit chip packaging is to protect the chip from interference from the external environment so that it can perform circuit functions stably, reliably and normally. Therefore, the packaging shell used to install semiconductor integrated circuit chips plays the role of placing, fixing, sealing, protecting the chip and enhancing the electrical and thermal performance.

[0003] With the development of miniaturization and integration of electronic chips, the heat generated by chips during operation is increasing. High temperature not only leads to chip performance degradation, but may also cause chip damage. Therefore, effective heat dissipation measures are crucial. Existing heat dissipation structures generally directly electroplate, encapsulate, and grind the chip and its electrical connection structure layer by layer to form a chip package. A heat dissipation shielding structure surrounded by five metal surfaces is installed or electroplated on the periphery of the chip package. The heat dissipation structure is separated from the internal chip by encapsulation material, resulting in poor heat dissipation shielding effect, complex process, and low production efficiency. Summary of the Invention

[0004] In order to solve the above problems in the prior art, the present invention provides a five-sided encapsulation packaging structure, a device and a packaging process thereof.

[0005] To achieve the above object, the present invention proposes a five-sided encapsulation process, comprising the following steps: Chip packaging: The chip is encapsulated in the package A, the surface of the chip back glue layer A is flush with the package A and exposed, the chip front is electroplated with circuit layers and conductive pillars, and the surface of the conductive pillars is flush with the package A and exposed; Fence plating: Provide a substrate, and electroplate a metal frame on the substrate, with the top surface of the metal frame flush with the exposed conductive posts; Mounting and encapsulation: Package A is mounted on the substrate in the middle of the wall through adhesive layer A. The wall is filled with encapsulation material and the top surface is cured and polished until the conductive pillars, metal frame and the top surface of the package are flush and exposed, forming package B. Packages A and B constitute the entire package. Outer layer electroplating: peel off the substrate, apply glue layer B on the back of the entire package, and electroplate a metal surface on the glue layer B. The metal surface covers the entire surface of the package and is sealed with the metal frame.

[0006] Furthermore, in the chip packaging step, the package body A is obtained by applying a glue layer A on the back of the chip, electroplating circuit layers and conductive pillars on the front of the chip layer by layer, and encapsulating and grinding to expose the top surface of the conductive pillars.

[0007] Furthermore, in the wall electroplating step, the metal frame electroplated on the substrate is stacked in one or more layers.

[0008] Furthermore, in the wall electroplating step, the width of the multiple-layer stacked metal frames gradually decreases from the lower layer to the upper layer.

[0009] Furthermore, in the wall electroplating step, the width difference of each layer of metal frame ranges from 10 to 25 μm, forming a width step.

[0010] Furthermore, in the outer layer electroplating step, solder feet are electroplated on the exposed conductive pillars and metal frame before the substrate is peeled off.

[0011] Furthermore, in the outer layer electroplating step, the adhesive layer B covers the adhesive layer A, and the adhesive layer B extends outward from the edge of the adhesive layer A by a distance of ≥100 μm. Both the adhesive layer A and the adhesive layer B are thermally and electrically conductive adhesives.

[0012] A five-sided encapsulation packaging structure includes a package as a whole, and further includes: Package A, wherein a chip is enclosed in the package A, the surface of the adhesive layer A on the back of the chip is flush with the package A and exposed, and the front of the chip is plated with a circuit layer and a conductive column, and the surface of the conductive column is flush with the package A and exposed; a fence formed by a plated metal frame; Package B: Package A is attached to the middle of the enclosure wall via adhesive layer A. The top surface of the metal frame is flush with the exposed conductive posts. A sealing compound is filled between the enclosure wall and package A and cured to form package B. Packages A and B form the entire package. The top surface is ground until the conductive posts, metal frame, and the top surface of the entire package are flush and exposed. Metal surface: Apply glue layer B on the back of the entire package, and electroplate the metal surface on the glue layer B. The metal surface covers the entire surface of the package and is sealed with the metal frame.

[0013] Furthermore, the package A is obtained by applying a glue layer A on the back of the chip, electroplating circuit layers and conductive pillars on the front of the chip in sequence, and then encapsulating and grinding to expose the top surface of the conductive pillars.

[0014] Furthermore, the metal frame is a stack of one or more electroplated layers.

[0015] Furthermore, when the metal frames are stacked in multiple layers, the width of the metal frames gradually decreases from the lower layer to the upper layer.

[0016] Furthermore, the width difference of each metal frame layer ranges from 10 to 25 μm, forming a width step.

[0017] Furthermore, the exposed conductive pillars and the metal frame are electroplated with solder pins.

[0018] Furthermore, the adhesive layer B covers the adhesive layer A, and the adhesive layer B extends outward from the edge of the adhesive layer A by a distance of ≥100 μm. Both the adhesive layer A and the adhesive layer B are thermally and electrically conductive adhesives.

[0019] A packaged device comprises the above-mentioned five-sided encapsulation packaging structure.

[0020] The present invention: 1. By first forming a semi-finished package structure, each part of the product can be pre-processed separately, greatly improving production efficiency and simplifying the process; directly providing a larger adhesive layer B on the adhesive layer A can effectively buffer the stress on the metal surface, protect the back of the chip, and make the entire package structure more stable and reliable; 2. The heat of the chip is directly transferred to the metal surface outside the package through the thermally conductive adhesive layer A and adhesive layer B, which improves the heat dissipation performance. The wall and metal surface form a five-sided sealing structure of the package as a whole, strengthening the electromagnetic shielding effect and providing good sealing. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1-Figure 7 A cross-sectional view of a chip packaging step in a five-sided encapsulation packaging process of the present invention; Figure 8 A cross-sectional view of a wall electroplating step of a five-sided encapsulation process of the present invention; Figure 9-10 A cross-sectional view of a mounting and encapsulation step of a five-sided encapsulation packaging process of the present invention; Figure 11-14 A cross-sectional view of an outer layer electroplating step of a five-layer encapsulation packaging process of the present invention; Figure 15 This is a cross-sectional view of a product of a five-sided encapsulated packaging structure of the present invention.

[0022] In the figure: 1. Package A; 2. Chip; 3. Glue layer A; 4. Circuit layer; 5. Conductive column; 6. Metal frame; 7. Package B; 8. Glue layer B; 9. Metal surface. DETAILED DESCRIPTION

[0023] The present invention will be described below with reference to specific embodiments, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar components or components with the same or similar functions.

[0024] Directional terms used in the present invention, such as up, down, left, right, front, back, inside, outside, front, back, and side, are merely referenced to the accompanying drawings. The embodiments described below with reference to the accompanying drawings and the directional terms used are exemplary and intended only to explain the present invention and are not to be construed as limiting the present invention. Furthermore, the various specific process and material examples provided herein are examples of other processes and / or materials that one of ordinary skill in the art would recognize.

[0025] In order to better understand the purpose, structure and function of the present invention, the following is a further detailed description of a five-sided encapsulation process proposed by the present invention in conjunction with the accompanying drawings. The process includes the following steps: Chip 2 packaging: Chip 2 is encapsulated in package A1. The surface of adhesive layer A3 on the back of chip 2 is flush with package A1 and exposed. The front of chip 2 is plated with circuit layer 4 and conductive pillar 5. The surface of conductive pillar 5 is flush with package A1 and exposed. Wall electroplating: Provide a substrate, electroplate a metal frame 6 on the substrate, and the top surface of the metal frame 6 is flush with the exposed conductive pillars 5; Mounting and encapsulation: Package A1 is mounted on the substrate in the middle of the wall through the adhesive layer A3. The wall is filled with encapsulation material and the top surface is cured and polished until the conductive pillars 4 and metal frame 6 are flush with the top surface of the entire package and exposed, forming package B7. Package A1 and package B7 constitute the entire package. Outer layer electroplating: peel off the substrate, apply glue layer B7 on the back of the entire package, and electroplate metal surface 9 on the glue layer B7. The metal surface 9 covers the entire surface of the package and is sealed with the metal frame 6.

[0026] Among them, such as Figure 1-Figure 7 As shown, in the chip 2 packaging step, the package body A1 is obtained by brushing a glue layer A3 on the back of the chip 2, electroplating a circuit layer 4 and a conductive column 5 on the front of the chip 2 in sequence, and encapsulating and grinding to expose the top surface of the conductive column 5. The chip 2 can be one of a variety of devices, such as a transistor, a memory, a diode, a triode or a MOS, etc. Specifically: a substrate is provided, which is a substrate of silicon, metal or other suitable materials commonly used in the field as a support platform for each step in the packaging process, and the chip 2 is placed on the substrate with the back side facing up. A layer of glue A3 is brushed on the back side of the chip 2 by steel screen printing, and the glue layer A3 completely covers the back area of ​​the chip 2 (such as Figure 1 ), the adhesive layer A3 is a conductive and thermally conductive adhesive, such as a conductive epoxy resin adhesive, and then the chip 2 is removed and turned over, and re-mounted on the substrate through the adhesive layer A3, and the chip 2 and the adhesive layer A3 on the chip 2 are encapsulated with an encapsulating material. After the encapsulating material is cured, the top surface of the encapsulating layer A3 is exposed by mechanical grinding (such as Figure 2 ), peel off the encapsulating material encapsulating the chip 2 and the adhesive layer A3 after curing and re-place it on the substrate upside down. At this time, the front side of the chip 2 is exposed outside the encapsulating material (such as Figure 3 ), a circuit layer 4 is plated on the front side of the chip 2 by electroplating process (such as Figure 4 ), and continue to electroplate the conductive pillar 5 on the circuit layer 4 (such as Figure 5 ), continue to use the encapsulation material to completely encapsulate the circuit layer 4 and the conductive column 5 on the basis of the first encapsulation, and expose the top surface of the conductive column 5 by horizontal mechanical grinding on the encapsulation surface (such as Figure 6), the sides formed by the two encapsulations are on the same vertical line, and after the encapsulation material is solidified, a whole encapsulation is formed, namely the encapsulation body A1, which is peeled off from the substrate (such as Figure 7 ), the surface of the adhesive layer A3 on the back of the chip 2 is flush with and exposed to the package body A1, and the surface of the conductive pillar 5 is flush with and exposed to the package body A1, thereby obtaining a semi-finished package body A1 structure for encapsulating the chip 2. By first forming the semi-finished package structure, the various parts of the product can be pre-processed separately, thereby greatly improving production efficiency and simplifying the process.

[0027] Furthermore, after electroplating the circuit layer 4 and before electroplating the conductive column 5, a plurality of evenly spaced circular holes are etched on the circuit layer 4 through an etching process commonly used in this field. When the encapsulation material is subsequently encapsulated, the circular holes are also filled with the encapsulation material. The circular holes can release the stress of the circuit layer 4, reduce the impact of the stress on the front of the chip 2, and protect the front of the chip 2.

[0028] Among them, such as Figure 8 As shown, in the wall electroplating step, after the package A1 is peeled off from the substrate, a metal frame 6 is electroplated on the substrate through an electroplating process. The metal frame 6 has a certain height to form a wall. The electroplated metal frame 6 is stacked in one or more layers. The width of the multi-layer stacked metal frame 6 gradually decreases from the lower layer to the upper layer, or the width of each layer of the metal frame 6 is different. The lower metal frame 6 refers to the metal frame 6 close to the substrate. This application takes multiple layers as an example, specifically two layers, and the width difference of each layer of the metal frame 6 is in the range of 10 to 25 μm. m, forming a width step, that is, the metal frame 6 of the lower layer is flush with the metal frame 6 of the upper layer on the side outside the wall, and the side width difference on the inside of the wall is between 10 and 25 μm, forming a width step. Subsequently, the encapsulation material is filled between the wall and the package A1, and the encapsulation material fills the width step between each layer of metal frame 6, so that there is sufficient contact area between the metal frame 6 and the package B7 formed by curing the encapsulation material. The step and the encapsulation material are clamped to each other, effectively preventing the metal frame 6 from separating from the encapsulation material and failing.

[0029] Among them, such as Figure 9-10 As shown, in the mounting and encapsulation step, the semi-finished package A1 formed in the chip 2 packaging step is mounted on the substrate through the adhesive layer A3 exposed on its surface, so that the package A1 is located in the middle of the wall (as shown in FIG. Figure 9 ), after mounting, fill the space between the wall and the package body A1 with encapsulation material, and grind the top surface of the package after the encapsulation material is cured until the conductive pillars 5 and the metal frame 6 are flush with the top surface of the package as a whole and exposed, forming the package body B7. The package body A1 and the package body B7 constitute the package as a whole (such as Figure 10 , package A1 as Figure 10 (shown by the dashed line in the middle).

[0030] Among them, such as Figure 11-14As shown, in the outer layer electroplating step, the package formed in the mounting and encapsulation step has the conductive pillars 5 and the metal frame 6 exposed on the top surface. In this application, the width difference of the metal frame 6 is 17 μm as an example. The solder feet are electroplated on the metal frame 6 and the conductive pillars 5 by the electroplating process (such as Figure 11 ), the solder feet are welded to the middle structure of the working area as the whole package, the whole structure is peeled off from the substrate and placed upside down on the substrate again, at this time the glue layer A3 is exposed, a layer of glue layer B8 is brushed on the exposed glue layer A3, and the glue layer B8 covers the glue layer A3 (such as Figure 12 ), the distance between the edge of the adhesive layer B8 and the adhesive layer A3 is ≥100μm, and the thickness of the adhesive layer B8 is 1 to 1.5 times the thickness of the adhesive layer A3. In this application, the thickness of the adhesive layer B8 is 1.3 times the thickness of the adhesive layer A3 as an example. The thickness of the adhesive layer A3 is set to 15μm, the thickness of the adhesive layer B8 is set to 20μm, and the distance between the edge of the adhesive layer B8 and the adhesive layer A3 is 100μm. The adhesive layer A3 and the adhesive layer B8 are both thermally conductive and electrically conductive adhesives. The adhesive layer B8 is directly adhered to the adhesive layer A3 and is larger than the adhesive layer A3. A complete metal surface 9 is electroplated on the surface of the adhesive layer B8, the entire package board, and the metal frame 6 through an electroplating process. The metal surface 9 is connected to the metal frame 6 to form a sealed connection (such as Figure 13 ), the product process is completed, and the substrate is finally peeled off to form the product (such as Figure 14 ); A larger-sized covering adhesive layer B8 is directly set on the adhesive layer A3, and a metal surface 9 in contact with the adhesive layer B8 is electroplated, which can effectively buffer the stress of the metal surface 9 and protect the back of the chip. The entire packaging structure is more stable and reliable. The heat of the chip 2 is directly transferred to the metal surface 9 outside the entire package through the heat-conductive adhesive layer A3 and the adhesive layer B8, and dissipated, so the heat dissipation performance is better; the wall and the metal surface 9 form a five-sided sealing structure of the entire package, which strengthens the electromagnetic shielding effect and has good sealing performance; multiple chips 2 can be placed in a reasonable layout according to the substrate area to perform the above-mentioned process flow operation, and finally multiple product structures are formed at one time. However, this application takes the placement of only one chip 2 on the substrate as an example.

[0031] A five-sided encapsulation structure can be obtained by the above five-sided encapsulation process. Figure 15 As shown, the packaging structure includes the packaging as a whole, and also includes: Package A1, encapsulating a chip 2. The surface of adhesive layer A3 on the back of chip 2 is flush with and exposed to the outside of package A1. A circuit layer 4 and conductive pillars 5 are plated on the front of chip 2. The surface of conductive pillars 5 is flush with and exposed to package A1. Package A1 is pre-formed by applying adhesive layer A3 on the back of chip 2, then sequentially plating circuit layers 4 and conductive pillars 5 on the front of chip 2, and then encapsulating and grinding to expose the top surface of conductive pillars 5. Furthermore, a plurality of evenly spaced circular holes are etched on the circuit layer 4 to release stress; The fence is formed by electroplating a metal frame 6. The metal frame 6 is a stack of one or more electroplated layers. When the metal frames 6 are stacked in multiple layers, the width of the metal frames 6 gradually decreases from the lower layer to the upper layer. The width difference of each layer of the metal frame 6 ranges from 10 to 25 μm, forming a width step. Package B7: Package A1 is attached to the middle of the enclosure wall via adhesive layer A3. The top surface of the metal frame 6 is flush with the exposed conductive posts 5. A sealing compound is filled between the enclosure wall and package A1 and cured to form package B7. Packages A1 and B form the entire package. The top surface is then ground until the conductive posts 5 and metal frame 6 are flush with the top surface of the entire package. Metal surface 9, brush glue layer B8 on the back of the entire package, glue layer B8 covers glue layer A3, glue layer B8 extends outward from the edge of glue layer A3 by a distance ≥ 100μm, glue layer A3 and glue layer B8 are both thermally conductive and electrically conductive glue, and metal surface 9 is electroplated on glue layer B8, metal surface 9 covers the entire surface of the package and is sealed with metal frame 6, and solder feet are electroplated on the exposed conductive columns 5 and metal frame 6.

[0032] A packaged device can also be obtained through the above-mentioned five-sided encapsulation packaging process. The packaged device includes the above-mentioned five-sided encapsulation packaging structure.

[0033] The encapsulation material used in the present invention is a plastic encapsulation material, and the specific material can be epoxy resin, cyanate, polyimide, etc. It has low cost and good curing performance. The packaging process plays an important role in the field of semiconductor manufacturing, mainly reflected in protection, connection, support, reliability and promotion of technological progress. The encapsulation method is the commonly used method in this field, such as compression molding.

[0034] All the steps of the electroplating process of the present invention are to first form electroplating protection on the surface through the photolithography technology of exposure and development, protect the areas that do not need to be electroplated, expose the areas that need to be electroplated, and then form a metal seed layer in the area to be electroplated by appropriate methods such as sputtering or copper deposition. The metal seed layer is made of copper or other metal materials. The metal seed layer is to ensure the bonding strength between the metals and the metals and between the metals and the encapsulation materials in the subsequent electroplating, and at the same time provide a surface for the attachment of conductive ions for electroplating to ensure the electroplating effect. The entire steps in the electroplating process and the materials used are also technical common sense in this field. The metals electroplated in all the electroplating processes of the present invention are all made of metallic copper.

[0035] The present invention forms a semi-finished package structure first, and each part of the product can be pre-processed separately, which greatly improves production efficiency and simplifies the process; the encapsulation material fills the width steps between each layer of metal frame 6, so that there is sufficient contact area between the metal frame 6 and the package body B7 formed by curing the encapsulation material, and the steps and the encapsulation material are clamped to each other, effectively preventing the metal frame 6 from separating from the encapsulation material and failing; a larger-sized covering adhesive layer B8 is directly set on the adhesive layer A3, and a metal surface 9 in contact with the adhesive layer B8 is electroplated, which can effectively buffer the stress of the metal surface 9 and protect the back of the chip 2. The entire packaging structure is more stable and reliable, and the heat of the chip 2 is directly transferred to the metal surface 9 outside the package through the heat-conductive adhesive layer A3 and the adhesive layer B8 to dissipate, so the heat dissipation performance is better; the wall and the metal surface 9 form a five-sided encapsulation structure of the package as a whole, which strengthens the electromagnetic shielding effect and has good sealing.

[0036] It will be understood that the present invention is described by way of some embodiments, and it will be appreciated by those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of the present invention are intended to be protected by the present invention.

Claims

1. A five-sided encapsulation packaging process, characterized in that: The following steps are involved: Chip packaging: The chip is encapsulated in the package body A, the surface of the adhesive layer A on the back of the chip is flush with the package body A and exposed, the circuit layer and the conductive column are electroplated on the front of the chip, and the surface of the conductive column is flush with the package body A and exposed; Fence plating: Provide a substrate, electroplate a metal frame on the substrate, and the top surface of the metal frame is flush with the exposed conductive pillars; Mounting and encapsulation: Package A is mounted on the substrate in the middle of the enclosure through adhesive layer A, and the enclosure is filled with encapsulation material and the top surface is cured and ground until the conductive column, metal frame and the top surface of the package are flush and exposed to form package B. Package A and B constitute the package as a whole; Outer layer electroplating: peel off the substrate, apply glue layer B on the back of the entire package, and electroplate a metal surface on the glue layer B. The metal surface covers the entire surface of the package and is sealed and connected to the metal frame.

2. The five-sided encapsulation packaging process according to claim 1, characterized in that: In the chip packaging step, the package body A is obtained by applying a glue layer A on the back of the chip, electroplating a circuit layer and a conductive column on the front of the chip in sequence, and encapsulating and grinding to expose the top surface of the conductive column.

3. The five-sided encapsulation packaging process according to claim 1, characterized in that: In the wall electroplating step, the metal frame electroplated on the substrate is stacked in one or more layers.

4. The five-sided encapsulation packaging process according to claim 3, characterized in that: In the wall electroplating step, multiple layers of metal frames are stacked, and the width of the metal frames gradually decreases from the lower layer to the upper layer.

5. The five-sided encapsulation packaging process according to claim 4, characterized in that: In the wall electroplating step, the width difference of each layer of metal frame ranges from 10 to 25 μm, forming a width step.

6. The five-sided encapsulation packaging process according to claim 1, characterized in that: In the outer layer electroplating step, solder feet are electroplated on the exposed conductive pillars and metal frame before the substrate is stripped.

7. The five-sided encapsulation packaging process according to claim 1, characterized in that: In the outer layer electroplating step, the adhesive layer B covers the adhesive layer A, and the adhesive layer B extends outward from the edge of the adhesive layer A by a distance of ≥100 μm. Both the adhesive layer A and the adhesive layer B are thermally and electrically conductive adhesives.

8. A five-sided encapsulation packaging structure, comprising a packaging whole, characterized in that: Also included are: Package A, wherein a chip is encapsulated in the package A, the surface of the adhesive layer A on the back of the chip is flush with the package A and exposed, and the front of the chip is plated with a circuit layer and a conductive column, and the surface of the conductive column is flush with the package A and exposed; A fence, the fence being formed by a plated metal frame; Package B, the package A is attached to the middle of the enclosure through the adhesive layer A, at this time, the top surface of the metal frame is flush with the exposed conductive column, and the encapsulation material is filled between the enclosure and the package A and solidified into the package B. The packages A and B constitute the package as a whole, and the top surface is ground until the conductive column, the metal frame and the top surface of the package as a whole are flush and exposed; Metal surface: a glue layer B is applied on the back of the entire package, and a metal surface is electroplated on the glue layer B. The metal surface covers the entire surface of the package and is sealed and connected to the metal frame.

9. The five-sided encapsulation packaging structure according to claim 8, characterized in that: The package body A is obtained by applying a glue layer A on the back of the chip, electroplating a circuit layer and a conductive column on the front of the chip in sequence, and encapsulating and grinding to expose the top surface of the conductive column.

10. The five-sided encapsulation packaging structure according to claim 8, characterized in that: The metal frame is a stack of one or more electroplated layers.

11. The five-sided encapsulation packaging structure according to claim 10, characterized in that: When the metal frames are stacked in multiple layers, the width of the metal frames gradually decreases from the lower layer to the upper layer.

12. The five-sided encapsulation packaging structure according to claim 11, characterized in that: The width difference of each layer of metal frame ranges from 10 to 25 μm, forming a width step.

13. The five-sided encapsulation packaging structure according to claim 8, characterized in that: The exposed conductive posts and metal frame have electroplated solder pins.

14. The five-sided encapsulation packaging structure according to claim 8, characterized in that: The adhesive layer B covers the adhesive layer A, and the adhesive layer B extends outward from the edge of the adhesive layer A by a distance of ≥100 μm. Both the adhesive layer A and the adhesive layer B are thermally and electrically conductive adhesives.

15. A packaging device, characterized in that: The invention comprises the five-sided encapsulation packaging structure as described in any one of claims 8 to 14.

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