Layout structure of power semiconductor module and power semiconductor module

Abstract

The application discloses a layout structure of a power semiconductor module and the power semiconductor module. The negative power terminal, the lower bridge arm chip, the upper bridge arm chip and the alternating current power terminal of the layout structure are sequentially arranged along a first direction of a substrate, each negative power terminal is arranged along a second direction of the substrate and is arranged on each first metal layer, each lower bridge arm chip is arranged along the second direction of the substrate and is arranged on each second metal layer, each upper bridge arm chip is arranged along the second direction of the substrate and is arranged on each fourth metal layer, each alternating current power terminal is arranged along the second direction of the substrate and is arranged on each third metal layer, the positive power terminal and each upper bridge arm chip are sequentially arranged along the second direction of the substrate and are arranged on the fourth metal layer. The layout structure of the power semiconductor module of the application improves the space utilization of the power semiconductor device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power semiconductors, in particular to a layout structure of a power semiconductor module and a power semiconductor module. BACKGROUND

[0002] In modern power systems, the application scenarios of power semiconductors are very wide and complex, which requires the functions of power semiconductors to be more and more integrated, and therefore the demand for the power density of power semiconductors is also increasing. However, in the design of traditional power semiconductor modules, such as insulated gate bipolar transistors (IGBT) or all silicon carbide (SiC) power semiconductor modules, the AC power terminals usually share the same metal layer with the lower bridge arm to realize current flow. However, this design has obvious limitations in the face of high power density requirements.

[0003] Specifically, because the AC power terminals share the metal layer with the lower bridge arm inside the traditional power semiconductor module, the space utilization efficiency inside the module is low, which limits the layout flexibility of the terminals and the current outflow path of the terminals, thereby affecting the overall heat dissipation performance and electrical characteristics of the power semiconductor module. In addition, this layout method also makes the current outflow position of the terminals not flexible, which makes it difficult for the power semiconductor module to increase the KS (Kelvin-Source) signal terminal for improving current accuracy, thereby limiting the improvement of the overall efficiency of the power module. SUMMARY

[0004] In view of the above problems, the present application provides a layout structure of a power semiconductor module and a power semiconductor module to solve the above technical problems.

[0005] In a first aspect, the present application provides a layout structure of a power semiconductor module, comprising: a substrate, at least one pair of lower bridge arm chips and upper bridge arm chips, the same number of negative power terminals as the lower bridge arm chips, the same number of AC power terminals as the lower bridge arm chips, and one positive power terminal.

[0006] The substrate is provided with the same number of first metal layers as the lower bridge arm chips, second metal layers, third metal layers, and one fourth metal layer;

[0007] The negative power terminals, the lower bridge arm chips, the upper bridge arm chips and the AC power terminals are sequentially arranged along the first direction of the substrate, and each negative power terminal is arranged along the second direction of the substrate and is respectively arranged on each first metal layer, each lower bridge arm chip is arranged along the second direction of the substrate and is respectively arranged on each second metal layer, each upper bridge arm chip is arranged along the second direction of the substrate and is arranged on the fourth metal layer, and each AC power terminal is arranged along the second direction of the substrate and is respectively arranged on each third metal layer;

[0008] The positive power terminals and the upper bridge arm chips are arranged in sequence along the second direction of the substrate and are disposed on the fourth metal layer.

[0009] In some embodiments, the layout structure of the power semiconductor module provided by the present application is configured such that the positive power terminals are configured to receive current and transmit the current to the upper bridge arm chips, the upper bridge arm chips are configured to transmit the current to the corresponding lower bridge arm chips and the corresponding alternating current power terminals respectively, and the lower bridge arm chips are configured to transmit the current to the corresponding negative power terminals.

[0010] In some embodiments, the layout structure of the power semiconductor module provided by the present application is configured such that at least one pair of lower bridge arm chips and upper bridge arm chips are configured to be connected in a half-bridge manner or are configured to be connected in a full-bridge manner.

[0011] In some embodiments, the layout structure of the power semiconductor module provided by the present application is further configured to have at least one signal terminal metal layer on the substrate, and each signal terminal metal layer is configured to have one signal terminal disposed thereon.

[0012] Each signal terminal metal layer is arranged in parallel with the first metal layer along the second direction of the substrate and is arranged in parallel with each third metal layer along the second direction of the substrate.

[0013] In some embodiments, the layout structure of the power semiconductor module provided by the present application is configured such that the signal terminals at least include a Kelvin source signal terminal.

[0014] In some embodiments, the layout structure of the power semiconductor module provided by the present application is configured such that the upper bridge arm chips and the lower bridge arm chips are silicon carbide metal oxide semiconductor field effect transistor chips.

[0015] In some embodiments, the layout structure of the power semiconductor module provided by the present application is configured such that the upper bridge arm chips and the lower bridge arm chips are insulated gate bipolar transistors.

[0016] In some embodiments, the layout structure of the power semiconductor module provided by the present application is further configured to have a thermistor disposed on the substrate for detecting the temperature of the power semiconductor module.

[0017] In some embodiments, the layout structure of the power semiconductor module provided by the present application is configured such that the substrate is a direct copper bonding structure or an advanced multi-layer bonding structure.

[0018] In a second aspect, the present application provides a power semiconductor module comprising at least one layout structure of a power semiconductor module according to any one of the first aspect.

[0019] The layout structure of the power semiconductor module and the power semiconductor module are provided in the application. In the layout structure of the power semiconductor module, the negative power terminals, the lower bridge arm chips, the upper bridge arm chips and the alternating current power terminals are sequentially arranged along a first direction of the substrate, and each negative power terminal is arranged on each first metal layer of the substrate along a second direction of the substrate. Each lower bridge arm chip is arranged on each second metal layer of the substrate along the second direction of the substrate. Each upper bridge arm chip is arranged on the fourth metal layer of the substrate along the second direction of the substrate. Each alternating current power terminal is arranged on each third metal layer of the substrate along the second direction of the substrate. The positive power terminals and each upper bridge arm chip are sequentially arranged along the second direction of the substrate and arranged on the fourth metal layer of the substrate. In the layout structure of the power semiconductor module, the negative power terminals are arranged close to the lower bridge arm chips, the alternating current power terminals are arranged close to the upper bridge arm chips, and the positive power terminals and the upper bridge arm chips are arranged on the same metal layer, so that the alternating current power terminals and the lower bridge arm chips are distributed on both sides of the upper bridge arm chips. Based on the layout structure of the power semiconductor module, the current can flow out of the positive power terminals to the upper bridge arm chips, and one side of the upper bridge arm chips flows out to the lower bridge arm chips while the other side flows out to the alternating current power terminals. Based on the layout structure of the power semiconductor module, more signal terminals can be added in the spare positions between the negative power terminals and the alternating current power terminals, and the space utilization of the power semiconductor module is greatly improved.

[0020] These aspects or other aspects of the application will be more apparent from the following description of the embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the application or in the prior art, the following will briefly introduce the drawings needed to be used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative effort.

[0022] Figure 1 A schematic diagram of a conventional power semiconductor module is shown.

[0023] Figure 2 A schematic diagram of the layout structure of the power semiconductor module provided in the embodiment of the application is shown.

[0024] Figure 3 Another schematic diagram of the layout structure of the power semiconductor module provided in the embodiment of the application is shown.

[0025] Figure 4 A schematic diagram of the lower bridge arm chip and the upper bridge arm chip connected in a half-bridge mode is shown.

[0026] Figure 5 A schematic diagram showing a lower bridge arm chip and an upper bridge arm chip connected in a full-bridge manner is shown.

[0027] Figure 6 Another schematic diagram showing a layout structure of a power semiconductor module provided by an embodiment of the present application is shown.

[0028] Figure 7 A schematic diagram showing a power semiconductor module provided by an embodiment of the present application is shown. DETAILED DESCRIPTION

[0029] In order to make the persons skilled in the art better understand the schemes of the present application, the technical schemes in the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by the persons skilled in the art without creative labor fall within the protection scope of the present application.

[0030] In the embodiments of the present application, it should be noted that, in this document, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between the entities or operations.

[0031] Moreover, the terms “comprising”, “containing” or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or equipment. Without more limitations, the element defined by the statement “including a…” does not exclude the presence of another identical element in the process, method, article or equipment including the element.

[0032] In addition, “a plurality of” in the embodiments of the present application means two or more, and therefore “a plurality of” in the embodiments of the present application can also be understood as “at least two”. “At least one” can be understood as one or more, for example, as one, two or more. For example, including at least one means including one, two or more, and does not limit which ones are included, for example, including at least one of A, B and C means including A, B, C, A and B, A and C, B and C, or A and B and C.

[0033] Figure 1 A schematic diagram showing a conventional power semiconductor module is shown as follows: Figure 1As shown in the design of a conventional power semiconductor module, such as an insulated gate bipolar transistor (IGBT) or a full silicon carbide (SiC) power semiconductor module, the AC power terminal AC is usually shared with the lower arm chip to realize current flow through the same metal layer. Obviously, this design leaves less layout position for the signal terminal, thereby limiting the layout flexibility of the terminal and the current outflow path of the terminal, thereby affecting the overall heat dissipation performance and electrical characteristics of the power semiconductor module. In addition, this layout method also leads to inflexible current outflow position of the terminal, thereby making it difficult for the conventional power semiconductor module to increase the KS (Kelvin-Source) signal terminal for improving current accuracy, thereby limiting the improvement of the overall efficiency of the power module. Especially in the face of miniaturized packaging, the internal layout space of the conventional power semiconductor module is further compressed, making the internal space utilization rate even lower. Therefore, how to break through these limitations through innovative internal layout design without sacrificing reliability has become one of the key problems to be solved in the current power semiconductor industry.

[0034] In view of the above problems, the layout structure of the power semiconductor module provided by the embodiments of the present application, Figure 2 The layout structure of the power semiconductor module provided by the embodiments of the present application is shown in the schematic diagram. Figure 2 As shown, the layout structure of the power semiconductor module provided by the embodiments of the present application includes a substrate 110, at least one pair of lower arm chips 210 and upper arm chips 220, the same number of negative power terminals (DC-) 310 as the lower arm chips 210, the same number of AC power terminals (AC) 410 as the lower arm chips 210, and one positive power terminal (DC+) 320.

[0035] As shown in the layout structure of the power semiconductor module provided by the embodiments of the present application, Figure 2 As shown, the substrate 110 is provided with the same number of first metal layers C1 as the lower arm chips 210, second metal layers C2, third metal layers C3, and one fourth metal layer C4. Among them, the negative power terminals 310, the lower arm chips 210, the upper arm chips 220, and the AC power terminals 410 are sequentially arranged along the first direction (y direction) of the substrate 110, and each negative power terminal 310 is arranged along the second direction (x direction) of the substrate 110 and is respectively arranged on each first metal layer C1, each lower arm chip 210 is arranged along the second direction (x direction) of the substrate 110 and is respectively arranged on each second metal layer C2, each upper arm chip 220 is arranged along the second direction (x direction) of the substrate 110 and is arranged on the fourth metal layer C4, each AC power terminal 410 is arranged along the second direction (x direction) of the substrate 110 and is respectively arranged on each third metal layer C3, and the positive power terminal 320 and each upper arm chip 220 are sequentially arranged along the second direction (x direction) of the substrate 110 and are arranged on the fourth metal layer C4.

[0036] The layout structure of the power semiconductor module provided by the embodiment of the present application is that the negative power terminal is arranged close to the lower bridge arm chip, the alternating current power terminal is arranged close to the upper bridge arm chip, and the positive power terminal and the upper bridge arm chip are arranged on the same metal layer, so that the alternating current power terminal and the lower bridge arm chip are distributed on both sides of the upper bridge arm chip. Based on the layout structure of the power semiconductor module, the current can flow from the positive power terminal to the upper bridge arm chip, and flow out of the lower bridge arm chip on one side of the upper bridge arm chip while flowing out of the alternating current power terminal on the other side. Based on the layout structure of the power semiconductor module, more signal terminals can be added in the free space between the negative power terminals and the alternating current power terminals according to the packaging characteristics of different packages, so that the space utilization of the power semiconductor module is greatly improved.

[0037] Compared with the traditional power semiconductor module, the space utilization of the embodiment of the present application is higher under the same volume, so that higher power density can be realized, and small packaging and high power density can be compatible.

[0038] In some embodiments, in the layout structure of the power semiconductor module provided by the embodiment of the present application, the positive power terminal is configured to receive current and transmit the current to each upper bridge arm chip, the upper bridge arm chip is configured to transmit the current to the corresponding lower bridge arm chip and the corresponding alternating current power terminal respectively, and the lower bridge arm chip is configured to transmit the current to the corresponding negative power terminal. Optionally, based on the layout structure of the power semiconductor module provided by the embodiment of the present application, the outflow direction of the current can be set as the positive power terminal, the upper bridge arm chip, the alternating current power terminal and the lower bridge arm chip, and the outflow position of the current of each terminal is flexible, thereby improving the space utilization of the layout structure.

[0039] In some embodiments, in the layout structure of the power semiconductor module provided by the embodiment of the present application, at least one pair of lower bridge arm chips and upper bridge arm chips are configured to be connected in a half-bridge mode as a layout structure of a half-bridge power semiconductor module, or are configured to be connected in a full-bridge mode as a layout structure of a three-phase full-bridge power semiconductor module.

[0040] In some embodiments, Figure 3 Another schematic diagram of the layout structure of the power semiconductor module provided by the embodiment of the present application is shown, as shown in Figure 3 As shown, in the layout structure of the power semiconductor module provided by the embodiment of the present application, at least one signal terminal metal layer C5 is further arranged on the substrate 110, and each signal terminal metal layer C5 is used to arrange one signal terminal 500.

[0041] The signal terminal metal layers C5 are arranged in parallel with the first metal layers C1 in the second direction (x direction) of the substrate 110 and in parallel with the third metal layers C3 in the second direction (x direction) of the substrate 110.

[0042] It can be understood that the layout position of the signal terminal in the layout structure of the power semiconductor module is determined by the packaging type. The layout structure of the power semiconductor module provided in the embodiments of the present application aims to provide a layout structure including a negative power terminal, a positive power terminal, an alternating current power terminal, a lower bridge arm chip and an upper bridge arm chip, so as to improve the layout space utilization rate of the power semiconductor module through the layout structure, thereby being able to increase more signal terminals. Therefore, the position of the signal terminal can be any idle position in the layout structure, and the specific position of the signal terminal should be determined by the packaging type, which is not limited in the embodiments of the present application.

[0043] In some embodiments, the layout structure of the power semiconductor module provided in the embodiments of the present application includes at least a Kelvin source signal terminal (Kelvin-Source, Ks signal terminal) in each signal terminal 500.

[0044] Compared with the low space utilization rate problem of the conventional power semiconductor module caused by the current outflow position limitation of the terminal, the layout structure of the power semiconductor module provided in the present application significantly improves the layout space utilization rate of the power semiconductor module. Based on this utilization rate, the layout structure of the power semiconductor module can further set an additional Kelvin source signal terminal to provide the performance of the power semiconductor.

[0045] In some embodiments, the layout structure of the power semiconductor module provided in the embodiments of the present application includes a silicon carbide metal oxide semiconductor field effect transistor (SiC MOSFET) chip as the upper bridge arm chip and the lower bridge arm chip.

[0046] In some embodiments, the layout structure of the power semiconductor module provided in the embodiments of the present application includes an insulated gate bipolar transistor (IGBT, Insulated Gate Bipolar Transistor) chip as the upper bridge arm chip and the lower bridge arm chip.

[0047] In some embodiments, Figure 4 A schematic diagram of the lower bridge arm chip and the upper bridge arm chip connected in a half-bridge mode is shown as follows, Figure 4As shown, the layout structure of the power semiconductor module provided by the embodiment of the present application is that the lower bridge arm chip and the upper bridge arm chip are (SiC MOSFET) chips or IGBT chips, the drain of the upper bridge arm chip is connected with the positive power terminal DC+, the source is respectively connected with the drain of the lower bridge arm chip and the alternating current power terminal AC, and the source of the lower bridge arm chip is connected with the negative power terminal DC-, wherein G1 and G2 respectively represent the gate of the upper bridge arm chip and the lower bridge arm chip, and S1 and S2 respectively represent the source of the upper bridge arm chip and the lower bridge arm chip.

[0048] In some embodiments, Figure 5 As shown, the schematic diagram of the lower bridge arm chip and the upper bridge arm chip connected in the full-bridge mode is shown. Figure 5 As shown, the layout structure of the power semiconductor module provided by the embodiment of the present application is that the lower bridge arm chip and the upper bridge arm chip are (SiC MOSFET) chips or IGBT chips, and the layout structure includes three pairs of parallelly connected lower bridge arm chips and upper bridge arm chips.

[0049] It can be understood that, Figure 5 The parallel connection mode of the three pairs of lower bridge arm chips and upper bridge arm chips is not shown, because the embodiment of the present application does not limit the specific circuit structure of the full-bridge structure.

[0050] In some embodiments, Figure 6 As shown, another schematic diagram of the layout structure of the power semiconductor module provided by the embodiment of the present application is shown. Figure 6 As shown, the layout structure of the power semiconductor module provided by the embodiment of the present application is that the substrate 110 is further provided with a thermistor 600 for detecting the temperature of the power semiconductor module.

[0051] In some embodiments, the layout structure of the power semiconductor module provided by the embodiment of the present application is that the substrate is a direct copper bonding (Direct Copper Bonding) structure, and optionally, the direct copper bonding substrate structure includes two upper and lower metal layers and an intermediate aluminum oxide layer, the metal layer is used to provide excellent electrical conductivity, and the aluminum oxide layer has good thermal conductivity and chemical stability, wherein the upper surface metal layer of the direct copper bonding substrate includes the first to fifth metal layers.

[0052] In some embodiments, the power semiconductor module layout structure provided in this application includes an advanced multilayer bonding (AMB) structure as the substrate. Optionally, the AMB substrate includes upper and lower metal layers and a middle silicon nitride layer. The metal layers provide excellent electrical conductivity, while the silicon nitride layer possesses good thermal conductivity, chemical stability, and mechanical strength. The upper surface metal layer of the AMB substrate includes a first to a fifth metal layer.

[0053] It is understood that the layout structure of the power semiconductor module provided in this application is intended to provide a layout structure including a negative power terminal, a positive power terminal, an AC power terminal, a lower bridge arm chip, and an upper bridge arm chip, so as to improve the layout space utilization of the power semiconductor module and thus increase more signal terminals. The structure of the substrate is not limited here, that is, the substrate is not limited to the direct copper bonding structure and the advanced multi-layer bonding structure described in the above embodiments.

[0054] In some embodiments, in the layout structure of the power semiconductor module provided in this application, the metal material of the first to fifth metal layers is preferably copper.

[0055] Based on the layout structure of the power semiconductor module provided in the above embodiments, this application embodiment also provides a power semiconductor module. The power semiconductor module provided in this application embodiment includes at least one layout structure of a power semiconductor module, so as to realize different functions through the layout structure of each power semiconductor module.

[0056] In some embodiments, Figure 7 A schematic diagram of a power semiconductor module provided in an embodiment of this application is shown, as follows: Figure 7 As shown, the power semiconductor module includes a layout structure of two three-phase full-bridge power semiconductor modules, which respectively realize rectification and motor drive functions by setting up the layout structure of the two three-phase full-bridge power semiconductor modules. In the layout structure of the two three-phase full-bridge power semiconductor modules, the negative power terminal 310, the lower bridge arm chip 210, the upper bridge arm chip 220, and the AC power terminal 410 are arranged sequentially along the first direction (y direction) of the substrate, and the positive power terminal 320 and each upper bridge arm chip 220 are arranged sequentially along the second direction (x direction) of the substrate and are located on the same metal layer. The metal layer where each signal terminal 500 is located is arranged side by side with the metal layer where the negative power terminal 310 is located along the second direction (x direction) of the substrate, and is arranged side by side with the metal layer where each AC power terminal 410 is located along the second direction (x direction) of the substrate. Optionally, asFigure 7 As shown, each signal terminal 500 at least includes a Kelvin source signal terminal 510.

[0057] The power semiconductor module provided by the embodiment of the present application has the negative power terminal arranged close to the lower bridge arm chip, the AC power terminal arranged close to the upper bridge arm chip, and the positive power terminal arranged in the same metal layer as the upper bridge arm chip, so that the AC power terminal and the lower bridge arm chip are distributed on both sides of the upper bridge arm chip. Based on the layout structure of the power semiconductor module, the current can flow from the positive power terminal to the upper bridge arm chip, and flow out of the lower bridge arm chip on one side of the upper bridge arm chip while flowing out of the AC power terminal on the other side. Further, based on the layout structure of the power semiconductor module, more signal terminals can be added in the free space between the negative power terminals and the AC power terminals according to the packaging features, greatly improving the space utilization of the power semiconductor module.

[0058] Compared with the conventional power semiconductor module, the space utilization of the embodiment of the present application is higher under the same volume, so that higher power density can be achieved, and the small packaging and high power density can be compatible.

[0059] The above is a further detailed description of the present application in combination with specific embodiments, and the specific implementation of the present application cannot be limited to these descriptions. For ordinary skilled persons in the technical field to which the present application belongs, some simple deductions or replacements can be made without departing from the concept of the present application, and all of them should be regarded as the protection scope of the present application.

Claims

1. A layout structure of a power semiconductor module, characterized by, The power semiconductor module comprises: a substrate, at least one pair of lower bridge arm chips and upper bridge arm chips, a number of negative power terminals equal to the number of lower bridge arm chips, a number of alternating current power terminals equal to the number of lower bridge arm chips, and one positive power terminal; the substrate is provided with a number of first metal layers equal to the number of lower bridge arm chips, a number of second metal layers, a number of third metal layers, and one fourth metal layer; the negative power terminals, the lower bridge arm chips, the upper bridge arm chips, and the alternating current power terminals are sequentially arranged along a first direction of the substrate, and each negative power terminal is arranged along a second direction of the substrate and disposed on each first metal layer, each lower bridge arm chip is arranged along the second direction of the substrate and disposed on each second metal layer, each upper bridge arm chip is arranged along the second direction of the substrate and disposed on the fourth metal layer, and each alternating current power terminal is arranged along the second direction of the substrate and disposed on each third metal layer; the positive power terminal and each upper bridge arm chip are sequentially arranged along the second direction of the substrate and disposed on the fourth metal layer; the substrate is further provided with at least one signal terminal metal layer, and each signal terminal metal layer is used to dispose one signal terminal; each signal terminal metal layer is arranged in parallel with the first metal layer along the second direction of the substrate, and arranged in parallel with each third metal layer along the second direction of the substrate.

2. The layout structure of a power semiconductor module according to claim 1, characterized by, The positive power terminal is configured to receive current and transmit the current to each upper bridge arm chip, the upper bridge arm chip is configured to transmit the current to the corresponding lower bridge arm chip and the corresponding alternating current power terminal, and the lower bridge arm chip is configured to transmit the current to the corresponding negative power terminal.

3. The layout structure of a power semiconductor module according to claim 1, characterized by, The at least one pair of lower bridge arm chips and upper bridge arm chips are configured to be connected in a half-bridge mode or in a full-bridge mode.

4. The layout structure of a power semiconductor module according to claim 3, characterized by, The signal terminal at least includes a Kelvin source signal terminal.

5. The layout structure of a power semiconductor module according to claim 1, wherein The upper bridge arm chip and the lower bridge arm chip are silicon carbide metal oxide semiconductor field effect transistor chips.

6. The layout structure of a power semiconductor module according to claim 1, wherein The upper bridge arm chip and the lower bridge arm chip are insulated gate bipolar transistor chips.

7. The layout structure of a power semiconductor module according to claim 1, wherein The substrate is further provided with a thermistor for detecting the temperature of the power semiconductor module.

8. The layout structure of a power semiconductor module according to claim 1, wherein The substrate is a direct copper bonding structure or an advanced multi-layer bonding structure.

9. A power semiconductor module, characterized by The layout structure comprises at least one power semiconductor module as claimed in any one of claims 1-8.

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