Substrate structure and manufacturing method thereof

Abstract

A substrate structure and a manufacturing method thereof are provided, the substrate structure comprising: a core layer having a plurality of conductive structures; a first build-up structure disposed on the core layer and having a plurality of first conductive pillars; the second layer-adding structure is arranged on the first layer-adding structure and is provided with a plurality of second conductive columns; wherein the first conductive column and the conductive structure are mutually staggered, and the second conductive column is correspondingly aligned with the conductive structure and is mutually staggered with the first conductive column.

Description

Technical Field

[0001] The present disclosure relates to a substrate structure and a manufacturing method thereof, and in particular to a substrate structure and a manufacturing method thereof capable of improving substrate utilization. Background Art

[0002] Figure 1A and Figure 1B They are respectively a cross-sectional schematic diagram and a top schematic diagram of the existing substrate structure 1. Figure 1A As shown, the substrate structure 1 includes a core layer 10, a first build-up layer structure 13 disposed on opposite sides of the core layer 10, a second build-up layer structure 14 disposed on the first build-up layer structure 13, and a third build-up layer structure 15 disposed on the second build-up layer structure 14. The core layer 10 has a plurality of conductive structures 12, the first build-up layer structure 13 has a first dielectric layer 130 and a plurality of first conductive pillars 132, the second build-up layer structure 14 has a second dielectric layer 140 and a plurality of second conductive pillars 142, and the third build-up layer structure 15 has a third dielectric layer 150 and a plurality of third conductive pillars 152.

[0003] However, the conductive structure 12, the first conductive pillar 132, the second conductive pillar 142 and the third conductive pillar 152 are arranged on the board edge B of the substrate structure 1 in a progressive manner in a staggered and non-overlapping manner, resulting in a certain width of the board edge B being reserved, thereby limiting the number of circuit areas A of the substrate structure 1.

[0004] Therefore, how to overcome the various problems of the above-mentioned prior art has become a topic that needs to be solved urgently. Summary of the invention

[0005] The present disclosure provides a substrate structure, including: a core layer, having a plurality of conductive structures; a first build-up layer structure, disposed on the core layer, and having a first dielectric layer and a plurality of first conductive pillars formed in the first dielectric layer; and a second build-up layer structure, disposed on the first build-up layer structure, and having a second dielectric layer and a plurality of second conductive pillars formed in the second dielectric layer; wherein the first conductive pillar and the conductive structure are offset from each other, and the second conductive pillar is aligned with the conductive structure and is offset from each other with respect to the first conductive pillar.

[0006] The substrate structure as mentioned above further includes a third build-up layer structure, which is disposed on the second build-up layer structure and has a third dielectric layer and a plurality of third conductive pillars formed in the third dielectric layer.

[0007] As in the aforementioned substrate structure, the third conductive pillar is aligned with the first conductive pillar and is offset from the second conductive pillar and the conductive structure.

[0008] As in the aforementioned substrate structure, the conductive structure, the first conductive pillar, the second conductive pillar and the third conductive pillar are adjacent to the board edge of the substrate structure.

[0009] As the aforementioned substrate structure, the core layer has a first surface and a second surface opposite to each other, and the first build-up layer structure is formed on the first surface and the second surface.

[0010] The present disclosure also provides a method for manufacturing a substrate structure, including: providing a core layer having a plurality of conductive structures; forming a first build-up layer structure on the core layer, wherein the first build-up layer structure has a first dielectric layer and a plurality of first conductive pillars formed in the first dielectric layer; forming a second build-up layer structure on the first build-up layer structure, wherein the second build-up layer structure has a second dielectric layer and a plurality of second conductive pillars formed in the second dielectric layer; wherein the first conductive pillar and the conductive structure are offset from each other, and the second conductive pillar is aligned with the conductive structure and is offset from the first conductive pillar.

[0011] The method for manufacturing the substrate structure as described above further includes forming a third build-up layer structure on the second build-up layer structure, wherein the third build-up layer structure has a third dielectric layer and a plurality of third conductive pillars formed in the third dielectric layer.

[0012] As in the aforementioned method for manufacturing the substrate structure, the third conductive pillar is aligned with the first conductive pillar and is offset from the second conductive pillar and the conductive structure.

[0013] As in the aforementioned method for manufacturing the substrate structure, the conductive structure, the first conductive pillar, the second conductive pillar and the third conductive pillar are adjacent to the board edge of the substrate structure.

[0014] As described in the above-mentioned method for manufacturing the substrate structure, the core layer has a first surface and a second surface opposite to each other, and the first build-up layer structure is formed on the first surface and the second surface.

[0015] In summary, the substrate structure and manufacturing method disclosed herein utilize a design in which the conductive columns of adjacent layers are staggered with each other and the conductive columns of alternate layers are aligned with each other, which can reduce the width of the board edge and improve the substrate utilization rate. The more carrier layers there are, the greater the difference in substrate utilization rate will be. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1A It is a cross-sectional schematic diagram of an existing substrate structure.

[0017] Figure 1B It is a top view schematic diagram of an existing substrate structure.

[0018] Figures 2A to 2G It is a cross-sectional schematic diagram of the method for manufacturing the substrate structure disclosed in the present invention.

[0019] Figure 3 It is a top view schematic diagram of the substrate structure disclosed in the present invention.

[0020] The reference numerals are described as follows:

[0021] 1,2 Substrate structure

[0022] 10,20 Core Layer

[0023] 20a First surface

[0024] 20b Second surface

[0025] 200 Through hole

[0026] 21 Circuit layer

[0027] 12,22 Conductive structure

[0028] 13,23 The first layer structure

[0029] 130,230 First dielectric layer

[0030] 231 First through hole

[0031] 132,232 First conductive column

[0032] 233 First circuit layer

[0033] 14,24 Second layer structure

[0034] 140,240 Second dielectric layer

[0035] 241 Second through hole

[0036] 142,242 Second conductive column

[0037] 243 Second circuit layer

[0038] 15,25 The third layer structure

[0039] 150,250 Third dielectric layer

[0040] 251 Third through hole

[0041] 152,252 Third conductive column

[0042] 253 Third Line Layer

[0043] A Line Area

[0044] B board edge. DETAILED DESCRIPTION

[0045] The following describes the implementation methods of the present disclosure by means of specific embodiments. Those skilled in the art can easily understand other advantages and technical effects of the present disclosure from the contents disclosed in this specification.

[0046] It should be noted that the structures, proportions, sizes, etc. shown in the drawings attached to this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of the present disclosure, so they have no substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size, without affecting the technical effects and objectives that can be achieved by the present disclosure, should still fall within the scope of the technical contents disclosed in the present disclosure. At the same time, the terms such as "upper", "first", "second", "third", etc. cited in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present disclosure. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the present disclosure without substantially changing the technical contents.

[0047] Figures 2A to 2G It is a cross-sectional schematic diagram of the manufacturing method of the substrate structure 2 disclosed in the present invention.

[0048] like Figure 2A As shown, a core layer 20 having a circuit layer 21 and a plurality of conductive structures 22 is provided.

[0049] In this embodiment, the core layer 20 has a first surface 20a and a second surface 20b opposite to each other. For example, the core layer 20 may be made of a substrate containing glass fiber and organic resin, such as BT (Bismaleimide Triazine), FR4 or FR5, etc., without any particular limitation.

[0050] In one embodiment, a plurality of through holes 200 can be formed in the core layer 20 by mechanical, laser, etching or other appropriate methods, and a plurality of columnar conductive structures 22 can be formed in the plurality of through holes 200 by utilizing processes such as plating through hole (PTH) and patterning processes (such as inner layer development etching stripping (DES)), and then a circuit layer 21 is formed on the plurality of conductive structures 22 and the core layer 20.

[0051] like Figure 2B As shown, a first dielectric layer 230 is formed on the first surface 20a and the second surface 20b of the core layer 20 by lamination. Then, a plurality of first through holes 231 are formed in the first dielectric layer 230 by mechanical, laser, etching or other appropriate methods, wherein the first through holes 231 do not penetrate the first dielectric layer 230 and do not expose the core layer 20.

[0052] like Figure 2C As shown, a plurality of first conductive pillars 232 such as copper are electroplated in the plurality of first through holes 231 according to the specification of a redistribution layer (RDL), and a first wiring layer 233 such as copper is formed on the plurality of first conductive pillars 232 and the first dielectric layer 230 .

[0053] In this embodiment, the first conductive pillars 232 and the conductive structures 22 are staggered with each other, and the first conductive pillars 232 located at different sides of the core layer 20 correspond to each other.

[0054] like Figure 2D As shown, a second dielectric layer 240 is formed on the first dielectric layer 230 by lamination. Then, a plurality of second through holes 241 are formed in the second dielectric layer 240 by mechanical, laser, etching or other appropriate methods, wherein the second through holes 241 do not penetrate the second dielectric layer 240 and do not expose the first dielectric layer 230.

[0055] like Figure 2E As shown, a plurality of second conductive pillars 242 , such as copper, are formed by electroplating in the plurality of second through holes 241 according to RDL specifications, and a second wiring layer 243 , such as copper, is formed on the plurality of second conductive pillars 242 and the second dielectric layer 240 .

[0056] In this embodiment, the second conductive pillars 242 correspond to the conductive structures 22 and are offset from the first conductive pillars 232 , and the conductive structures 22 and the second conductive pillars 242 located on different sides of the core layer 20 correspond to each other.

[0057] like Figure 2F As shown, a third dielectric layer 250 is formed on the second dielectric layer 240 by lamination. Then, a plurality of third through holes 251 are formed in the third dielectric layer 250 by mechanical, laser, etching or other appropriate methods, wherein the third through holes 251 do not penetrate the third dielectric layer 250 and do not expose the second dielectric layer 240.

[0058] like Figure 2G As shown, a plurality of third conductive pillars 252 such as copper are electroplated in the plurality of third through holes 251 according to RDL specifications, and a third wiring layer 253 such as copper is formed on the plurality of third conductive pillars 252 and the third dielectric layer 250 to obtain the substrate structure 2 of the present disclosure.

[0059] In this embodiment, the third conductive pillar 252 is aligned with the first conductive pillar 232 and is offset from the conductive structure 22 and the second conductive pillar 242 . The first conductive pillar 232 and the third conductive pillar 252 located on different sides of the core layer 20 correspond to each other.

[0060] In the present embodiment, the material forming the first dielectric layer 230, the second dielectric layer 240 and the third dielectric layer 250 may be, for example, Ajinomoto build-up film (ABF), polybenzoxazole (PBO), polyimide (PI), glass fiber prepreg (PP) or other dielectric materials, and the materials of the first dielectric layer 230, the second dielectric layer 240 and the third dielectric layer 250 may be the same or different, and the present disclosure is not limited thereto.

[0061] By virtue of the first conductive pillar 232 in the substrate structure 2 of the present disclosure correspondingly aligning with the third conductive pillar 252 (or the first through hole 231 correspondingly aligning with the third through hole 251), the second conductive pillar 242 correspondingly aligning with the conductive structure 22 (or the second through hole 241 correspondingly aligning with the through hole 200), and the first conductive pillar 232 and the second conductive pillar 242 / conductive structure 22 are misaligned with each other (or the first through hole 231 and the second through hole 241 / through hole 200 are misaligned with each other), and the third conductive pillar 252 and the second conductive pillar 242 / conductive structure 22 are misaligned with each other (or the third through hole 251 and the second through hole 241 / through hole 200 are misaligned with each other), as shown in FIG. Figure 3 As shown, compared with the prior art, the board edge B of the substrate structure 2 of the present disclosure can be reduced, thereby increasing the circuit area A, for example Figure 1B The existing circuit area A can only arrange 12, while the present invention can arrange 14, which effectively improves the substrate utilization rate.

[0062] In summary, the substrate structure and manufacturing method disclosed herein utilize a design in which the conductive columns of adjacent layers are staggered with each other and the conductive columns of alternate layers are aligned with each other, which can reduce the width of the board edge and improve the substrate utilization rate. The more carrier layers there are, the greater the difference in substrate utilization rate will be.

[0063] The above embodiments are used to illustrate the principles and technical effects of the present disclosure, but are not used to limit the present disclosure. Those skilled in the art may modify the above embodiments without violating the concept and scope of the present disclosure. Therefore, the scope of protection of the present disclosure should be as listed in the claims.

Claims

1. A substrate structure, comprising: a core layer having a plurality of conductive structures; A first build-up layer structure is disposed on the core layer and has a first dielectric layer and a plurality of first conductive pillars formed in the first dielectric layer; as well as A second build-up layer structure is disposed on the first build-up layer structure and has a second dielectric layer and a plurality of second conductive pillars formed in the second dielectric layer; The first conductive column and the conductive structure are misaligned with each other, and the second conductive column is aligned with the conductive structure and is misaligned with the first conductive column.

2. The substrate structure according to claim 1, characterized in that: The substrate structure further includes a third build-up layer structure, which is disposed on the second build-up layer structure and has a third dielectric layer and a plurality of third conductive pillars formed in the third dielectric layer.

3. The substrate structure according to claim 2, characterized in that: The third conductive pillar is aligned with the first conductive pillar and is offset from the second conductive pillar and the conductive structure.

4. The substrate structure according to claim 2, characterized in that: The conductive structure, the first conductive column, the second conductive column and the third conductive column are adjacent to the board edge of the substrate structure.

5. The substrate structure according to claim 1, characterized in that: The core layer has a first surface and a second surface opposite to each other, and the first build-up layer structure is formed on the first surface and the second surface.

6. A method for manufacturing a substrate structure, comprising: providing a core layer having a plurality of conductive structures; forming a first build-up layer structure on the core layer, wherein the first build-up layer structure has a first dielectric layer and a plurality of first conductive pillars formed in the first dielectric layer; and forming a second build-up layer structure on the first build-up layer structure, wherein the second build-up layer structure has a second dielectric layer and a plurality of second conductive pillars formed in the second dielectric layer; The first conductive column and the conductive structure are misaligned with each other, and the second conductive column is aligned with the conductive structure and is misaligned with the first conductive column.

7. The method for manufacturing a substrate structure according to claim 6, wherein: The manufacturing method further includes forming a third build-up layer structure on the second build-up layer structure, wherein the third build-up layer structure has a third dielectric layer and a plurality of third conductive pillars formed in the third dielectric layer.

8. The method for manufacturing a substrate structure according to claim 7, wherein: The third conductive pillar is aligned with the first conductive pillar and is offset from the second conductive pillar and the conductive structure.

9. The method for manufacturing a substrate structure according to claim 7, wherein: The conductive structure, the first conductive column, the second conductive column and the third conductive column are adjacent to the board edge of the substrate structure.

10. The method for manufacturing a substrate structure according to claim 6, wherein: The core layer has a first surface and a second surface opposite to each other, and the first build-up layer structure is formed on the first surface and the second surface.

Images