SiC mosfet double protection circuit based on di / dt detection

Abstract

The application discloses a SiC MOSFET double protection circuit based on d i / dt detection, which comprises a current sampling module, input ends of the current sampling module are connected with two ends of a parasitic inductor L Ss , an auxiliary source of a SiC MOSFET is grounded, output ends of the current sampling module are connected with input ends of a short-circuit fault judging module and an overload fault judging module respectively, output ends of the short-circuit fault judging module and the overload fault judging module are connected with an input end of a fault signal latching module, an output end of the fault signal latching module is connected with an input end of an output stage and a soft turn-off module, and an output end of the output stage and the soft turn-off module is connected with a gate of the SiC MOSFET. i The SiC MOSFET double protection circuit based on d / dt detection can realize reliable protection of hard switching faults, load short-circuit faults and overload faults of a device by using a single detection circuit, has a soft turn-off function, is more comprehensive and effective, improves the working life of the power device, and increases the reliability of a system.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of short-circuit protection, and relates to a SiC MOSFET double protection circuit based on d i / dt detection. BACKGROUND

[0002] Compared with traditional Si MOSFET and IGBT, wide bandgap power semiconductors such as SiC devices have high withstand voltage, low on-resistance, small parasitic parameters and other excellent characteristics due to their greater band gap and higher critical field strength. However, due to the characteristics of small chip area, large short-circuit current and concentrated heat position of SiC MOSFET, the short-circuit resistance time is shorter and the resistance capacity is weaker. The short-circuit resistance time of IGBT is generally 10 us, compared with traditional IGBT, the short-circuit resistance time of SiC MOSFET is generally only 3-4 us, and the action time of the driving chip is in the us level, which greatly improves the risk of reliable protection of SiC MOSFET, and it is very likely that the device cannot be reliably protected. On the other hand, the off resistance value of SiC MOSFET during normal operation will affect the off speed during short-circuit protection, and a single off resistance value cannot change the off speed, and the oscillation amplitude of the peak voltage during the off process is uncontrollable, which cannot reliably protect the device. Therefore, when designing the driving protection circuit, the response speed of the detection and protection circuit needs to be fast, so as to ensure that the SiC MOSFET works in a safe working area.

[0003] At present, the short-circuit protection of SiC MOSFET mostly directly learns from the short-circuit protection mode of Si IGBT. From the detection principle, the short-circuit protection detection technology for SiC MOSFET mainly includes the following: desaturation detection, d i / dt detection, shunt detection, gate voltage detection, current sensor detection and the like. In the prior art, only a single protection function can be achieved by using one detection mode, and reliable protection of hard switching failure, load short-circuit failure and overload failure of the device cannot be achieved at the same time while ensuring simple detection mode. SUMMARY

[0004] The application aims to provide a SiC MOSFET double protection circuit based on d iThe application discloses a double protection circuit for SiC MOSFET based on di / dt detection.

[0005] The application adopts the technical scheme of i The double protection circuit for SiC MOSFET based on di / dt detection comprises a current sampling module, input ends of the current sampling module are connected with two ends of a parasitic inductor L Ss , two ends of the parasitic inductor L Ss are connected with a power source electrode and an auxiliary source electrode of SiC MOSFET respectively, the auxiliary source electrode of SiC MOSFET is grounded, output ends of the current sampling module are connected with input ends of a short-circuit fault judging module and an overload fault judging module respectively, output ends of the short-circuit fault judging module and the overload fault judging module are connected with an input end of a fault signal latching module, an output end of the fault signal latching module is connected with an input end of an output stage and a soft turn-off module, and an output end of the output stage and the soft turn-off module is connected with a gate electrode of SiC MOSFET.

[0006] The application also has the characteristics of:

[0007] The current sampling module comprises a current detection circuit and a reset circuit.

[0008] The current detection circuit comprises a capacitor C s , one end of the capacitor C s is connected with the auxiliary source electrode of SiC MOSFET and one end of the parasitic inductor L Ss , and the other end of the capacitor C s is connected with a source electrode of an NMOS tube M1, one end of a resistor R s , an input end of the short-circuit fault judging module and an input end of the overload fault judging module.

[0009] The other end of the resistor R s is connected with an anode of a diode D iode and one end of a resistor R g ; the other end of the resistor R g is connected with a cathode of the diode D iode , one end of the parasitic inductor L Ss which is not connected with the capacitor C s , and the power source electrode of SiC MOSFET.

[0010] The reset circuit comprises a comparator A1, a positive input end of the comparator A1 is connected with a reference voltage V th1 , and a negative input end of the comparator A1 is connected with an input signal V INThe output end of the comparator A1 is connected with one end of the capacitor C0, the other end of the capacitor C0 is connected with the gate of the NMOS transistor M1 and one end of the resistor R0, the other end of the resistor R0 is grounded; the drain of the NMOS transistor M1 is connected with the auxiliary source of the SiC MOSFET, the source of the NMOS transistor M1 is connected with one end of the resistor R s The other end of the resistor R s The input end of the short-circuit fault judgment module and the input end of the overload fault judgment module are connected.

[0011] The short-circuit fault judgment module comprises a comparator A2, the positive input end of the comparator A2 is connected with one end of the capacitor C s The source of the NMOS transistor M1 and the resistor R s The input end of the overload fault judgment module is connected, the negative input end of the comparator A2 is connected with the reference voltage V th2 The output end of the comparator A2 is connected with the input end of the fault signal latch module.

[0012] The overload fault judgment module comprises a comparator A3, the positive input end of the comparator A3 is connected with one end of the capacitor C s The source of the NMOS transistor M1 and the resistor R s The input end of the short-circuit fault judgment module is connected, the negative input end of the comparator A3 is connected with the reference voltage V th3 The output end of the comparator A3 is connected with the D end of the first flip-flop D1, the Q end of the first flip-flop D1 is connected with the D end of the second flip-flop D2, the Q end of the second flip-flop D2 is connected with the D end of the third flip-flop D3, the Q end of the third flip-flop D3 is connected with the three-input AND gate, the output end of the three-input AND gate is connected with the input end of the fault signal latch module.

[0013] The input ends of the three-input AND gate are respectively connected with the Q end of the first flip-flop D1, the Q end of the second flip-flop D2 and the Q end of the third flip-flop D3; the Clk end of the first flip-flop D1, the Clk end of the second flip-flop D2 and the Clk end of the third flip-flop D3 are connected with the input signal V IN The input signal V

[0014] The output end of the first flip-flop D1 The output end of the second flip-flop D2 The output end of the third flip-flop D3 The output end of the inverter INV is connected with the input signal V IN The RST end of the first flip-flop D1, the RST end of the second flip-flop D2 and the RST end of the third flip-flop D3 are connected with the reset signal V RST The reset signal V

[0015] The fault signal latching module comprises an OR gate, input ends of the OR gate are connected with an output end of the comparator A2 and an output end of the three-input AND gate respectively, and an output end of the OR gate is connected with a D end of a latch D4, a Q end of the latch D4 is connected with an input end of the output stage and the soft turn-off module.

[0016] The application has the advantages that: the application can detect different types of short-circuit faults, i.e., hard switching faults and load short-circuit faults, and can simultaneously detect overload faults by using a single detection circuit, and has a soft turn-off function, so that the driving protection circuit is more comprehensive and effective, thereby improving the working life of the power device and increasing the reliability of the system; the application can realize two protection mechanisms, i.e., fast and reliable protection for different types of short-circuit faults and overload faults, and can provide a gate drive chip for SiC MOSFET; the application solves the problem in the prior art that a single protection function can be realized by using a single detection method, and reliable protection for hard switching faults, load short-circuit faults and overload faults of the device cannot be realized while ensuring that the detection method is simple. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 The application is based on d i / dt detection of SiC MOSFET double protection circuit structure diagram;

[0018] Figure 2 The application is based on d i / dt detection of SiC MOSFET double protection circuit structure diagram;

[0019] Figure 3 The application is based on d i / dt detection of SiC MOSFET double protection circuit structure diagram of current sampling module.

[0020] In the figure, 1, current sampling module; 110, current detection circuit; 120, reset circuit; 2, short-circuit fault judgment module; 3, overload fault judgment module; 4, fault signal latching module; 5, output stage and soft turn-off module. DETAILED DESCRIPTION

[0021] The application will be described in detail below in combination with the drawings and specific embodiments.

[0022] Embodiment 1

[0023] The application is based on d i / dt detection of SiC MOSFET double protection circuit, comprising a current sampling module 1, input ends of the current sampling module 1 are connected with two ends of a parasitic inductance L Ss Ss ​The two ends of the current sampling module 1 are connected to the power source and auxiliary source of the SiC MOSFET, respectively. The auxiliary source of the SiC MOSFET is grounded. The output of the current sampling module 1 is connected to the input of the short-circuit fault judgment module 2 and the input of the overload fault judgment module 3, respectively. The output of the short-circuit fault judgment module 2 and the output of the overload fault judgment module 3 are connected to the input of the fault signal latch module 4. The output of the fault signal latch module 4 is connected to the input of the output stage and soft turn-off module 5. The output of the output stage and soft turn-off module 5 is connected to the gate of the SiC MOSFET.

[0024] Example 2

[0025] This embodiment proposes a method based on d i The SiC MOSFET dual protection circuit for / dt detection includes a current sampling module 1, whose input terminals are respectively connected to the parasitic inductance L. Ss The two ends are connected, and the parasitic inductance L Ss The two ends of the current sampling module 1 are connected to the power source and auxiliary source of the SiC MOSFET, respectively. The auxiliary source of the SiC MOSFET is grounded. The output of the current sampling module 1 is connected to the input of the short-circuit fault judgment module 2 and the input of the overload fault judgment module 3, respectively. The output of the short-circuit fault judgment module 2 and the output of the overload fault judgment module 3 are connected to the input of the fault signal latch module 4. The output of the fault signal latch module 4 is connected to the input of the output stage and soft turn-off module 5. The output of the output stage and soft turn-off module 5 is connected to the gate of the SiC MOSFET.

[0026] The current sampling module 1 includes a current detection circuit 110 and a reset circuit 120; the current detection circuit 110 includes a capacitor C. s Capacitor C s One end is connected to the auxiliary source of the SiC MOSFET and the parasitic inductance L. Ss One end is connected, capacitor C s The other end is connected to the source of NMOS transistor M1 and resistor R. s One end is connected to the input terminal of the short-circuit fault judgment module 2 and the input terminal of the overload fault judgment module 3; resistor R s The other end is connected to diode D iode anode, resistance R g One end is connected; resistor R g The other end is connected to diode D iode Cathode, parasitic inductance L Ss Unconnected capacitor C s One end is connected to the SiC MOSFET power source.

[0027] Example 3

[0028] The embodiment proposes a SiC MOSFET double protection circuit based on d i / dt detection, which comprises a current sampling module 1, input ends of the current sampling module 1 are connected with both ends of a parasitic inductance L Ss , both ends of the parasitic inductance L Ss are connected with a power source electrode and an auxiliary source electrode of a SiC MOSFET respectively, the auxiliary source electrode of the SiC MOSFET is grounded, output ends of the current sampling module 1 are connected with input ends of a short-circuit fault judgment module 2 and an overload fault judgment module 3 respectively, output ends of the short-circuit fault judgment module 2 and the overload fault judgment module 3 are connected with an input end of a fault signal latch module 4, an output end of the fault signal latch module 4 is connected with an input end of an output stage and soft turn-off module 5, and an output end of the output stage and soft turn-off module 5 is connected with a gate electrode of the SiC MOSFET.

[0029] The current sampling module 1 comprises a current detection circuit 110 and a reset circuit 120; the current detection circuit 110 comprises a capacitor C s , one end of the capacitor C s is connected with the auxiliary source electrode of the SiC MOSFET and one end of the parasitic inductance L Ss , the other end of the capacitor C s is connected with a source electrode of an NMOS tube M1, one end of a resistor R s , an input end of the short-circuit fault judgment module 2 and an input end of the overload fault judgment module 3; the other end of the resistor R s is connected with an anode of a diode D iode and one end of a resistor R g ; the other end of the resistor R g is connected with a cathode of the diode D iode , one end of the parasitic inductance L Ss which is not connected with the capacitor C s , and the power source electrode of the SiC MOSFET. The reset circuit 120 comprises a comparator A1, a positive input end of the comparator A1 is connected with a reference voltage V th1 , a negative input end of the comparator A1 is connected with an input signal V IN , an output end of the comparator A1 is connected with one end of a capacitor C0, the other end of the capacitor C0 is connected with a gate electrode of the NMOS tube M1 and one end of a resistor R0, the other end of the resistor R0 is grounded; a drain electrode of the NMOS tube M1 is connected with the auxiliary source electrode of the SiC MOSFET, a source electrode of the NMOS tube M1 is connected with one end of the capacitor C s , one end of the resistor R s , the input end of the short-circuit fault judgment module 2 and the input end of the overload fault judgment module 3.

[0030] Embodiment 4

[0031] The embodiment proposes a SiC MOSFET double protection circuit based on di The SiC MOSFET double protection circuit detected by / dt includes a current sampling module 1, the input ends of the current sampling module 1 are connected with the two ends of a parasitic inductance L Ss , the two ends of the parasitic inductance L Ss are connected with the power source and the auxiliary source of a SiC MOSFET respectively, the auxiliary source of the SiC MOSFET is grounded, the output ends of the current sampling module 1 are connected with the input ends of a short-circuit fault judgment module 2 and an overload fault judgment module 3 respectively, the output ends of the short-circuit fault judgment module 2 and the overload fault judgment module 3 are connected with the input end of a fault signal latch module 4, the output end of the fault signal latch module 4 is connected with the input end of an output stage and soft turn-off module 5, and the output end of the output stage and soft turn-off module 5 is connected with the gate of the SiC MOSFET.

[0032] The current sampling module 1 includes a current detection circuit 110 and a reset circuit 120; the current detection circuit 110 includes a capacitor C s , one end of the capacitor C s is connected with the auxiliary source of the SiC MOSFET and one end of the parasitic inductance L Ss , the other end of the capacitor C s is connected with the source of an NMOS tube M1, one end of a resistor R s , the input end of the short-circuit fault judgment module 2 and the input end of the overload fault judgment module 3; the other end of the resistor R s is connected with the anode of a diode D iode and one end of a resistor R g ; the other end of the resistor R g is connected with the cathode of the diode D iode , one end of the parasitic inductance L Ss which is not connected with the capacitor C s , and the power source of the SiC MOSFET. The reset circuit 120 includes a comparator A1, the positive input end of the comparator A1 is connected with a reference voltage V th1 , the negative input end of the comparator A1 is connected with an input signal V IN , one end of a capacitor C0 connected with the output end of the comparator A1, the other end of the capacitor C0 is connected with the gate of the NMOS tube M1 and one end of a resistor R0, the other end of the resistor R0 is grounded; the drain of the NMOS tube M1 is connected with the auxiliary source of the SiC MOSFET, the source of the NMOS tube M1 is connected with one end of the capacitor C s , one end of the resistor R s , the input end of the short-circuit fault judgment module 2 and the input end of the overload fault judgment module 3.

[0033] The short-circuit fault judgment module 2 includes a comparator A2, the positive input end of the comparator A2 is connected with the capacitor C sone end, source of NMOS transistor M1, one end of resistor R s one end, input end of overload fault judging module 3, negative input end of comparator A2 and reference voltage V are connected th2 connection; output end of comparator A2 and input end of fault signal latching module 4 are connected.

[0034] Example 5

[0035] This embodiment proposes a SiC MOSFET double protection circuit based on d i / dt detection, which comprises a current sampling module 1, two ends of parasitic inductance L Ss are connected to the input ends of the current sampling module 1, two ends of the parasitic inductance L Ss are connected to the power source and auxiliary source of the SiC MOSFET respectively, the auxiliary source of the SiC MOSFET is grounded, the output ends of the current sampling module 1 are connected to the input ends of the short-circuit fault judging module 2 and the input ends of the overload fault judging module 3, the output ends of the short-circuit fault judging module 2 and the output ends of the overload fault judging module 3 are connected to the input end of the fault signal latching module 4, the output end of the fault signal latching module 4 is connected to the input end of the output stage and soft turn-off module 5, and the output end of the output stage and soft turn-off module 5 is connected to the gate of the SiC MOSFET.

[0036] The current sampling module 1 comprises a current detection circuit 110 and a reset circuit 120; the current detection circuit 110 comprises a capacitor C s , one end of the capacitor C s is connected to the auxiliary source of the SiC MOSFET and one end of the parasitic inductance L Ss , the other end of the capacitor C s is connected to the source of the NMOS transistor M1 and one end of the resistor R s , the input ends of the short-circuit fault judging module 2 and the input ends of the overload fault judging module 3; the other end of the resistor R s is connected to the anode of the diode D iode and one end of the resistor R g ; the other end of the resistor R g is connected to the cathode of the diode D iode and the parasitic inductance L Ss , and the other end of the capacitor C s is connected to the power source of the SiC MOSFET. The reset circuit 120 comprises a comparator A1, the positive input end of the comparator A1 is connected to the reference voltage V th1 , and the negative input end of the comparator A1 is connected to the input signal V INThe comparator A1 output is connected to one end of capacitor C0, and the other end of capacitor C0 is connected to the gate of NMOS transistor M1 and one end of resistor R0. The other end of resistor R0 is grounded. The drain of NMOS transistor M1 is connected to the auxiliary source of the SiC MOSFET, and the source of NMOS transistor M1 is connected to capacitor C0. s One end, resistor R s One end is connected to the input end of the short-circuit fault judgment module 2 and the input end of the overload fault judgment module 3.

[0037] Short-circuit fault detection module 2 includes comparator A2, the positive input terminal of comparator A2 is connected to capacitor C s One end, the source of NMOS transistor M1, and resistor R s One end is connected to the input terminal of the overload fault judgment module 3, and the negative input terminal of comparator A2 is connected to the reference voltage V. th2 Connection; the output of comparator A2 is connected to the input of fault signal latch module 4.

[0038] Overload fault detection module 3 includes comparator A3, the positive input terminal of comparator A3 is connected to capacitor C s One end, the source of NMOS transistor M1, and resistor R s One end is connected to the input terminal of the short-circuit fault detection module 2, and the negative input terminal of comparator A3 is connected to the reference voltage V. th3 The comparator A3's output is connected to the D terminal of the first flip-flop D1. The Q terminal of the first flip-flop D1 is connected to the D terminal of the second flip-flop D2. The Q terminal of the second flip-flop D2 is connected to the D terminal of the third flip-flop D3. The Q terminal of the third flip-flop D3 is connected to a three-input AND gate. The output of the three-input AND gate is connected to the input of the fault signal latch module 4. The inputs of the three-input AND gate are connected to the Q terminals of the first flip-flop D1, the second flip-flop D2, and the third flip-flop D3, respectively. The Clk terminals of the first flip-flop D1, the second flip-flop D2, and the third flip-flop D3 are connected to the input signal V. IN Connection. The first flip-flop D1... Terminal, second flip-flop D2 Terminal, third flip-flop D3 The input terminal is connected to the output terminal of the inverter INV, and the input terminal of the inverter INV is connected to the input signal V. IN Connections: The RST terminals of the first flip-flop D1, the second flip-flop D2, and the third flip-flop D3 are connected to the reset signal V. RST connect.

[0039] Example 6

[0040] This embodiment proposes a method based on d iThe application discloses a double protection circuit for SiC MOSFET detected by / dt, which comprises a current sampling module 1, input ends of the current sampling module 1 are connected with two ends of a parasitic inductor L Ss , two ends of the parasitic inductor L Ss are connected with a power source electrode and an auxiliary source electrode of SiC MOSFET respectively, the auxiliary source electrode of SiC MOSFET is grounded, output ends of the current sampling module 1 are connected with input ends of a short-circuit fault judging module 2 and an overload fault judging module 3 respectively, output ends of the short-circuit fault judging module 2 and the overload fault judging module 3 are connected with an input end of a fault signal latching module 4, an output end of the fault signal latching module 4 is connected with an input end of an output stage and a soft turn-off module 5, and an output end of the output stage and the soft turn-off module 5 is connected with a gate electrode of SiC MOSFET.

[0041] The current sampling module 1 comprises a current detection circuit 110 and a reset circuit 120; the current detection circuit 110 comprises a capacitor C s , one end of the capacitor C s is connected with the auxiliary source electrode of SiC MOSFET and one end of the parasitic inductor L Ss , the other end of the capacitor C s is connected with a source electrode of an NMOS tube M1, one end of a resistor R s , an input end of the short-circuit fault judging module 2 and an input end of the overload fault judging module 3; the other end of the resistor R s is connected with an anode of a diode D iode and one end of a resistor R g ; the other end of the resistor R g is connected with a cathode of the diode D iode , one end of the parasitic inductor L Ss , which is not connected with the capacitor C s , and the power source electrode of SiC MOSFET; the reset circuit 120 comprises a comparator A1, a positive input end of the comparator A1 is connected with a reference voltage V th1 , a negative input end of the comparator A1 is connected with an input signal V IN , an output end of the comparator A1 is connected with one end of a capacitor C0, the other end of the capacitor C0 is connected with a gate electrode of the NMOS tube M1 and one end of a resistor R0, the other end of the resistor R0 is grounded; a drain electrode of the NMOS tube M1 is connected with the auxiliary source electrode of SiC MOSFET, a source electrode of the NMOS tube M1 is connected with one end of the capacitor C s , one end of the resistor R s , the input end of the short-circuit fault judging module 2 and the input end of the overload fault judging module 3.

[0042] The short-circuit fault judging module 2 comprises a comparator A2, a positive input end of the comparator A2 is connected with one end of the capacitor C s , the source electrode of the NMOS tube M1 and the resistor Rs One end, the input end of the overload fault judgment module 3 is connected, the negative input end of the comparator A2 is connected with the reference voltage V th2 The output end of the comparator A2 is connected with the input end of the fault signal latching module 4.

[0043] The overload fault judgment module 3 includes the comparator A3, the positive input end of the comparator A3 is connected with the capacitor C s One end, the source of the NMOS tube M1, the resistance R s One end, the input end of the short-circuit fault judgment module 2 is connected, the negative input end of the comparator A3 is connected with the reference voltage V th3 The output end of the comparator A3 is connected with the D end of the first flip-flop D1, the Q end of the first flip-flop D1 is connected with the D end of the second flip-flop D2, the Q end of the second flip-flop D2 is connected with the D end of the third flip-flop D3, the Q end of the third flip-flop D3 is connected with the three-input AND gate, the output end of the three-input AND gate is connected with the input end of the fault signal latching module 4. The input end of the three-input AND gate is connected with the Q end of the first flip-flop D1, the Q end of the second flip-flop D2 and the Q end of the third flip-flop D3 respectively; the Clk end of the first flip-flop D1, the Clk end of the second flip-flop D2 and the Clk end of the third flip-flop D3 are connected with the input signal V IN The output end of the comparator A2 is connected with the input end of the fault signal latching module 4. The output end of the comparator A2 is connected with the input end of the fault signal latching module 4. The output end of the comparator A2 is connected with the input end of the fault signal latching module 4. The output end of the comparator A2 is connected with the input end of the fault signal latching module 4. IN The RST end of the first flip-flop D1, the RST end of the second flip-flop D2 and the RST end of the third flip-flop D3 are connected with the reset signal V RST The RST end of the first flip-flop D1, the RST end of the second flip-flop D2 and the RST end of the third flip-flop D3 are connected with the reset signal V

[0044] The fault signal latching module 4 includes the OR gate OR, the input end of the OR gate OR is connected with the output end of the comparator A2 and the output end of the three-input AND gate respectively, the output end of the OR gate OR is connected with the D end of the latch D4, the Q end of the latch D4 is connected with the input end of the output stage and soft shutdown module 5.

[0045] The present application is based on d i / dt detection SiC MOSFET double protection circuit, such as Figure 1As shown, including current sampling module 1, short circuit fault judgment module 2, overload fault judgment module 3, fault signal latch module 4, output stage and soft turn-off module 5, the output stage and soft turn-off module 5 is connected with the gate G of SiC MOSFET, the power source S of SiC MOSFET is connected with current sampling module 1, the auxiliary source s of SiC MOSFET is grounded, and the power source S and the auxiliary source s of SiC MOSFET are connected with the parasitic inductance L in current sampling module 1 Ss ;

[0046] Current sampling module 1 includes current detection circuit 110 and reset circuit 120, current detection circuit 110 is used for sampling current signal, and the induced voltage on the parasitic inductance of SiC MOSFET is converted into current for short circuit protection and overload protection, and reset circuit 120 can ensure that the detection voltage V test Changes from zero when SiC MOSFET is turned on, wherein the NMOS transistor M1 has sufficient current capacity, thereby ensuring the normal triggering of short circuit protection and overload protection functions;

[0047] Short circuit fault judgment module 2 is used for judging whether SiC MOSFET occurs hard switching fault or load short circuit fault, so as to judge whether short circuit fault signal is generated; overload fault judgment module 3 is used for judging whether SiC MOSFET occurs overload fault, so as to judge whether overload fault signal is generated; fault signal latch module 4 is used for receiving short circuit fault and overload fault signal, and once receiving fault signal, the module will trigger signal latch, regardless of which fault signal, to ensure that the fault signal is accurately input to output stage and soft turn-off module 5; output stage and soft turn-off module 5 is used for controlling the turn-on and turn-off of SiC MOSFET, when receiving the fault signal of fault signal latch module 4, the drive signal becomes soft turn-off signal for making the power switch turn off, so as to reduce the overcurrent fault voltage peak and realize fast and reliable protection; otherwise, output stage and soft turn-off module 5 remains normal work.

[0048] As shown in Figure 2 , current sampling module 1 includes parasitic inductance L Ss , resistance R0, resistance R g , resistance R s , capacitor C0, capacitor C s , diode D iode , NMOS tube M1 and comparator A1, one end of capacitor C s is connected with one end of parasitic inductance L Ss , auxiliary source s of SiC MOSFET and drain of NMOS tube M1, and the other end of capacitor C s is connected with resistance R sOne end of the capacitor is connected to the source of NMOS transistor M1, the positive input of comparator A2, and the positive input of comparator A3, and capacitor C is connected to the source of NMOS transistor M1, the positive input of comparator A2, and the positive input of comparator A3. s A resistor R is connected s One end of the current sampling module 1 is the source of NMOS transistor M1, the positive input of comparator A2, and the positive input of comparator A3. test resistance R s The other end is connected to a diode D. iode anode and resistance R g One end, resistor R g The other end is connected to a diode D. iode Cathode, parasitic inductance L Ss The other end of the capacitor is connected to the power source S of the SiC MOSFET. The gate of the NMOS transistor M1 is connected to one end of the capacitor C0 and one end of the resistor R0. The other end of the resistor R0 is grounded. The other end of the capacitor C0 is connected to the output of comparator A1. The positive input of comparator A1 is connected to the reference voltage V. th1 The negative input terminal is connected to the input signal V. IN .

[0049] The short-circuit fault detection module 2 includes a comparator A2. The positive input terminal of the comparator A2 is the input terminal of the short-circuit fault detection module 2, and it is connected to the output terminal V of the current sampling module 1. test The positive input terminal of comparator A3 and the negative input terminal of comparator A2 are connected to a reference voltage V. th2 The output V of comparator A2 Fault_SC This is a short-circuit fault signal.

[0050] The overload fault detection module 3 includes a comparator A3, a first flip-flop D1, a second flip-flop D2, a third flip-flop D3, an inverter INV, and a three-input AND gate. The positive input terminal of comparator A3, which is also the input terminal of the overload fault detection module 3, is connected to the output terminal V of the current sampling module 1. test The input terminal of the short-circuit fault detection module 2 and the negative input terminal of comparator A3 are connected to the reference voltage V. th3 The output V of comparator A3 fault_OL The D terminal of the first flip-flop D1 is connected to the D terminal of the first flip-flop D1. The Clk terminal of the first flip-flop D1 is connected to the Clk terminal of the second flip-flop D2, the Clk terminal of the third flip-flop D3, the input terminal of the inverter INV, and the input signal V. IN The first trigger D1 The terminal is connected to the second flip-flop D2. Terminal, third flip-flop D3 The output terminal of the inverter INV, the RST terminal of the first flip-flop D1 is connected to the RST terminal of the second flip-flop D2, the RST terminal of the third flip-flop D3, and the reset signal V. RST, the Q terminal of the first flip-flop D1 is connected with the D terminal of the second flip-flop D2 and the first input terminal Q1 of the three-input AND gate, the Q terminal of the second flip-flop D2 is connected with the D terminal of the third flip-flop D3 and the second input terminal Q2 of the three-input AND gate, the Q terminal of the third flip-flop D3 is connected with the third input terminal Q3 of the three-input AND gate, and the output terminal V Fault_OL is connected with the input terminal of the fault signal latching module 4.

[0051] The fault signal latching module 4 comprises an OR gate D4 and a latch D4, the input terminal of the OR gate is connected with the output terminal V Fault_SC of the short-circuit fault judging module 2, the other input terminal is connected with the output terminal V Fault_OL of the overload fault judging module 3, and the output terminal V Fault of the OR gate is connected with the D terminal of the latch D4, the Q terminal of the latch D4 is connected with the output stage and soft turn-off module 5. The output stage and soft turn-off module 5 is connected with the gate G of the SiC MOSFET.

[0052] As shown in Figure 3 , the current sampling module 1 is composed of a current detection circuit 110 and a reset circuit 120, the current detection circuit 110 comprises a parasitic inductor L Ss , a capacitor C s , a resistor R s , a resistor R g , a diode D iode , one end of the capacitor C s is connected with one end of the parasitic inductor L Ss , the auxiliary source s of the SiC MOSFET and the drain of the NMOS tube M1, the other end of the capacitor C s is connected with one end of the resistor R s , the source of the NMOS tube M1, the input terminal of the short-circuit fault judging module 2 and the input terminal of the overload fault judging module 3; the other end of the resistor R s is connected with the anode of the diode D iode and one end of the resistor R g , and the other end of the resistor R g is connected with the cathode of the diode D iode , the other end of the parasitic inductor L Ss and the power source S of the SiC MOSFET; the reset circuit 120 comprises a comparator A1, a capacitor C0, a resistor R0 and a NMOS tube M1, the drain of the NMOS tube M1 is connected with the auxiliary source of the SiC MOSFET, one end of the parasitic inductor L Ss and one end of the capacitor C s , the source of the NMOS tube M1 is connected with one end of the capacitor C s , the resistor R sOne end of the NMOS transistor M1 is connected to the input terminal of the short-circuit fault judgment module 2 and the input terminal of the overload fault judgment module 3. The gate of the NMOS transistor M1 is connected to one end of the capacitor C0 and one end of the resistor R0. The other end of the resistor R0 is grounded. The other end of the capacitor C0 is connected to the output terminal of the comparator A1. The positive input terminal of the comparator A1 is connected to the reference voltage V. th1 The negative input terminal is connected to the input signal V. IN A parasitic inductance L is connected between the power source S and the auxiliary source S of a SiC MOSFET. Ss The auxiliary source s of the SiC MOSFET is grounded.

[0053] In this invention, the current detection circuit 110 controls the parasitic inductance L between the power source S and the auxiliary source S. Ss By integrating the induced voltage on the circuit, the measured d during the overcurrent fault can be obtained. I D / dt recovers to a rapidly rising current I D The actual measured value is the fault current level. If most of the short-circuit circuit frequency components are higher than the filter's cutoff frequency f... c The current flowing through the SiCMOSFETT will be sampled by the capacitor C. s The voltage signal on it is captured proportionally, thereby generating a signal proportional to the current I. D Proportional detection voltage V test The function of a diode is to utilize its unidirectional conductivity to avoid the sampling capacitance C caused by the uncertainty of the timing of a load short-circuit fault. s The discharge phenomenon enhances the accuracy of the detection circuit and improves system efficiency. The reset circuit 120 ensures the detection voltage V... test The current changes from zero when the SiC MOSFET is turned on, and the NMOS transistor M1 has sufficient current capability to ensure proper triggering of short-circuit protection and overload protection functions.

[0054] Overcurrent fault detection signal V test The input signal is sent to the short-circuit fault detection module 2 as the input signal for this module, and the detected voltage V is converted by comparator A2. test With short-circuit fault reference voltage V th2 Compare, if V test Greater than V th2 This indicates that a short circuit fault has occurred in the system, and a high-level short circuit fault signal V is output. Fault_SC .

[0055] Similarly, the overcurrent fault detection signal V test The input signal is given to the overload fault judgment module 3 as one of the input signals of the module, and the detected voltage V is converted by comparator A3. test With overload fault reference voltage Vth3 Comparing, if V test is greater than V th3 , output high level overload judgment signal V fault_OL . Under the action of the rising edge of the input voltage VIN, namely the rising edge of the CIK signal, the overload judgment signal V fault_OL is transmitted to the output end Q of the first flip-flop D1, denoted as Q1; the output voltage of the first flip-flop D1 is transmitted to the output end Q of the second flip-flop D2 through the second flip-flop D2, denoted as Q2; the output voltage of the second flip-flop D2 is transmitted to the output end Q of the third flip-flop D3 through the third flip-flop D3, denoted as Q3, and the output voltages of the first flip-flop D1, the second flip-flop D2 and the third flip-flop D3 serve as three input ends of a three-input AND gate. The process is to accumulate the overload judgment signal, namely, in the case that the overload judgment signal V fault_OL is high in the three consecutive on periods of the SiC MOSFET, the output voltages of the first flip-flop D1, the second flip-flop D2 and the third flip-flop D3 are all high, so that the output voltage of the three-input AND gate, namely the overload fault signal V Fault_OL , changes from low to high, at which time it is determined that the system has an overload fault, triggering the overload protection function. The reset signal V RST can ignore the high and low levels of the CLK signal, initialize the output of the D flip-flop, and make the output voltage Q low. The overload fault judgment module 3 uses three D flip-flops to detect three consecutive overload faults of the SiC MOSFET, so as to avoid the false triggering of the overload protection and increase the flexibility of the response speed of the overload fault detection.

[0056] The short-circuit fault signal V Fault_SC and the overload fault signal V Fault_OL are input into the fault signal latching module 4 as two input signals of the module, and the two fault signals are subjected to OR logic operation to finally output the total fault signal V Fault . That is, no matter whether a short-circuit fault or an overload fault occurs, the OR gate can trigger the total fault signal V Fault , and then transmit the signal to the latch D4 for fault signal latching, so as to ensure that the fault signal is accurately input into the output stage and soft turn-off module 5.

[0057] When the output stage and soft turn-off module 5 receives the fault signal of the fault signal latching module 4, the module makes the drive signal become a soft turn-off signal for turning off the power switch through logic control, so as to reduce the overcurrent fault voltage spike and realize fast and reliable protection. If no short-circuit fault or overload fault occurs, the output stage and soft turn-off module 5 remains normal working, that is, outputting the drive signal in the normal working state.

Claims

1. Based on d i A SiC MOSFET double protection circuit detected by / dt, characterized by, The current sampling module (1) is connected with the two ends of the parasitic inductance L Ss respectively, the two ends of the parasitic inductance L Ss are connected with the power source and the auxiliary source of the SiC MOSFET respectively, the auxiliary source of the SiC MOSFET is grounded, the output end of the current sampling module (1) is connected with the input end of the short-circuit fault judgment module (2) and the input end of the overload fault judgment module (3) respectively, the output end of the short-circuit fault judgment module (2) and the output end of the overload fault judgment module (3) are connected with the input end of the fault signal latch module (4), the output end of the fault signal latch module (4) is connected with the input end of the output stage and soft turn-off module (5), and the output end of the output stage and soft turn-off module (5) is connected with the gate of the SiC MOSFET. The current sampling module (1) comprises a current detection circuit (110) and a reset circuit (120); The current detection circuit (110) comprises a capacitor C s , one end of the capacitor C s is connected with an auxiliary source of the SiC MOSFET, and a parasitic inductor L Ss , the other end of the capacitor C s is connected with a source of an NMOS tube M1, one end of a resistor R s , an input end of a short-circuit fault judgment module (2), and an input end of an overload fault judgment module (3). The resistance R s The other end is connected with the anode of the diode D iode , the resistance R g One end is connected; the resistance R g The other end is connected with the cathode of the diode D iode , the end of the parasitic inductance L Ss Not connected with the capacitor C s One end, SiC MOSFET power source is connected; The reset circuit (120) comprises a comparator A1, a positive input terminal of the comparator A1 is connected with a reference voltage V th1 , a negative input terminal of the comparator A1 is connected with an input signal V IN , an output terminal of the comparator A1 is connected with one end of a capacitor C0, the other end of the capacitor C0 is connected with a gate of an NMOS transistor M1 and one end of a resistor R0, the other end of the resistor R0 is grounded; a drain of the NMOS transistor M1 is connected with an auxiliary source of a SiC MOSFET, a source of the NMOS transistor M1 is connected with one end of a capacitor C s , the other end of the capacitor C s , an input terminal of a short-circuit fault judging module (2) and an input terminal of an overload fault judging module (3) are connected. The short-circuit fault judging module (2) comprises a comparator A2, a positive input end of the comparator A2 is connected with the capacitor C s One end, source of NMOS transistor M1, resistance R s One end, input end of the overload fault judging module (3) is connected, a negative input end of the comparator A2 is connected with a reference voltage V th2 Connection; an output end of the comparator A2 is connected with an input end of the fault signal latching module (4); The overload fault judging module (3) comprises a comparator A3, a positive input end of the comparator A3 is connected with the capacitor C s One end, the source of the NMOS transistor M1, the resistance R s One end, the input end of the short circuit fault judging module (2) is connected, a negative input end of the comparator A3 is connected with the reference voltage V th3 The output end of the comparator A3 is connected with the D end of the first flip-flop D1, the Q end of the first flip-flop D1 is connected with the D end of the second flip-flop D2, the Q end of the second flip-flop D2 is connected with the D end of the third flip-flop D3, the Q end of the third flip-flop D3 is connected with a three-input AND gate, the output end of the three-input AND gate is connected with the input end of the fault signal latching module (4); The input end of the three-input AND gate is connected with the Q end of the first flip-flop D1, the Q end of the second flip-flop D2 and the Q end of the third flip-flop D3 respectively; the Clk end of the first flip-flop D1, the Clk end of the second flip-flop D2 and the Clk end of the third flip-flop D3 are connected with the input signal V IN in. The output end of the first flip-flop D1 is connected with the input end of the second flip-flop D2, and the output end of the second flip-flop D2 is connected with the input end of the third flip-flop D3. The output end of the third flip-flop D3 is connected with the input end of the inverter INV, and the output end of the inverter INV is connected with the input signal V The output end of the third flip-flop D3 is connected with the input end of the inverter INV, and the output end of the inverter INV is connected with the input signal V The output end of the third flip-flop D3 is connected with the input end of the inverter INV, and the output end of the inverter INV is connected with the input signal V IN The RST end of the first flip-flop D1, the RST end of the second flip-flop D2 and the RST end of the third flip-flop D3 are connected with the reset signal V RST The RST end of the first flip-flop 2. The d i A SiC MOSFET double protection circuit detected by / dt, characterized by, The fault signal latch module (4) comprises an OR gate, input ends of the OR gate are connected with an output end of the comparator A2 and an output end of the three-input AND gate respectively, an output end of the OR gate is connected with a D end of a latch D4, and a Q end of the latch D4 is connected with an input end of the output stage and the soft shutdown module (5).

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