An inverter and its drive device

Abstract

The present application provides an inverter and its driving device. The driving device includes a driving signal generation module configured to generate a first driving signal; an isolation sampling module configured to sample the first driving signal to obtain an ideal driving signal; a driving current amplification circuit module, the driving current amplification circuit module is configured with a common reference ground with the isolation sampling module, and the driving current amplification circuit module is configured to receive the first driving signal and generate a driving reference signal based on the first driving signal; a comparison isolation compensation circuit module configured to compare and compensate the ideal driving signal and the driving reference signal to obtain a second driving signal, and the inverter is driven based on the second driving signal. The driving device provided by the present application can alleviate the problem that the narrow pulse wave generation signal near the PWM passing through the zero-sequence point is prone to distortion.

Description

Technical Field

[0001] This application relates to the technical field of inverter control, and particularly to an inverter and its driving device. Background Art

[0002] In an NPC three-level inverter, the driving signals generated through the action of DSP (Digital Signal Processing) and CPLD (Complex Programmable Logic Device) are transmitted to a three-phase IGBT driving board. The three-phase driving board performs level processing and power amplification on the CPLD driving signals and then drives the IGBT module. In the three-phase driving board, due to the delay characteristics of electronic devices such as resistors and capacitors and the problem of stray inductance characteristics in the circuit, the narrow pulse wave signals near the zero crossing point of PWM often generate distortion. After the distorted PWM signal is used as the Vge voltage signal for driving the IGBT gate, an instantaneous pulse spike is generated in the Vce voltage when the IGBT collector turns off, posing a potential damage risk to the IGBT driving tube. At the same time, it also causes uneven voltage stress and switching losses among different driving tubes in the IGBT module. However, in the prior art, most of them achieve the effect of correcting the CPLD-generated PWM signal by correcting the triangular carrier signal, ignoring the influence of the driving circuit board on the PWM signal. Because the PWM signal sent from the CPLD can only be used as the Vge voltage signal for driving the IGBT gate after passing through the current amplification circuit in the driving circuit board. Therefore, after correcting the triangular carrier signal in the prior art, there is still a possibility of distortion in the Vge voltage signal for driving the IGBT gate in the actual hardware circuit finally. And such correction methods have complex calculation time and long periods, with slow hardware response speeds.

[0003] In addition, for the method described in the patent CN116885931A: calculating the modulation wave range to avoid narrow pulses, and obtaining the modulation wave by adding the zero-sequence voltage after judging the difference between the upper capacitor voltage and the lower capacitor voltage. However, there will be a difference between the calculated modulation wave range to avoid narrow pulses and the modulation wave range actually generating narrow pulses in the circuit. Therefore, there will be a deviation between the numerical range obtained by calculation and the numerical range generated by the actual circuit. Secondly, judging the difference between the upper capacitor voltage and the lower capacitor voltage as the modulation wave obtained by adding the zero-sequence voltage later will also have a certain deviation. This cannot ensure that the first narrow pulse generated in the actual circuit will not be distorted, and thus cannot ensure that the Vge square wave for driving the IGBT generated by the first narrow pulse will not be distorted. Therefore, it also cannot ensure that the first Vce voltage stress generated by the IGBT drive is within the rated range of the IGBT tube.

[0004] The method described in the CN105450068A patent: In the method of suppressing PWM narrow pulses by sampling the peak point of the output voltage and selecting corresponding strategies, when the output voltage has already reached the peak point, the IGBT gate drive may have been affected by the first narrow pulse. This method cannot guarantee that the circuit does not generate narrow pulses, but only reduces the number of narrow pulses generated. When the output passes through the zero crossing point, switching the three-level modulation to two-level modulation, such a modulation strategy has lost the characteristic of less harmonic content of the three-level modulation and brings back the problem of large harmonic content of the two-level modulation. Summary of the Invention

[0005] The purpose of the present application is to provide a technical solution to alleviate the problem in the related art that the narrow pulse wave signal near the zero crossing point of PWM is distorted, posing a potential damage risk to the driving tube.

[0006] Based on the above purpose, the present application provides a driving device for an inverter, which is applied to a three-level inverter. The driving device includes:

[0007] A driving signal generation module configured to generate a first driving signal;

[0008] An isolation sampling module configured to sample the first driving signal to obtain an ideal driving signal;

[0009] A driving current amplification circuit module. The driving current amplification circuit module is configured with a common reference ground with the isolation sampling module. The driving current amplification circuit module is configured to receive the first driving signal and generate a driving reference signal based on the first driving signal;

[0010] A comparison isolation compensation circuit module configured to compare and compensate the ideal driving signal and the driving reference signal to obtain a second driving signal, and the inverter is driven based on the second driving signal.

[0011] According to the above description, the driving device provided by the present application is provided with a sampling circuit module and a driving current amplification circuit module configured with a common reference ground, and a comparison isolation compensation circuit module is provided to compare and compensate between the driving reference signal and the ideal driving signal, so as to correct the driving waveform to obtain a second driving signal and alleviate the problem that the narrow pulse wave signal near the zero crossing point of PWM is prone to distortion.

[0012] Further, a voltage dividing circuit, a first optocoupler, and a MOS transistor circuit, wherein,

[0013] The voltage dividing circuit receives the first driving signal, and the output terminal of the voltage dividing circuit is connected to the primary side of the first optocoupler. The first optocoupler is configured as a first optocoupler of the logic gate circuit output type. The secondary side output of the first optocoupler outputs an intermediate signal opposite to the first driving signal, and the intermediate signal is inverted through the MOS transistor circuit to obtain an ideal driving signal.

[0014] Further, the drive current amplification circuit module includes a second optocoupler and an amplification circuit, where

[0015] The primary input terminal of the second optocoupler receives the first drive signal. The secondary side of the second optocoupler is connected to the amplification circuit, and a drive reference signal is output through the amplification circuit. The secondary side of the second optocoupler and the secondary side of the first optocoupler are configured with a common reference ground.

[0016] Further, the drive signal generation module includes:

[0017] A PWM drive signal generation circuit configured to generate a PWM drive signal;

[0018] A level conversion circuit configured to convert the PWM drive signal into a drive voltage adapted to the drive tube of the inverter;

[0019] A logic gate circuit configured to invert the output timing of the level conversion circuit to obtain the first drive signal.

[0020] Further, the comparison isolation compensation circuit module includes:

[0021] A square wave signal memory configured to latch an ideal drive signal and a drive reference signal;

[0022] A square wave signal sampling extractor configured to sample and extract the maximum amplitude, the starting moment of the maximum amplitude, and the ending moment of the maximum amplitude of the ideal drive signal and / or the drive reference signal;

[0023] A maximum amplitude starting moment predictor configured to predict based on the sampled value of the starting moment of the maximum amplitude of the ideal drive signal to obtain a repaired prediction value of the starting moment of the rising edge, and the repaired prediction value of the starting moment of the rising edge is used to repair the rising edge of the drive reference signal;

[0024] A maximum amplitude ending moment predictor configured to predict based on the sampled value of the ending moment of the maximum amplitude of the ideal drive signal to obtain a repaired prediction value of the starting moment of the falling edge, and the repaired prediction value of the starting moment of the falling edge is used to repair the falling edge of the drive reference signal;

[0025] An amplitude comparator configured to compare the amplitude of the drive reference signal with the amplitude of the ideal drive signal;

[0026] An amplitude repairer configured to repair the amplitude of the drive reference signal after edge repair based on the comparison result of the amplitude comparator so that the amplitude of the repaired output signal is consistent with the amplitude of the ideal drive signal;

[0027] The comparison isolation compensation circuit module outputs a second drive signal, and the second drive signal is a square wave signal that has been repaired at the starting moments of the rising edge and falling edge and in terms of amplitude.

[0028] Further, the amplitude comparator includes a first operational amplifier and a second operational amplifier. Among them, the non-inverting input terminal of the first operational amplifier receives an ideal drive signal, the inverting input terminal receives a drive reference signal, and the output terminal of the first operational amplifier is connected to the inverting input terminal of the first operational amplifier through an RC parallel circuit;

[0029] The non-inverting input terminal of the second operational amplifier is connected to the output terminal of the first operational amplifier, the output terminal of the second operational amplifier is connected to the inverting input terminal of the second operational amplifier, and moreover, the output terminal of the second operational amplifier outputs a feedback signal through a resistor;

[0030] The amplitude restorer restores the amplitude of the drive reference signal after edge restoration based on the feedback signal.

[0031] Further, the driving device further includes a turn-on resistor and a turn-off resistor;

[0032] The second drive signal generates a drive tube drive signal through the turn-on resistor, and the drive tube drive signal is used to drive the turn-on of the inverter drive tube;

[0033] The second drive signal generates a drive tube drive signal through the turn-off resistor, and the drive tube drive signal is used to drive the turn-off of the inverter drive tube;

[0034] The comparison isolation compensation circuit module further includes:

[0035] A discharge time detection and restoration device, configured to receive the drive tube drive signal and adjust the discharge time of the corresponding drive tube in the inverter.

[0036] Further, the discharge time detection and restoration device includes:

[0037] A discharge time detection circuit, and the discharge time detection circuit includes: a zener diode, a diode, and an RC circuit. Among them, the drive tube drive signal passes through the zener diode, the diode, and the RC circuit in sequence, and a discharge duration feedback signal is output at the high potential end of the RC circuit.

[0038] Further, the discharge time detection and restoration device further includes:

[0039] A discharge time adjustment circuit, including:

[0040] A triode, the emitter of the triode is grounded, the base of the triode is grounded through a resistor, and moreover, a capacitor is arranged in parallel at both ends of the grounding resistor;

[0041] The first input terminal receives a driving signal for the driving transistor. Moreover, the first input terminal is electrically connected to the base of the triode through a resistor.

[0042] The second input terminal receives a discharge control signal. Moreover, the second input terminal is electrically connected to the base of the triode through a resistor and a diode, where the discharge control signal is generated based on a discharge duration feedback signal.

[0043] In a second aspect, the present application further provides an inverter, including an inversion unit and the driving device described in any one of the above. The driving device is used to drive the driving transistor in the inversion unit.

[0044] In this technical solution, since the inverter adopts the inverter driving device in any one of the above technical solutions, it has all the beneficial effects of the inverter driving device, which will not be elaborated here. Description of the Drawings

[0045] Figure 1 Schematic diagram of the NPC three-phase inverter current topology in the related art;

[0046] Figure 2 Schematic diagram of the driving device provided by an embodiment of the present application;

[0047] Figure 3 Schematic diagram of the PWM driving signal generation circuit provided by an embodiment of the present application;

[0048] Figure 4 Schematic diagram of the level conversion circuit provided by an embodiment of the present application;

[0049] Figure 5 Schematic diagram of the logic gate circuit provided by an embodiment of the present application;

[0050] Figure 6 Schematic diagram of the driving device provided by another embodiment of the present application;

[0051] Figure 7 Schematic diagram of the narrow pulse distortion waveform provided by an embodiment of the present application;

[0052] Figure 8 Schematic diagram of the isolation sampling module provided by an embodiment of the present application;

[0053] Figure 9 Schematic diagram of the comparison isolation compensation circuit module provided by an embodiment of the present application;

[0054] Figure 10 Schematic diagram of implementing the function of the comparison isolation compensation circuit module by using a DSP chip circuit and a CPLD chip circuit in an embodiment of the present application;

[0055] Figure 11Schematic diagram of the amplitude comparator provided by the embodiment of the present application;

[0056] Figure 12 Schematic diagram of the discharge time detection circuit provided by the embodiment of the present application;

[0057] Figure 13 Schematic diagram of the discharge time adjustment circuit provided by the embodiment of the present application. Detailed implementation manners

[0058] The present application will be described in detail below in combination with the specific implementation manners shown in the accompanying drawings. However, these implementation manners do not limit the present application. Structural, method, or functional transformations made by those of ordinary skill in the art based on these implementation manners are all included within the protection scope of the present application.

[0059] The purpose of the present application is to alleviate or solve the problem that the narrow pulse wave signal near the zero crossing point of PWM in a three-level inverter often causes distortion. After the distorted PWM signal is used as the driving signal of the driving tube, there is a hidden danger of damaging the driving tube. In practical applications, there are various forms of inverter driving tubes. The driving tube can be an IGBT, or a switching device such as SiC, or a switching module, and the switching module includes several switching devices. Regardless of the form of the driving tube, the inverter is driven based on the PWM control principle. Taking the IGBT as an example, after the distorted PWM signal is used as the Vge voltage signal for driving the gate of the IGBT, an instantaneous pulse peak is generated in the Vce voltage when the IGBT collector is turned off, which poses a hidden danger of damaging the IGBT driving tube. At the same time, it will also cause uneven voltage stress and switching losses of different driving tubes in the IGBT module. For the convenience of description, in the embodiment of the present application, the driving tube is taken as an IGBT for illustration.

[0060] Based on the above purpose, the present application provides a driving device for an inverter, which is applied to a three-level inverter. Exemplarily, in the embodiment of the present application, the driving device is described by taking the current topology structure of an NPC three-phase inverter as an example. As Figure 1 shown, the NPC three-phase inverter circuit topology includes three-phase circuits of phase A, phase B, and phase C. Each phase circuit includes an IGBT module, and each IGBT module includes 4 driving tubes (i.e., IGBTs). The driving device provided by the present application is used to drive the switching state change of each phase driving tube. Among them, the driving strategies of the driving device for each phase driving tube are similar. For the convenience of description, in the embodiment of the present application, the driving strategy of each driving tube in phase A is taken as an example for description. The driving tubes in the phase A bridge arm are respectively called the first to fourth driving tubes. Among them, the first driving tube TA1 and the fourth driving tube TA4 are outer tubes, and the second driving tube TA2 and the third driving tube TA3 are inner tubes.

[0061] As Figure 2As shown, as an optional implementation, the driving device includes a driving signal generating module, an isolation sampling module, a driving current amplifying circuit module and a comparison isolation compensation circuit module.

[0062] The drive signal generation module is configured to generate a first drive signal, which is used as the basis for the subsequent control of each drive tube. Exemplarily, the drive signal generation module may include a PWM drive signal generation circuit and a level conversion circuit, wherein the PWM drive signal generation circuit is configured to generate a PWM drive signal, and the level conversion circuit converts the PWM drive signal into a drive voltage adapted to the drive tube of the inverter.

[0063] like Figure 3 As shown in FIG. 1 , a method for implementing a drive signal generation module is shown. The PWM drive signal generation circuit includes an isolation sampling circuit, a DSP (Digital Signal Processing, digital signal processor) and a CPLD (Complex Programmable Logic Device, complex programmable logic device). Figure 3 As shown, the isolated sampling circuit is configured to collect the following electrical parameter information, which includes: DC side voltage Vdc, DC side current Idc, internal inductor currents Ia1, Ia2, Ia3, internal capacitor voltages Ua1, Ua2, Ua3, AC measured external inductor currents Iao1, Iao2, Iao3, AC side voltages Uao1, Uao2, Uao3. At least part of the above electrical parameter information enters the DSP for FOC calculation, and is compared with the carrier wave to form a PWM wave after the calculation and send it to the CPLD. The CPLD determines the opening and closing timing of the internal and external tubes and then sends a PWM drive signal. The PWM drive signal of each drive tube of phase A is recorded as DR_An_3.3V, n=1, 2, 3, 4.

[0064] As an optional implementation, Figure 4 As shown, the level conversion circuit can be implemented using transistor Q1 to convert Figure 3 The DR_An_3.3V level signal generated by the CPLD is converted into a 15V voltage signal that matches the driver tube, such as Figure 4 As shown, after the level conversion, the signal corresponding to each driving tube is recorded as DR_An_15V, n=1, 2, 3, 4.

[0065] As an optional implementation, the structures of the level conversion circuits corresponding to the various drive tubes are consistent, and only the level conversion circuit corresponding to the first drive tube in phase A is used as an example for description. Figure 4As shown in the figure, the level conversion circuit includes a triode Q1. The collector of the triode Q1 is sequentially connected to a 15V voltage source through a resistor R2 and a resistor R1. The base of the triode Q1 receives a PWM drive signal DR_A1_3.3V through a resistor R3. The emitter of the triode Q1 is grounded, and the emitter of the triode Q1 is connected to the base through a resistor R4.

[0066] As Figure 5 shown in the figure, further, the drive signal generation module further includes a logic gate circuit configured to invert the output timing of the level conversion circuit to obtain a first drive signal. Specifically, in the embodiment of the present application, a level conversion circuit is used to convert a 3.3V to 15V level signal. Based on the structural characteristics of the level conversion circuit, the DR_A1_15V signal output by the level conversion circuit is inverted with the DR_A1_3.3V signal. The Schmitt NAND logic circuit can be set to invert the timing of the DR_A1_15V signal, so that the finally output first drive signal is in phase with the DR_A1_3.3V signal. For the convenience of description, in the embodiment of the present application, the first drive signals corresponding to each drive tube in the A phase are denoted as PWMAn_15V, where n = 1, 2, 3, 4.

[0067] Through the above settings, the drive device provided by the embodiment of the present application obtains the first drive signal. However, in actual applications, the drive signal can only be used as the IGBT gate drive Vge voltage signal after passing through the current amplification circuit in the drive circuit board. Considering the problems of the delay characteristics of electronic devices such as resistors and capacitors and the stray inductance characteristics of the circuit in the three-phase drive board, the narrow pulse wave signal near the zero crossing point of the PWM often generates distortion. After the distorted PWM signal is used as the Vge voltage signal for driving the IGBT gate, an instantaneous pulse peak is generated in the IGBT collector turn-off Vce voltage, which poses a potential damage to the IGBT drive tube. To solve the above problems, the present application further designs the drive device as follows. The drive device further includes:

[0068] an isolation sampling module configured to sample the first drive signal to obtain an ideal drive signal;

[0069] a drive current amplification circuit module. The drive current amplification circuit module and the isolation sampling module are configured with a common reference ground. The drive current amplification circuit module is configured to receive the first drive signal and generate a drive reference signal based on the first drive signal;

[0070] a comparison isolation compensation circuit module configured to compare and compensate the ideal drive signal and the drive reference signal to obtain a second drive signal, and the inverter is driven based on the second drive signal.

[0071] As Figure 6As shown, the drive signal generation module is used to generate a first drive signal. The first drive signal includes four groups of PWM signal waves for driving the four drive tubes of the A phase. For ease of explanation, in the embodiments of the present application, the signal waves corresponding to the respective drive tubes of the A phase in the first drive signal are denoted as PWMAn_15V, where n = 1, 2, 3, 4. Of course, the drive signal generation module also includes PWM signal waves for driving the B and C phases. The driving principles of the B and C phases are similar to that of the A phase and can be referred to the description of the A phase.

[0072] For the A phase, the first to fourth isolation sampling modules are provided to respectively collect the first drive signals of the corresponding drive tubes to generate the ideal drive signals corresponding to the first to fourth drive tubes. For ease of explanation, the ideal drive signals corresponding to the first to fourth drive tubes of the A phase are denoted as PWMAn_n_15V, where n = 1, 2, 3, 4.

[0073] For the A phase, the first to fourth drive current amplification circuit modules are provided to respectively collect the first drive signals of the corresponding drive tubes to generate the drive reference signals corresponding to the first to fourth drive tubes. For ease of explanation, the drive reference signals corresponding to the first to fourth drive tubes of the A phase are denoted as GAn_15V, where n = 1, 2, 3, 4.

[0074] It should be noted that in the embodiments of the present application, the drive current amplification circuit module and the isolation sampling module are configured with a common reference ground. Specifically, for the Nth drive tube of the A phase, the Nth isolation sampling module and the Nth drive current amplification circuit module are set with a common reference ground, where N = 1, 2, 3, 4. Through this setting, the subsequent comparison isolation compensation circuit module can compare and compensate the drive reference signal and the ideal drive signal for any drive tube.

[0075] Since the ideal drive signal output by the isolation sampling module is equivalent to the PWM wave directly output by the chip and can be regarded as an ideal waveform, while the drive reference signal output by the drive current amplification circuit module may be distorted after passing through the drive current amplification circuit module. Therefore, the ideal drive signal output by the isolation sampling module is more ideal than the PWM waveform output by the drive current amplification circuit module, so it is called the ideal drive signal, which does not represent absolute ideal. Schematically, such as Figure 7As shown, compared with the ideal drive signal PWMA1_15V which is a reference square wave, the narrow pulse distortion waveforms can be divided into four categories: 1. The rising and falling edges become slower, and there are pulse spikes; 2. The rising edge becomes slower and the waveform is missing, the falling edge becomes slower and there are pulse spikes; 3. The rising edge becomes slower and there are pulse spikes, the falling edge becomes slower and the waveform is missing; 4. The rising and falling edges become slower, and there are both missing parts. In this application, by making the drive reference signal and the ideal drive signal share the same reference ground, comparison and compensation can be performed between the drive reference signal and the ideal drive signal, so that the drive waveform can be corrected to obtain the second drive signal, alleviating the problem that the narrow pulse wave signal near the PWM passing through the zero sequence point is prone to distortion.

[0076] Exemplarily, as Figure 8 shown, an implementation manner of an isolation sampling module is provided. The isolation sampling module includes: a voltage dividing circuit, a first optocoupler, and a MOS transistor circuit. As Figure 8 shown, the voltage dividing circuit includes resistors R26, R28, R29, and a triode Q5. The base of the triode Q5 receives the first drive signal PWMA1_15V through the resistor R26. The collector of the triode Q5 is connected to the 15V voltage. The emitter of the triode Q5 is grounded through the resistors R28 and R29. Among them, the connection node between the resistors R28 and R29 is connected to the second pin of the first optocoupler. The base of the triode Q5 is connected to the third pin of the first optocoupler through the resistor R27. For the secondary side of the first optocoupler, the seventh and eighth pins are connected to the 5V voltage, and, one end of the resistor R31 connected to the ground is connected to the fifth pin of the first optocoupler, the other end of the resistor R31 is also connected to the sixth pin of the first optocoupler, and a capacitor is also provided between the fifth and sixth pins of the first optocoupler. The gate of the MOS transistor is connected to the sixth pin of the first optocoupler, the drain of the MOS transistor is connected to the fifth pin of the first optocoupler through the resistor R33, and the source of the MOS transistor is connected to the 15V potential through the resistor R32.

[0077] Based on the above isolation sampling module, the first drive signal PWMA1_15V enters the first optocoupler through the voltage dividing circuit and is output from the sixth pin of the first optocoupler. At this time, the signal voltage of the sixth pin is reversed with the PWMA1_15V signal, and by setting the MOS transistor circuit to reverse again, the ideal drive signal PWMA1_1_15V is obtained.

[0078] As an optional implementation manner, the drive current amplification circuit module can also be configured as an optocoupler-isolated drive current amplification circuit module. Exemplarily, the drive current amplification circuit module includes a second optocoupler and an amplification circuit, where,

[0079] The primary input terminal of the second optocoupler receives the first driving signal. The secondary side of the second optocoupler is connected to the amplification circuit, and the driving reference signal is output through the amplification circuit. The secondary side of the second optocoupler and the secondary side of the first optocoupler are configured with a common reference ground. Specifically, the reference ground of the secondary side of the second optocoupler and the reference ground of the secondary side of the first optocoupler can be set to be common. By configuring the secondary side of the second optocoupler and the secondary side of the first optocoupler with a common reference ground, the common reference ground configuration of the driving current amplification circuit module and the isolation sampling module is realized, so that the subsequent comparison isolation compensation circuit module can compare and compensate the driving reference signal and the ideal driving signal for any driving transistor.

[0080] As Figure 9 shown, as an optional implementation, the comparison isolation compensation circuit module includes:

[0081] A square wave signal memory configured to latch the ideal driving signal and the driving reference signal;

[0082] A square wave signal sampling extractor configured to obtain the maximum amplitude, the starting time of the maximum amplitude, and the ending time of the maximum amplitude of the ideal driving signal and / or the driving reference signal;

[0083] A maximum amplitude starting time predictor configured to predict based on the sampled value of the maximum amplitude starting time to obtain a repaired prediction value of the starting time of the rising edge, and the repaired prediction value of the starting time of the rising edge is used to repair the rising edge of the driving reference signal;

[0084] A maximum amplitude ending time predictor configured to predict based on the sampled value of the maximum amplitude ending time to obtain a repaired prediction value of the starting time of the falling edge, and the repaired prediction value of the starting time of the falling edge is used to repair the falling edge of the driving reference signal;

[0085] An amplitude comparator configured to compare the amplitude of the repaired driving reference signal with the amplitude of the ideal driving signal;

[0086] An amplitude repairer configured to repair the amplitude of the repaired driving reference signal based on the comparison result of the amplitude comparator to make the amplitude of the repaired output signal consistent with the amplitude of the ideal driving signal;

[0087] The comparison isolation compensation circuit module outputs a second driving signal, and the second driving signal is a square wave signal that has been repaired at the starting time of the rising edge and the falling edge and the amplitude has been repaired.

[0088] Illustratively, taking the comparison isolation compensation circuit module for the first driving transistor as an example for explanation, the working methods of other comparison isolation compensation circuit modules are similar and will not be described in detail. Specifically as follows:

[0089] The square-wave signal memory latches the input signals (including the ideal drive signal PWMA1-1-15V and the drive reference signal GA1_15V) after assigning them different address bit information. The square-wave signal sampler extracts the start time of the maximum amplitude, the end time of the maximum amplitude, and samples the maximum amplitude of the ideal drive signal PWMA1-1-15V and the drive reference signal GA1_15V stored in the square-wave signal memory respectively.

[0090] The start time predictor of the maximum amplitude predicts based on the sampled value of the start time of the maximum amplitude to obtain the repaired predicted value of the start time of the rising edge, and stores the repaired predicted value of the start time of the rising edge in the corresponding address bit of the square-wave signal memory to repair the rising edge of the drive reference signal.

[0091] The end time predictor of the maximum amplitude predicts based on the sampled value of the end time of the maximum amplitude to obtain the repaired predicted value of the start time of the falling edge, and stores the repaired predicted value of the start time of the falling edge in the corresponding address bit of the square-wave signal memory to repair the falling edge of the drive reference signal.

[0092] The amplitude comparator is used to compare the amplitudes between the ideal drive signal PWMA1-1-15V and the drive reference signal GA1_15V, and repair the waveforms above and below the maximum amplitude of the ideal drive signal PWMA1-1-15V.

[0093] After the above-mentioned repairs of the start times of the rising and falling edges and the amplitude repair, the comparison isolation compensation circuit module can output the second drive signal. Among them, the second drive signal corresponding to the first drive tube of phase A is denoted as the GATE_A1 signal.

[0094] As an optional implementation, the drive device further includes a turn-on resistor R18. The second drive signal GATE_A1 becomes the drive tube drive signal GA1_1_15V corresponding to the first drive tube after passing through the turn-on resistor R18, and the drive tube drive signal GA1_1_15V is used to drive the turn-on of the first drive tube.

[0095] As an optional implementation, the drive device further includes: a turn-off resistor R19 and a discharge time detection and repairer. Among them, the second drive signal generates a drive tube drive signal after passing through the turn-off resistor, and the drive tube drive signal is used to drive the turn-off of the inverter drive tube; the discharge time detection and repairer is configured to receive the drive tube drive signal and adjust the discharge time of the corresponding drive tube in the inverter. In this way, the most optimized discharge time design can be carried out, which is convenient for efficiently matching the turn-on and turn-off resistors of the IGBT drive tube during the double-pulse experiment.

[0096] To further illustrate the driving device provided by the embodiments of the present application, the internal functions in the comparison isolation compensation circuit module are described in detail below.

[0097] As Figure 10 shown, the functions of the comparison isolation compensation circuit module are implemented by a DSP chip circuit and a CPLD chip circuit. The square wave signal sampling extraction is composed of the W11 pin of the DSP chip and the internal circuit of the chip. The PWM square wave latching is composed of the K19 pin of the DSP chip and the internal circuit of the chip. The B16, B17, A17, and B18 pins of the DSP chip are respectively connected to the G13, H13, G12, and F12 pins of the CPLD as signal transmission control connections. The D15 pin of the DSP and its internal circuit predict the starting moment of the maximum amplitude, the A14 pin of the DSP and its internal circuit predict the ending moment of the maximum amplitude, the C15 and its internal circuit perform the function of repairing the starting moment of the rising edge, and the B14 pin of the DSP and its internal circuit perform the function of repairing the starting moment of the falling edge.

[0098] The A9 pin of the CPLD and its internal circuit function as the feedback signal of the amplitude comparison circuit. The A10 pin of the CPLD and its internal circuit perform the sampling function of the discharge time detection and repair circuit. The A7 pin of the CPLD outputs the second driving signal GATE_A1.

[0099] Specifically, Figure 10 in, the driving reference signal GA1_15V and the ideal driving signal PWMA1-1-15V are respectively sent to the D15 and A14 pins of the DSP chip after square wave signal sampling extraction. The D15 pin of the DSP and its internal circuit predict the starting moment of the maximum amplitude, and the A14 pin of the DSP and its internal circuit predict the ending moment of the maximum amplitude. After prediction, the C15 pin circuit of the DSP chip repairs the starting moment of the rising edge, and the B14 pin circuit of the DSP chip repairs the starting moment of the falling edge. The repaired waveform is latched in the K19 pin circuit of the DSP.

[0100] At the same time, after the driving reference signal GA1_15V and the ideal driving signal PWMA1-1-15V signals are compared in amplitude by the amplitude comparison circuit, the feedback signal AD_AMP_CPLD is output to the A9 pin circuit of the CPLD chip. The A7 pin of the CPLD and its internal circuit perform square wave signal repair based on the amplitude comparison AD_AMP_CPLD feedback signal of the A9 pin of the CPLD chip and the latch signal in the K19 pin circuit of the DSP, so as to output the second driving signal GATE_A1.

[0101] Further, as Figure 11As shown, it exemplarily shows an implementation manner of an amplitude comparator. The amplitude comparator includes a first operational amplifier and a second operational amplifier. Among them, the positive and negative power supply terminals of the first operational amplifier are respectively connected to ±15V voltages. The non-inverting input terminal of the first operational amplifier receives an ideal drive signal PWMA1-1-15V, and the inverting input terminal receives a drive reference signal GA1_15V. Moreover, the output terminal of the first operational amplifier is connected to the inverting input terminal of the first operational amplifier through an RC parallel circuit. The output terminal of the first operational amplifier is also connected to the non-inverting input terminal of the second operational amplifier through a resistor R37. The output terminal of the second operational amplifier is connected to the inverting input terminal of the second operational amplifier. Moreover, the output terminal of the second operational amplifier outputs an AD_AMP_CPLD signal through a resistor R39. Among them, the connection node between the resistor R37 and the non-inverting input terminal of the second operational amplifier is grounded through an RC parallel circuit, and the resistor R39 is grounded through a capacitor C4.

[0102] The present invention can not only reduce the generation of distorted narrow pulse signals and reduce the risk of Vce overvoltage pulses caused by distorted voltage signals to damage IGBTs, but also make the Vce pulse voltages and voltage stresses of different IGBTs uniform, which is convenient for design engineers to efficiently match the on-resistance and off-resistance values of IGBT driver tubes during double-pulse experiments.

[0103] As an alternative implementation manner, the discharge time detection and repairer includes: a discharge time detection circuit. As Figure 12 shown, the discharge time detection circuit includes: a zener diode, a diode, and an RC circuit. Among them, one end of a resistor R40 receives a drive signal GA1_1_15V of a driver tube. The other end of the resistor R40 is connected to the negative electrode of a zener diode ZD1. The positive electrode of the zener diode ZD1 is connected to the positive electrode of a diode D2. The negative electrode of the diode D2 is connected to one end of a resistor R41. The other end of the resistor R41 is grounded through an RC parallel circuit. The connection node between the resistor R41 and the RC parallel circuit serves as the output port of the discharge time detection circuit for outputting a discharge duration feedback signal AD_DT_CPLD. The discharge time (i.e., the turn-off time of the IGBT) can be detected through the discharge time detection circuit, which is beneficial for further determining the value of the turn-off resistance adapted to the IGBT. In this embodiment, from another perspective, by setting the zener diode ZD1, the current magnitude of the discharge time detection circuit can be changed by selecting the type of ZD1, so as to slow down or accelerate the discharge time, which is beneficial for determining the value of the turn-off resistance adapted to the IGBT. By setting the RC circuit, the current magnitude of the discharge time detection circuit can also be changed by designing the parameters of the RC circuit, so as to slow down or accelerate the discharge time to achieve the same effect.

[0104] As an alternative implementation manner, as Figure 13As shown, the discharge time detection and repairer further includes a discharge time adjustment circuit, and the discharge time adjustment circuit includes:

[0105] A triode, the emitter of the triode is grounded, the base of the triode is grounded through a resistor, and a capacitor is connected in parallel across both ends of the grounding resistor;

[0106] A first input terminal, the first input terminal receives the driving tube driving signal GA1_1_15V, and the first input terminal is electrically connected to the base of the triode through a resistor R43;

[0107] A second input terminal, the second input terminal receives the discharge control signal DT_C_CPLD, and the second input terminal is electrically connected to the base of the triode through a resistor R44 and a diode D2. Among them, the discharge control signal DT_C_CPLD is generated based on the discharge duration feedback signal AD_DT_CPLD. Specifically, the CPLD controls whether the output DT_C_CPLD signal is high level or low level according to the discharge duration feedback signal AD_DT_CPLD, so as to control whether the triode Q5 is turned on or off. By controlling the on / off of the triode Q5, it plays a role in accelerating / slowing down the discharge time of the driving tube driving signal GA1_1_15V. In this embodiment, the turn-off signal of the IGBT enters the discharge time adjustment circuit for optimizing the discharge time design, which further facilitates the design engineer to efficiently match the resistance value of the turn-off resistor of the IGBT driving tube during the double-pulse experiment.

[0108] This application also provides an inverter, including an inversion unit and the driving device as described above, and the driving device is used to drive the driving tubes in the inversion unit.

[0109] In this technical solution, since the inverter adopts the inverter driving device in any of the above technical solutions, it has all the beneficial effects of the inverter driving device, which will not be elaborated here.

[0110] What is disclosed above is only the preferred embodiments of this application. However, it is not used to limit the scope of the rights of this application. Those of ordinary skill in the art can understand that within the spirit and scope of this application and the appended claims, changes, modifications, substitutions, combinations, and simplifications should all be equivalent replacement methods and still fall within the scope covered by the invention.

Claims

1. An inverter driving device, applied to a three-level inverter, characterized in that: The driving device comprises: A driving signal generating module, configured to generate a first driving signal; an isolation sampling module, configured to sample the first driving signal to obtain an ideal driving signal; a driving current amplifying circuit module, wherein the driving current amplifying circuit module and the isolation sampling module are configured with a common reference ground, and the driving current amplifying circuit module is configured to receive the first driving signal and generate a driving reference signal based on the first driving signal; A comparison isolation compensation circuit module is configured to compare and compensate the ideal drive signal and the drive reference signal to obtain a second drive signal, and the inverter is driven based on the second drive signal; The comparison isolation compensation circuit module comprises: A square wave signal memory configured to latch the ideal driving signal and the driving reference signal; A square wave signal sampling extractor is configured to sample and extract the maximum amplitude, the maximum amplitude starting time and the maximum amplitude ending time of the ideal driving signal and / or the driving reference signal; a maximum amplitude starting time predictor, configured to predict according to the sampling value of the maximum amplitude starting time of the ideal driving signal to obtain a repair prediction value of the starting time of the rising edge, wherein the repair prediction value of the starting time of the rising edge is used to repair the rising edge of the driving reference signal; a maximum amplitude end time predictor, configured to predict according to the sampled value of the maximum amplitude end time of the ideal drive signal to obtain a repair prediction value of the start time of the falling edge, wherein the repair prediction value of the start time of the falling edge is used to repair the falling edge of the drive reference signal; an amplitude comparator configured to compare the amplitude of the driving reference signal with the amplitude of the ideal driving signal; an amplitude repairer configured to perform amplitude repair on the edge-repaired driving reference signal based on the comparison result of the amplitude comparator, so that the amplitude of the repaired output signal is consistent with the amplitude of the ideal driving signal; The comparison isolation compensation circuit module outputs the second drive signal, which is a square wave signal with the rising edge and the falling edge starting time repaired and the amplitude repaired.

2. The inverter driving device according to claim 1, characterized in that: The isolated sampling module comprises: A voltage divider circuit, a first optical coupler and a MOS tube circuit, wherein: The voltage divider circuit receives the first drive signal, and the output end of the voltage divider circuit is connected to the primary side of the first optocoupler, the first optocoupler is configured as a logic gate circuit output type first optocoupler, the secondary side of the first optocoupler outputs an intermediate signal that is opposite to the first drive signal, and the intermediate signal is inverted by the MOS tube circuit to obtain the ideal drive signal.

3. The inverter driving device according to claim 2, characterized in that: The driving current amplifying circuit module includes a second optical coupler and an amplifying circuit, wherein: The primary input end of the second optocoupler receives the first drive signal, the secondary side of the second optocoupler is connected to the amplifier circuit, the drive reference signal is output through the amplifier circuit, and the secondary side of the second optocoupler is configured with a common reference ground as the secondary side of the first optocoupler.

4. The inverter driving device according to claim 1, characterized in that: The driving signal generating module comprises: A PWM drive signal generating circuit is configured to generate a PWM drive signal; A level conversion circuit is configured to convert the PWM drive signal into a drive voltage adapted to a drive tube of an inverter; The logic gate circuit is configured to invert the output timing of the level conversion circuit to obtain the first driving signal.

5. The inverter driving device according to claim 1, characterized in that: The amplitude comparator comprises a first operational amplifier and a second operational amplifier, wherein the non-inverting input terminal of the first operational amplifier receives the ideal driving signal, the inverting input terminal receives the driving reference signal, and the output terminal of the first operational amplifier is connected to the inverting input terminal of the first operational amplifier through an RC parallel circuit; The non-inverting input terminal of the second operational amplifier is connected to the output terminal of the first operational amplifier, the output terminal of the second operational amplifier is connected to the inverting input terminal of the second operational amplifier, and the output terminal of the second operational amplifier outputs a feedback signal through a resistor; The amplitude repairer performs amplitude repair on the edge-repaired driving reference signal based on the feedback signal.

6. The inverter driving device according to claim 1, characterized in that: The driving device also includes an on-resistance and an off-resistance; The second driving signal generates a driving tube driving signal through the turn-on resistor, and the driving tube driving signal is used to drive the inverter driving tube to turn on; The second driving signal generates a driving tube driving signal through the turn-off resistor, and the driving tube driving signal is used to drive the inverter driving tube to turn off; The comparison isolation compensation circuit module also includes: The discharge time detection and repair device is configured to receive the drive tube driving signal and adjust the discharge time of the corresponding drive tube in the inverter.

7. The inverter driving device according to claim 6, characterized in that: The discharge time detection repair device comprises: A discharge time detection circuit, the discharge time detection circuit comprises: a voltage stabilizing diode, a diode and an RC circuit, wherein the drive tube driving signal passes through the voltage stabilizing diode, the diode and the RC circuit in sequence, and then outputs a discharge time feedback signal at the high potential end of the RC circuit.

8. The inverter driving device according to claim 7, characterized in that: The discharge time detection repairer also includes: The discharge time adjustment circuit comprises: A triode, wherein the emitter of the triode is grounded, the base of the triode is grounded through a resistor, and a capacitor is connected in parallel to both ends of the grounding resistor; A first input terminal, the first input terminal receives the driving signal of the driving tube, and the first input terminal is electrically connected to the base of the transistor through a resistor; A second input terminal, the second input terminal receives a discharge control signal, and the second input terminal is electrically connected to the base of the transistor through a resistor and a diode, wherein the discharge control signal is generated based on the discharge duration feedback signal.

9. An inverter, characterized in that: It comprises an inverter unit and a driving device as claimed in any one of claims 1 to 8, wherein the driving device is used to drive a driving tube in the inverter unit.

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