A step-down converter based on on-time control

Abstract

This application belongs to the field of buck converter technology and discloses a buck converter based on conduction time control, including: a logic control module for generating a first drive signal and a second drive signal based on received turn-off signal, start signal, and bias comparison signal, and sending them to a dead-time control module and a sleep time detection module; a sleep time detection module for generating a mode control signal based on the first drive signal and the second drive signal; sending the mode control signal to a bias loop comparison module and an error amplification module respectively; and a bias loop comparison module for generating a bias comparison signal based on a first bias current and sending it to the logic control module when the mode control signal is high, and generating a bias comparison signal based on a second bias current and sending it to the logic control module when the mode control signal is low; the second bias current is less than the first bias current. This application can reduce the static current consumption under ultra-light loads while maintaining the fast response speed under conventional loads, thereby improving the efficiency of ultra-light loads.

Description

Technical Field

[0001] This application relates to the field of buck converter technology, and in particular to a buck converter based on conduction time control. Background Technology

[0002] With the rapid growth of Internet of Things (IoT) devices, the operating current of devices that rely on random, sparse events can drop to the microamp (µA) level when no critical event is detected. Conversely, once a critical event is captured, the current demand can surge to tens or even hundreds of milliamps (mA). A buck converter, a circuit that converts a larger input voltage into a smaller output voltage, uses a control circuit to generate a control square wave with a specific duty cycle to control the switching of power transistors, ensuring a constant output voltage while meeting the load's current requirements. Therefore, the demand for buck converters that can provide long-lasting power is increasingly urgent.

[0003] Adaptive on-time control offers numerous advantages, including high efficiency, good transient response, and frequency stability. However, traditional adaptive on-time control still cannot achieve low quiescent current consumption at load current levels in the μA range. Summary of the Invention

[0004] This application provides a buck converter based on on-time control, which can reduce static current consumption under ultra-light loads and improve efficiency under ultra-light loads while maintaining fast response speed under conventional loads.

[0005] In a first aspect, embodiments of this application provide a buck converter based on on-time control, comprising:

[0006] The shortest time shutdown module is used to receive the first turn-on signal of the first switch, generate a shutdown signal when the first turn-on signal is high, and send it to the logic control module.

[0007] The conduction time generation module is used to receive the second conduction signal of the second switch, generate a start signal when the second conduction signal is high, and send it to the logic control module.

[0008] The logic control module is used to generate a first drive signal and a second drive signal based on the received shutdown signal, startup signal and bias comparison signal, and send them to the dead time control module and the sleep time detection module.

[0009] The dead time control module is used to generate a first turn-on signal and a second turn-on signal based on the first drive signal and the second drive signal, send the first turn-on signal to the gate of the first switch and the shortest time turn-off module, and send the second turn-on signal to the gate of the second switch and the turn-on time generation module.

[0010] The sleep time detection module is used to generate a mode control signal based on the first drive signal and the second drive signal; and send the mode control signal to the bias loop comparison module and the error amplification module respectively.

[0011] The bias loop comparison module is used to generate a bias comparison signal based on the first bias current and send it to the logic control module when the mode control signal is high, and to generate a bias comparison signal based on the second bias current and send it to the logic control module when the mode control signal is low; the second bias current is less than the first bias current.

[0012] Furthermore, it also includes an error amplification module, a soft-start module, a feedback resistor array, a loop compensation module, and a selection module;

[0013] The outputs of the error amplification module and the loop compensation module are both connected to the input of the selection module; the output of the selection module is connected to the negative input of the bias loop comparison module.

[0014] The soft-start module amplifies the reference voltage selection signal based on the received first enable signal and sends it to the error amplification module until the voltage of the reference voltage selection signal equals the preset reference voltage.

[0015] The feedback resistor array is used to generate a feedback voltage signal based on the input voltage signal and send it to the error amplification module;

[0016] The sleep time detection module is also used to send mode control signals to the selection module and the error amplification module;

[0017] The error amplification module is used to generate an error amplification signal based on the feedback voltage signal and the reference voltage selection signal when the mode control signal is high, and send it to the selection module; it is turned off when the mode control signal is low.

[0018] The selection module sends the error amplification signal to the bias loop comparator module when the mode control signal is high, and sends the second enable signal to the bias loop comparator module when the mode control signal is low.

[0019] Furthermore, the sleep time detection module is also used to send the mode control signal to the loop compensation module;

[0020] The loop compensation module is turned off when the mode control signal is low.

[0021] Furthermore, the soft-start module is also used to perform a shutdown operation when the voltage of the reference voltage selection signal is equal to the preset reference voltage.

[0022] Furthermore, the buck converter also includes an inductor current sampling module;

[0023] The inductor current sampling module is connected in parallel with the inductor in the buck converter. It is used to generate an inductor induction signal based on the sampled inductor current value and input it to the positive input terminal of the bias loop comparison module.

[0024] The bias loop comparison module is specifically used to generate a bias comparison signal based on the inductor sensing signal, the error amplification signal, and the first bias current, or based on the inductor sensing signal, the second enable signal, and the second bias current.

[0025] Furthermore, the buck converter also includes a current zero-crossing detection module;

[0026] The dead time control module is also used to send the first conduction signal to the current zero-crossing detection module;

[0027] The current zero-crossing detection module is used to receive the inductor voltage signal, generate a current detection signal based on the first conduction signal and the inductor voltage signal, and send it to the logic control module;

[0028] The logic control module is specifically used to generate a first drive signal and a second drive signal based on the turn-off signal, the start signal, the current detection signal, and the bias comparison signal.

[0029] Furthermore, the current zero-crossing detection module includes a delay unit and a detection unit that are interconnected;

[0030] The delay unit is used to delay the first conduction signal and send it to the detection unit;

[0031] The detection unit is used to determine whether the inductor voltage signal is lower than the preset detection threshold when the first conduction signal after the delay is high. If it is, it outputs a high-level current detection signal; otherwise, it outputs a low-level current detection signal.

[0032] Furthermore, the sleep time detection module includes a counting unit, an oscillation control unit, an RC oscillation unit, and a mode selection unit; the counting unit is used to generate a sleep signal based on the first drive signal and the second drive signal; and to count the received clock signal based on the sleep signal to obtain a first count value, a second count value, and a third count value.

[0033] The oscillation control unit is used to generate an initial control signal based on a first count value, a second count value, and a third count value, and send it to the mode selection unit; and to generate an oscillation control signal based on the initial control signal and the sleep signal of the counting unit, and send it to the RC oscillation unit; the RC oscillation unit is used to generate a clock signal based on the oscillation control signal and send it to the counting unit.

[0034] The mode selection unit is used to generate a mode control signal based on the sleep signal and the initial control signal.

[0035] Furthermore, the counting unit includes an XOR gate, a first inverter, a second inverter, a first counter, a second counter, and a third counter; the input of the XOR gate is used to receive a first driving signal and a second driving signal.

[0036] An XOR gate, a first inverter, and a second inverter are connected in sequence; the second inverter is used to output a sleep signal and send it to the reset ports of the first counter, the second counter, and the third counter.

[0037] The clock input terminal of the first counter is used to receive clock signals, and the data input terminal and the second output terminal are both connected to the clock input terminal of the second counter. The first output terminal is used to output the first count value. The data input terminal and the second output terminal of the second counter are both connected to the clock input terminal of the third counter. The first output terminal is used to output the second count value. The data input terminal and the second output terminal of the third counter are connected, and the first output terminal is used to output the third count value.

[0038] Furthermore, the oscillation control unit is specifically used to perform an AND operation on the first count value and the third count value to obtain the fourth count value; to perform an AND operation on the second count value and the third count value to obtain the fifth count value; to perform a NOR operation on the third count value, the fourth count value and the fifth count value to obtain the initial control signal; and to perform an AND operation on the initial control signal and the sleep signal to obtain the oscillation control signal.

[0039] Furthermore, the mode selection unit is specifically used to invert the sleep signal and input it along with the initial control signal into the D flip-flop to obtain the mode control signal.

[0040] In summary, compared with the prior art, the beneficial effects of the technical solution provided in this application include at least the following:

[0041] This application provides a buck converter based on on-time control. The added sleep time detection module utilizes the characteristic that the first and second drive signals change with the load. Based on the two drive signals, it determines whether the buck converter is operating in a normal load mode or an ultra-light load mode. If it is the former, a high-level mode control signal is output; if it is the latter, a low-level mode control signal is output. At the same time, the bias loop comparison module in the buck converter switches the corresponding operating mode according to the mode control signal, reducing the bias current and thus reducing the static current consumption of the circuit. Attached Figure Description

[0042] Figure 1 The circuit diagram of a buck converter based on on-time control is provided for one embodiment of this application.

[0043] Figure 2 The key nodes and waveforms of each signal in CCM mode are provided in one embodiment of this application.

[0044] Figure 3 A circuit diagram of a counting unit, an oscillation control unit, and a mode selection unit provided in one embodiment of this application.

[0045] Figure 4 The circuit structure diagram of an RC oscillation unit provided in one embodiment of this application is shown.

[0046] Figure 5 The waveform diagram shows the operation of a sleep time detection module provided in one embodiment of this application.

[0047] Figure 6 This is an internal circuit diagram of a bias loop comparison module provided in one embodiment of this application.

[0048] Figure 7 This is an internal circuit diagram of a current zero-crossing detection module provided in one embodiment of this application.

[0049] Figure 8 This is an internal circuit diagram of a soft-start module provided in one embodiment of this application.

[0050] Figure 9 The waveform diagram shows the operation of a soft-start module provided in one embodiment of this application. Detailed Implementation

[0051] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0052] Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0053] Please see Figure 1 This application provides a buck converter based on on-time control, comprising:

[0054] The shortest time shutdown module is used to receive the first turn-on signal of the first switch, generate a shutdown signal when the first turn-on signal is high, and send it to the logic control module.

[0055] The conduction time generation module is used to receive the second conduction signal of the second switch, generate a start signal when the second conduction signal is high, and send it to the logic control module.

[0056] It can be assumed that the shortest time turn-off module only works when the first switch is turned on, and the turn-on time generation module only works when the second switch is turned on, thereby reducing the static current consumption of these two circuits.

[0057] The logic control module is used to generate a first drive signal and a second drive signal based on the received shutdown signal, start signal and bias comparison signal, and send them to the dead time control module and the sleep time detection module.

[0058] The dead time control module is used to generate a first turn-on signal and a second turn-on signal based on the first drive signal and the second drive signal, send the first turn-on signal to the gate of the first switch and the shortest time turn-off module, and send the second turn-on signal to the gate of the second switch and the turn-on time generation module.

[0059] The sleep time detection module is used to generate a mode control signal based on the first drive signal and the second drive signal; and send the mode control signal to the bias loop comparison module and the error amplification module respectively.

[0060] The bias loop comparison module is used to generate a bias comparison signal based on the first bias current and send it to the logic control module when the mode control signal is high, and to generate a bias comparison signal based on the second bias current and send it to the logic control module when the mode control signal is low; the second bias current is less than the first bias current.

[0061] The first switching transistor is Figure 1 The high-side switching power transistor SP is the second switching transistor. Figure 1 In the low-side switching power transistor SN, the first turn-on signal is signal N, the second turn-on signal is signal P, and the turn-off signal is T. OFF.MIN The start signal is T ON The first drive signal is PWM_N, and the second drive signal is PWM_P; the mode control signal is Mode, and the bias loop comparator module is... Figure 1 The COMP output bias comparator signal is V. C .

[0062] Furthermore, the buck converter also includes a current zero-crossing detection module (ZCD).

[0063] The dead time control module is also used to send the first conduction signal to the current zero-crossing detection module.

[0064] The current zero-crossing detection module is used to receive the inductor voltage signal V. SW Based on the first turn-on signal N and the inductor voltage signal V SW Generate current detection signal V ZCD And send it to the logic control module; the logic control module is specifically used to determine the turn-off signal, start signal, and current detection signal V based on the turn-off signal, start signal, and current detection signal V. ZCD Compare with bias signal V C Generate the first drive signal and the second drive signal.

[0065] It is understandable that the aforementioned shortest time turn-off module, turn-on time generation module, logic control module, dead time control module, bias loop comparison module, and current zero-crossing detection module are all inherent modules in existing buck converters.

[0066] In Continuous On-Mode (CCM), the waveforms of various signals in the circuit change as follows: Figure 2 As shown, their working principles are all based on the existing buck converter principles, which will not be elaborated on here.

[0067] The improvement of this application lies in the addition of a sleep time detection module, which generates a mode control signal based on the first drive signal and the second drive signal, and the internal structure of the bias loop comparison module has been improved so that it switches the working mode according to the mode control signal.

[0068] First, for the newly added sleep time detection module in this application, please refer to the internal circuit structure. Figure 3 and Figure 4 The sleep time detection module includes a counting unit (3-bit counter), an oscillation control unit (RC_OSC_Control), an RC oscillation unit (RC_OSC), and a mode selection unit (MODE Selector).

[0069] The counting unit is used to generate a sleep signal based on the first drive signal and the second drive signal; and to count the received clock signal based on the sleep signal to obtain a first count value CNT1, a second count value CNT2 and a third count value CNT4.

[0070] Depend on Figure 3 It can be seen that the counting unit includes an XOR gate, a first inverter, a second inverter, a first counter, a second counter, and a third counter; the input terminal of the XOR gate is used to receive the first driving signal and the second driving signal.

[0071] An XOR gate, a first inverter, and a second inverter are connected in sequence; the second inverter is used to output the sleep signal T. SLEEP And send it to the reset port RDN of the first counter, the second counter and the third counter.

[0072] The clock input of the first counter is used to receive the clock signal CLK_OSC. The data input and the second output are both connected to the clock input of the second counter. The first output is used to output the first count value CNT1. The data input and the second output of the second counter are both connected to the clock input of the third counter. The first output is used to output the second count value CNT2. The data input and the second output of the third counter are connected. The first output is used to output the third count value CNT4.

[0073] The oscillation control unit generates an initial control signal based on a first count value, a second count value, and a third count value, and sends it to the mode selection unit; and generates an oscillation control signal based on the initial control signal and the sleep signal of the counting unit, and sends it to the RC oscillation unit; for details, please refer to [link to relevant documentation]. Figure 3 In the oscillation control unit, the first and third count values ​​are ANDed to obtain the fourth count value S5, and the second and third count values ​​are ANDed to obtain the fifth count value S6. Then, the third, fourth, and fifth count values ​​are ORed to obtain the initial control signal SUMR. The initial control signal SUMR and the sleep signal T are then... SLEEP Perform an AND operation to obtain the oscillation control signal EN_OSC.

[0074] See Figure 4 The RC oscillation unit generates a clock signal CLK_OSC based on the oscillation control signal EN_OSC and sends it to the counting unit. The mode selection unit generates a mode control signal based on the sleep signal and the initial control signal.

[0075] Specifically, the mode selection unit is used to select the sleep signal T SLEEP After being inverted by the input inverter, the input D flip-flop is combined with the initial control signal SUMR to obtain the mode control signal.

[0076] This can be understood as the sleep time detection module obtaining the corresponding sleep time length based on the drive signals of the two switching power transistors, thereby determining the current load condition of the buck converter and adjusting the working mode of the buck converter control loop.

[0077] Please see Figure 5 At the start of a switching cycle, PWM_P and PWM_N are low, the high-side power transistor SP is turned on, and the low-side power transistor SN is turned off. At this time, the sleep signal T... SLEEP When the signal is low, the counting unit is reset. After the high-side power transistor SP is turned on for a period of time, PWM_P and PWM_N become high. Afterward, the high-side power transistor SP is turned off, and the low-side power transistor SN is turned on. At this time, the sleep signal T... SLEEP It remains at a low level, and the counting unit is still in the reset phase.

[0078] The discussion then proceeds to two scenarios: continuous conduction mode (CCM) and intermittent conduction mode (DCM). In CCM, the current zero-crossing detection module fails to detect the inductor current crossing zero, and within one switching cycle, the sleep signal T... SLEEPWhen the current is 0, the RC oscillation unit is not working, and the three counters are in the reset phase. Under DCM, when the current zero-crossing detection module detects that the inductor current has crossed zero, PWM_N goes low. Afterwards, for the remainder of one switching cycle, PWM_P is high and PWM_N is low. SLEEP When the signal goes high, the counting unit begins counting the rising edges of the CLK_OSC output by the RC oscillation unit; under CCM, the sleep signal T... SLEEP Since the EN_OSC level is always low, the RC oscillation unit is not working. At this time, only a few gate circuits and the D flip-flop are working, resulting in almost zero power consumption. Under DCM, when the sleep signal T... SLEEP When the signal becomes high, the RC oscillation unit starts working. If the rising edge of CLK_OSC output by the RC oscillation unit has not reached level 4, CNT4, S5, and S6 are all low. After passing through the NAND gate, the output SUMR is high, therefore the enable signal EN_OSC of the RC oscillation unit is high, and the RC oscillation unit continues to output the clock signal CLK_OSC. If the rising edge of CLK_OSC has not reached level 4 within one switching cycle, the RC oscillation unit will switch to sleep mode based on the sleep signal T. SLEEP Upon reset, if the rising edge of CLK_OSC reaches 4 within one switching cycle, then after the counting unit outputs 4 (CNT4 = 1), SUMR goes low. For the remainder of one switching cycle, EN_OSC is 0, the RC oscillation unit remains off, and only a few gate circuits and D flip-flops operate, resulting in almost zero power consumption. The mode selection unit includes only one inverter and one D flip-flop. Under normal load mode, whether in CCM or DCM, SUMR remains high until the counting unit reaches 4, and the mode control signal remains high. When the circuit enters ultra-light load mode, within one switching cycle, after the counting unit reaches 4, CNT4 remains high, SUMR goes low, and T... SLEEP After passing through the inverter, it becomes the input clock signal of the D flip-flop. When the next switching cycle arrives, T... SLEEP The inverter is initially at a high level, and the output mode control signal is SUMR at a low level at the end of the previous switching cycle.

[0079] Load current at Figure 1 It is V OUT / R LOAOWhether the load current decreases to the ultra-light load threshold is determined by whether the third count value reaches 4 within one switching cycle. Within one cycle, when PWM_P = 0 / PWM_N = 0, the high-side switch is on and the low-side switch is off, which is the charging stage, and the charging time is t1. When PWM_P = 1 / PWM_N = 1, the high-side switch is off and the low-side switch is on, which is the discharging stage, and the discharging time is t2. When PWM_P = 1 / PWM_N = 0, the high-side switch is off and the low-side switch is also off, which is the stage of neither charging nor discharging, and the time of neither charging nor discharging is t3. In CCM mode (i.e., heavier load), t3 = 0. In DCM mode (i.e., lighter load / ultra-light load), t3 > 0. The duty cycle D = t1 / (t1 + t2 + t3), and the duty cycle is proportional to the load current.

[0080] Therefore, this application can be based on the sleep signal T. SLEEP The characteristic of changing with load can be used to switch the circuit operating mode by detecting the sleep time. Once the load current decreases to the threshold of the ultra-light load mode, the buck converter control loop enters the ultra-light load mode to minimize the system's static current consumption.

[0081] Secondly, for improvements to the bias loop comparator module, please refer to [link / reference]. Figure 6 The shaded portion in this application illustrates the self-biasing current technology employed in the bias loop comparator module. Since the bias loop comparator module is a continuously operating circuit and cannot be switched on or off, when MODE = 0, MPS1 is on and MPS2 is off, with the bias current of the bias loop comparator module being S_IB_COMP, which is relatively small. When MODE = 1, MPS1 is off and MPS2 is on, with the bias current being L_IB_COMP, which is relatively large. This allows for the use of a larger first bias current L_IB_COMP for biasing when the load current is at a normal value, resulting in better comparator performance. When the load current is less than the threshold for entering the ultra-light load mode, a smaller second bias current S_IB_COMP is used for biasing, thereby reducing the static current consumption of the bias loop comparator module.

[0082] Finally, please see Figure 7 Regarding the shaded area, this application also improves the current zero-crossing detection module, which includes a delay unit and a detection unit connected to each other.

[0083] The delay unit is used to delay the first conduction signal and send it to the detection unit.

[0084] The delay unit is Figure 7 The leftmost shaded area represents the detection unit, which is the analog circuit on the right.

[0085] The detection unit is used to determine whether the inductor voltage signal is lower than a preset detection threshold when the first conduction signal after the delay is high. If so, it outputs a high-level current detection signal; otherwise, it outputs a low-level current detection signal. This application's zero-crossing current detection module can be understood to have three functions: switching function, anti-output mis-flipping function, and early flipping function.

[0086] For the switching function, the current zero-crossing detection module only works during the inductor current discharge phase. That is, it determines whether the inductor current is discharging based on the first conduction signal. If the first conduction signal is high, the inductor current is detected. At other times, it remains off and does not perform the detection work to minimize the static current consumption of the circuit.

[0087] Regarding the output mis-flipping prevention function, since the existing circuit structure has already implemented a low-power design for the current zero-crossing detection module, mis-flipping may occur due to ringing. To avoid this situation, this application uses an inverter, a delay circuit, and an OR gate to design a delay unit that can realize the mis-flipping prevention function. In the initial stage of inductor current discharge, that is, when the first conduction signal becomes high, the delay circuit is used to shield the high level of the first conduction signal N of the low-side switching power transistor, delaying the start of the detection circuit. The circuit only works when both NA and NB are low.

[0088] For the early switching function, due to a certain delay in the control loop, in order to minimize the efficiency loss caused by inductor current backflow, this application uses two NMOS transistors MN1 and MN2 as pseudo-resistors in the detection unit to pre-set the output switching threshold, increasing the mismatch at the input of the current zero-crossing detection module, so that the V output of the current zero-crossing detection module is set before the inductor current discharges to zero. ZCD The signal flips from low to high in advance, thus turning off the low-side switch. These three functional designs minimize the circuit's quiescent current consumption, improve circuit robustness, and minimize efficiency loss.

[0089] The buck converter based on conduction time control provided in the above embodiments firstly utilizes the characteristic that the first and second drive signals change with the load to determine whether the buck converter is operating in a normal load mode or an ultra-light load mode based on the two drive signals. The sleep signal T is generated when both the high-side and low-side power transistors are turned off within one switching cycle. SLEEP The sleep time duration increases as the load current decreases; therefore, the sleep time detection module measures the sleep signal T. SLEEP Perform the detection. Under CCM, the sleep signal T SLEEPThe signal is always low, at which point the RC oscillation unit does not operate, and the circuit consumes almost zero power. Under DCM, when the sleep signal T... SLEEP When the signal goes high, the RC oscillation unit starts working and the counting unit starts counting. If the rising edge of the output clock of the RC oscillation unit has not reached 4, a high-level mode control signal is output, i.e., MODE=1, so that the control loop is in the normal load mode. If the rising edge of the output clock of the RC oscillation unit reaches 4, the RC oscillation unit is turned off after the clock reaches 4, and a low-level mode control signal is output, i.e., MODE=0, so that the control loop enters the ultra-light load mode. After that, the sleep time detection module consumes almost zero power.

[0090] Secondly, the adaptive bias design of the bias loop comparator module allows it to use a larger bias current in normal load mode to achieve better response speed, and a smaller bias current in ultra-light load mode to achieve the lowest possible static current consumption.

[0091] Finally, the inductor current is detected by the current zero-crossing detection module. To solve the problem of false flipping in the early stage of inductor current discharge, a delay unit is used to shield the high-level first conduction signal in the early stage of inductor current discharge, and the detection function of the circuit is turned on after a delay. An OR gate is used to prevent false flipping caused by VSW ringing and oscillation. The resistance of the pseudo resistor MN2 is set to be greater than that of MN1 to form a preset detection threshold greater than 0 to achieve early flipping and reduce inductor current backflow.

[0092] Please see Figure 1 In some embodiments, the buck converter further includes an error amplification module, a soft-start module, a feedback resistor array, a loop compensation module, and a selection module; the output of the error amplification module and the output of the loop compensation module are both connected to the input of the selection module; the output of the selection module is connected to the negative input of the bias loop comparison module.

[0093] Furthermore, the sleep time detection module is also used to send the mode control signal to the loop compensation module.

[0094] The loop compensation module is turned off when the mode control signal is low.

[0095] The soft-start module amplifies the reference voltage selection signal based on the received first enable signal and sends it to the error amplification module until the voltage of the reference voltage selection signal equals the preset reference voltage.

[0096] The first enable signal EN_SS is provided externally. When the circuit needs to work, an external signal EN_SS, which transitions from a high level to a low level, will be provided.

[0097] The feedback resistor array is used to generate a feedback voltage signal based on the input voltage signal and send it to the error amplification module.

[0098] The sleep time detection module is also used to send mode control signals to the selection module and the error amplification module.

[0099] The error amplification module is used to generate an error amplification signal based on the feedback voltage signal and the reference voltage selection signal when the mode control signal is high, and then send it to the selection module; it is turned off when the mode control signal is low.

[0100] The feedback voltage signal is Figure 1 V in FB The reference voltage selection signal is Figure 1 V in REF_SEL .

[0101] Specifically, the input signal of the error amplification module EA is V. FB and V REF_SEL MODE is the mode control signal, I REF_EA It is the bias current; when the circuit enters the ultra-light load mode, MODE=0, thereby shutting down the error amplifier module EA.

[0102] The selection module sends the error amplification signal to the bias loop comparator module when the mode control signal is high, and sends the second enable signal to the bias loop comparator module when the mode control signal is low.

[0103] Here, the error amplification signal is the error amplification signal V after compensation by the loop compensation module. EA .

[0104] The selection module consists of an inverter and two gate circuits TG. The mode control signal is input to the first gate circuit after being inverted twice, and output to the second gate circuit after being inverted once. The first gate circuit receives the error amplification signal and operates when the mode control signal is high, sending the error amplification signal to the bias loop comparator module. The second gate circuit receives the second enable signal V. REF2 When the mode control signal is low, that is, when both the loop compensation module and the error amplification module are in the off state, the second enable signal is sent to the bias loop comparison module to ensure the normal operation of the bias loop comparison module.

[0105] Furthermore, the buck converter also includes an inductor current sampling module.

[0106] The inductor current sampling module is connected in parallel with the inductor in the buck converter to generate an inductor induced signal V based on the sampled inductor current value. SEN And input the positive input terminal of the bias loop comparator module.

[0107] The bias loop comparison module is specifically used to generate a bias comparison signal based on the inductor sensing signal, the error amplification signal, and the first bias current, or based on the inductor sensing signal, the second enable signal, and the second bias current.

[0108] It is understood that the aforementioned error amplification module, soft-start module, feedback resistor array, loop compensation module, and inductor current sampling module are all inherent modules in existing buck converters. The difference lies in the fact that this application incorporates circuit switching technology into the error amplification module and loop compensation module. Specifically, in ultra-light load mode, the error amplification module and loop compensation module are turned off, effectively reducing the static current consumption of the buck converter under ultra-light load conditions.

[0109] Meanwhile, considering that the bias loop comparator module cannot be turned off, a selection module was added to ensure that the bias loop comparator module still has normal input and output when the circuit enters the ultra-light load mode.

[0110] The circuit switching technology introduced in the above embodiments into the modules of existing buck converters enables the shutdown of some circuit modules in ultra-light load mode without affecting the modules that need to work, thereby reducing static current consumption.

[0111] Please see Figure 8 and Figure 9 In some embodiments, this application also makes some improvements to the soft-start module: the soft-start module is also used to perform a shutdown operation when the voltage of the reference voltage selection signal is equal to the preset reference voltage.

[0112] The soft-start module of this application includes a ramp voltage generation circuit, a self-shutting soft-start circuit, and a reference voltage selector; the self-shutting soft-start circuit is... Figure 8 The shaded area in the diagram will automatically turn off after the buck converter system completes its soft start. The soft start module consists of three operating phases: initial phase, ramp voltage generation phase, and completion phase.

[0113] In the initial stage, the first enable signal EN_SS of the soft-start module is high, ENB is low, and ENA is high. Therefore, ENP_RAMP is low and ENN_RAMP is high. At this time, capacitor C_SS is discharged to zero potential through MOSFET MN0. The comparator is effective when ENP_RAMP is low, and V_SS is at zero potential, which is less than the preset reference voltage V. REF1 Therefore, the comparator output B1 is low, so the D flip-flop outputs A high and B low. At this time, the reference voltage selection signal V... REF_SEL=V_SS. During the ramp voltage generation phase, the first enable signal EN_SS goes low, then ENB goes high and ENA goes low, and the capacitor voltage V_SS is still less than the preset reference voltage V. REF1 Therefore, the comparator output B1 remains low, resulting in the D flip-flop outputs A high and B low. Consequently, ENP_RAMP becomes high and ENN_RAMP becomes low. At this time, the current IB_SS, after being proportionally reduced, charges the capacitor C_SS to generate a ramp voltage. The reference voltage selection signal remains V. REF_SEL =V_SS. During the completion phase, when the capacitor voltage V_SS reaches the preset reference voltage V... REF1 At this time, the comparator output B1 toggles to a high level, then A goes low and B goes high. Therefore, ENP_RAMP is low and ENN_RAMP is high. After this, the comparator turns off, MOSFET MN0 discharges capacitor C_SS, and no current charges capacitor C_SS. The reference voltage selection signal V... REF_SEL =V REF1 .

[0114] After the buck converter system completes its soft start, this circuit can automatically shut down to minimize the power consumption of the soft start circuit.

[0115] Specifically, when V_SS increases from zero to greater than or equal to VREF1, the comparator output B1 flips from low to high. The rising edge of B1 causes the D flip-flop output Q to change from low to high, thereby shutting down the soft-start module.

[0116] In the above embodiments, the soft-start module automatically shuts down the soft-start circuit after the buck converter completes the soft-start, thereby eliminating the static current consumption of the soft-start circuit and further improving the conversion efficiency of the buck converter.

[0117] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0118] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A buck converter based on on-time control, characterized in that, include: The shortest time shutdown module is used to receive the first turn-on signal of the first switch, generate a shutdown signal when the first turn-on signal is high, and send it to the logic control module. The conduction time generation module is used to receive the second conduction signal of the second switch, generate a start signal when the second conduction signal is high, and send it to the logic control module. The logic control module is used to generate a first drive signal and a second drive signal based on the received shutdown signal, startup signal and bias comparison signal, and send them to the dead time control module and the sleep time detection module. The dead time control module is used to generate a first turn-on signal and a second turn-on signal according to the first drive signal and the second drive signal, send the first turn-on signal to the gate of the first switch and the shortest time turn-off module, and send the second turn-on signal to the gate of the second switch and the turn-on time generation module. A sleep time detection module is used to generate a mode control signal based on the first drive signal and the second drive signal; and to send the mode control signal to the bias loop comparison module and the error amplification module respectively; the sleep time detection module includes a counting unit, an oscillation control unit, an RC oscillation unit and a mode selection unit; the counting unit is used to generate a sleep signal according to the first drive signal and the second drive signal; and to count the received clock signal according to the sleep signal to obtain a first count value, a second count value and a third count value; the oscillation control unit is used to generate an initial control signal according to the first count value, the second count value and the third count value, and send it to the mode selection unit; and to generate an oscillation control signal according to the initial control signal and the sleep signal of the counting unit, and send it to the RC oscillation unit; The RC oscillation unit is used to generate a clock signal according to the oscillation control signal and send it to the counting unit; the mode selection unit is used to generate the mode control signal according to the sleep signal and the initial control signal. The bias loop comparison module is used to generate a bias comparison signal based on a first bias current and send it to the logic control module when the mode control signal is high, and to generate a bias comparison signal based on a second bias current and send it to the logic control module when the mode control signal is low. The second bias current is less than the first bias current.

2. The buck converter based on conduction time control according to claim 1, characterized in that, It also includes an error amplification module, a soft-start module, a feedback resistor array, a loop compensation module, and a selection module; The output terminals of the error amplification module and the loop compensation module are both connected to the input terminal of the selection module; the output terminal of the selection module is connected to the negative input terminal of the bias loop comparison module. The soft-start module is used to amplify the reference voltage selection signal according to the received first enable signal and send it to the error amplification module until the voltage of the reference voltage selection signal is equal to the preset reference voltage. The feedback resistor array is used to generate a feedback voltage signal based on the input voltage signal and send it to the error amplification module; The sleep time detection module is also used to send the mode control signal to the selection module and the error amplification module; The error amplification module is used to generate an error amplification signal based on the feedback voltage signal and the reference voltage selection signal when the mode control signal is high, and send it to the selection module; and to turn off when the mode control signal is low. The selection module is used to send an error amplification signal to the bias loop comparison module when the mode control signal is high, and to send a second enable signal to the bias loop comparison module when the mode control signal is low.

3. The buck converter based on conduction time control according to claim 2, characterized in that, The sleep time detection module is also used to send the mode control signal to the loop compensation module; The loop compensation module is turned off when the mode control signal is low.

4. The buck converter based on conduction time control according to claim 2, characterized in that, The soft-start module is also used to perform a shutdown operation when the voltage of the reference voltage selection signal is equal to a preset reference voltage.

5. The buck converter based on conduction time control according to claim 1, characterized in that, It also includes an inductor current sampling module; the inductor current sampling module is connected in parallel with the inductor in the buck converter, and is used to generate an inductor induction signal based on the sampled inductor current value, and input it to the positive input terminal of the bias loop comparison module; The bias loop comparison module is specifically used to generate a bias comparison signal based on the inductor sensing signal, the error amplification signal, and the first bias current, or based on the inductor sensing signal, the second enable signal, and the second bias current.

6. The buck converter based on conduction time control according to claim 1, characterized in that, It also includes a current zero-crossing detection module; the dead time control module is further used to send the first conduction signal to the current zero-crossing detection module; The current zero-crossing detection module is used to receive the inductor voltage signal, generate a current detection signal based on the first conduction signal and the inductor voltage signal, and send it to the logic control module; The logic control module is specifically used to generate the first drive signal and the second drive signal based on the shutdown signal, the start signal, the current detection signal and the bias comparison signal.

7. The buck converter based on conduction time control according to claim 6, characterized in that, The current zero-crossing detection module includes a delay unit and a detection unit that are interconnected. The delay unit is used to delay the first conduction signal and send it to the detection unit; The detection unit is used to determine whether the inductor voltage signal is lower than a preset detection threshold when the first conduction signal after the delay is high. If it is, it outputs a high-level current detection signal; otherwise, it outputs a low-level current detection signal.

8. The buck converter based on conduction time control according to claim 1, characterized in that, The counting unit includes an XOR gate, a first inverter, a second inverter, a first counter, a second counter, and a third counter; The input terminal of the XOR gate is used to receive the first driving signal and the second driving signal; The XOR gate, the first inverter, and the second inverter are connected in sequence; the second inverter is used to output the sleep signal and send it to the reset ports of the first counter, the second counter, and the third counter. The clock input terminal of the first counter is used to receive the clock signal, the data input terminal and the second output terminal are both connected to the clock input terminal of the second counter, and the first output terminal is used to output the first count value. The data input terminal and the second output terminal of the second counter are both connected to the clock input terminal of the third counter, and the first output terminal is used to output the second count value; the data input terminal and the second output terminal of the third counter are connected, and the first output terminal is used to output the third count value.

9. The buck converter based on on-time control according to claim 8, characterized in that, The oscillation control unit is specifically used to perform an AND operation on the first count value and the third count value to obtain a fourth count value; perform an AND operation on the second count value and the third count value to obtain a fifth count value; perform a NOR operation on the third count value, the fourth count value, and the fifth count value to obtain the initial control signal; and perform an AND operation on the initial control signal and the sleep signal to obtain the oscillation control signal.

10. The buck converter based on conduction time control according to claim 8, characterized in that, The mode selection unit is specifically used to invert the sleep signal and input it along with the initial control signal into a D flip-flop to obtain a mode control signal.

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