Discontinuous pulse width modulation of continuous carriers using phase current amplitude comparison

Abstract

The invention relates to discontinuous pulse width modulation of continuous carriers using phase current amplitude comparison. Embodiments of the present disclosure provide an inverter controller that is operable to perform an inverter controller operation that includes performing a continuous carrier alignment method on an inverter. The continuous carrier alignment method comprises the following steps: for a current sampling period, evaluating the shape of a carrier waveform from a previous sampling period; and determining whether to insert the intermediate carrier shape into the carrier waveform during the current sampling period based at least in part on an end position of the carrier waveform from the previous sampling period.

Description

Background Art

[0001] Known configurations of electric motor drive systems include an electric motor and an inverter operable to convert a direct current (DC) input to an alternating current (AC) output that powers and controls the electric motor (e.g., speed, torque, etc.). Appropriate motor control can be used to improve motor efficiency. For example, the speed of the motor should be controlled to closely match the task to be performed by the motor, thereby avoiding inefficiencies that waste energy and / or materials.

[0002] A common technique for controlling the AC voltage output waveform produced by an inverter is pulse width modulation (PWM). In general, a PWM scheme reduces the average power of a signal by chopping the signal into discrete parts. The name PWM stems from the fact that the width of the discrete parts (i.e., pulses) is modulated to produce the desired output signal. In a typical three-phase full-bridge inverter, there are six switching elements (e.g., transistors) organized into three "phase legs", where each phase leg includes two switching elements connected in series and between the positive DC rail and the negative DC rail. At any given moment, up to three inverter switching elements are turned on, while the other three inverter switching elements are turned off. The phase node is located between the two switching elements of each phase leg to provide three phases of the three-phase AC waveform output. Figure 2 An example three-phase AC waveform 200 is depicted in FIG. A single conductor is coupled between each phase node and one of the three motor terminals to transmit the three-phase AC waveform 200 to the motor. Each phase of the three-phase AC waveform 200 has the same frequency and voltage amplitude relative to a common reference, but has a phase difference of one-third of a cycle between each phase (i.e., 120 degrees out of phase). Due to the phase difference, the voltage on any conductor reaches its peak one-third of a cycle after one of the other conductors and one-third of a cycle before the remaining conductor. This phase delay provides constant power delivery to a balanced linear load.

[0003] The purpose of PWM is to achieve a desired low frequency output voltage by changing the duty cycle of the inverter switching elements. The duty cycle represents the portion of the cycle that the corresponding inverter switching element is on. Therefore, PWM adjusts the time (duty cycle) that the inverter switching element is closed and opened. By changing the duty cycle at a fast rate, the desired output voltage for each of the three phases can be achieved.

[0004] Carrier-based PWM is a modulation scheme that provides low harmonic distortion characteristics and simple implementation. In general, a carrier-based PWM scheme compares a reference (or control) signal with a carrier (or modulation) signal in each phase leg of the inverter. Whenever these two signals (reference signal / carrier signal) cross, the associated inverter switching element is turned on or off. The carrier signal is a sawtooth signal or a triangular signal with a desired switching frequency. In conventional implementations, a triangular carrier signal is used to modulate all three phase legs in a three-phase voltage source inverter because its symmetrical switching sequence results in lower power loss and lower total harmonic distortion (THD).

[0005] Discontinuous PWM (DPWM) is a type of PWM in which the duty cycle or each phase is clamped to the DC rail for one-third of each cycle. DPWM enables reduced switching losses because, for example, only two (2) switches are turned on and off in one switching cycle, compared to three (3) switches turned on and off in one switching cycle when using, for example, continuous PWM (CPWM). In DPWM, power efficiency is improved by reducing the switching losses of the inverter, especially at high switching frequencies. With better power efficiency, the inverter requires less cooling equipment.

[0006] There are many alternatives to the reference signal previously described. For example, a modulation technique called space vector PWM (SV-PWM) can be used to generate the reference signal. SV-PWM is a modulation scheme for controlling the inverter switching elements in a manner that applies a given voltage vector to a three-phase electric motor (e.g., a permanent magnet motor or an induction motor). With six (6) switching elements in a conventional inverter, there are eight discrete voltage vectors that can be applied instantaneously. Of these eight vectors, there are only six non-zero vectors, and all of these six non-zero vectors produce different voltage angles. For high performance motor control, a smoothly rotating voltage vector is desired rather than a voltage vector that jumps sixty (60) degrees with each step. The SV-PWM scheme controls the inverter switching elements to rotate the motor in a manner that simulates a smoothly rotating voltage vector. The SV-PWM technique generates a pulse width modulated signal, thereby controlling the switching elements of the inverter in a manner that generates and combines voltage vectors to form a three-phase AC waveform output (e.g., Figure 2 The three phases of the three-phase AC waveform 200) shown in FIG.

[0007] In SV-PWM, in order to avoid the inverter input capacitor (e.g. Figure 4 The capacitor 442 shown in FIG. 4 is short-circuited, and both switching elements in one phase leg are never turned on at the same time. Therefore, the three (3) inverter phase nodes (in Figure 3Each output (shown as "A", "B" and "C") in the figure can be in one of two phase node states. In one phase node state, the upper inverter switch element is closed (conductive), the lower inverter switch element is open (non-conductive), and this closed / open state is represented as a "one" (1) phase node state. In another phase node state, the upper inverter switch element is open (non-conductive), the lower inverter switch element is closed (conductive), and this open / closed state is represented as a zero (0) phase node state. Figure 3 As shown in Table I 330, eight (2 3 ) total phase node states can be used to output (for example, Figure 3 The V 0 -V 7 ). These phase node states are called basis vectors. The eight basis vectors can be plotted on a hexagonal star diagram, an example of which is Figure 6 The hexagonal star diagram 600 depicted in FIG. Figure 6 As shown, each vector (for example, Figure 3 and Figure 6 The V 0 -V 7 ) form the spokes of a six-pointed star, where adjacent vectors have a phase difference of sixty (60) degrees. Figure 3 The V shown at the inverter 310 shown in FIG. 7 =(1 1 1)) or all negative (for example, in Figure 3 The V shown at the inverter 320 shown in FIG. 0 =(0 0 0)) output two vectors (V 0 and V 7 ) is called the zero vector and is drawn at the center (origin) of the six-pointed star. The goal of SV-PWM is to produce an "average vector" during the PWM cycle. A PWM cycle means applying a V ref or V out How long. The PWM period is usually equal to the period of the carrier waveform and the current sampling period. Determine V on the star chart ref The position of the sector and constrain the basis vectors of the sector (such as V 1 and V 2 ) together with one of the zero vectors is used to synthesize the desired voltage. This is done by applying V 1 Lasts for a specified time (T 1 ), apply V 2 Lasts for a specified time (T 2 ) and applying a zero vector for a specified time (T 0 ) to provide a voltage equal to V ref or V outIf the DC voltage, reference (or control) signal and carrier (or modulation) signal waveform entering the inverter are known, the amplitude and frequency of the inverter output voltage can be calculated.

[0008] Known SV-PWM and DPWM techniques generally effectively achieve their high-level goals of generating a rotation voltage that does not skip sixty (60) degrees per step, and reducing switching losses by pinning one of the three switching elements during each PWM cycle. However, there remains a need for inverter control methods based on known SV-PWM and DPWM techniques to further reduce inverter switching losses (beyond the reduction achievable through known SV-PWM and DPWM techniques) and to further optimize the performance and reliability of these modulation operations. Summary of the invention

[0009] Embodiments of the present disclosure provide an inverter controller operable to perform inverter controller operations including performing a continuous carrier alignment method on an inverter. The continuous carrier alignment method includes: for a current sampling period, evaluating a shape of a carrier waveform from a previous sampling period; and determining whether to insert an intermediate carrier shape into the carrier waveform during the current sampling period based at least in part on an end position of the carrier waveform from the previous sampling period.

[0010] An embodiment of the present disclosure provides a controller-implemented method, which includes using a processor of the controller to perform a continuous carrier alignment method on an inverter. The continuous carrier alignment method includes: for a current sampling period, evaluating a shape of a carrier waveform from a previous sampling period; and determining whether to insert an intermediate carrier shape into the carrier waveform during the current sampling period based at least in part on an end position of the carrier waveform from the previous sampling period. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a simplified block diagram illustrating a non-limiting example of an electric drive motor system according to aspects of the present disclosure;

[0012] Figure 2 is a simplified diagram illustrating a non-limiting example of a three-phase AC output waveform that may be generated using embodiments of the present disclosure;

[0013] Figure 3 are simplified block diagrams and tables illustrating various aspects of the present disclosure;

[0014] Figure 4 It is a diagram showing various aspects of the present disclosure. Figure 1 A simplified block diagram of a non-limiting example of how an inverter of an electric motor drive system may be implemented as a voltage source inverter is shown in;

[0015] Figure 5 It is to show that the embodiment of the present disclosure can be used Figure 1 and Figure 4 A simplified flow chart of a computer-implemented method implemented by an inverter controller of an electric motor drive system as shown in;

[0016] Figure 6 It is shown that it can be used to execute Figure 5 A simplified hexagonal constellation diagram of the Space Vector Pulse Width Modulation (SV-PWM) technique of the various parts of the computer-implemented method shown in;

[0017] Figure 7 It shows that it can be used to perform Figure 5 Non-limiting examples of equations for portions of the computer-implemented method shown in;

[0018] Figure 8 It is to show how the embodiments according to the present disclosure can be implemented Figure 5 A table of a portion of a computer-implemented method as shown in;

[0019] Fig. 9 is a simplified flow chart showing a PWM alignment mode selection method for preventing discontinuities in a PWM waveform according to an embodiment of the present disclosure, wherein the PWM alignment mode strategy may be Figure 5 A portion of the computer-implemented method shown in ;

[0020] Fig.10 The present invention is used to implement the embodiment of the present invention. Fig. 9 A set of simplified diagrams of PWM alignment mode options of the PWM alignment mode selection method shown in;

[0021] Fig.11A It is to show how the embodiments according to the present disclosure can be implemented Figure 5 A first part of a table of a portion of a computer-implemented method as shown in;

[0022] Fig. 11B It is to show how the embodiments according to the present disclosure can be implemented Figure 5 A portion of the computer-implemented method shown in Fig.11A The second part of the table shown in;

[0023] Fig. 11C is the first part of a table showing how SV-PWM may be implemented;

[0024] Fig.11D is to show how SV-PWM can be implemented Fig. 11C the second part of the table shown in ; and

[0025] Fig.12 is a simplified block diagram illustrating a computer system that is operable to implement embodiments of the present disclosure. DETAILED DESCRIPTION

[0026] Embodiments of the present disclosure provide a novel inverter control method for efficiently and effectively controlling the switching and modulation operations in the inverter for generating alternating current (AC) in an electric motor drive system. In an embodiment of the present disclosure, the electric motor drive system includes: an electric motor, which is operable to receive and use AC; a multi-level three-phase inverter, which is operable to receive direct current (DC) from an energy source and generate AC into a three-phase AC waveform; and an inverter controller, which is operable to control how to generate the three-phase AC waveform at a required frequency and amplitude in a novel manner. In an embodiment of the present disclosure, a novel carrier-based SV-DPWM scheme is used, which selects the clamping state (positive or negative clamping) and the phase leg to be clamped from the three phase legs according to a clamping state selection strategy, which is operable to further reduce the inverter switching losses to more than what can be achieved using known DPWM techniques. The clamp state selection strategy used in the embodiments of the present disclosure is applied to each sector of the SV hexagram, which requires corresponding selection of a carrier waveform that matches the selected clamp state.

[0027] When a clamping state is selected according to a novel clamping state selection strategy, the inverter controller is operable to implement a novel continuous carrier alignment method that selectively inserts an unclamped intermediate duty cycle carrier between given clamping state transitions when needed to ensure that any changes in the carrier waveform occur in a continuous manner. For example, a phase leg clamped to a positive DC rail may require a different carrier waveform than the case where the same phase leg or another phase leg is clamped to a negative DC rail. If the carrier waveform changes too abruptly (e.g., bringing the waveform from a high (or topmost) position to a low (or bottommost) position in less than a predetermined time period required by the associated hardware), the physical switching elements may be unable to execute such a change. Therefore, the novel continuous carrier alignment method selectively inserts a selected type of unclamped intermediate duty cycle carrier between given carrier waveform transitions when needed to avoid abrupt changes that the switching elements cannot execute, thereby ensuring that any changes in the carrier waveform occur in a continuous manner that can be executed by the switching elements.

[0028] When there is a clamp state selection according to aspects of the present disclosure, the inverter controller determines the ending position of the carrier waveform from the previous PWM cycle and also determines the desired ending position of the carrier waveform for the current PWM cycle. If the carrier waveform of the previous PWM cycle ends at a high (or topmost) position (e.g., Fig.10), and if the desired end position of the carrier waveform for the current PWM cycle is the high (or topmost) position (e.g., Fig.10 Similarly, if the carrier of the previous PWM cycle ends at the low (or bottom) position (e.g., Fig.10 ), and if the desired end position of the carrier waveform for the current PWM cycle is the low (or bottom-most) position (e.g., Fig.10 ), no intermediate duty cycle carrier is inserted. However, if the carrier of the previous PWM cycle ended in the high (or topmost) position (e.g., Fig.10 ), and if the desired end position of the carrier waveform for the current PWM cycle is the low (or bottom-most) position (e.g., Fig.10 ), an unclamped mid-duty cycle carrier is inserted to prevent discontinuities in the PWM carrier waveform. For example, when the carrier of the previous PWM cycle ends in a high (or topmost) position (e.g., Fig.10 ), and the desired end position of the carrier of the current PWM cycle is the low (or bottom-most) position (e.g., Fig.10 In the case of the “inverse center” carrier shown in ), an unclamped mid-duty-cycle carrier is inserted (e.g., Fig.10 ) to transition the carrier from its high (or topmost) position to its low (or bottommost) position, thereby avoiding discontinuities in the PWM carrier waveform. Similarly, if the carrier of the previous PWM cycle ended in a low (or bottommost) position (e.g., Fig.10 ), and if the desired end position of the carrier of the current PWM cycle is the high (or topmost) position (e.g., Fig.10 ), an unclamped mid-duty cycle carrier is inserted to prevent discontinuities in the PWM carrier waveform. For example, if the carrier of the previous PWM cycle ends at a low (or bottom) position (e.g., Fig.10 ), and the desired end position of the carrier of the current PWM cycle is the high (or topmost) position (e.g., Fig.10 In the case of a “center” carrier shown in ), an unclamped mid-duty-cycle carrier is inserted (e.g., Fig.10 The “edge” carrier shown in FIG. 10 ) is used to transition the carrier from its low (or bottom-most) position to its high (or top-most) position, thereby avoiding discontinuities in the PWM carrier waveform.

[0029] As previously described, the novel clamping state selection strategy is operable to select a clamping state (positive or negative clamping) and a phase leg to be clamped from the three phase legs in a manner that further reduces inverter switching losses beyond what is achievable using known DPWM techniques. In some embodiments of the present disclosure, the novel clamping state selection strategy is based on a comparison between the current amplitudes of the candidate phase legs. Based on the observation that inverter switching losses are directly related to the amplitude of the phase current, the novel clamping state selection strategy clamps the phase with the highest current amplitude to minimize switching losses and maximize efficiency. For example, referring to SV hexagon 600 ( Figure 6 ), in hexagonal sector zero (0), when |IA| ≥ |IC|, phase A is selected to be clamped to the positive DC rail 402 ( Figure 4 ), otherwise, phase C is clamped to the negative DC rail 404 ( Figure 4 For all hexagonal sectors, the clamp state selection strategy is shown in Table II ( Figure 8 ) is shown in ).

[0030] Turning now to a more detailed description of embodiments of the present disclosure, Figure 1 A system 100 embodying aspects of the present disclosure is depicted. The system 100 includes an energy source 110 electrically coupled to an electric motor drive system 102. Figure 1 In the depicted embodiment, the electric motor drive system 102 includes an inverter 120, an AC motor 130, and an inverter controller 140 configured and arranged as shown. The inverter controller 140 also includes a clamp state strategy module 142 and a continuous carrier module 144. Although the inverter 120, the AC motor 130, and the inverter controller 140 are depicted as separate components, it should be understood that the inverter 120, the AC motor 130, and the inverter controller 140 can be combined in any suitable combination. For example, the inverter controller 140 can be incorporated into the inverter 120; the inverter 120 can be incorporated into the AC motor 130; and / or the inverter 120 and the inverter controller 140 can be incorporated into the AC motor 130.

[0031] The energy source 110 can be implemented in various forms, including, for example, as a battery. In some embodiments, the battery can be a battery pack having one or more individual battery cells connected in series or in parallel in groups, and operated under the control of one or more controllers, such as a battery control module (BCM) that monitors and controls the performance of the battery pack. For example, the BCM can monitor several battery level characteristics, such as the battery current, battery voltage, and battery temperature measured by a current sensor. The battery pack can be recharged by an external power source (not shown). The battery pack can include power conversion electronics that are operable to adjust the power from the external power source to provide the battery pack with appropriate voltage and current levels. The individual battery cells in the battery pack can be composed of various chemical formulas. The battery pack chemistry can include, but is not limited to, lead acid, nickel cadmium (NiCd), nickel-metal hydride (NIMH), lithium ion, or lithium ion polymer.

[0032] The AC motor 130 can be any electric motor design suitable for the work to be performed by the motor. Examples of work that can be done by the motor in conventional automotive-based motor applications include operating or moving power windows; power seats; fans for heaters and radiators; windshield wipers; and / or the engine of a vehicle with a hybrid electric vehicle configuration or a pure electric vehicle configuration. Regardless of the type of AC motor 130, it relies on electromagnetic and moving magnetic fields to generate mechanical power. Conventional implementations of AC motors 130 include four basic parts, namely, a stator; a rotor; a solid shaft, and a coil. The windings of the stator in an AC motor are pairs of electromagnet rings that are energized in sequence, which produce a rotating magnetic field. Induction motors typically use what is called a squirrel cage structure. The squirrel cage structure in an AC motor is a group of rotor bars connected to two rings, one at each end. The squirrel cage rotor goes inside the stator. When AC power is sent through the stator, it generates an electromagnetic field. The bars in the squirrel cage rotor are conductors, so they respond to the movement of the stator poles, which causes the rotor to rotate and generate its own magnetic field. Some AC motors use a wound rotor that is wound with wire rather than a squirrel cage.For permanent magnet motors, magnets are mounted on the surface of or inserted into the rotor core to create a magnetic field.

[0033] The inverter 120 is electrically coupled between the energy source 110 and the AC motor 130 to transfer energy from the energy source 110 to the AC motor 130. In an embodiment of the present disclosure, the inverter 120 is operable to convert the DC voltage received from the energy source 110 into a three-phase AC current required for the AC motor 130 to function. In an embodiment of the present disclosure, the inverter 120 can be a three-phase full-bridge inverter with six switches organized into three "phase legs". Each phase leg can include two switches connected in series and between the positive DC rail and the negative DC rail. At any given moment, up to three inverter switches are turned on, while the other three inverter switches are turned off. The phase node can be positioned between the two switches of each phase leg to provide three phases of the three-phase AC waveform output. Figure 2 An example three-phase AC waveform 200 is depicted in FIG. A single conductor may be coupled to each of the phase nodes to carry AC having the same frequency and voltage amplitude relative to a common reference, but with a phase difference of one-third of a cycle (i.e., 120 degrees out of phase) between each phase node, as shown in FIG. Figure 2 Because of the phase difference, the voltage on any conductor reaches its peak one-third of a cycle after one of the other conductors and one-third of a cycle before the remaining conductor. This phase delay provides constant power transfer to a balanced linear load.

[0034] The inverter controller 140 is operable to control in a novel manner how the inverter 120 generates a three-phase AC waveform at a desired frequency and amplitude. In an embodiment of the present disclosure, the inverter controller 140 includes a clamping state strategy module 142 and a continuous carrier module 144 in accordance with aspects of the present disclosure. The clamping strategy state module 142 is operable to select a clamping state (positive or negative clamping) and a phase leg to be clamped from the three inverter phase legs according to a clamping state selection strategy that is operable to further reduce inverter switching losses beyond what is achievable using known DPWM techniques. The clamping state selection strategy implemented by the module 142 is applied to the SV Hexagram 600 ( Figure 6 ), which requires corresponding selection of a carrier waveform that matches the selected clamping state. In some embodiments of the present disclosure, a novel clamping state selection strategy is based on a comparison between the current amplitudes of the candidate phase legs. Based on the observation that the inverter switching losses are directly related to the amplitude of the phase current, the novel clamping state selection strategy clamps the phase with the highest current amplitude to minimize switching losses and maximize efficiency. For example, referring to SV hexagon 600 ( Figure 6 ), in hexagonal sector zero (0), when |IA| ≥ |IC|, phase A is selected to be clamped to the positive DC rail 402 ( Figure 4 ), otherwise, phase C is clamped to the negative DC rail 404 ( Figure 4Additional details of how the clamp state strategy 142 may be implemented according to embodiments of the present disclosure are provided in Figure 5-11B and described in more detail later herein.

[0035] When a clamping state is selected according to a novel clamping state selection strategy, the inverter controller 140 is operable to implement a novel continuous carrier alignment method using a continuous carrier module 144, which selectively inserts an unclamped intermediate duty cycle carrier between given carrier waveform transitions when needed to ensure that any changes to the carrier waveform occur in a continuous manner. For example, a phase leg clamped to a positive DC rail may require a different carrier waveform than the case where the same phase leg or another phase leg is clamped to a negative DC rail. If the carrier waveform changes too abruptly (e.g., bringing the waveform from a high (or topmost) position to a low (or bottommost) position in less than a predetermined time period required by the associated hardware), the physical switching elements may be unable to execute such a change. Therefore, the novel continuous carrier alignment method selectively inserts a selected type of unclamped intermediate duty cycle carrier between given carrier waveform transitions when needed to avoid abrupt changes that the switching elements may not be able to execute, thereby ensuring that any changes to the carrier waveform occur in a continuous manner that can be executed by the switching elements. Additional details of how the continuous carrier module 144 can be implemented according to embodiments of the present disclosure are described in detail in the accompanying drawings. Figure 5-11B and described in more detail later herein.

[0036] Figure 4 A system 100A is depicted having an energy source 110 electrically coupled to an electric motor drive system 102A. The system 100A is a system 100 (in Figure 1 ), and the electric motor drive system 102A is the electric motor drive system 102 (shown in Figure 1 1. The electric motor drive system 102A may be implemented as a voltage source inverter (VSI) 120A electrically coupled to an inverter controller 140 and an electric motor 130A. The electric motor 130A is an AC motor 130 (in Figure 1 1 and 12. Although the VSI 120A, the motor 130A, and the inverter controller 140 are depicted as separate components, it should be understood that the VSI 120A, the motor 130A, and the inverter controller 140 may be configured and arranged in any suitable combination of components. For example, the inverter controller 140 may be incorporated into the VSI 120A; the VSI 120A may be incorporated into the motor 130A; and / or the VSI 120A and the inverter controller 140 may be incorporated into the motor 130A.

[0037] The VSI 120A is electrically connected to a DC bus formed by a positive DC rail 402 and a negative DC rail 404. The VSI 120A is also electrically connected to a motor 130A, which may be a multi-phase AC electric motor / generator. The inverter controller 140 may be implemented as various types of computing devices (including computers, microprocessors, digital signal processors, etc.) that are configured and operable to execute software commands and programs and may include associated firmware such that the controller is configured and operable to control how the VSI 120A generates a three-phase AC waveform (e.g., Figure 2 In some embodiments of the present disclosure, the inverter controller 140 may also be configured and arranged to include a computing system 1200 ( Fig.12 ) features and functions shown in . The motor 140 may be a permanent magnet synchronous device, an induction motor, etc. The VSI 120A is electrically connected to the energy source 110 via a positive high-voltage DC power bus (HV+) (i.e., a positive DC rail) 402 and a negative high-voltage DC power bus (HV-) (i.e., a negative DC rail) 404. The energy source 110 may be implemented in various forms, including, for example, a high-voltage DC power source, such as a high-voltage battery or capacitor; a high-voltage generator; and / or another related device or system.

[0038] The VSI 120A may include a bus capacitor 442 and a resistor 444 operable to provide noise suppression, load balancing, etc. The VSI 120A includes a plurality of switches 412, 414, 422, 424, 432, 434 organized in switch pairs including an upper switch (e.g., upper switch 412) connected in series with a lower switch (e.g., lower switch 414) and separated by a phase node (e.g., first phase node 416). More specifically, the upper switch 412 and the lower switch 414 are electrically connected at the first phase node 416 and are connected in series with each other between HV+402 and HV-404; the upper switch 422 and the lower switch 424 are electrically connected at the second phase node 426 and are connected in series with each other between HV+402 and HV-404; and the upper switch 432 and the lower switch 434 are electrically connected at the third phase node 436 and are connected in series with each other between HV+402 and HV-404. Each switch pair of the upper / lower switch pairs 412 and 414, 422 and 424, and 432 and 434 defines a phase leg of the VSI 120A and corresponds to a phase of the motor 130A. The nodes 416, 426, and 436 are electrically connected to the nominal first phase, the second phase, and the third phase of the motor 130A to deliver power thereto.

[0039] The upper switches 412, 422, 432 are referred to as high-side switches, and the lower switches 414, 424, 434 are referred to as low-side switches. The first high-side gate drive circuit 406 controls the activation and deactivation of the first high-side switches 412, 422, and 432, and the second low-side gate drive circuit 408 controls the activation and deactivation of the second low-side switches 414, 424, and 434. The first high-side gate drive circuit 406 and the second low-side gate drive circuit 408 include any suitable electronic devices capable of activating and deactivating the upper / lower switches 412 and 414, 422 and 424, and 432 and 434 in response to control signals originating from the inverter controller 140 to cause power transfer between one of the HV+402 and HV-404 and the phase of the motor 130A. The inverter controller 140 generates control signals that are transmitted to the first high-side gate drive circuit 406 and the second low-side gate drive circuit 408 to activate and deactivate the upper / lower switches 412 and 414 , 422 and 424 , and 432 and 434 in response to the inverter switching control mode.

[0040] Each of the upper high-side switches 412, 422, and 432 and the lower low-side switches 414, 424, and 434 can be controlled (e.g., by a command signal from the controller 140 applied to the drive circuits 406, 408) to an on state or an off state. Each of the phase legs formed by the upper / lower switch pairs 412 and 414, 422 and 424, and 432 and 434 can be controlled to a control state of one (1) or zero (0). A control state of one (1) for one of the phase legs corresponds to activation of one of the upper high-side switches 412, 422, and 432, and the corresponding lower low-side switch 414, 424, or 434, respectively, is deactivated (e.g., as shown in FIG. 1 ). Figure 3 310 in FIG. 1 ). A control state of zero (0) in one of the phase legs corresponds to activation of one of the lower low-side switches 414, 424, and 434, and the corresponding upper high-side switch 412, 422, or 432, respectively, is deactivated (e.g., as shown in FIG. 1 ). Figure 3320 of ). Each of the upper high-side switches 412, 422, and 432 is preferably configured as a normally closed switch, which means that the switch conducts current only when activated by the first high-side gate driver 406. In one example, the upper high-side switches 412, 422, and 432 are insulated gate bipolar transistors (IGBTs) each having a diode arranged in parallel. The first high-side gate driver 406 activates each of the upper high-side switches 412, 422, and 432 in response to the selected inverter switch control mode so that current flows therethrough. Each of the lower low-side switches 414, 424, and 434 is typically configured as a normally closed switch, which means that the switch conducts current only when activated by the second low-side gate driver 408. The lower low-side switches 414, 424, and 434 can be any suitable normally closed semiconductor switches, including, for example, IGBT switches each having a diode arranged in parallel. During operation, the first high-side gate drive circuit 406 and the second low-side gate drive circuit 408 generate activation signals to activate and deactivate the upper high-side switches 412, 422, and 432 and the lower low-side switches 414, 424, and 434, thereby operating the motor 130A to generate torque. The VSI 120A is operably electrically connected to the motor 130A, because the action of selectively activating and deactivating the upper / lower switches 412 and 414, 422 and 424, and 432 and 434 in response to the control signal originating from the inverter controller 120A to cause power transfer between one of the HV+ 402 and HV- 404 and the phases of the multi-phase motor 130A induces a magnetic field in elements of the stator of the motor 130A, which acts on elements of the rotor to cause the rotor to move within the stator, thereby inducing torque in a shaft member mechanically coupled to the rotor.

[0041] The inverter controller 120A monitors signal inputs from sensors such as rotational position sensors and voltage and / or current sensors (not shown separately from the motor 130A), and selectively controls the operation of the VSI 120A to perform a novel carrier-based SV-DPWM scheme in accordance with aspects of the present disclosure. The novel carrier-based SV-DPWM includes performing functions associated with a clamped state strategy module 142 and a continuous carrier module 144. Additional details of how the clamped state strategy module 142 and the continuous carrier module 144 may be implemented in accordance with embodiments of the present disclosure are described in detail below. Figure 5-11B and described in more detail below.

[0042] Figure 5 is a simplified flowchart illustrating a computer-implemented method 500 that may be used to drive an electric motor system 102, 102A (in Figure 1 and Figure 4 The inverter controller 120, 120A (shown in Figure 1 and Figure 4 ) is implemented. Method 500 is a non-limiting example implementation of the novel carrier-based SV-DPWM scheme described herein according to aspects of the present disclosure, and includes functions performed by the clamp state strategy module 142 and the continuous carrier module 144. Method 500 starts at box 502 and then moves to box 504, where the inverter controller 140 receives the SV-PWM voltage angle and modulation index command. In general, the voltage angle is essentially the phase of the voltage, and the modulation index (or modulation depth) of the modulation scheme describes how much the modulation variable of the carrier signal varies around its unmodulated level. At box 506, method 500 uses the values ​​received or accessed at box 504 (where MI is the modulation index, and θ V is the SV-PWM voltage angle) and Figure 7 The duty cycle D is calculated using equations (1)-(3) shown in 0 , D 1 , D 2 . refer to Figure 6 SV-PWM hexagonal star diagram 600 depicted in FIG. 6 , conventional SV-PWM is used in a stationary reference frame in a 3-phase 2-level VSI (e.g., Figure 4 When implementing conventional SV-PWM, the control voltage vector V ref Rotate within the PWM voltage limit hexagon 600. The vectors from the center of the hexagon 600 to each vertex of the hexagon 600 represent the magnitude and phase of the stationary frame voltage applied for all possible active switching states of the inverter (labeled V1 to V6). The center of the hexagon 600 represents the inverter (e.g., Figure 4 The VSI 120A shown in FIG. 1 has a zero voltage output and is connected to the lower DC voltage rail 404 ( Figure 4 ) (i.e., Figure 3 V shown at 320 0 =(000)) or all three phases are connected to the upper DC voltage rail 402 ( Figure 4 ) (i.e., Figure 3 V shown at 310 7 =(111)). These states are Figure 6 In the 0 and V 7 By setting V ref Projection to Figure 6 The ratio of the time spent in the adjacent switching states to the duration of the entire PWM cycle for the two adjacent switching state vectors V1 and V2 shown is the duty cycle D 0 , D1 , D 2 , and can be used Figure 7 is determined using equations (1)-(3) shown.

[0043] At block 508, method 500 determines whether an inverter (eg, Figure 4 The inverter 120A shown in FIG. 1 is to be clamped for the novel version of DPWM in the phase leg, and further determines that the phase leg selected to be clamped is to be clamped to the positive DC rail (eg, Figure 4 ) or a negative DC rail (eg, Figure 4 In an embodiment of the present disclosure, the operation at block 508 corresponds to the operation of the clamp state strategy module 142 ( Figure 1 The conventional CPWM will use equations (1)-(3) ( Figure 7 The calculated D 0 , D 1 and D 2 A duty cycle is applied to each phase so that all three (3) inverter phases undergo switching state changes when operating using CPWM. In addition, when operating using CPWM, each PWM cycle utilizes two zero voltage states (V 0 、V 7 According to aspects of the present disclosure, to reduce switching losses from CPWM, one of the phases may be clamped to the positive DC rail of the inverter (e.g., VSI 120A) for the entire PWM cycle (e.g., Figure 4 ) or a negative DC rail (e.g., Figure 4 In this case, only three (3) phases are switched per PWM cycle (i.e., Figure 3 A, B, or C) shown at 330 in Table I of FIG. 1 and utilizing only one (1) of the zero vectors (i.e., V 0 or V 7 ). In each hexagonal sector ( Figure 6 In sectors 0, 1, 2, 3, 4, 5) shown in , there is one (1) phase that must be switched. For example, in hexagonal sector zero (0), because the adjacent hexagonal vertex is V 1 (100) and V 2 (110), so phase B must be switched. This leaves the need to clamp phase A to the positive DC rail for the entire PWM cycle (and then use V 7 as a zero vector state) or clamping Phase C to the negative DC rail for the entire PWM cycle (and then using V 0 As an option for zero vector state). Because the switching loss is related to the amplitude of the phase current ( Figure 2 and Figure 4 IA, IB or IC) shown in FIG, so the clamp state strategy module 142 ( Figure 1 ) is operable to determine the phase with the highest current amplitude and clamp the phase leg associated with the highest phase current amplitude (i.e., the phase leg will not be switched on or off during the PWM cycle) as a scheme to minimize switching losses and maximize efficiency. For example, in hexagonal sector zero (0), when |IA| ≥ |IC|, phase A is selected to be clamped to the positive DC rail, otherwise, phase C is clamped to the negative DC rail. Figure 8 This clamp state selection strategy is shown in Table II for all hexagonal sectors.

[0044] At box 510, the method 500 uses the clamp state selection determined at box 508 to determine the PWM alignment mode (PWM-AM). In the embodiment of the present disclosure, PWM-AM refers to the carrier waveform that will be used to perform the novel "continuous carrier" implementation of carrier-based DPWM. As previously described, carrier-based PWM is a modulation scheme that provides low harmonic distortion characteristics and simple implementation by comparing a reference (or control) signal with a carrier (or modulation) signal in each phase leg of the inverter. Whenever these two signals (reference signal / carrier signal) cross, the associated inverter switching element is turned on or off. The carrier signal is typically a sawtooth signal or a triangular signal with a desired switching frequency. In conventional carrier-based PWM implementations, one triangular carrier signal is used to modulate all three phase legs in a three-phase VSI because its symmetrical switching sequence results in lower power losses and lower THD. However, for the embodiment of the present disclosure where the novel clamp state determination performed at box 508 results in a change in the clamp state, an unclamped intermediate duty cycle carrier is inserted to prevent discontinuity in the carrier waveform used in the PWM scheme. When inserting an unclamped mid-duty cycle carrier to prevent unwanted PWM pulses, a specific PWM carrier alignment pattern is manipulated based on the clamping state. Fig.10 These alignment modes are depicted in Fig. 9 The method 900 shown in can be used to implement the alignment determination strategy. In an embodiment of the present disclosure, the method 900 can be Figure 1 The continuous carrier module 144 is shown to execute.

[0045] Now refer to Fig.10 PWM-AM utilized in various aspects of the present disclosure is described. Fig.10Organized into four (4) quadrants, labeled Q1, Q2, Q3, and Q4. Each quadrant Q1, Q2, Q3, Q4 depicts a leftmost graph and a rightmost graph. The leftmost graph plots the movement of the reference signal (i.e., duty cycle) and the carrier signal of each phase A, B, C over time (i.e., within the duration of a given PWM cycle); while the rightmost graph plots the corresponding on / off state of each phase A, B, C over time (i.e., within the duration of a given PWM cycle). Fig.10 The figures depicted in provide examples of carrier waveforms and corresponding on / off states when a random duty cycle is provided. In the leftmost figure, when the reference signal is higher than the carrier signal, the corresponding phase is turned on (conducting), and when the reference signal is lower than the carrier signal, the corresponding phase is disconnected (not conducting). This relationship defines the duty cycle of a given phase and is reflected by the (one or more) duty cycles shown in the rightmost figure. In Q1, the PWM-AM is identified as a "center" PWM-AM. In Q2, the PWM-AM is identified as an "inverse center" PWM-AM. In Q3, the PWM-AM is an intermediate duty cycle carrier identified as an "edge" PWM-AM. In Q4, the PWM-AM is an intermediate duty cycle carrier identified as an "inverse edge" PWM-AM. A phase leg clamped to a positive DC rail may require a different carrier waveform than the case where the same phase leg or another phase leg is clamped to a negative DC rail. If the carrier waveform changes too abruptly (e.g., bringing the carrier waveform from a high (or topmost) position to a low (or bottommost) position in less than a predetermined period of time required by the associated hardware), the physical switch element may be unable to perform the change. Fig. 9 ) and described in more detail below) selectively inserts a selected type of unclamped intermediate duty cycle carrier (edge, anti-edge) between given carrier waveform transitions when necessary to avoid abrupt changes that the switching element cannot execute, thereby ensuring that any changes in the carrier waveform occur in a continuous manner that can be executed by the switching element.

[0046] Using the clamp state selection determined at block 508, at block 510, the inverter controller 140 (at Figure 1 ) of the continuous carrier module 144 (shown in Figure 1 ) determines the ending position of the carrier waveform from the previous PWM cycle, and also determines the expected ending position of the carrier waveform of the current PWM cycle. If the carrier waveform of the previous PWM cycle ends at a high (or topmost) position (e.g., Fig.10 ), and if the desired end position of the carrier waveform for the current PWM cycle is the high (or topmost) position (e.g., Fig.10Similarly, if the carrier of the previous PWM cycle ends at the low (or bottom) position (e.g., Fig.10 ), and if the desired end position of the carrier waveform for the current PWM cycle is the low (or bottom-most) position (e.g., Fig.10 ), no intermediate duty cycle carrier is inserted. However, if the carrier of the previous PWM cycle ended in the high (or topmost) position (e.g., Fig.10 ), and if the desired end position of the carrier waveform for the current PWM cycle is the low (or bottom-most) position (e.g., Fig.10 ), an unclamped mid-duty cycle carrier is inserted to prevent discontinuities in the PWM carrier waveform. For example, when the carrier of the previous PWM cycle ends in a high (or topmost) position (e.g., Fig.10 ), and the desired end position of the carrier of the current PWM cycle is the low (or bottom-most) position (e.g., Fig.10 In the case of the “inverse center” carrier shown in ), an unclamped mid-duty-cycle carrier is inserted (e.g., Fig.10 ) to transition the carrier from its high (or topmost) position to its low (or bottommost) position, thereby avoiding discontinuities in the PWM carrier waveform. Similarly, if the carrier of the previous PWM cycle ended in a low (or bottommost) position (e.g., Fig.10 ), and if the desired end position of the carrier of the current PWM cycle is the high (or topmost) position (e.g., Fig.10 ), an unclamped mid-duty cycle carrier is inserted to prevent discontinuities in the PWM carrier waveform. For example, if the carrier of the previous PWM cycle ends at a low (or bottom) position (e.g., Fig.10 ), and the desired end position of the carrier of the current PWM cycle is the high (or topmost) position (e.g., Fig.10 In the case of a “center” carrier shown in ), an unclamped mid-duty-cycle carrier is inserted (e.g., Fig.10 The “edge” carrier shown in FIG. 10 ) is used to transition the carrier from its low (or bottom-most) position to its high (or top-most) position, thereby avoiding discontinuities in the PWM carrier waveform.

[0047] Fig. 9 A non-limiting example method 900 is depicted that may be used to utilize the continuous carrier module 144 (in Figure 1 ) to implement the method 500 (in Figure 5The method 900 starts at block 902 and then moves to decision block 904, where it is inquired whether block 508 of the method 500 has selected a positive clamp for the phase leg to be clamped for the current PWM cycle (e.g., as Figure 8 ). If the answer to the inquiry at decision box 904 is true (T), positive clamping is selected at box 508 of method 500, which means that the carrier will generally be an inverse center carrier. Decision box 906 evaluates whether the PWM-AM in the previous sample (k-1, where k is the current sample) is an inverse center or an inverse edge, both of which end in a low (or bottommost) position. If the answer to the inquiry at decision box 906 is true (T), box 908 determines that the PWM-AM for the current sample k should be an inverse center, which starts in a low (or bottommost) position, thereby providing a continuous carrier when moving from the k-1 sample to the k sample. If the answer to the inquiry at decision box 906 is false (F), the PWM-AM in the previous sample k-1 is neither an inverse center nor an inverse edge, which means that the k-1 carrier ends in a high (or topmost) position. In the case where the k-1 carrier ends at a high (or topmost) position, block 910 determines that the PWM-AM for the current sample k should be an inverse edge, which starts at a high (or topmost) position, thereby providing a continuous carrier when moving from the k-1 sample to the k sample. The inverse edge PWM-AM also ends at a low (or bottommost) position. This is ready for the next sampling moment, assuming that decision block 904 will return true again. Therefore, decision block 906 is F at (k), but will be expected to return T at (k+1).

[0048] Returning to decision box 904, if the answer to the inquiry at decision box 904 is false (F), then negative clamping is selected at box 508 of method 500, which means that the carrier will usually be a center carrier. Decision box 912 evaluates whether the PWM-AM in the previous sample k-1 is the center or the edge, both of which end in a high (or topmost) position. If the answer to the inquiry at decision box 912 is true (T), then box 914 determines that the PWM-AM for the current sample k should be the center, which starts at a high (or topmost) position, thereby providing a continuous carrier when moving from the k-1 sample to the k sample. If the answer to the inquiry at decision box 912 is false (F), the PWM-AM in the previous sample k-1 is neither the center nor the edge, which means that the k-1 carrier ends in a low (or bottommost) position. In the case where the k-1 carrier ends at a low (or bottom) position, box 916 determines that the PWM-AM for the current sample k should be an edge, which starts at a low (or bottom) position, thereby providing a continuous carrier when moving from the k-1 sample to the k sample. The edge PWM-AM also ends at a high (or top) position. This is ready for the next sampling moment, assuming that the decision box 904 will return true again. Therefore, the decision box 912 is F at (k), but it will be expected to return T at (k+1). From any one of the boxes 908, 910, 914, 916, the method 900 moves to box 920 and ends.

[0049] Now return to Figure 5 In the method 500 shown in FIG. 5 , after block 510 , at block 512 , the method 500 is performed according to Fig.11A , Fig. 11B The duty cycle D calculated at block 506 is calculated as shown in Table III. 0 , D 1 , D 2 is applied to each phase A, phase B, and phase C. At block 514, the inverter controller 140 generates a PWM voltage to control the inverter 120, 120A using the calculations at Table III to generate an AC waveform having minimized switching losses (beyond what is achievable with conventional DPWM) and continuous carrier transitions that avoid glitches that occur from switching the carrier waveform in less time than is required by the associated switching hardware. More specifically, as shown under the column "Duty Cycle X", considering a hexagonal sector, the continuous carrier module 144 ( Figure 1 ) and the PWM-AM generated by the clamp state selection module 142 ( Figure 1 The result of the clamp state selection analysis performed as shown in Figure 1 is used to apply the duty cycle D 0 , D 1 , D 2 .

[0050] Fig. 11C and Fig.11D Table IV is depicted, which is a method for determining the Fig.11A and Fig. 11B Examples of starting points for duty cycles A, B, C are shown under the column "Duty Cycle X" in FIG. Fig. 11C and Fig.11D Table IV shows the results based on 6 different hexagonal sectors using equations (1)-(3) ( Figure 7 For DPWM, the duty cycles A, B, and C are calculated for the generated Table IV ( Fig. 11C and Fig.11D The strategy shown in Table III is modified to Fig.11A , Fig. 11B ) to be compatible with both positive and negative rail clamping. Using sector zero (0) (case 0) as an example, it can be observed from Table III that when clamping to the negative rail is required, the duty cycle C should always be zero (0) instead of 0.5*D0, and the duty cycle B=D 2 + Duty cycle C(0) = D2, Duty cycle A is still equal to Duty cycle B + D 1 Similarly, when clamping to positive rail is required, duty cycle A should always be 1 instead of duty cycle B+D. 1 , duty cycles B and C should be calculated based on duty cycle A, and then duty cycle B becomes duty cycle A(1)-D 1 , and the duty cycle C is the duty cycle BD 2 When inserting unclamped intermediate duty cycle carriers (edge ​​carrier and inverse edge carrier), the CPWM duty cycle calculation can still be used since there is no clamping.

[0051] Fig.12 An example of a computer system 1200 that can be used to implement computer-based components in accordance with various aspects of the present disclosure is shown. The computer system 1200 includes an exemplary computing device ("computer") 1202 that is configured to perform various aspects of the content-based semantic monitoring operations described herein in accordance with various aspects of the present disclosure. In addition to the computer 1202, the exemplary computer system 1200 also includes a network 1214 that connects the computer 1202 to additional systems (not depicted) and can include one or more wide area networks (WANs) and / or local area networks (LANs), such as the Internet, (one or more) intranets, and / or (one or more) wireless communication networks. The computer 1202 and the additional systems communicate via the network 1214, for example, to transfer data between them.

[0052] The exemplary computer 1202 includes a processor core 1204, a main memory ("memory") 1210, and input / output component(s) 1212, which communicate via a bus 1203. The processor core 1204 includes a cache memory ("cache") 1206 and a control 1208, which includes a branch prediction structure and associated search, hit, detection, and update logic, which will be described in more detail below. The cache 1206 may include multiple cache levels (not depicted) on-chip or off-chip of the processor 1204. The memory 1210 may include various data stored therein, such as instructions, software, routines, etc., which may be transferred to / from the cache 1206 by the control 1208, for example, for execution by the processor 1204. The input / output component(s) 1212 may include one or more components that facilitate local and / or remote input / output operations to / from the computer 1202, such as a display, keyboard, modem, network adapter, etc. (not depicted).

[0053] The cloud computing system 50 is in wired or wireless electronic communication with the computer system 1200. The cloud computing system 50 can supplement, support or replace some or all functions (in any combination) of the computer system 1200. In addition, some or all functions of the computer system 1200 can be implemented as nodes of the cloud computing system 50.

[0054] Therefore, it can be seen from the foregoing detailed description that embodiments of the present disclosure provide a novel inverter control method for efficiently and effectively controlling inverter switching and modulation operations for generating alternating current (AC) in an electric motor drive system. More specifically, embodiments of the present disclosure provide improvements to known DPWM schemes. In general, DPWM can be implemented in an electric motor drive system to reduce switching losses because, compared to three (3) switches that can be turned on and off in one switching cycle when using CPWM, only two (2) switches are turned on and off in one switching cycle using DPWM. In the novel inverter control method, in each of the SVPWM hexagonal sectors, by comparing the current amplitudes of two (2) of the three (3) phases, the DPWM zero voltage vector is determined to be clamped to the positive DC rail or the negative DC rail to minimize switching losses and maximize the efficiency of the inverter. In addition, when switching the clamping mode, the PWM carrier alignment is manipulated according to embodiments of the present disclosure to ensure continuous switching states.

[0055] To reduce switching losses from the CPWM strategy, embodiments of the present disclosure clamp one of the phases to the positive or negative DC rail throughout the PWM cycle. In this case, only two (2) of the three (3) phases (i.e., A, B, or C) are switched per PWM cycle and only one of the zero vectors (i.e., V0 or V 7 ). In each SVPWM hexagonal sector, there is one phase that must be switched. For example, in hexagonal sector zero (0), since the adjacent hexagonal vertex is V 1 (100) and V 2 (110), so phase B must be switched. This leaves the need to clamp phase A to the positive DC rail for the entire PWM cycle (and then use V 7 as a zero (0) vector state) or clamping Phase C to the negative DC rail for the entire PWM cycle (and subsequently using V 0 As an option for the zero (0) vector state). Utilizing the inventors' observation that switching losses are directly related to the amplitude of the phase current, clamping the phase with the highest current amplitude can be utilized in accordance with aspects of the present disclosure to minimize switching losses and maximize efficiency. For example, in hexagonal sector zero (0), when |IA|≥|IC|, phase A is selected to be clamped to the positive DC rail. Otherwise, phase C is clamped to the negative DC rail. This selection strategy is shown for all hexagonal sectors in Table II.

[0056] In addition to the clamp state determination, when there is a clamp state change, an unclamped intermediate duty cycle carrier is inserted to prevent discontinuities in the PWM waveform. When inserting the intermediate duty cycle carrier, in order to prevent undesired PWM pulses, specific PWM carrier alignment patterns are manipulated based on the clamp state. These alignment patterns are Fig.10 and the alignment determination strategy is depicted in Fig. 9 By using Table II ( Figure 8 ) to determine the PWM clamp and use Fig. 9 Determine the PWM carrier alignment and according to Table III ( Fig.11A and Fig. 11B The D calculated in equations (1)-(3) is 0 , D 1 and D 2 Applied to each phase to implement a complete DPWM strategy.

[0057] Many functional units of the system described in this specification have been labeled as modules. Embodiments of the present disclosure are applicable to a variety of module implementations. For example, a module can be implemented as a hardware circuit including a custom VLSI circuit or gate array, a ready-made semiconductor such as a logic chip, a transistor or other discrete components. A module can also be implemented in a programmable hardware device such as a field programmable gate array, a programmable array logic, a programmable logic device, etc. A module can also be implemented in software for execution by various types of processors. For example, a module of an identified executable code may include one or more physical or logical blocks of computer instructions, which may be organized, for example, as an object, a process or a function. However, the executable file of the identified module does not need to be physically located together, but may include different instructions stored in different locations, which, when logically connected together, serve as a module and implement the purpose of the module.

[0058] For ease of illustration and explanation, the various components / modules / models of the system shown herein are depicted separately. In the embodiments of the present disclosure, unless otherwise specifically stated, the functions performed by the various components / modules / models may be distributed differently than shown without departing from the scope of the various embodiments of the present disclosure described herein.

[0059] Various embodiments of the present disclosure are described herein with reference to the relevant drawings. Without departing from the scope of the present disclosure, alternative embodiments of the present disclosure may be designed. In the following description and the accompanying drawings, various connections and positional relationships (e.g., above, below, adjacent, etc.) are described between elements. Unless otherwise indicated, these connections and / or positional relationships may be direct or indirect, and the present disclosure is not intended to be limited in this respect. Therefore, the coupling of entities may refer to direct or indirect coupling, and the positional relationship between entities may be direct or indirect positional relationship. In addition, the various tasks and process steps described herein may be incorporated into a more comprehensive program or process with additional steps or functions not described in detail herein.

[0060] In some embodiments, various functions or actions can occur at a given location and / or occur in association with the operation of one or more devices or systems. In some embodiments, a portion of a given function or action can be performed at a first device or location, and the remainder of the function or action can be performed at one or more additional devices or locations.

[0061] The terms used herein are only used for the purpose of describing specific embodiments and are not restrictive. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when used in this specification, the terms "include" and / or "comprise" specify the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups thereof.

[0062] The corresponding structures, materials, actions, and equivalents of all means or step-plus-function elements in the following claims are intended to include any structure, material, or action for performing a function in conjunction with other claimed elements specifically claimed. The present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosed forms. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the present disclosure. The embodiments are selected and described in order to best explain the principles and practical applications of the present disclosure, and to enable those of ordinary skill in the art to understand the present disclosure of various embodiments with various modifications suitable for the intended specific use.

[0063] The figures depicted herein are illustrative. Without departing from the spirit of the present disclosure, there may be many variations of the figures or steps (or operations) described therein. For example, actions may be performed in different orders, or actions may be added, deleted, or modified. In addition, the term "coupled" describes having a signal path between two elements, and does not mean a direct connection between elements without an intermediate element / connection therebetween. All of these variations are considered to be a part of the present disclosure.

[0064] The following definitions and abbreviations will be used to interpret the claims and specification. As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," "contains," or "containing" or any other variation thereof are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that includes a list of elements is not necessarily limited to only those elements but may include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.

[0065] Additionally, the term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" should be understood to include any integer greater than or equal to one, i.e., one, two, three, four, etc. The term "plurality" is understood to include any integer greater than or equal to two, i.e., two, three, four, five, etc. The term "connected" may include both indirect "connections" and direct "connections."

[0066] The terms "about," "substantially," "approximately," and variations thereof are intended to include the degree of error associated with the measurement of a particular quantity based on the equipment available at the time the application was filed. For example, "about" may include a range of ±8% or 5% or 2% of a given value.

[0067] Aspects of the present disclosure may be embodied as systems, methods, and / or computer program products at any possible level of technical detail integration. A computer program product may include a computer-readable storage medium (or multiple media) having computer-readable program instructions thereon for causing a processor to perform aspects of the present disclosure.

[0068] A computer-readable storage medium may be a tangible device that can retain and store instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disc (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a raised structure in a groove on which instructions are recorded, and any suitable combination of the foregoing. The computer-readable storage medium used herein should not be interpreted as a transient signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated through a waveguide or other transmission medium (e.g., a light pulse through a fiber optic cable), or an electrical signal transmitted through a wire.

[0069] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded to an external computer or external storage device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network). The network can include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in a computer-readable storage medium in the corresponding computing / processing device.

[0070] The computer-readable program instructions for performing the operation of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, configuration data of integrated circuits, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, and process programming languages ​​such as "C" programming language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as an independent software package, partially on the user's computer and partially on a remote computer or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network (including a local area network (LAN) or a wide area network (WAN)), or may be connected to an external computer (e.g., using an Internet service provider via the Internet). In some embodiments, the electronic circuit including, for example, a programmable logic circuit, a field programmable gate array (FPGA) or a programmable logic array (PLA) may be executed by using the state information of the computer-readable program instructions to personalize the electronic circuit to execute the computer-readable program instructions, so as to perform various aspects of the present disclosure.

[0071] Various aspects of the present disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, devices (systems) and computer program products according to embodiments of the present disclosure. It should be understood that each block of the flowchart illustration and / or block diagram and the combination of blocks in the flowchart illustration and / or block diagram can be implemented by computer-readable program instructions.

[0072] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device create a device for implementing the functions / actions specified in one or more boxes of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, which can instruct the computer, programmable data processing device, and / or other device to function in a specific manner, so that the computer-readable storage medium having the instructions stored therein includes an article of manufacture, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0073] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing device, or other apparatus, so that a series of operational steps are performed on the computer, other programmable device, or other apparatus to produce a computer-implemented process, so that the instructions executed on the computer, other programmable device, or other apparatus implement the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0074] The flow charts and block diagrams in the accompanying drawings illustrate the possible implementation architectures, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flow chart or block diagram may represent a module, segment or part of an instruction, which includes one or more executable instructions for implementing a specified logical function. In some alternative embodiments, the functions indicated in the box may not occur in the order indicated in the figure. For example, the two boxes shown in succession can actually be executed substantially simultaneously, or these boxes can sometimes be executed in reverse order, depending on the functions involved. It will also be noted that each box illustrated in the block diagram and / or flow chart and the combination of boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs a specified function or action or performs a combination of dedicated hardware and computer instructions.

[0075] The description of various embodiments of the present disclosure has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, practical applications, or technical improvements to technologies found in the marketplace, or to enable those of ordinary skill in the art to understand the embodiments described herein.

[0076] Although the present invention has been described with reference to exemplary embodiments, it will be appreciated by those skilled in the art that various changes may be made and elements thereof may be replaced with equivalents without departing from the scope of the present invention. In addition, many modifications may be made to adapt specific circumstances or materials to the teachings of the present invention without departing from the essential scope of the present invention. Therefore, it is intended that the present invention is not limited to the specific embodiments disclosed as the best mode for carrying out the present invention, but that the present invention will include all embodiments falling within the scope of the claims.

Claims

1. An inverter controller, the inverter controller being operable to perform an inverter controller operation, the inverter controller operation comprising: A continuous carrier alignment method is performed on an inverter, the continuous carrier alignment method comprising: For a current sampling period, evaluating the shape of the carrier waveform from a previous sampling period; and Whether to insert an intermediate carrier shape into the carrier waveform during the current sampling period is determined based at least in part on an ending position of the carrier waveform from the previous sampling period.

2. The inverter controller according to claim 1, wherein: The inverter controller operation also includes calculating a three-phase duty cycle based at least in part on a carrier waveform of the current sampling period.

3. The inverter controller according to claim 1, wherein: The height of the ending position of the carrier waveform from the previous sampling period is substantially the same as the height of the starting position of the carrier waveform during the current sampling period.

4. The inverter controller according to claim 3, wherein: Determining whether to insert the intermediate carrier shape includes determining not to insert the intermediate carrier shape into the carrier waveform during the current sampling period.

5. The inverter controller according to claim 1, wherein: The height of the ending position of the carrier waveform from the previous sampling period is different from the height of the starting position of the carrier waveform during the current sampling period.

6. The inverter controller according to claim 5, wherein: Determining whether to insert the intermediate carrier shape includes determining to insert the intermediate carrier shape into the carrier waveform during the current sampling period.

7. The inverter controller according to claim 6, wherein: The height of the ending position of the carrier waveform from the previous sampling period is substantially the same as the height of the starting position of the intermediate carrier waveform.

8. The inverter controller according to claim 7, wherein: The height of the ending position of the intermediate carrier waveform is substantially the same as the height of the starting position of the carrier waveform during the current sampling period.

9. The inverter controller according to claim 1, wherein: The inverter comprises a plurality of phase legs; and The inverter controller operation also includes executing a clamping state selection method, the clamping state selection method including selecting one of the plurality of phase legs as a phase leg to be clamped.

10. The inverter controller according to claim 9, wherein: The clamp state selection method further includes selecting one of the plurality of phase legs as a phase leg to be clamped based at least in part on a comparison of current amplitudes associated with the plurality of phase legs; as well as Determining whether to insert the intermediate carrier shape into the carrier waveform during the current sampling period is also based at least in part on a result of the comparison of current amplitudes associated with the plurality of phase legs.

11. A controller-implemented method, comprising: A continuous carrier alignment method is performed on an inverter using a processor of a controller, the continuous carrier alignment method comprising: For a current sampling period, evaluating the shape of the carrier waveform from a previous sampling period; and Whether to insert an intermediate carrier shape into the carrier waveform during the current sampling period is determined based at least in part on an ending position of the carrier waveform from the previous sampling period.

12. The controller-implemented method of claim 11 , further comprising: The three-phase duty cycles are calculated based at least in part on the carrier waveform of the current sampling period.

13. The controller-implemented method of claim 11, wherein: The height of the ending position of the carrier waveform from the previous sampling period is substantially the same as the height of the starting position of the carrier waveform during the current sampling period.

14. The controller-implemented method of claim 13, wherein: Determining whether to insert the intermediate carrier shape includes determining not to insert the intermediate carrier shape into the carrier waveform during the current sampling period.

15. The controller-implemented method of claim 11, wherein: The height of the ending position of the carrier waveform from the previous sampling period is different from the height of the starting position of the carrier waveform during the current sampling period.

16. The controller-implemented method of claim 15, wherein: Determining whether to insert the intermediate carrier shape includes determining to insert the intermediate carrier shape into the carrier waveform during the current sampling period.

17. The controller-implemented method of claim 16, wherein: The height of the ending position of the carrier waveform from the previous sampling period is substantially the same as the height of the starting position of the intermediate carrier waveform.

18. The controller-implemented method of claim 17, wherein: The height of the ending position of the intermediate carrier waveform is substantially the same as the height of the starting position of the carrier waveform during the current sampling period.

19. The controller-implemented method of claim 11, wherein: The inverter comprises a plurality of phase legs; and The inverter controller operation also includes executing a clamping state selection method, the clamping state selection method including selecting one of the plurality of phase legs as a phase leg to be clamped.

20. The controller-implemented method of claim 19, wherein: The clamp state selection method further includes selecting one of the plurality of phase legs as a phase leg to be clamped based at least in part on a comparison of current amplitudes associated with the plurality of phase legs; as well as Determining whether to insert the intermediate carrier shape into the carrier waveform during the current sampling period is also based at least in part on a result of the comparison of current amplitudes associated with the plurality of phase legs.

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