Signal frequency multiplication method and device, storage medium and electronic equipment
By measuring and finely adjusting the frequency of the frequency multiplier signal in real time, using the coarse and fine adjustment delay module and the binary search method, the problems of design complexity, extended locking time and high power consumption in PLL technology are solved, and the frequency control of fast locking, low power consumption and high precision is achieved.
Patent Information
- Application Number
- CN202411987017.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2025-04-29
AI Technical Summary
The existing PLL technology has problems such as design complexity, extended lock time and high power consumption in the frequency synthesis and frequency doubling process, which limits its application in high-speed communication and dynamic frequency adjustment systems.
By measuring the actual frequency of the frequency doubling signal in real time, and using the coarse and fine adjustment delay modules to perform frequency adjustment, combining the binary search method to quickly determine the optimal gear, achieving fine and accurate frequency control.
This method can quickly shorten the lock time of the system, improve frequency stability and response speed, and reduce power consumption, and is suitable for high-speed communication and dynamic frequency adjustment systems.
Smart Images
Figure CN119906369A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of signal processing, and in particular to a signal frequency multiplication method, device, storage medium and electronic equipment. Background Art
[0002] In modern electronic systems, frequency synthesis and signal multiplication technologies play a vital role. They are the basis for achieving precise clock generation, communication signal processing, and the functions of various electronic devices. Phase-Locked Loop (PLL), as a widely used frequency synthesis and multiplication technology, has shown significant advantages in wireless communication, clock recovery, data synchronization and other fields with its high frequency stability and low phase noise. PLL can achieve phase locking of the input reference signal through the core modules such as the internal phase detector (PD), loop filter (LF) and voltage-controlled oscillator (VCO), and generate an output signal with the required frequency and phase characteristics.
[0003] However, despite the excellent performance of PLL technology in frequency synthesis, its inherent design complexity and limitations cannot be ignored. First, the design of the PLL system involves multiple interrelated and highly sensitive modules, including precise phase detection mechanism, loop filter design, and VCO control strategy. The parameter tuning requirements between these modules are extremely high, and any slight deviation may lead to system performance degradation, such as increased phase error and impaired stability, which increases the difficulty and cost of system design.
[0004] Secondly, the lock time of the PLL is an important performance indicator, which determines the time required for the system to reach a stable state after startup or frequency switching. Especially in the case of high multiplication factors, the lock time of the PLL is significantly extended because the loop takes longer to adjust the output frequency of the VCO to match the phase of the input reference signal. This feature limits the applicability of the PLL in application scenarios that require fast frequency changes or instant response, such as some high-speed communication systems and dynamic frequency adjustment systems.
[0005] In addition, power consumption is also a major challenge facing PLL technology. As modern electronic systems have increasingly higher requirements for energy efficiency, low-power design has become an important consideration. However, due to its complex circuit structure and continuous operation characteristics, PLL usually has high power consumption, which is a disadvantage that cannot be ignored for battery-powered portable devices or systems with strict power consumption restrictions. Summary of the invention
[0006] The embodiments of the present application provide a signal frequency multiplication method, device, storage medium and electronic device, which can solve the problem of frequency multiplication of reference clock signals in the prior art. The technical solution is as follows:
[0007] In a first aspect, an embodiment of the present application provides a signal frequency doubling method, the method comprising:
[0008] Real-time measurement of the actual frequency of the output frequency-multiplied signal; the frequency-multiplied signal is generated by frequency-multiplied processing of the input reference clock signal;
[0009] If the current actual frequency is not equal to the target frequency, the deviation value between the current actual frequency and the target frequency is calculated, and based on the deviation value, a binary search method is used to determine the optimal coarse adjustment gear position among multiple coarse adjustment gear positions of the coarse adjustment delay module; the coarse adjustment delay module is used to perform signal delay processing, and the coarse adjustment delay module includes multiple coarse adjustment delay units, and different coarse adjustment gear positions correspond to different numbers of coarse adjustment delay units;
[0010] Under the optimal coarse adjustment gear, determining whether the current actual frequency is equal to the target frequency;
[0011] If yes, end the adjustment process;
[0012] If not, calculate the deviation value between the current actual frequency and the target frequency, and determine the optimal fine-tuning gear position from multiple fine-tuning gear positions of the fine-tuning delay module using a binary search method based on the deviation value; the fine-tuning delay module is connected in series with the coarse-tuning delay module, the coarse-tuning delay module is used to perform signal delay processing, the fine-tuning delay module includes multiple fine-tuning delay units, and different fine-tuning gear positions correspond to different numbers of fine-tuning delay units.
[0013] In a second aspect, an embodiment of the present application provides a digital frequency multiplier, including:
[0014] A measuring unit, used for measuring in real time the actual frequency of the output frequency-multiplied signal; the frequency-multiplied signal is generated by frequency-multiplied processing of the input reference clock signal;
[0015] A coarse control unit, used for calculating the deviation between the current actual frequency and the target frequency if the current actual frequency is not equal to the target frequency, and determining the optimal coarse adjustment gear position from among the multiple coarse adjustment gear positions of the coarse adjustment delay module by using a binary search method based on the deviation value; the coarse adjustment delay module is used for performing signal delay processing, and the coarse adjustment delay module includes multiple coarse adjustment delay units, and different coarse adjustment gear positions correspond to different numbers of coarse adjustment delay units;
[0016] A judging unit, used to judge whether the current actual frequency is equal to the target frequency under the optimal coarse adjustment gear;
[0017] An end unit, used for ending the adjustment process if the answer is yes;
[0018] A fine control unit is used to calculate the deviation value between the current actual frequency and the target frequency if the answer is no, and to determine the optimal fine adjustment gear position from multiple fine adjustment gear positions of the fine adjustment delay module by using a binary search method based on the deviation value; the fine adjustment delay module is connected in series with the coarse adjustment delay module, the coarse adjustment delay module is used to perform signal delay processing, the fine adjustment delay module includes multiple fine adjustment delay units, and different fine adjustment gear positions correspond to different numbers of fine adjustment delay units.
[0019] In a third aspect, an embodiment of the present application provides a computer storage medium, wherein the computer storage medium stores a plurality of instructions, wherein the instructions are suitable for being loaded by a processor and executing the above-mentioned method steps.
[0020] In a fourth aspect, an embodiment of the present application provides an electronic device, which may include: a processor and a memory; wherein the memory stores a computer program, and the computer program is suitable for being loaded by the processor and executing the above-mentioned method steps.
[0021] The beneficial effects brought about by the technical solutions provided by some embodiments of the present application include at least:
[0022] By measuring the actual frequency of the frequency-multiplied signal in real time and comparing it with the target frequency, this method can detect and correct the frequency deviation in a timely manner. The introduction of the coarse delay module and the fine delay module makes the frequency adjustment more precise and accurate, which helps to reduce the phase error and improve the frequency stability and accuracy of the system.
[0023] Using a binary search method to determine the optimal coarse and fine adjustment positions can quickly narrow the frequency deviation range, thereby significantly shortening the time required for the system to reach a stable state after startup or frequency switching. Especially in the case of high multiplication factors, this method can more quickly adjust the output frequency of the DCO (or other multiplication mechanism) to match the phase of the input reference signal, thereby improving the response speed of the system.
[0024] Through the precise frequency adjustment mechanism, this method can reduce the number of unnecessary frequency adjustments and power consumption. The series use of coarse adjustment and fine adjustment delay modules enables the system to reduce overall power consumption by optimizing the adjustment strategy while ensuring frequency accuracy. Compared with traditional PLL technology, this method may not require a complex circuit structure that runs continuously, thus helping to reduce the overall power consumption of the system. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0026] Figure 1 is a flow chart of a signal frequency doubling method provided in an embodiment of the present application;
[0027] Figure 2 Schematic diagram of the connection between the coarse delay module and the fine delay module provided in the embodiment of the present application;
[0028] Figure 3 is a structural diagram of a coarse adjustment delay module provided in an embodiment of the present application;
[0029] Figure 4 is a schematic diagram of the structure of the fine-tuning delay module provided in an embodiment of the present application;
[0030] Figure 5 is a connection diagram of a digitally controlled oscillator provided in an embodiment of the present application;
[0031] Figure 6 It is a structural schematic diagram of a digital frequency multiplier provided by the present application. DETAILED DESCRIPTION
[0032] In order to make the objectives, technical solutions and advantages of the present application more clear, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.
[0033] See also Figure 1 , which is a flow chart of a signal frequency doubling method provided in an embodiment of the present application. Figure 1 As shown, the method of the embodiment of the present application may include the following steps:
[0034] S101, measuring the actual frequency of the output frequency-multiplied signal in real time; the frequency-multiplied signal is generated by performing frequency-multiplied processing on the input reference clock signal.
[0035] Among them, the digital frequency multiplier receives an input reference clock signal (REF_CLK), multiplies REF_CLK through internal frequency multiplication logic (i.e., the coarse adjustment delay module and the fine adjustment delay module of the present application), and generates a multiplied output signal (OUT_CLK). In order to measure the actual frequency of OUT_CLK in real time, a frequency counter can be integrated inside the digital frequency multiplier. The counter counts the rising edge or falling edge of OUT_CLK within a fixed time window (such as 1 second), and then calculates the actual frequency of OUT_CLK according to the length of the time window. The measured actual frequency is fed back to the control logic of the digital frequency multiplier for subsequent comparison and adjustment.
[0036] S102: If the current actual frequency is not equal to the target frequency, calculate the deviation between the current actual frequency and the target frequency, and determine the optimal coarse adjustment gear position from among multiple coarse adjustment gear positions of the coarse adjustment delay module using a binary search method based on the deviation.
[0037] Among them, see Figure 2 As shown, the coarse adjustment delay module is used to perform signal delay processing. The coarse adjustment delay module includes multiple coarse adjustment delay units. The multiple coarse adjustment delay units are connected end to end. Different coarse adjustment gears correspond to different numbers of coarse adjustment delay units.
[0038] The control logic of the digital frequency multiplier compares the actual frequency with the target frequency and calculates the deviation between the two (Frequency Error = Actual Frequency - Target Frequency). In order to quickly determine the optimal coarse adjustment gear, the digital frequency multiplier uses a binary search method. First, the middle gear of the coarse adjustment delay module is selected as the starting point, and then the gear is adjusted according to the deviation direction (positive or negative) between the actual frequency and the target frequency. If the deviation is positive, a larger (modification point) gear is selected (increase delay); if the deviation is negative, a smaller (modification point) gear is selected (reduce delay). This process is repeated until a gear is found so that the deviation between the actual frequency and the target frequency is within the allowable error range or the upper limit of the number of iterations of the binary search is reached. After the binary search, the digital frequency multiplier determines an optimal coarse adjustment gear, and the number of coarse adjustment delay units corresponding to this gear can make the actual frequency closest to the target frequency.
[0039] In some embodiments of the present application, determining the optimal coarse adjustment gear position includes:
[0040] Obtain a first coarse adjustment gear position corresponding to an actual frequency F1 which is above the target frequency Fg and closest to the target frequency; obtain a second coarse adjustment gear position corresponding to an actual frequency F2 which is below the target frequency and closest to the target frequency;
[0041] Compare the size between |F1-Fg| and |F2-Fg|;
[0042] The coarse adjustment gear position corresponding to the smaller one is taken as the optimal coarse adjustment gear position.
[0043] Among them, the digital frequency multiplier first measures multiple actual frequencies adjusted by the coarse adjustment delay module in real time through the internal frequency counter. For each coarse adjustment gear, the digital frequency multiplier will record a corresponding actual frequency. A mapping relationship will be formed between these gears and the actual frequencies. Among all the measured actual frequencies, the digital frequency multiplier will look for two specific frequencies: F1 (located above the target frequency Fg and closest to Fg) and F2 (located below the target frequency Fg and closest to Fg). It usually involves sorting or traversing the measured frequency data and finding the two frequency values closest to the target frequency. For the found F1 and F2, the digital frequency multiplier will calculate their deviation values from the target frequency Fg respectively: |F1-Fg| and |F2-Fg|.
[0044] The digital frequency multiplier compares the two deviation values. The coarse adjustment gear corresponding to the frequency with the smaller deviation value is selected as the optimal coarse adjustment gear because it makes the actual frequency closer to the target frequency.
[0045] S103: Under the optimal coarse adjustment gear, determine whether the current actual frequency is equal to the target frequency.
[0046] After determining the optimal coarse adjustment gear, the digital frequency multiplier measures the actual frequency of OUT_CLK again, and compares the re-measured actual frequency with the target frequency to determine whether the two are equal or the difference is within the allowable error range.
[0047] S104: If yes, end the adjustment process.
[0048] If the actual frequency is equal to the target frequency or the difference is within the allowable error range, the digital frequency multiplier considers that the adjustment is successful and ends the adjustment process.
[0049] S105, if not, calculate the deviation between the current actual frequency and the target frequency, and determine the optimal fine-tuning gear position from among multiple fine-tuning gear positions of the fine-tuning delay module using a binary search method based on the deviation.
[0050] See also Figure 2 As shown, the fine-tuning delay module is connected in series with the coarse-tuning delay module, the coarse-tuning delay module is used to perform signal delay processing, the fine-tuning delay module includes multiple fine-tuning delay units, and the multiple fine-tuning delay units are connected end to end, and different fine-tuning gears correspond to different numbers of fine-tuning delay units.
[0051] Among them, if the actual frequency is not equal to the target frequency, the digital frequency multiplier recalculates the deviation value. Similar to determining the optimal coarse adjustment gear, the digital frequency multiplier uses a binary search method to determine an optimal fine adjustment gear among multiple fine adjustment gears of the fine adjustment delay module. The fine adjustment delay module usually has a smaller delay step than the coarse adjustment delay module, so it can achieve a finer frequency adjustment. After the binary search, the digital frequency multiplier determines the optimal fine adjustment gear and adjusts the number of fine adjustment delay units to further approach the target frequency. After determining the optimal fine adjustment gear, the digital frequency multiplier measures the actual frequency of OUT_CLK again and confirms whether it is equal to the target frequency or the difference is within the allowable error range. If the conditions are met, the adjustment process ends; if the conditions are not met, it may be necessary to re-enter the coarse adjustment and fine adjustment cycle until a satisfactory adjustment result is achieved.
[0052] In some embodiments of the present application, determining the optimal fine-tuning gear position includes:
[0053] Acquire a first fine adjustment gear position corresponding to an actual frequency f1 which is above the target frequency and closest to the target frequency; acquire a second fine adjustment gear position corresponding to an actual frequency f2 which is below the target frequency and closest to the target frequency;
[0054] Compare the size between |f1-Fg| and |f2-Fg|;
[0055] The fine-tuning gear position corresponding to the smaller one is taken as the optimal fine-tuning gear position.
[0056] Among them, after determining the optimal coarse adjustment gear, the digital frequency multiplier will further adjust the fine adjustment delay module under the gear and measure multiple actual frequencies after fine adjustment. A mapping relationship is also formed between the actual frequency and the fine adjustment gear. Similar to coarse adjustment, the digital frequency multiplier will look for two specific frequencies among all measured fine adjustment actual frequencies: f1 (located above the target frequency Fg and closest to Fg) and f2 (located below the target frequency Fg and closest to Fg). For the f1 and f2 found, the digital frequency multiplier will calculate their deviation values from the target frequency Fg respectively: |f1-Fg| and |f2-Fg|. The digital frequency multiplier will compare the sizes of these two deviation values. The fine adjustment gear corresponding to the frequency with the smaller deviation value is selected as the optimal fine adjustment gear because it further fine-tunes the actual frequency to make it closer to the target frequency.
[0057] For details, see Figure 3As shown in FIG. 1 , a schematic diagram of the structure of a coarse adjustment delay unit is shown. Each coarse adjustment delay unit is composed of a plurality of NAND gates connected in series. A NAND gate is a logic gate circuit whose output is the result of a logical AND operation after the logical NOT of the input signal. In digital circuits, NAND gates are often used to generate delays because it takes a certain amount of time for a signal to pass through a gate circuit.
[0058] When the input signal passes through the first NAND gate, it is converted to the opposite logic level and a certain delay is generated. This signal is then passed to the next NAND gate, where the logic level is converted again and an additional delay is generated. By connecting multiple NAND gates in series, the delay amount can be accumulated, thereby achieving the larger delay range required for the coarse delay unit. By selecting different numbers of NAND gates in series, the total delay amount of the coarse delay unit can be adjusted. For example, if a larger delay is required, more NAND gates can be selected in series; if a smaller delay is required, fewer NAND gates can be selected.
[0059] See also Figure 4 The structural diagram of the fine-adjustment delay unit shown in FIG. 1 is a schematic diagram of the structure of the fine-adjustment delay unit. Each fine-adjustment delay unit consists of two NOT gates connected in series. NOT gate is a simple logic gate circuit whose output is opposite to the logic level of the input signal. Compared with the coarse-adjustment delay unit, the fine-adjustment delay unit uses fewer logic gates, so the delay generated is smaller and is suitable for fine-tuning.
[0060] When the input signal passes through the first NOT gate, it is converted to the opposite logic level and a certain delay is generated. The signal is then passed to the second NOT gate, where the logic level is converted again and an additional delay is generated (but the total delay is less than the coarse delay unit). Since the structure of the fine delay unit is relatively simple, the adjustment of its delay amount usually depends on changing other parameters of the circuit (such as power supply voltage, operating temperature, etc.), or by connecting more fine delay units in series (although this increases complexity). In practical applications, it is more common to achieve most of the delay requirements by precisely controlling the coarse delay unit, while the fine delay unit is used for fine-tuning to ensure the accuracy of the final output frequency.
[0061] Furthermore, the coarse adjustment delay module is set with 15 coarse adjustment gears, which means that the delay amount can be adjusted by selecting different gears to achieve different frequency outputs. The bit width of the coarse adjustment frequency control word is 4 bits. Since a 4-bit binary number can represent 0 to 15 (a total of 16 states, but only 15 gears are used here, and one state is reserved or used for special functions), a 4-bit control word is sufficient to cover all coarse adjustment gears. The digital frequency multiplier selects different coarse adjustment gears by changing the value of the coarse adjustment frequency control word. For example, if the control word is 0001 (modification point), the first (or lowest) coarse adjustment gear may be selected; if the control word is 1111 (modification point), the highest (or 15th) coarse adjustment gear may be selected.
[0062] The fine-tuning delay module has 31 fine-tuning gears, which are used to further fine-tune the frequency based on the coarse adjustment.
[0063] The bit width of the fine frequency control word is 5 bits. A 5-bit binary number can represent 0 to 31 (a total of 32 states, but again, only 31 gears are used here), so a 5-bit control word is sufficient to cover all fine gears. Similar to coarse adjustment, the digital frequency multiplier selects different fine gears by changing the value of the fine frequency control word. For example, if the control word is 00001 (modification point), the first (or lowest) fine gear may be selected; if the control word is 11111 (modification point), the highest (or 31st) fine gear may be selected.
[0064] A control logic circuit is required inside the digital frequency multiplier to interpret the values of the coarse and fine frequency control words and select the gears of the coarse and fine delay modules accordingly. Due to the limited number of coarse and fine gears, the output frequency of the digital frequency multiplier will have a certain resolution. This resolution depends on the total number of coarse and fine gears and the relative delay between them. In practical applications, the digital frequency multiplier may need to be calibrated and tested to ensure the accuracy of its output frequency. This includes measuring the actual delay amount of each gear and adjusting it as needed. In order to improve the accuracy of frequency control, the digital frequency multiplier may adopt a closed-loop control system to achieve precise frequency control by measuring the output frequency in real time and adjusting the coarse and fine control words as needed.
[0065] Through the above implementation, the digital frequency multiplier can use the coarse adjustment and fine adjustment delay modules and the corresponding control words to accurately adjust the output frequency, thereby meeting the needs of various application scenarios.
[0066] For further information, see Figure 5 As shown, the digital frequency multiplier of the present application includes two digital controlled oscillators: a first digital controlled oscillator and a second digital controlled oscillator. The two digital controlled oscillators can independently receive a frequency control word and generate a signal of a corresponding frequency according to the control word.
[0067] First, the target frequency is determined according to the application requirements. The target frequency may be input by the user through an external interface or automatically calculated by the digital frequency multiplier. Once the target frequency is determined, the digital frequency multiplier calculates the corresponding frequency control word. This frequency control word includes a coarse frequency control word and a fine frequency control word, which are used to accurately control the output frequency of the digital controlled oscillator. Next, the digital frequency multiplier uses the modified frequency control word to drive the currently unused digital controlled oscillator (for example, if the first digital controlled oscillator is in use, the second digital controlled oscillator is driven; vice versa). The purpose of this is to test and prepare the new digital controlled oscillator without interrupting the current signal output. The digital frequency multiplier monitors the signal output by the unused digital controlled oscillator. Once it is detected that the signal reaches a stable state (that is, the parameters such as the frequency, amplitude and phase of the signal remain unchanged for a certain period of time), it can be considered that the digital controlled oscillator is ready for work switching. When the output signal of the unused digital controlled oscillator is stable, the digital frequency multiplier performs a switching operation to switch the currently used digital controlled oscillator to the standby state and switch the previously unused digital controlled oscillator to the working state. This switching process should be as smooth as possible to avoid adverse effects on external circuits or loads. After the switch is completed, the digital frequency multiplier may continue to monitor the output signal of the new working digital controlled oscillator to ensure its stability and accuracy. At the same time, the digital frequency multiplier may also adjust the frequency control word as needed to further optimize the accuracy and stability of the output frequency.
[0068] The switching of the digital controlled oscillator should be performed during the idle time or low load period of the signal output to reduce the impact on system performance. A switching logic circuit is required inside the digital frequency multiplier to control the switching process of the digital controlled oscillator. This logic circuit should be able to accurately detect the signal stability and perform the switching operation at the appropriate time. After the switching is completed, the frequency calibration of the new working digital controlled oscillator may be required to ensure the accuracy of its output frequency, which is achieved by comparing with the reference signal and adjusting the frequency control word.
[0069] Through the above implementation, the digital frequency multiplier can achieve smooth switching and precise frequency control of the digital controlled oscillator without interrupting the signal output, thereby meeting the needs of various application scenarios.
[0070] The embodiments of the present application specifically include the following beneficial effects:
[0071] By measuring the actual frequency of the frequency-multiplied signal in real time and comparing it with the target frequency, this method can detect and correct the frequency deviation in time. The introduction of the coarse adjustment delay module and the fine adjustment delay module makes the frequency adjustment more precise and accurate (some content has been deleted), improving the frequency stability and accuracy of the system.
[0072] Using the binary search method to determine the optimal coarse and fine adjustment gears can quickly narrow the frequency deviation range, thereby significantly shortening the time required for the system to reach a stable state after startup or frequency switching. This method is applicable to various multiplication factors and can quickly adjust the output frequency of the DCO (or multiplication mechanism) to make it consistent with the target frequency, thereby improving the response speed and stability of the system. (Because the multiplication speed has little to do with the multiplication factor, and the digital multiplier generally has little to do with the clock phase)
[0073] Through the precise frequency adjustment mechanism, this method can reduce unnecessary frequency adjustment times and power consumption. The series use of coarse and fine delay modules enables the system to reduce overall power consumption by optimizing the adjustment strategy while ensuring frequency accuracy. Compared with traditional PLL technology, this method does not need to rely on complex circuit structures that run continuously, thereby effectively reducing the overall power consumption of the system. In addition, by using digital circuits instead of analog circuits, the chip area of the system is greatly reduced, further improving the integration and efficiency of the design.
[0074] The following are device embodiments of the present application, which can be used to execute the method embodiments of the present application. For details not disclosed in the device embodiments of the present application, please refer to the method embodiments of the present application.
[0075] See also Figure 6 , which shows a schematic diagram of the structure of a digital frequency multiplier provided by an exemplary embodiment of the present application, hereinafter referred to as digital frequency multiplier 6. The digital frequency multiplier 6 can be implemented as all or part of the electronic device through software, hardware or a combination of both. The digital frequency multiplier 6 includes: a measuring unit 401, a coarse control unit 602, a judgment unit 603, an end unit 604, and a fine control unit 605.
[0076] The measuring unit 601 is used to measure in real time the actual frequency of the output frequency-multiplied signal; the frequency-multiplied signal is generated by frequency-multiplied processing of the input reference clock signal;
[0077] A coarse control unit 602 is used to calculate the deviation between the current actual frequency and the target frequency if the current actual frequency is not equal to the target frequency, and to determine the optimal coarse adjustment gear position from among multiple coarse adjustment gear positions of the coarse adjustment delay module using a binary search method based on the deviation value; the coarse adjustment delay module is used to perform signal delay processing, and the coarse adjustment delay module includes multiple coarse adjustment delay units, and different coarse adjustment gear positions correspond to different numbers of coarse adjustment delay units;
[0078] A judging unit 603 is used to judge whether the current actual frequency is equal to the target frequency under the optimal coarse adjustment gear;
[0079] End unit 604, used for ending the adjustment process if the answer is yes;
[0080] The fine control unit 605 is used to calculate the deviation value between the current actual frequency and the target frequency if the answer is no, and determine the optimal fine adjustment gear position from multiple fine adjustment gear positions of the fine adjustment delay module by using a binary search method based on the deviation value; the fine adjustment delay module is connected in series with the coarse adjustment delay module, the coarse adjustment delay module is used to perform signal delay processing, and the fine adjustment delay module includes multiple fine adjustment delay units, and different fine adjustment gear positions correspond to different numbers of fine adjustment delay units.
[0081] In one or more possible embodiments, determining the optimal coarse adjustment gear position includes:
[0082] Obtain a first coarse adjustment gear corresponding to an actual frequency F1 that is above the target frequency Fg and closest to the target frequency; obtain a second coarse adjustment gear corresponding to an actual frequency F2 that is below the target frequency and closest to the target frequency;
[0083] Compare the size between |F1-Fg| and |F2-Fg|;
[0084] The coarse adjustment gear position corresponding to the smaller one is taken as the optimal coarse adjustment gear position;
[0085] Wherein, determining the optimal fine-tuning gear position includes:
[0086] Acquire a first fine adjustment gear position corresponding to an actual frequency f1 which is above the target frequency and closest to the target frequency; acquire a second fine adjustment gear position corresponding to an actual frequency f2 which is below the target frequency and closest to the target frequency;
[0087] Compare the size between |f1-Fg| and |f2-Fg|;
[0088] The fine-tuning gear position corresponding to the smaller one is taken as the optimal fine-tuning gear position.
[0089] In one or more possible embodiments, each coarse-adjusting delay unit includes a plurality of serially connected NAND gates; and each fine-adjusting delay unit includes two serially connected NOT gates.
[0090] In one or more possible embodiments, the number of coarse adjustment gears set in the coarse adjustment delay module is 15, and the bit width of the coarse adjustment frequency control word is 4 bits; the number of fine adjustment gears of the fine adjustment delay module is 31, and the bit width of the fine adjustment frequency control word is 5 bits; the coarse adjustment gear of the coarse adjustment delay module is controlled by the coarse adjustment frequency control word, and the fine adjustment gear of the fine adjustment delay module is controlled by the fine adjustment frequency control word.
[0091] In one or more possible embodiments, a first digitally controlled oscillator and a second digitally controlled oscillator are provided inside the digital frequency multiplier;
[0092] The method further comprises:
[0093] A switching unit, used to modify the current frequency control word based on the target frequency, and use the modified frequency control word to drive the unused digitally controlled oscillator to output a signal; the frequency control word includes a coarse frequency control word and a fine frequency control word;
[0094] When it is detected that the signal output by the unused digital controlled oscillator reaches stability, the unused digital controlled oscillator is switched to a working state.
[0095] It should be noted that the digital frequency multiplier 6 provided in the above embodiment only uses the division of the above functional modules as an example when executing the signal frequency multiplication method. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the above functions. In addition, the digital frequency multiplier provided in the above embodiment and the signal frequency multiplication method embodiment belong to the same concept, and the implementation process thereof is detailed in the method embodiment, which will not be repeated here.
[0096] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.
[0097] The present application also provides a computer storage medium, which can store multiple instructions, and the instructions are suitable for being loaded and executed by a processor as described above. Figure 1 The method steps of the embodiment shown in the figure can be found in the specific implementation process. Figure 1 The specific description of the illustrated embodiment will not be repeated here.
[0098] The present application also provides a computer program product, which stores at least one instruction, and the at least one instruction is loaded and executed by the processor to implement the signal frequency doubling method described in the above embodiments.
[0099] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a disk, an optical disk, a read-only storage memory, or a random access memory, etc.
[0100] The above disclosure is only the preferred embodiment of the present application, which certainly cannot be used to limit the scope of rights of the present application. Therefore, equivalent changes made according to the claims of the present application are still within the scope covered by the present application.
Claims
1. A signal frequency doubling method, characterized in that: include: Real-time measurement of the actual frequency of the output frequency-multiplied signal; the frequency-multiplied signal is generated by frequency-multiplied processing of the input reference clock signal; If the current actual frequency is not equal to the target frequency, the deviation value between the current actual frequency and the target frequency is calculated, and based on the deviation value, a binary search method is used to determine the optimal coarse adjustment gear position among multiple coarse adjustment gear positions of the coarse adjustment delay module; the coarse adjustment delay module is used to perform signal delay processing, and the coarse adjustment delay module includes multiple coarse adjustment delay units, and different coarse adjustment gear positions correspond to different numbers of coarse adjustment delay units; Under the optimal coarse adjustment gear, determining whether the current actual frequency is equal to the target frequency; If yes, end the adjustment process; If not, calculate the deviation value between the current actual frequency and the target frequency, and determine the optimal fine-tuning gear position from multiple fine-tuning gear positions of the fine-tuning delay module using a binary search method based on the deviation value; the fine-tuning delay module is connected in series with the coarse-tuning delay module, the coarse-tuning delay module is used to perform signal delay processing, the fine-tuning delay module includes multiple fine-tuning delay units, and different fine-tuning gear positions correspond to different numbers of fine-tuning delay units.
2. The method according to claim 1, characterized in that The determining of the optimal coarse adjustment gear position comprises: Obtain a first coarse adjustment gear corresponding to an actual frequency F1 that is above the target frequency Fg and closest to the target frequency; obtain a second coarse adjustment gear corresponding to an actual frequency F2 that is below the target frequency and closest to the target frequency; Compare the size between |F1-Fg| and |F2-Fg|; The coarse adjustment gear position corresponding to the smaller one is taken as the optimal coarse adjustment gear position; Wherein, determining the optimal fine-tuning gear position includes: Acquire a first fine adjustment gear position corresponding to an actual frequency f1 which is above the target frequency and closest to the target frequency; acquire a second fine adjustment gear position corresponding to an actual frequency f2 which is below the target frequency and closest to the target frequency; Compare the size between |f1-Fg| and |f2-Fg|; The fine-tuning gear position corresponding to the smaller one is taken as the optimal fine-tuning gear position.
3. The method according to claim 1, characterized in that Each coarse-adjusting delay unit includes a plurality of serially connected NAND gates; each fine-adjusting delay unit includes two serially connected NAND gates.
4. The method according to claim 1, characterized in that: The number of coarse adjustment gears set in the coarse adjustment delay module is 15, and the bit width of the coarse adjustment frequency control word is 4 bits; the number of fine adjustment gears of the fine adjustment delay module is 31, and the bit width of the fine adjustment frequency control word is 5 bits; the coarse adjustment gear of the coarse adjustment delay module is controlled by the coarse adjustment frequency control word, and the fine adjustment gear of the fine adjustment delay module is controlled by the fine adjustment frequency control word.
5. The method according to claim 4, characterized in that The digital frequency multiplier is internally provided with a first digitally controlled oscillator and a second digitally controlled oscillator; The method further comprises: Modify the current frequency control word based on the target frequency, and use the modified frequency control word to drive the unused digitally controlled oscillator to output a signal; the frequency control word includes a coarse frequency control word and a fine frequency control word; When it is detected that the signal output by the unused digital controlled oscillator reaches stability, the unused digital controlled oscillator is switched to a working state.
6. A digital frequency multiplier, characterized in that: include: A measuring unit, used for measuring in real time the actual frequency of the output frequency-multiplied signal; the frequency-multiplied signal is generated by frequency-multiplied processing of the input reference clock signal; A coarse control unit, used for calculating the deviation between the current actual frequency and the target frequency if the current actual frequency is not equal to the target frequency, and determining the optimal coarse adjustment gear position from among the multiple coarse adjustment gear positions of the coarse adjustment delay module by using a binary search method based on the deviation value; the coarse adjustment delay module is used for performing signal delay processing, and the coarse adjustment delay module includes multiple coarse adjustment delay units, and different coarse adjustment gear positions correspond to different numbers of coarse adjustment delay units; A judging unit, used to judge whether the current actual frequency is equal to the target frequency under the optimal coarse adjustment gear; An end unit, used for ending the adjustment process if the answer is yes; A fine control unit is used to calculate the deviation value between the current actual frequency and the target frequency if the answer is no, and to determine the optimal fine adjustment gear position from multiple fine adjustment gear positions of the fine adjustment delay module by using a binary search method based on the deviation value; the fine adjustment delay module is connected in series with the coarse adjustment delay module, the coarse adjustment delay module is used to perform signal delay processing, the fine adjustment delay module includes multiple fine adjustment delay units, and different fine adjustment gear positions correspond to different numbers of fine adjustment delay units.
7. A computer storage medium, characterized in that: The computer storage medium stores a plurality of instructions, and the instructions are suitable for being loaded by a processor and executing the method steps according to any one of claims 1 to 5.
8. An electronic device, characterized in that: include: A processor and a memory; wherein the memory stores a computer program, and the computer program is suitable for being loaded by the processor and executing the method steps as claimed in any one of claims 1 to 5.