Power-on reset circuit for high-precision multi-power-supply detection

Abstract

The invention discloses a power-on reset circuit for high-precision multi-power-supply detection, and mainly solves the problem that the existing power-on reset circuit cannot carry out power-on reset on a plurality of power supplies. The circuit comprises a power supply detection unit and a buffer unit. Wherein the power supply detection unit is used for detecting power-on and power-off of a power supply and giving a reset signal with an accurate threshold value, and comprises two power supply voltage division modules, two power supply threshold value modules and a high-to-low module; and the buffer unit is used for outputting a final reset signal and generating a feedback output signal to the power supply detection unit. The feedback output is respectively transmitted to the first power supply voltage division module and the high-to-low module for voltage division and conversion, the conversion voltage is output through the high-to-low module, then is converted again through the second power supply voltage division module, is respectively output to the two power supply threshold modules for comparison and combination, and is transmitted to the buffer unit for outputting a final reset signal. The power-on and power-off threshold precision and the temperature characteristic can be improved, the power consumption is reduced, and the method can be used for detecting a plurality of power supplies of a chip.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog integrated circuits, and in particular relates to a power-on reset circuit, which can be used to detect multiple power supplies of a chip to ensure that the chip works within a power supply range with an accurate threshold. Background Art

[0002] During the chip power-on process, each module inside the circuit is in an uncertain state, and some modules have minimum power supply voltage requirements, so a power-on reset circuit is needed to output a power-on reset signal when the power supply voltage reaches the threshold, which is used to reset these modules so that each module inside the circuit outputs the expected default signal to ensure that the power supply voltage meets the minimum power supply voltage requirements of each module. In some application scenarios, the power supply of the chip requires multiple power supplies such as digital and analog, and there are requirements for the power-on and power-off thresholds of these multiple power supplies, so a power-on reset circuit that can detect multiple power supplies and each power supply has a threshold is needed.

[0003] The existing power-on reset circuit is often implemented by a cascade resistor string, a bandgap reference and a comparator circuit. The bandgap reference circuit provides a reference voltage, the cascade resistor string is used to divide the power supply voltage, and the comparator is used to determine whether the divided voltage of the cascade resistor string is greater than the reference voltage given by the bandgap reference circuit. When the power supply is powered on, the bandgap reference circuit can quickly output a stable reference voltage that is greater than the divided voltage of the cascade resistor string, and the comparator output is a low level at this time. When the power supply voltage continues to increase, so that the divided voltage of the cascade resistor string is greater than the reference voltage given by the bandgap reference circuit, the comparator output is a high level, and the reset is completed. This type of power-on reset circuit has a simple structure and principle. Although it can provide a high-precision power-on and power-off threshold, it requires a bandgap reference circuit and a comparator circuit, and the power-on threshold and the power-off threshold are the same voltage, and there is no hysteresis interval. Therefore, the power consumption is high, and only the voltage of a single power supply can be detected, which cannot meet the needs of power-on reset detection of multiple power supplies.

[0004] In order to meet the needs of multiple power supply detection, multiple PMOS tubes and resistors can be used to detect the power supply voltage, and finally an OR gate is used to output the power-on reset signal. This implementation method is simple and can be configured as a power-on reset circuit for multiple power supply detection, but the accuracy of its upper and lower power threshold voltages is not high, and the hysteresis interval of the upper and lower power thresholds cannot be configured. Another power-on reset circuit for multiple power supply detection with high threshold accuracy can be implemented by multiple cascaded resistor strings, comparators, and bandgap reference circuits. The cascaded resistor strings divide the voltages of multiple power supplies respectively, and the bandgap reference circuit provides reference voltages of different sizes. The comparator compares the cascaded resistor string voltage division and the bandgap reference circuit reference voltage, and finally the comparison result is output by an AND gate, thereby obtaining the power-on reset results of multiple power supply detection. Although this method can realize the power-on reset detection of multiple power supplies, it requires multiple comparators and multiple reference voltages, consumes a large amount of power consumption and area, and this implementation method requires the bandgap reference circuit to power on faster, which is difficult to achieve in some chips.

[0005] The patent document of application number CN201811440767.0 proposes a power-on reset circuit, which uses a combination of a comparator and a Schmitt trigger to divide the power supply through a cascade resistor string, and then compares the divided voltage signal with the reference voltage through a comparator. The Schmitt trigger receives the low-level comparison result and outputs it to complete the power-on reset of the circuit. The circuit feeds back different divided voltage signals according to the result of the power-on reset, thereby obtaining different power-on thresholds and power-off thresholds. However, the circuit can only detect the voltage of a single power supply, and cannot meet the needs of power-on reset detection of multiple power supplies. In addition, the comparator has a complex structure and requires an additional reference voltage, which is not conducive to reducing power consumption. Summary of the invention

[0006] The purpose of the present invention is to address the deficiencies of the above-mentioned prior art and to propose a high-precision power-on reset circuit with multi-power supply detection to improve the accuracy of upper and lower power thresholds and temperature characteristics, reduce power consumption, and realize power-on reset circuit detection of multiple power supplies.

[0007] The technical solution for achieving the purpose of the present invention is: using a cascaded resistor string to divide the voltage to detect multiple power supply voltages, wherein the main power supply obtains an accurate threshold through a bandgap reference-like structure, and the remaining multiple power supplies lower than the main power supply voltage use the transistor's own threshold as the voltage division threshold of the cascaded resistor string, and these detection results are input into a buffer module, and finally a power-on reset signal is output.

[0008] According to the above ideas, the present invention provides a high-precision multi-power supply detection power-on reset circuit, and a scheme for power-on reset and power-off protection using the power-on reset circuit is as follows:

[0009] 1. A high-precision multi-power supply detection power-on reset circuit, comprising a power supply detection unit and a buffer unit, characterized in that:

[0010] The power supply detection unit is used to detect the power on and off of the power supply and give a reset signal with an accurate threshold value. It includes two power supply voltage divider modules, two power supply threshold modules and a high-to-low module. The output fed back by the buffer unit is transmitted to the first power supply voltage divider module and the high-to-low module for voltage division and conversion respectively; the conversion voltage output by the high-to-low module is converted again by the second power supply voltage divider module, and then output to the first power supply threshold module and the second power supply threshold module for comparison and merging, and transmitted to the buffer unit to output the final reset signal.

[0011] Further, the first power supply voltage dividing module has an input end connected to the feedback output of the buffer unit, an output end connected to the input end of the first power supply threshold module, and an output end of the first power supply threshold module connected to the input end of the buffer unit;

[0012] The high-to-low conversion module has an input end connected to the feedback output of the buffer unit, and an output end connected to the input end of the second power supply voltage divider module;

[0013] The second power supply voltage dividing module, whose output end is connected to the input end of the second power supply threshold module, and the output end of the second power supply threshold module is connected to the input of the buffer unit;

[0014] The operating voltage of each module is supplied by an external power supply, and the power supply includes a first power supply VDD1 and a second power supply VDD2.

[0015] 2. A method for performing power-on reset using the power-on reset circuit according to claim 1, characterized in that it comprises the following steps:

[0016] Set the first power supply VDD1 and the second power supply VDD2 to enter the power-on state, so that the power supply voltage gradually rises. At this time, the power detection unit receives the high-level feedback signal ENB of the buffer unit and transmits it to the high-to-low module to convert it into a low voltage signal;

[0017] The low voltage signal and the high level feedback signal ENB are respectively transmitted to the second power supply voltage divider module and the first power supply voltage divider module to generate respective power-on voltage dividers, and then respectively transmitted to the second power supply threshold module and the first power supply threshold module for comparison. When the power-on voltage divider is greater than the power-on thresholds of the two threshold modules, the threshold module outputs a comparison result of a high level, and then transmits the comparison result to the buffer unit;

[0018] The buffer unit receives the high level of the comparison result and outputs it, completing the power-on reset of the circuit.

[0019] 3. A method for power-off protection using the power-on reset circuit of claim 1, characterized in that it comprises the following steps:

[0020] After the power-on reset is completed, the first power supply VDD1 and the second power supply VDD2 are set to enter the power-off state, so that the power supply voltage gradually decreases. At this time, the power detection unit receives the low-level feedback signal ENB of the buffer unit and transmits it to the high-to-low module to convert it into a low voltage signal;

[0021] The low voltage signal and the low level feedback signal ENB are respectively transmitted to the second power supply voltage divider module and the first power supply voltage divider module to generate respective power-off voltage dividers, and then respectively transmitted to the second power supply threshold module and the first power supply threshold module for comparison. When the power-off voltage divider is lower than the power-off thresholds of the two threshold modules, the threshold module outputs a comparison result of a low level, and then transmits the comparison result to the buffer unit;

[0022] The buffer unit receives the low level of the comparison result and outputs it, completing the power-off protection of the circuit.

[0023] Compared with the prior art, the present invention has the following advantages:

[0024] Firstly, the present invention designs a power-on reset circuit including a power detection unit, utilizes the quasi-bandgap reference structure of the first power threshold module and the threshold of the device itself in the second power threshold module, thereby improving the accuracy of the power-on and power-off thresholds of the power-on reset circuit, ensuring that the threshold of the first power threshold module is stable over the entire temperature range, and reducing the difficulty of implementing the threshold of the second power threshold module.

[0025] Secondly, the present invention divides the power supply voltage through the first power supply voltage divider module and the second power supply voltage divider module, and connects cascade resistors of different proportions in series to the power supply voltage according to the existing output result of the power-on reset circuit, so as to obtain an adjustable hysteresis interval between the power-on threshold and the power-off threshold, thereby improving the stability of the reset signal output by the power-on reset circuit.

[0026] Thirdly, the present invention charges and discharges the common node in the buffer unit through the multi-channel output of the power detection unit, so that multiple power supply voltages with different power-on and power-off sequences can obtain the required reset signal, reducing the configuration difficulty of the multi-power supply power-on reset circuit, and eliminating the need for an additional bandgap reference circuit, thereby reducing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is the overall circuit block diagram of the present invention;

[0028] Figure 2 is a circuit diagram of a power supply detection unit in the present invention;

[0029] Figure 3is a circuit diagram of a buffer unit in the present invention;

[0030] Figure 4 A node waveform diagram in which the first power supply is powered on before the second power supply and powered off after the second power supply in the present invention;

[0031] Figure 5 This is a node waveform diagram in which the first power supply is powered on later than the second power supply and powered off earlier than the second power supply in the present invention. DETAILED DESCRIPTION

[0032] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, other embodiments obtained by ordinary technicians in this field without creative work should all fall within the scope of protection of the present invention.

[0033] Reference Figure 1 The power-on reset circuit of the high-precision multi-power supply detection in this example includes a power supply detection unit 1 and a buffer unit 2. The input end of the power supply detection unit 1 is connected to the feedback output end ENB of the buffer unit 2; the input end of the buffer unit 2 is connected to the two output ends of the power supply detection unit 1, and its final output end EN outputs a power-on reset signal. Among them:

[0034] The power detection unit 1 includes two power voltage dividing modules 11 and 14 , two power threshold modules 12 and 15 and a high-to-low conversion module 13 . The first power supply voltage divider module 11 is powered by the first power supply VDD1, and its input end is connected to the feedback output ENB of the buffer unit 2, and its output end is connected to the input end of the first power supply threshold module 12; the first power supply threshold module 12 is powered by the first power supply VDD1, receives the output of the first power supply voltage divider module 11, and its output end is connected to the input end of the buffer unit 2; the high-to-low module 13 is powered by both the first power supply VDD1 and the second power supply VDD2, and its input end is connected to the feedback output ENB of the buffer unit 2, and its output end is connected to the input end of the second power supply voltage divider module 14; the second power supply voltage divider module 14 is powered by the second power supply VDD2, receives the conversion output of the high-to-low module 13, and its output end is connected to the input end of the second power supply threshold module 15; the second power supply threshold module 15 is powered by both the first power supply VDD1 and the second power supply VDD2, receives the voltage divided by the second voltage divider module 14, and its output end is connected to the input end of the buffer unit 2;

[0035] The buffer unit 2 includes two inverters, wherein the first inverter receives two outputs of the power detection unit 1, outputs a feedback output signal ENB, and transmits the feedback output signal to the second inverter, and the second inverter finally outputs a power-on reset signal EN of the entire circuit.

[0036] The following is an example of the structure of each unit in the power-on reset circuit:

[0037] Embodiment 1: Structure of the power supply detection unit 1.

[0038] Reference Figure 2 In this embodiment, the two power voltage divider modules 11 and 14, the two power threshold modules 12 and 15 and the high-to-low conversion module 13 in the power detection unit 1 have the following structures:

[0039] The first power supply voltage divider module 11 includes a first resistor R1, a second resistor R2, a third resistor R3 and a hysteresis transistor M1; the first resistor R1 has a head end connected to the first power supply VDD1, and a tail end connected to the head end of the second resistor R2; the tail end of the second resistor R2 is connected to the head end of the third resistor R3, and the tail end of the third resistor R3 is connected to the power ground; the hysteresis transistor M1 is a PMOS tube, a source of which is connected to the first power supply VDD1, a drain is connected to the tail end of the first resistor R1, and a gate is connected to the feedback output ENB of the buffer unit 2.

[0040] The first power supply threshold module 12 includes threshold bipolar transistors Q0 and Q1, load transistors M2 and M3, a driving transistor M4, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6 and a load capacitor C0; the threshold bipolar transistors Q0 and Q1, the bases of which are connected to the output end of the first power supply voltage divider module 11, the emitters are respectively connected to the first ends of the fifth resistor R5 and the fourth resistor R4, and the collectors are respectively connected to the drains of the load transistors M2 and M3; the load transistors M2 and M3 are PMOS tubes, the gates of which are connected to the collector of the bipolar transistor Q0, and the sources of which are connected to the first power supply voltage divider module 11. The source VDD1 is connected, and the drain is connected to the collectors of the bipolar transistors Q0 and Q1 respectively; the driving transistor M4 is a PMOS tube, whose source is connected to the first power supply VDD1, the gate is connected to the collector of the bipolar transistor Q1, and the drain is connected to the first end of the sixth resistor R6 and the load capacitor C0; the fourth resistor R4 and the fifth resistor R5, whose first ends are connected to the emitters of the threshold bipolar transistors Q1 and Q0 respectively, and whose tail ends are connected to the power ground and the first end of the fourth resistor R4 respectively; the sixth resistor R6 and the load capacitor C0, whose tail ends are both connected to the power ground, and the head end is connected to the drain of the driving transistor M4.

[0041] The high-to-low module 13 includes conversion pull-up transistors M13 and M15, and conversion pull-down transistors M14 and M16; the conversion pull-up transistor M13 and the conversion pull-down transistor M14 have sources connected to the power supply VDD1 and the power ground, respectively, the gates are connected to the output ENB of the buffer unit 2, and the drains are connected to the gate of the conversion pull-down transistor M16; the conversion pull-up transistor M15 and the conversion pull-down transistor M16 have sources connected to the power supply VDD2 and the power ground, respectively, the gates are connected to the drain of the conversion pull-up transistor M13, and the drains are used as the output ends of the high-to-low module 13.

[0042] The second power supply voltage divider module 14 includes a seventh resistor R7, an eighth resistor R8, a ninth resistor R9 and a hysteresis transistor M9; the seventh resistor R7 has a head end connected to the second power supply VDD2, and a tail end connected to the head end of the eighth resistor R8; the tail end of the eighth resistor R8 is connected to the head end of the ninth resistor R9, and the tail end of the ninth resistor R9 is connected to the power ground; the hysteresis transistor M9 is a PMOS tube, a source of which is connected to the second power supply VDD2, a drain is connected to the tail end of the seventh resistor R7, and a gate is connected to the output of the high-to-low module 13.

[0043] The second power supply threshold module 15 includes a weak pull-up transistor M10, a threshold transistor M11 and a pull-down transistor M12; the weak pull-up transistor M10 is a PMOS tube, whose source is connected to the first power supply VDD1, the gate is connected to the power ground, and the drain is connected to the drain of the threshold transistor M11; the threshold transistor M11 is an NMOS tube, whose source is connected to the power ground, and the gate is connected to the output end of the second power supply voltage divider module 14; the pull-down transistor M12 is an NMOS tube, whose source is connected to the power ground, the gate is connected to the drain of the threshold transistor M11, and the drain serves as the output end of the module.

[0044] Embodiment 2: Structure of buffer unit 2.

[0045] Reference Figure 3 , the structures of the first inverter and the second inverter in the buffer unit 1 of this example are as follows:

[0046] The first inverter comprises a first buffer pull-up transistor M5 and a first buffer pull-down transistor M6; the first buffer pull-up transistor M5 has a source connected to the first power supply VDD1, a gate connected to the gate of the first buffer pull-down transistor M6, and the gate is used as the input end of the buffer unit 2, and the drain is connected to the drain of the first buffer pull-down transistor M6; the first buffer pull-down transistor M6 has a source connected to the power supply ground, a gate connected to the gate of the first buffer pull-up transistor M5, and a drain used as the ENB output end of the buffer unit 2;

[0047] The second inverter includes a second buffer pull-up transistor M7 and a second buffer pull-down transistor M8; the second buffer pull-up transistor M7 has a source connected to the first power supply VDD1, a gate connected to the gate of the second buffer pull-down transistor M8, and a drain connected to the drain of the second buffer pull-down transistor M8; the second buffer pull-down transistor M8 has a source connected to the power ground, a gate connected to the gate of the second buffer pull-up transistor M7, and a drain used as the EN output terminal of the buffer unit 2.

[0048] Embodiment 3: Perform power-on reset based on the above circuit.

[0049] The power-on reset occurs during the power-on process of the first power supply VDD1 and the second power supply VDD2. At this time, the remaining circuits on the chip are in an initial reset state. In order to put them into working state, the power-on reset circuit needs to change the output EN signal from a low level to a high level when both power supply voltages are greater than the power-on threshold of their respective power domains, and output it to these circuits to complete their power-on reset.

[0050] The method for power-on reset using the above circuit in this example includes the following steps:

[0051] The first power supply VDD1 and the second power supply VDD2 are set to enter the power-on state, so that the power supply voltage gradually increases. At this time, the power detection unit 1 receives the high-level feedback signal ENB of the buffer unit 2 and transmits it to the high-to-low module 13 to convert it into a low voltage signal;

[0052] The low voltage signal is transmitted to the transistor M9 in the second power supply voltage divider module 14, and turns it off, so as to obtain the power-on voltage divider of the second power supply voltage divider module 14; the power-on voltage divider is transmitted to the threshold transistor M11 in the second power supply threshold module 15, so that the transistor M11 generates a current. When the current is greater than the pull-up current generated by the weak pull-up transistor M10, the pull-down transistor M12 is turned off, so that the second power supply threshold module 15 does not output the pull-down current;

[0053] The high-level feedback signal ENB is transmitted to the transistor M1 in the first power voltage divider module 11 and turns it off, thereby obtaining the power-on voltage divider of the first power voltage divider module 11; the power-on voltage divider is transmitted to the threshold bipolar transistors Q0 and Q1 in the first power threshold module 12 and generates two branch currents. The first branch current generated by the transistor Q0 is copied through the load transistors M2 and M3. If the copied first branch current is less than the second branch current generated by the transistor Q1, the gate voltage of the driving transistor M4 is reduced, so that the first power threshold module 12 outputs a high level;

[0054] The buffer unit 2 receives the high level output of the first power threshold module 12, and because the second power threshold module 15 does not output a pull-down current, it outputs a high level EN signal to complete the power-on reset of the circuit.

[0055] Example 4: Power-off protection based on the above circuit.

[0056] The power-off protection occurs during the power-off process of the first power supply VDD1 and the second power supply VDD2. At this time, the remaining circuits on the chip are in working state. In order to avoid abnormal operation of these circuits during power-off, they need to be reset for protection. When the voltage of any one of the two power supplies of the power-on reset circuit is less than its power-off threshold, the output EN signal is changed from high level to low level and output to these circuits to complete their power-off protection.

[0057] The method for power-off protection using the above circuit in this example includes the following steps:

[0058] The first power supply VDD1 and the second power supply VDD2 are set to enter a power-off state, so that the power supply voltage gradually decreases. At this time, the power supply detection unit 1 receives the low-level feedback signal ENB of the buffer unit 2 and transmits it to the high-to-low module 13 to convert it into a low voltage signal;

[0059] The low voltage signal is transmitted to the transistor M9 in the second power voltage divider module 14, and turns it on, thereby obtaining the power-off voltage division of the second power voltage divider module 14; the power-off voltage division is transmitted to the threshold transistor M11 in the second power threshold module 15, and the generated pull-down current is less than the pull-up current generated by the weak pull-up transistor M10, so that the pull-down transistor M12 is turned on, so that the second power threshold module 15 outputs the pull-down current;

[0060] The above-mentioned high-level feedback signal ENB is transmitted to the transistor M1 in the first power supply voltage divider module 11, and turns it on, so as to obtain the power-off voltage division of the first power supply voltage divider module 11; the power-off voltage division is transmitted to the threshold bipolar transistors Q0 and Q1 in the first power supply threshold module 12 and generates two branch currents, the first branch current generated by the transistor Q0 is copied through the load transistors M2 and M3, and the copied first branch current is greater than the second branch current generated by the transistor Q1, so that the gate voltage of the driving transistor M4 increases, so that the first power supply threshold module 12 outputs a low level;

[0061] The buffer unit 2 receives the low level output of the first power threshold module 12, and because the second power threshold module 15 outputs a pull-down current, it outputs a low level EN signal to complete the power-off protection of the circuit.

[0062] The effect of the present invention can be further illustrated by the following simulation experiment.

[0063] 1. Simulation conditions

[0064] Using Cadance Virtuoso software, set the temperature to 27°C, the first power supply voltage to 2.5V, and the second power supply voltage to 1.2V.

[0065] 2. Simulation content

[0066] Simulation 1: Based on the above simulation conditions, the power-on reset circuits of Embodiments 1 and 2 of the present invention are subjected to timing simulation in which the first power supply is powered on before the second power supply and is powered off later than the second power supply. The results are as follows: Figure 4 As shown, the power-on threshold and power-off threshold of the first power supply are 2.3V and 1.53V respectively, the voltage of node C changes with the second power supply, and after the voltage of node C is greater than the threshold voltage, the voltage of node B is increased, thereby outputting a high-level EN signal, so that the feedback output ENB signal is pulled down through the voltage of the output node D of the high-to-low conversion module.

[0067] Simulation 2, according to the above simulation conditions, the power-on reset circuits of Embodiments 1 and 2 of the present invention are subjected to timing simulation in which the first power supply is powered on later than the second power supply and powered off earlier than the second power supply. The results are as follows: Figure 5 As shown, the power-on threshold and power-off threshold of the second power supply are 0.92V and 0.73V respectively, the voltage of node A changes with the first power supply, and after the voltage of node A is greater than the threshold voltage, the voltage of node B is increased, thereby outputting a high-level EN signal, so that the feedback output ENB signal is pulled down through the voltage of the output node D of the high-to-low conversion module.

[0068] from Figure 4 and Figure 5 It can be seen that the power-on reset circuit of Embodiment 1 and Embodiment 2 of the present invention outputs a high-level EN signal to complete the power-on reset of the circuit only when both the first power supply and the second power supply are greater than the power-on threshold, and outputs a low-level EN signal to complete the power-off protection of the circuit only when either the first power supply or the second power supply is less than the power-off threshold.

[0069] The above simulation results show that the power-on reset circuit of the present invention can perform power-on reset and power-off protection on multiple power supplies, and has a high-precision power-on threshold and power-off threshold, and there is an adjustable hysteresis interval between the two thresholds.

[0070] The above descriptions are only several specific examples of the present invention and do not constitute any limitation to the present invention. Obviously, for professionals in this field, after understanding the content and principles of the present invention, various modifications and changes in form and details may be made without departing from the principles and structures of the present invention. For example, in addition to the second power supply voltage divider module and the second power supply threshold module given in this example, the number of modules of the power supply detection unit can be increased or decreased; in addition to the ratio and size of the cascade resistor string unit given in this example, the ratio and size of the two power supply voltage divider modules can be modified; in addition to the size and ratio of the two bipolar transistors and the two resistors given in this example, the size and ratio of the first power supply threshold module can be increased or decreased; in addition to the weak pull-up transistor and the threshold transistor given in this example, the number of transistors of the second power supply threshold module can be increased or decreased. In addition to the relationship given in this example, other connection relationships can be adopted according to different devices used for the connection of components in each circuit, but these modifications and changes based on the idea of ​​the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A high-precision multi-power supply detection power-on reset circuit, comprising a power supply detection unit (1) and a buffer unit (2), characterized in that: The power supply detection unit (1) is used to detect the power on and off of the power supply and to provide a reset signal with an accurate threshold value, and comprises two power supply voltage division modules (11, 14), two power supply threshold modules (12, 15) and a high-to-low module (13). The output fed back by the buffer unit (2) is transmitted to the first power supply voltage division module (11) and the high-to-low module (13) for voltage division and conversion; the conversion voltage output by the high-to-low module (13) is converted again by the second power supply voltage division module (14), and then output to the first power supply threshold module (12) and the second power supply threshold module (15) for comparison and merging, and then transmitted to the buffer unit (2) to output a final reset signal.

2. The circuit according to claim 1, characterized in that: The first power supply voltage dividing module (11) has an input end connected to the feedback output of the buffer unit (2), an output end connected to the input end of the first power supply threshold module (12), and an output end of the first power supply threshold module (12) connected to the input end of the buffer unit (2); The high-to-low conversion module (13) has an input end connected to the feedback output of the buffer unit (2), and an output end connected to the input end of the second power supply voltage dividing module (14); The second power supply voltage dividing module (14) has an output end connected to the input end of the second power supply threshold module (15), and the output end of the second power supply threshold module (15) is connected to the input of the buffer unit (2); The operating voltages of the above modules are all supplied by an external power supply, which includes a first power supply VDD1 and a second power supply VDD2.

3. The circuit according to claim 2, characterized in that The first power supply voltage divider module (11) comprises a first resistor R1, a second resistor R2, a third resistor R3 and a hysteresis transistor M1, and is used to detect the power supply voltage and provide a voltage divider output, wherein: The first resistor R1 has a first end connected to the first power source VDD1 and a tail end connected to a first end of the second resistor R2; The tail end of the second resistor R2 is connected to the head end of the third resistor R3, and the tail end of the third resistor R3 is connected to the power ground; The hysteresis transistor M1 is a PMOS transistor, a source of which is connected to the first power supply VDD1, a drain of which is connected to the tail end of the first resistor R1, and a gate of which is connected to the feedback output ENB of the buffer unit (2).

4. The circuit according to claim 2, characterized in that The first power supply threshold module (12) comprises threshold bipolar transistors Q0 and Q1, load transistors M2 and M3, a driving transistor M4, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6 and a load capacitor C0, and is used to generate an accurate power-on threshold and a power-off threshold of the first power supply and output a detection result of the first power supply, wherein: The threshold bipolar transistors Q0 and Q1 have bases connected to the output end of the first power voltage divider module (11), emitters connected to the first ends of the fifth resistor R5 and the fourth resistor R4, and collectors connected to the drains of the load transistors M2 and M3; The load transistors M2 and M3 are PMOS transistors, the gates of which are connected to the collector of the bipolar transistor Q0, the sources of which are connected to the first power supply VDD1, and the drains of which are connected to the collectors of the bipolar transistors Q0 and Q1 respectively; The driving transistor M4 is a PMOS transistor, a source of which is connected to the first power supply VDD1, a gate of which is connected to the collector of the bipolar transistor Q1, and a drain of which is connected to the sixth resistor R6 and the first end of the load capacitor C0; The fourth resistor R4 and the fifth resistor R5 have their first ends connected to the emitters of the threshold bipolar transistors Q1 and Q0 respectively, and their tail ends are connected to the power ground and the first end of the fourth resistor R4 respectively; the sixth resistor R6 and the load capacitor C0 have their tail ends connected to the power ground, and their first ends are connected to the drain of the driving transistor M4.

5. The circuit according to claim 2, characterized in that The high-to-low conversion module (13) comprises conversion pull-up transistors M13 and M15, and conversion pull-down transistors M14 and M16, which are used to convert the output level of the buffer module from a high voltage to a low voltage, wherein: The conversion pull-up transistor M13 and the conversion pull-down transistor M14 have their sources connected to the power supply VDD1 and the power ground respectively, their gates connected to the output ENB of the buffer unit (2), and their drains connected to the gate of the conversion pull-down transistor M16; The conversion pull-up transistor M15 and the conversion pull-down transistor M16 have their sources connected to the power supply VDD2 and the power ground respectively, and their gates are connected to the drain of the conversion pull-up transistor M13, and the drain is used as the output end of the high-to-low module (13).

6. The circuit according to claim 2, characterized in that The second power supply voltage dividing module (14) comprises a seventh resistor R7, an eighth resistor R8, a ninth resistor R9 and a hysteresis transistor M9, and is used to detect the second power supply voltage and provide a voltage dividing output, wherein: The seventh resistor R7 has a first end connected to the second power source VDD2 and a second end connected to a first end of an eighth resistor R8; The tail end of the eighth resistor R8 is connected to the head end of the ninth resistor R9, and the tail end of the ninth resistor R9 is connected to the power ground; The hysteresis transistor M9 is a PMOS transistor, a source of which is connected to the second power supply VDD2, a drain of which is connected to the tail end of the seventh resistor R7, and a gate of which is connected to the output of the high-to-low conversion module (13).

7. The circuit according to claim 2, characterized in that The second power supply threshold module (15) comprises a weak pull-up transistor M10, a threshold transistor M11 and a pull-down transistor M12, and is used to generate a power-on threshold and a power-off threshold of the second power supply and output a detection result of the second power supply, wherein: The weak pull-up transistor M10 is a PMOS transistor, a source of which is connected to the first power supply VDD1, a gate of which is connected to the power supply ground, and a drain of which is connected to the drain of the threshold transistor M11; The threshold transistor M11 is an NMOS transistor, a source of which is connected to the power ground, and a gate of which is connected to the output end of the second power voltage divider module (14); The pull-down transistor M12 is an NMOS transistor, a source of which is connected to the power ground, a gate of which is connected to the drain of the threshold transistor M11, and the drain serves as the output end of the module.

8. The circuit according to claim 2, characterized in that The buffer unit (2) comprises two buffer pull-up transistors M5 and M7, and two buffer pull-down transistors M6 and M8, which are used to unify the outputs of multiple power detection units and output a final power-on reset signal, wherein: The first buffer pull-up transistor M5 has a source connected to the first power supply VDD1, a gate connected to the gate of the first buffer pull-down transistor M6, and the gate is used as an input terminal of the buffer unit (2), and a drain connected to the drain of the first buffer pull-down transistor M6; The first buffer pull-down transistor M6 has a source connected to the power ground, a gate connected to the gate of the first buffer pull-up transistor M5, and a drain used as an ENB output terminal of the buffer unit (2); The second buffer pull-up transistor M7 has a source connected to the first power supply VDD1, a gate connected to the gate of the second buffer pull-down transistor M8, and a drain connected to the drain of the second buffer pull-down transistor M8; The second buffer pull-down transistor M8 has a source connected to the power ground, a gate connected to the gate of the second buffer pull-up transistor M7, and a drain serving as the EN output terminal of the buffer unit (2).

9. A method for performing power-on reset using the power-on reset circuit of claim 1, characterized in that: These include: The first power supply VDD1 and the second power supply VDD2 are set to enter a power-on state so that the power supply voltage gradually rises. At this time, the power supply detection unit (1) receives a high-level feedback signal ENB from the buffer unit (2) and transmits it to a high-to-low conversion module (13) to convert it into a low-voltage signal; The low voltage signal and the high level feedback signal ENB are transmitted to the second power voltage divider module (14) and the first power voltage divider module (11) respectively to generate respective power-on voltage dividers, and then transmitted to the second power threshold module (15) and the first power threshold module (12) respectively for comparison; when the power-on voltage divider is greater than the power-on thresholds of the two threshold modules, the threshold module outputs a comparison result of a high level, and then transmits the comparison result to the buffer unit (2); The buffer unit (2) receives the high level of the comparison result and outputs it, completing the power-on reset of the circuit.

10. A method for power-off protection using the power-on reset circuit of claim 1, characterized in that: These include: After the power-on reset is completed, the first power supply VDD1 and the second power supply VDD2 are set to enter a power-off state, so that the power supply voltage gradually decreases. At this time, the power supply detection unit (1) receives the low-level feedback signal ENB from the buffer unit (2) and transmits it to the high-to-low module (13) to convert it into a low voltage signal; The low voltage signal and the low level feedback signal ENB are transmitted to the second power voltage divider module (14) and the first power voltage divider module (11) respectively to generate respective power-off voltage dividers, and then transmitted to the second power threshold module (15) and the first power threshold module (12) respectively for comparison; when the power-off voltage divider is lower than the power-off thresholds of the two threshold modules, the threshold module outputs a comparison result of a low level, and then transmits the comparison result to the buffer unit (2); The buffer unit (2) receives the low level of the comparison result and outputs it, thereby completing the power-off protection of the circuit.

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