Sampling method of analog-to-digital converter in single-chip microcomputer and single

Abstract

The invention provides a sampling method of an analog-to-digital converter in a single-chip microcomputer and the single-chip microcomputer. The method comprises the following steps: acquiring the data volume of a plurality of sampling segments and the number of the sampling segments, wherein the data volume of each sampling segment is smaller than or equal to the storage capacity of a memory; according to the data volume of the plurality of sampling segments, the number of the sampling segments, the sampling frequency of the analog-to-digital converter, the signal frequency of the sampled signal and the number of complete cycles, the offset from the second sampling segment to the pth sampling segment is determined, and p is the number of the sampling segments; and acquiring a synchronization point of each sampling section, controlling the analog-to-digital converter to sample the sampled signal according to the synchronization point of each sampling section and the offset from the second sampling section to the pth sampling section, obtaining a sampling section, controlling the analog-to-digital converter to stop sampling, transmitting the obtained sampling section to a memory, and storing the memory. And after the sampling segments stored in the memory are sent out, the analog-to-digital converter is continuously controlled to sample the sampled signal until the pth sampling segment is transmitted to the memory.

Description

Technical Field

[0001] The present application relates to the field of signal sampling, and in particular to a sampling method of an analog-to-digital converter in a single-chip microcomputer, a computer program product, a computer-readable storage medium and a single-chip microcomputer. Background Art

[0002] IEEE1241 defines the index parameters and test methods of ADC (Analog-to-Digital Converter). The main task of ADC test evaluation is to determine its voltage transmission relationship. Ideally, the transmission relationship between the input voltage and the midpoint of the ADC output code is a straight line, and the width of each output code is the same. The actual voltage transmission relationship is different from the ideal situation. The IEEE1241 standard provides several optional test steps and methods. At present, one of the most mainstream methods is: code density test method based on sine wave signal and statistical histogram.

[0003] In the process of measuring and evaluating the ADC inside the single-chip microcomputer using the above method, since the minimum total amount of ADC sampling data is much larger than the SRAM capacity inside the single-chip microcomputer, the "segmented sampling + data splicing" method is generally used to divide the entire sampling cycle into several sub-segments, and the segmented sampling data is temporarily stored in the internal SRAM, and then sequentially transmitted to the host computer or other large-capacity storage before sampling the next sub-segment, and finally multiple sampling data are spliced ​​into a complete sampling sample data file for parameter calculation. This method can solve the problem that the total amount of ADC sampling data cannot be fully stored due to insufficient SRAM space, but it will introduce a new problem, that is, the initial sampling point position of each new sub-segment is uncertain, resulting in the sampling point interval between sub-segments no longer following the inherent sampling cycle, which in turn causes the final sampled signal to have a spectrum leakage problem. Summary of the invention

[0004] The main purpose of the present application is to provide a sampling method of an analog-to-digital converter in a single-chip microcomputer, a computer program product, a computer-readable storage medium and a single-chip microcomputer, so as to at least solve the problem of spectrum leakage of the ADC sampling signal in the single-chip microcomputer in the prior art.

[0005] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a sampling method for an analog-to-digital converter in a single-chip microcomputer is provided, the single-chip microcomputer also including a memory, the method comprising: obtaining the data amount of multiple sampling segments and the number of sampling segments, the data amount of each sampling segment is less than or equal to the storage capacity of the memory, and the multiple sampling segments are obtained by segmenting the sampling samples of the analog-to-digital converter; according to the data amount of the multiple sampling segments, the number of sampling segments, the sampling frequency of the analog-to-digital converter, the signal frequency of the sampled signal and the number of complete cycles, determining the offset from the second sampling segment to the pth sampling segment, the offset being the difference between the synchronization point at the start of sampling and the start of sampling The difference between the actual values ​​at the moment, the number of complete cycles is the number of complete cycles of the sampled signal contained in the sampling sample, and p is the number of sampling segments; the synchronization point of each sampling segment is obtained, and according to the synchronization point of each sampling segment and the offset from the second sampling segment to the pth sampling segment, the analog-to-digital converter is controlled to sample the sampled signal to obtain a sampling segment and the analog-to-digital converter is controlled to stop sampling, and the obtained sampling segment is transmitted to the memory, and after the sampling segment stored in the memory is sent, the analog-to-digital converter is continuously controlled to sample the sampled signal until the pth sampling segment is transmitted to the memory.

[0006] Optionally, determining the offset from the second sampling segment to the pth sampling segment according to the data volume of the plurality of sampling segments, the number of sampling segments, the sampling frequency of the analog-to-digital converter, the signal frequency of the sampled signal, and the number of complete cycles comprises: determining the offset of the qth sampling segment as: Δq=F S (q-1)S q -F IN Q, where Δq is the offset of the qth sampling segment, F S is the sampling frequency, q is the sequence number of the sampling segment, S q is the data volume of the qth sampling segment, F IN is the signal frequency, Q is the number of complete cycles, and 1<q≤p.

[0007] Optionally, obtaining the synchronization point of each of the sampling segments includes: each time an interrupt triggered by a comparator in the single-chip microcomputer is received, determining that a synchronization point is obtained, the synchronization point being the triggering moment of the interrupt, obtaining a plurality of synchronization points arranged in order from early to late within a predetermined time length, the predetermined time length being the total time length for sampling the sampled signal to obtain the sampled sample, and the interrupt being triggered by the comparator whenever the voltage value of the sampled signal is equal to a predetermined threshold.

[0008] Optionally, according to the synchronization point of each sampling segment and the offset from the second sampling segment to the pth sampling segment, the analog-to-digital converter is controlled to sample the sampled signal to obtain a sampling segment and the analog-to-digital converter is controlled to stop sampling, the obtained sampling segment is transmitted to the memory, and after the sampling segment stored in the memory is issued, the analog-to-digital converter is continuously controlled to sample the sampled signal until the pth sampling segment is transmitted to the memory, including: a sampling step, when the sampled signal starts to be received and the interrupt is received for the first time, the analog-to-digital converter is controlled to sample the sampled signal, and when the sampling stop condition is met, the analog-to-digital converter is controlled to stop sampling to obtain the first sampling segment. The method comprises the following steps: a sampling segment is selected and the first sampling segment is transmitted to the memory; a timing step is performed, when the q-1th sampling segment stored in the memory has been issued and the interrupt is received for the qth time, the timer is controlled to start timing, and when the timing time reaches the offset corresponding to the qth sampling segment, the analog-to-digital converter is controlled to sample the sampled signal; a stopping step is performed, when the sampling stopping condition is met, the analog-to-digital converter is controlled to stop sampling, the qth sampling segment is obtained, and the qth sampling segment is transmitted to the memory; a looping step is performed, when q is not equal to p, the q+1th sampling segment is determined to be the new qth sampling segment, and the timing step and the stopping step are looped until q is equal to p, so as to obtain all the sampling segments.

[0009] Optionally, according to the synchronization point of each sampling segment and the offset from the second sampling segment to the pth sampling segment, the analog-to-digital converter is controlled to sample the sampled signal to obtain a sampling segment and the analog-to-digital converter is controlled to stop sampling, the obtained sampling segment is transmitted to the memory, and after the sampling segment stored in the memory is issued, the analog-to-digital converter is continuously controlled to sample the sampled signal until the pth sampling segment is transmitted to the memory, including: determining that the actual value of the first sampling segment is the synchronization point of the first sampling segment; calibrating the synchronization point of the qth sampling segment according to the offset of the qth sampling segment to obtain the pth sampling segment. The actual values ​​of q sampling segments, the actual value of the qth sampling segment is the sum of the synchronization point of the qth sampling segment and the offset of the qth sampling segment, wherein 1<q≤p; when the actual value is reached at the moment of receiving the sampled signal, the analog-to-digital converter is controlled to sample the sampled signal to obtain a sampling segment and the analog-to-digital converter is controlled to stop sampling, and the obtained sampling segment is transferred to the memory; after the sampling segment stored in the memory is sent and the moment of receiving the sampled signal reaches the next actual value, the analog-to-digital converter is controlled to continue sampling the sampled signal until the pth sampling segment is transferred to the memory.

[0010] Optionally, obtaining the data volume of multiple sampling segments and the number of sampling segments includes: obtaining the storage capacity, the signal frequency, the sampling frequency and the number of cycles sampled by the sampled signal; determining the number of samples as the product of the signal frequency and the number of cycles divided by the sampling frequency based on the signal frequency, the sampling frequency and the number of cycles sampled by the sampled signal, wherein the sampling samples include multiple samples; determining the data volume of the sampling samples as the product of the number of samples and the number of storage bits occupied by each sample based on the number of samples and the number of storage bits occupied by each sample; determining the number of sampling segments based on the data volume of the sampling samples and the storage capacity of the memory, wherein the number of sampling segments is greater than or equal to the ratio of the data volume of the sampling samples to the storage capacity; determining the data volume of each sampling segment based on the number of sampling segments and the data volume of the sampling samples.

[0011] Optionally, determining the data volume of each sampling segment according to the number of sampling segments and the data volume of the sampling samples includes: when the number of sampling segments is greater than the ratio of the data volume of the sampling samples to the storage capacity, determining, according to the number of sampling segments and the data volume of the sampling samples, that the data volumes of the first sampling segment to the p-1th sampling segment are all first target data volumes, the first target data volume is less than or equal to the storage capacity, and determining the data volume of the pth sampling segment as a second target data volume, the second target data volume is Sp=Ssum-(p-1)S, S sum is the data volume of the sampling sample, S is the first target data volume; when the number of sampling segments is equal to the ratio of the data volume of the sampling sample to the storage capacity, according to the number of sampling segments and the data volume of the sampling sample, it is determined that the data volume of each sampling segment is the ratio of the data volume of the sampling sample to the number of sampling segments.

[0012] According to another aspect of the present application, a computer program product is provided, comprising computer instructions, wherein when the computer instructions are executed by a processor, any one of the methods described above is implemented.

[0013] According to another aspect of the present application, a computer-readable storage medium is provided, wherein the computer-readable storage medium includes a stored program, wherein when the program is executed, the device where the computer-readable storage medium is located is controlled to execute any one of the methods described.

[0014] According to another aspect of the present application, a single chip microcomputer is provided, comprising: an analog-to-digital converter; a memory; and a controller, for executing any one of the methods described.

[0015] By applying the technical solution of the present application, the sampled samples are divided into multiple sampling segments, so that the amount of data in each sampling segment is not greater than the storage capacity of the memory in the single-chip microcomputer, ensuring that each sampling segment can be stored in the memory of the single-chip microcomputer, and each storage is after the memory sends out the sampling segment stored therein; at the same time, the present application sets a synchronization point for the sampling start time for each sampling segment, and uses the synchronization point as a reference to calibrate the sampling start time according to the offset from the second to the last sampling segment, and controls the analog-to-digital converter to perform segmented discontinuous sampling according to the calibrated sampling start time, ensuring that the sampling interval duration between the sampling segments is consistent. The method of the present application not only solves the problem of data loss caused by insufficient storage space of the sampling data of the analog-to-digital converter, but also avoids the problem of sampling spectrum leakage caused by inconsistent sampling intervals before and after the sampling segment of the analog-to-digital converter during the sampling process. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings constituting part of the present application are used to provide a further understanding of the present application. The exemplary embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0017] Figure 1 A hardware structure block diagram of a mobile terminal for executing a sampling method of an analog-to-digital converter in a single-chip microcomputer provided in an embodiment of the present application is shown;

[0018] Figure 2 A schematic flow chart of a sampling method of an analog-to-digital converter in a single-chip microcomputer provided according to an embodiment of the present application is shown;

[0019] Figure 3 A schematic diagram of implementing ADC segmented sampling and compensation calibration according to an embodiment of the present application is shown;

[0020] Figure 4 A structural block diagram of a sampling device of an analog-to-digital converter in a single-chip microcomputer provided according to an embodiment of the present application is shown;

[0021] Figure 5 A schematic diagram of the structure of a single chip microcomputer provided according to an embodiment of the present application is shown;

[0022] Figure 6 A sampling flow chart of an analog-to-digital converter in a single-chip microcomputer provided according to an embodiment of the present application is shown.

[0023] The above drawings include the following reference numerals:

[0024] 102, processor; 104, memory; 106, transmission device; 108, input and output devices. DETAILED DESCRIPTION

[0025] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0026] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0027] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the accompanying drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0028] As introduced in the background technology, there is a problem of spectrum leakage in the ADC sampling signal in the microcontroller in the prior art. To solve the above problem, the embodiments of the present application provide a sampling method of an analog-to-digital converter in a microcontroller, a computer program product, a computer-readable storage medium and a microcontroller.

[0029] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0030] The method embodiments provided in the embodiments of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Taking running on a mobile terminal as an example, Figure 1 1 is a hardware structure block diagram of a mobile terminal of a sampling method of an analog-to-digital converter in a single-chip microcomputer according to an embodiment of the present invention. Figure 1 As shown, the mobile terminal may include one or more ( Figure 1 Only one is shown in the figure) a processor 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the mobile terminal may also include a transmission device 106 and an input / output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is for illustration only and does not limit the structure of the mobile terminal. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations are shown.

[0031] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the sampling method of the analog-to-digital converter in the single-chip microcomputer in the embodiment of the present invention. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, the method described is implemented. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the mobile terminal via a network. Examples of the network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof. The transmission device 106 is used to receive or send data via a network. The specific example of the network may include a wireless network provided by a communication provider of the mobile terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 may be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0032] In this embodiment, a sampling method for an analog-to-digital converter in a single-chip microcomputer running in a mobile terminal, a computer terminal or a similar computing device is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0033] Figure 2 1 is a flow chart of a sampling method of an analog-to-digital converter in a single-chip microcomputer according to an embodiment of the present application. The single-chip microcomputer (Microcontroller Unit, referred to as MCU) includes an analog-to-digital converter (ADC) and a memory, such as Figure 2 As shown, the method comprises the following steps:

[0034] Step S201, obtaining the data volume and number of sampling segments of a plurality of sampling segments, wherein the data volume of each sampling segment is less than or equal to the storage capacity of the memory, and the plurality of sampling segments are obtained by segmenting the sampling samples of the analog-to-digital converter;

[0035] Specifically, the sampling samples are obtained by the analog-to-digital converter continuously sampling the sampled signal. The number of sampling segments is the total number of sampling segments. The product of the data volume of the sampling segment and the number of sampling segments must be greater than or equal to the minimum sampling sample data volume of the analog-to-digital converter.

[0036] Step S202, determining an offset from the second sampling segment to the pth sampling segment according to the data volume of the plurality of sampling segments, the number of sampling segments, the sampling frequency of the analog-to-digital converter, the signal frequency of the sampled signal, and the number of complete cycles, wherein the offset is the difference between the synchronization point at the start of sampling and the actual value at the start of sampling, the number of complete cycles is the number of complete cycles of the sampled signal contained in the sample, and p is the number of sampling segments;

[0037] Specifically, the number of complete cycles is a positive integer. The sampled signal is a sinusoidal wave signal.

[0038] Step S203, obtaining the synchronization point of each sampling segment, and controlling the analog-to-digital converter to sample the sampled signal according to the synchronization point of each sampling segment and the offset from the second sampling segment to the pth sampling segment, obtaining a sampling segment and controlling the analog-to-digital converter to stop sampling, transmitting the obtained sampling segment to the memory, and continuing to control the analog-to-digital converter to sample the sampled signal after the sampling segment stored in the memory is sent out, until the pth sampling segment is transmitted to the memory.

[0039] Specifically, the memory can send the received sampling segment to a host computer or other large-capacity non-volatile memory. Subsequently, multiple sampling segments in the host computer or other large-capacity non-volatile memory are spliced ​​into a complete sampling sample data file, which is used to measure and evaluate the static parameters DNL (Differential nonlinearity), INL (Integral Nonlinearity), dynamic parameters ENOB (Effective number of bits), SINAD (Signal-to-Noise and Distortion Ratio), SNR (Signal to Noise Ratio), THD (Total harmonic distortion), etc. of the built-in ADC of the MCU.

[0040] Through the embodiment, the number of sampling segments of the analog-to-digital converter and the amount of data in each sampling segment are first obtained, so that the amount of data in each sampling segment is not greater than the storage capacity of the memory; then, based on the number of sampling segments, the amount of data in each sampling segment, the sampling frequency, the signal frequency of the sampled signal, and the number of complete cycles, the offset from the second to the last sampling segment is determined, and the offset represents the difference between the synchronization point at the start of sampling and the actual value; finally, the synchronization point of each sampling segment is obtained, and based on the synchronization point and the offset, the analog-to-digital converter is controlled to sample the sampled signal, and sampling is stopped after a sampling segment is obtained, the sampling segment is stored in the memory, and sampling is continued only after the sampling segment in the memory is sent, until all the sampling segments are sampled and stored in the memory. The present application divides the sampled samples into multiple sampling segments, so that the amount of data in each sampling segment is not greater than the storage capacity of the memory in the single-chip microcomputer, ensuring that each sampling segment can be stored in the memory of the single-chip microcomputer, and each storage is after the memory sends out the sampling segment stored therein; at the same time, the present application sets a synchronization point for the sampling start time for each sampling segment, and uses the synchronization point as a reference, calibrates the sampling start time according to the offset from the second to the last sampling segment, and controls the analog-to-digital converter to perform segmented discontinuous sampling according to the calibrated sampling start time, ensuring that the sampling interval duration between the sampling segments is consistent. The method of the present application not only solves the problem of data loss caused by insufficient storage space of the sampling data of the analog-to-digital converter, but also avoids the problem of sampling spectrum leakage caused by inconsistent sampling intervals before and after the sampling segment of the analog-to-digital converter during the sampling process.

[0041] Specifically, the sampled signal may be provided by a dedicated sine wave signal source device, and the frequency and amplitude of the sampled signal may be set.

[0042] Specifically, the memory may be an SRAM. The SRAM is used to store ADC sampling data, and generally has a capacity of tens of KB to hundreds of KB.

[0043] In an optional solution, according to the data volume of the plurality of sampling segments, the number of the sampling segments, the sampling frequency of the analog-to-digital converter, the signal frequency of the sampled signal, and the number of complete cycles, determining the offset from the second sampling segment to the pth sampling segment includes: according to the data volume of the plurality of sampling segments, the number of the sampling segments, the sampling frequency of the analog-to-digital converter, the signal frequency of the sampled signal, and the number of complete cycles, determining the offset of the qth sampling segment as: Δq=F S (q-1)S q -F IN Q, where Δq is the offset of the qth sampling segment, F S is the sampling frequency, q is the sequence number of the sampling segment, S qis the data volume of the qth sampling segment, F IN is the signal frequency, Q is the number of complete cycles, and 1<q≤p. The formula is used to determine the phase offset of the actual value of the sampling start time of the sampling segment on the continuous sine wave signal (i.e., the sampled signal) compared to the synchronization point, which is used for position calibration at the sampling start time, further ensuring that the sampling point intervals between adjacent sampling segments are consistent with other sampling point intervals, that is, further ensuring that the segmented sampling frequency is consistent with the ideal continuous sampling frequency, thereby further avoiding the spectrum leakage problem caused by frequency inconsistency.

[0044] Specifically, the multiple sampling segments are divided into the first sampling segment, the second sampling segment, the third sampling segment..., the qth sampling segment,..., the pth sampling segment according to the sampling order. When calculating the offset of the second sampling segment, q in the formula is 2; when calculating the offset of the third sampling segment, q in the formula is 3, and so on, to obtain the offset corresponding to the second sampling segment to the pth sampling segment.

[0045] Optionally, obtaining the synchronization point of each sampling segment includes: each time an interrupt triggered by a comparator in the single-chip microcomputer is received, determining to obtain a synchronization point, the synchronization point being the triggering moment of the interrupt, obtaining a plurality of synchronization points arranged in order from early to late within a predetermined time length, the predetermined time length being the total time length of sampling the sampled samples from the sampled signal, and the interrupt being triggered by the comparator whenever the voltage value of the sampled signal is equal to a predetermined threshold. In the present application, the signal period of the sampled signal can be obtained by using the comparator in the single-chip microcomputer, that is, the sampling synchronization point of each sampling segment is determined by comparing the voltage value of the input sampled signal with the predetermined threshold through the comparator, and the interrupt is triggered when the voltage value of the sampled signal is the same as the predetermined threshold, as the sampling synchronization point of the sampling segment.

[0046] Specifically, the digital-to-analog converter (DAC) in the single-chip microcomputer can provide the comparator with a level signal of the predetermined threshold value. The comparator converts the sinusoidal wave signal into a square wave signal by comparing the sinusoidal wave signal with the level signal of the predetermined threshold value, and outputs the square wave signal. The timer calculates the period of the square wave signal using the capture function to obtain the signal period of the sinusoidal wave signal.

[0047] According to some further embodiments of the present application, step S203: according to the synchronization point of each sampling segment and the offset from the second sampling segment to the pth sampling segment, controlling the analog-to-digital converter to sample the sampled signal, obtaining a sampling segment and controlling the analog-to-digital converter to stop sampling, transmitting the obtained sampling segment to the memory, and continuing to control the analog-to-digital converter to sample the sampled signal after the sampling segment stored in the memory is sent, until the pth sampling segment is transmitted to the memory, including:

[0048] Step S2031: a sampling step, when the sampled signal starts to be received and the interrupt is received for the first time, controlling the analog-to-digital converter to sample the sampled signal, and controlling the analog-to-digital converter to stop sampling when a sampling stop condition is met, to obtain the first sampling segment, and transmitting the first sampling segment to the memory;

[0049] Specifically, when the interrupt is received for the first time, it is indicated that this is the synchronization point of the sampling start time of the first sampling segment.

[0050] Step S2032: a timing step, when the q-1th sampling segment stored in the memory has been issued and the interrupt is received for the qth time, controlling the timer to start timing, and when the timing duration reaches the offset corresponding to the qth sampling segment, controlling the analog-to-digital converter to sample the sampled signal;

[0051] Step S2033: a stop step, controlling the analog-to-digital converter to stop sampling when the sampling stop condition is met, obtaining the qth sampling segment, and transmitting the qth sampling segment to the memory;

[0052] Step S2034: a loop step, when q is not equal to p, determining the q+1th sampling segment as the new qth sampling segment, and looping the timing step and the stop step until q is equal to p, thereby obtaining all the sampling segments.

[0053] In the embodiment, in the sampling stage, the synchronization point of the start sampling moment of each sampling segment is determined. When the interrupt is triggered, the offset between the synchronization point of the sampling segment obtained in the sampling preprocessing stage and the actual value is called, and the sampling is started after the sampling point moves the offset from the synchronization point through the timer delay, further ensuring that the sampling interval duration between the sampling segments is consistent. In addition, the present application will pause sampling after collecting a sampling segment, transfer the sampling segment to the memory, and then wait for the data in the memory to be uploaded to the host computer or other large-capacity non-volatile memory before executing sampling, further avoiding the problem that the total amount of sampling data of the analog-to-digital converter cannot be fully stored due to the limited capacity of the memory, and further ensuring the integrity and reliability of the sampling data.

[0054] Specifically, the sampling stop condition may include at least one of the following: whether the amount of collected data reaches the amount of data in each sampling segment; whether the collection time reaches the collection time of each sampling segment.

[0055] According to some further embodiments of the present application, step S203: according to the synchronization point of each sampling segment and the offset from the second sampling segment to the pth sampling segment, controlling the analog-to-digital converter to sample the sampled signal, obtaining a sampling segment and controlling the analog-to-digital converter to stop sampling, transmitting the obtained sampling segment to the memory, and continuing to control the analog-to-digital converter to sample the sampled signal after the sampling segment stored in the memory is sent, until the pth sampling segment is transmitted to the memory, including:

[0056] Step S2031': Determine that the actual value of the first sampling segment is the synchronization point of the first sampling segment;

[0057] Step S2032′: Calibrate the synchronization point of the qth sampling segment according to the offset of the qth sampling segment to obtain the actual value of the qth sampling segment, the actual value of the qth sampling segment being the sum of the synchronization point of the qth sampling segment and the offset of the qth sampling segment, wherein 1<q≤p;

[0058] Step S2033': when the moment of receiving the sampled signal reaches the actual value, controlling the analog-to-digital converter to sample the sampled signal to obtain a sampling segment and controlling the analog-to-digital converter to stop sampling, and transmitting the obtained sampling segment to the memory;

[0059] Step S2034': after the sampling segment stored in the memory is sent out and when the moment of receiving the sampled signal reaches the next actual value, control the analog-to-digital converter to continue sampling the sampled signal until the pth sampling segment is transmitted to the memory.

[0060] In the embodiment, the actual value of the first sampling segment is determined to be its synchronization point, and the synchronization point is calibrated according to the offset from the second sampling segment to the pth sampling segment to obtain the actual value from the second sampling segment to the pth sampling segment, and when each actual value is reached at the sampling moment, the analog-to-digital converter is controlled to sample the sampled signal, further ensuring that the sampling interval duration between the sampling segments is consistent. In addition, the present application will pause sampling after collecting a sampling segment, transfer the sampling segment to the memory, and then wait for the data in the memory to be uploaded to the host computer or other large-capacity non-volatile memory before executing sampling, further avoiding the problem that the total amount of sampling data of the analog-to-digital converter cannot be completely stored due to the limited capacity of the memory, and further ensuring the integrity and reliability of the sampled data.

[0061] Specifically, the schematic diagram of the ADC segmentation sampling and compensation calibration is as follows: Figure 3 As shown, Fs0 is the actual value at the sampling start time of the first sampling segment, Fs1 is the actual value at the sampling start time of the second sampling segment, Fs2, ..., Fsp-1 and so on. S1 is the first sampling segment, S2 is the second sampling segment, S3, ..., Sp-1, Sp and so on. △1+TS is the offset of the second sampling segment, △2+TS is the offset of the third sampling segment, and the offsets of other sampling segments are expressed in the same way.

[0062] In order to further ensure that the data volume of each sampling segment is not greater than the storage capacity of the memory in the single-chip microcomputer, thereby further ensuring that each sampling segment can be stored in the memory of the single-chip microcomputer, in some embodiments, step S201: obtaining the data volume and the number of sampling segments of multiple sampling segments, includes:

[0063] Step S2011: acquiring the storage capacity, the signal frequency, the sampling frequency and the number of cycles sampled by the sampled signal;

[0064] Specifically, a threshold value V is set for the comparator inside the MCU, and the input sinusoidal wave signal is converted into an output square wave through the comparator. The square wave width is counted using the timer capture function to obtain the period duration Tin=K*Ttimer of the sinusoidal wave signal. The inverse of the period is the signal frequency, where K is the number of timer counts and Ttimer is the period of the timer.

[0065] Step S2012: According to the signal frequency, the sampling frequency and the number of cycles sampled by the sampled signal, the number of samples is determined as the product of the signal frequency and the number of cycles divided by the sampling frequency, and the sampled sample includes a plurality of the samples;

[0066] Step S2013: according to the number of samples and the number of storage bits occupied by each sample, determine the data volume of the sampled sample as the product of the number of samples and the number of storage bits;

[0067] Step S2014: determining the number of sampling segments according to the data volume of the sample and the storage capacity of the memory, wherein the number of sampling segments is greater than or equal to the ratio of the data volume of the sample to the storage capacity;

[0068] Step S2015: Determine the data volume of each sampling segment according to the number of sampling segments and the data volume of the sampling samples.

[0069] In a specific embodiment, according to the number of sampling segments and the data volume of the sampling samples, determining the data volume of each sampling segment includes: when the number of sampling segments is greater than the ratio of the data volume of the sampling samples to the storage capacity, according to the number of sampling segments and the data volume of the sampling samples, determining that the data volumes of the first sampling segment to the p-1th sampling segment are all the first target data volumes, that is, S1=S2=…=S (p-1) =S, the first target data volume is less than or equal to the storage capacity, and the data volume of the pth sampling segment is determined to be the second target data volume, and the second target data volume is S p =S sum -(p-1)S,S sum is the data volume of the sample, S is the first target data volume; when the number of sampling segments is equal to the ratio of the data volume of the sample to the storage capacity, the data volume of each sampling segment is determined to be the ratio of the data volume of the sample to the number of sampling segments according to the number of sampling segments and the data volume of the sample. In the embodiment, the sample is divided into p segments so that the capacity of each segment is not greater than the size of the memory.

[0070] In order to enable those skilled in the art to more clearly understand the technical solution of the present application, the implementation process of the sampling method of the analog-to-digital converter in the single-chip microcomputer of the present application will be described in detail below in combination with specific embodiments.

[0071] It should be noted that the steps shown in the flowcharts of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and that, although a logical order is shown in the flowcharts, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0072] The present application embodiment also provides a sampling device for an analog-to-digital converter in a single-chip microcomputer. It should be noted that the sampling device for an analog-to-digital converter in a single-chip microcomputer in the present application embodiment can be used to execute the sampling method for an analog-to-digital converter in a single-chip microcomputer provided in the present application embodiment. The device is used to implement the embodiments and preferred implementations, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware for a predetermined function. Although the device described in the following embodiments is preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceived.

[0073] The following is an introduction to the sampling device of the analog-to-digital converter in the single-chip microcomputer provided in the embodiment of the present application.

[0074] Figure 4 Schematic diagram of a sampling device of an analog-to-digital converter in a single-chip microcomputer according to an embodiment of the present application. Figure 4 As shown, the device comprises:

[0075] A first acquisition unit 10 is used to acquire the data volume and number of sampling segments of a plurality of sampling segments, wherein the data volume of each sampling segment is less than or equal to the storage capacity of the memory, and the plurality of sampling segments are obtained by segmenting the sampling samples of the analog-to-digital converter;

[0076] Specifically, the sampling samples are obtained by the analog-to-digital converter continuously sampling the sampled signal. The number of sampling segments is the total number of sampling segments. The product of the data volume of the sampling segment and the number of sampling segments must be greater than or equal to the minimum sampling sample data volume of the analog-to-digital converter.

[0077] A determination unit 20 is used to determine an offset from the second sampling segment to the pth sampling segment according to the data amount of the plurality of sampling segments, the number of the sampling segments, the sampling frequency of the analog-to-digital converter, the signal frequency of the sampled signal, and the number of complete cycles, wherein the offset is the difference between the synchronization point at the start of sampling and the actual value at the start of sampling, the number of complete cycles is the number of complete cycles of the sampled signal contained in the sampled sample, and p is the number of the sampling segments;

[0078] Specifically, the number of complete cycles is a positive integer. The sampled signal is a sinusoidal wave signal.

[0079] The second acquisition unit 30 is used to acquire the synchronization point of each sampling segment, and control the analog-to-digital converter to sample the sampled signal according to the synchronization point of each sampling segment and the offset from the second sampling segment to the pth sampling segment to obtain a sampling segment and control the analog-to-digital converter to stop sampling, and transfer the obtained sampling segment to the memory, and continue to control the analog-to-digital converter to sample the sampled signal after the sampling segment stored in the memory is sent, until the pth sampling segment is transferred to the memory.

[0080] Specifically, the memory can send the received sampling segment to a host computer or other large-capacity non-volatile memory. Subsequently, multiple sampling segments in the host computer or other large-capacity non-volatile memory are spliced ​​into a complete sampling sample data file for measuring and evaluating the static parameters DNL and INL, and the dynamic parameters ENOB, SINAD, SNR, THD, etc. of the built-in ADC of the MCU.

[0081] The sampling device of the analog-to-digital converter in the single-chip microcomputer includes a processor and a memory, the first acquisition unit, the determination unit and the second acquisition unit are all stored in the memory as program units, and the processor executes the program units stored in the memory to implement corresponding functions. The modules are all located in the same processor; or the modules are located in different processors in any combination.

[0082] The processor includes a kernel, which retrieves the corresponding program unit from the memory. One or more kernels can be provided, and the problem of spectrum leakage of ADC sampling signals in the single-chip microcomputer in the prior art can be at least solved by adjusting kernel parameters.

[0083] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM, and the memory includes at least one memory chip.

[0084] An embodiment of the present invention provides a computer-readable storage medium, which includes a stored program, wherein when the program is executed, the device where the computer-readable storage medium is located is controlled to execute a sampling method of an analog-to-digital converter in the single-chip microcomputer.

[0085] Specifically, the sampling method of the analog-to-digital converter in the single-chip microcomputer includes:

[0086] Step S201, obtaining the data volume and number of sampling segments of a plurality of sampling segments, wherein the data volume of each sampling segment is less than or equal to the storage capacity of the memory, and the plurality of sampling segments are obtained by segmenting the sampling samples of the analog-to-digital converter;

[0087] Specifically, the sampling samples are obtained by the analog-to-digital converter continuously sampling the sampled signal. The number of sampling segments is the total number of sampling segments. The product of the data volume of the sampling segment and the number of sampling segments must be greater than or equal to the minimum sampling sample data volume of the analog-to-digital converter.

[0088] Step S202, determining an offset from the second sampling segment to the pth sampling segment according to the data volume of the plurality of sampling segments, the number of sampling segments, the sampling frequency of the analog-to-digital converter, the signal frequency of the sampled signal, and the number of complete cycles, wherein the offset is the difference between the synchronization point at the start of sampling and the actual value at the start of sampling, the number of complete cycles is the number of complete cycles of the sampled signal contained in the sample, and p is the number of sampling segments;

[0089] Specifically, the number of complete cycles is a positive integer. The sampled signal is a sinusoidal wave signal.

[0090] Step S203, obtaining the synchronization point of each sampling segment, and controlling the analog-to-digital converter to sample the sampled signal according to the synchronization point of each sampling segment and the offset from the second sampling segment to the pth sampling segment, obtaining a sampling segment and controlling the analog-to-digital converter to stop sampling, transmitting the obtained sampling segment to the memory, and continuing to control the analog-to-digital converter to sample the sampled signal after the sampling segment stored in the memory is sent out, until the pth sampling segment is transmitted to the memory.

[0091] Specifically, the memory can send the received sampling segment to a host computer or other large-capacity non-volatile memory. Subsequently, multiple sampling segments in the host computer or other large-capacity non-volatile memory are spliced ​​into a complete sampling sample data file for measuring and evaluating the static parameters DNL and INL, and the dynamic parameters ENOB, SINAD, SNR, etc. of the built-in ADC of the MCU.

[0092] Optionally, determining the offset from the second sampling segment to the pth sampling segment according to the data volume of the plurality of sampling segments, the number of sampling segments, the sampling frequency of the analog-to-digital converter, the signal frequency of the sampled signal, and the number of complete cycles comprises: determining the offset of the qth sampling segment as: Δq=F S (q-1)S q -F IN Q, where Δq is the offset of the qth sampling segment, F S is the sampling frequency, q is the sequence number of the sampling segment, S q is the data volume of the qth sampling segment, F IN is the signal frequency, Q is the number of complete cycles, and 1<q≤p.

[0093] Optionally, obtaining the synchronization point of each of the sampling segments includes: each time an interrupt triggered by a comparator in the single-chip microcomputer is received, determining that a synchronization point is obtained, the synchronization point being the triggering moment of the interrupt, obtaining a plurality of synchronization points arranged in order from early to late within a predetermined time length, the predetermined time length being the total time length for sampling the sampled signal to obtain the sampled sample, and the interrupt being triggered by the comparator whenever the voltage value of the sampled signal is equal to a predetermined threshold.

[0094] Optionally, according to the synchronization point of each sampling segment and the offset from the second sampling segment to the pth sampling segment, the analog-to-digital converter is controlled to sample the sampled signal to obtain a sampling segment and the analog-to-digital converter is controlled to stop sampling, the obtained sampling segment is transmitted to the memory, and after the sampling segment stored in the memory is issued, the analog-to-digital converter is continuously controlled to sample the sampled signal until the pth sampling segment is transmitted to the memory, including: a sampling step, when the sampled signal starts to be received and the interrupt is received for the first time, the analog-to-digital converter is controlled to sample the sampled signal, and when the sampling stop condition is met, the analog-to-digital converter is controlled to stop sampling to obtain the first sampling segment. The method comprises the following steps: a sampling segment is selected and the first sampling segment is transmitted to the memory; a timing step is performed, when the q-1th sampling segment stored in the memory has been issued and the interrupt is received for the qth time, the timer is controlled to start timing, and when the timing time reaches the offset corresponding to the qth sampling segment, the analog-to-digital converter is controlled to sample the sampled signal; a stopping step is performed, when the sampling stopping condition is met, the analog-to-digital converter is controlled to stop sampling, the qth sampling segment is obtained, and the qth sampling segment is transmitted to the memory; a looping step is performed, when q is not equal to p, the q+1th sampling segment is determined to be the new qth sampling segment, and the timing step and the stopping step are looped until q is equal to p, so as to obtain all the sampling segments.

[0095] Optionally, according to the synchronization point of each sampling segment and the offset from the second sampling segment to the pth sampling segment, the analog-to-digital converter is controlled to sample the sampled signal to obtain a sampling segment and the analog-to-digital converter is controlled to stop sampling, the obtained sampling segment is transmitted to the memory, and after the sampling segment stored in the memory is issued, the analog-to-digital converter is continuously controlled to sample the sampled signal until the pth sampling segment is transmitted to the memory, including: determining that the actual value of the first sampling segment is the synchronization point of the first sampling segment; calibrating the synchronization point of the qth sampling segment according to the offset of the qth sampling segment to obtain the pth sampling segment. The actual values ​​of q sampling segments, the actual value of the qth sampling segment is the sum of the synchronization point of the qth sampling segment and the offset of the qth sampling segment, wherein 1<q≤p; when the actual value is reached at the moment of receiving the sampled signal, the analog-to-digital converter is controlled to sample the sampled signal to obtain a sampling segment and the analog-to-digital converter is controlled to stop sampling, and the obtained sampling segment is transferred to the memory; after the sampling segment stored in the memory is sent and the moment of receiving the sampled signal reaches the next actual value, the analog-to-digital converter is controlled to continue sampling the sampled signal until the pth sampling segment is transferred to the memory.

[0096] Optionally, obtaining the data volume of multiple sampling segments and the number of sampling segments includes: obtaining the storage capacity, the signal frequency, the sampling frequency and the number of cycles sampled by the sampled signal; determining the number of samples as the product of the signal frequency and the number of cycles divided by the sampling frequency based on the signal frequency, the sampling frequency and the number of cycles sampled by the sampled signal, wherein the sampling samples include multiple samples; determining the data volume of the sampling samples as the product of the number of samples and the number of storage bits occupied by each sample based on the number of samples and the number of storage bits occupied by each sample; determining the number of sampling segments based on the data volume of the sampling samples and the storage capacity of the memory, wherein the number of sampling segments is greater than or equal to the ratio of the data volume of the sampling samples to the storage capacity; determining the data volume of each sampling segment based on the number of sampling segments and the data volume of the sampling samples.

[0097] Optionally, determining the data volume of each sampling segment according to the number of sampling segments and the data volume of the sampling samples includes: when the number of sampling segments is greater than the ratio of the data volume of the sampling samples to the storage capacity, determining, according to the number of sampling segments and the data volume of the sampling samples, that the data volumes of the first sampling segment to the p-1th sampling segment are all first target data volumes, the first target data volume is less than or equal to the storage capacity, and determining the data volume of the pth sampling segment as a second target data volume, the second target data volume is Sp=Ssum-(p-1)S, S sum is the data volume of the sampling sample, S is the first target data volume; when the number of sampling segments is equal to the ratio of the data volume of the sampling sample to the storage capacity, according to the number of sampling segments and the data volume of the sampling sample, it is determined that the data volume of each sampling segment is the ratio of the data volume of the sampling sample to the number of sampling segments.

[0098] An embodiment of the present invention provides a processor, which is used to run a program, wherein the program executes a sampling method of an analog-to-digital converter in the single-chip microcomputer when the program is running.

[0099] Specifically, the sampling method of the analog-to-digital converter in the single-chip microcomputer includes:

[0100] Step S201, obtaining the data volume and number of sampling segments of a plurality of sampling segments, wherein the data volume of each sampling segment is less than or equal to the storage capacity of the memory, and the plurality of sampling segments are obtained by segmenting the sampling samples of the analog-to-digital converter;

[0101] Specifically, the sampling samples are obtained by the analog-to-digital converter continuously sampling the sampled signal. The number of sampling segments is the total number of sampling segments. The product of the data volume of the sampling segment and the number of sampling segments must be greater than or equal to the minimum sampling sample data volume of the analog-to-digital converter.

[0102] Step S202, determining an offset from the second sampling segment to the pth sampling segment according to the data volume of the plurality of sampling segments, the number of sampling segments, the sampling frequency of the analog-to-digital converter, the signal frequency of the sampled signal, and the number of complete cycles, wherein the offset is the difference between the synchronization point at the start of sampling and the actual value at the start of sampling, the number of complete cycles is the number of complete cycles of the sampled signal contained in the sample, and p is the number of sampling segments;

[0103] Specifically, the number of complete cycles is a positive integer. The sampled signal is a sinusoidal wave signal.

[0104] Step S203, obtaining the synchronization point of each sampling segment, and controlling the analog-to-digital converter to sample the sampled signal according to the synchronization point of each sampling segment and the offset from the second sampling segment to the pth sampling segment, obtaining a sampling segment and controlling the analog-to-digital converter to stop sampling, transmitting the obtained sampling segment to the memory, and continuing to control the analog-to-digital converter to sample the sampled signal after the sampling segment stored in the memory is sent out, until the pth sampling segment is transmitted to the memory.

[0105] Specifically, the memory can send the received sampling segment to a host computer or other large-capacity non-volatile memory. Subsequently, multiple sampling segments in the host computer or other large-capacity non-volatile memory are spliced ​​into a complete sampling sample data file for measuring and evaluating the static parameters DNL and INL, and the dynamic parameters ENOB, SINAD, SNR, etc. of the built-in ADC of the MCU.

[0106] Optionally, determining the offset from the second sampling segment to the pth sampling segment according to the data volume of the plurality of sampling segments, the number of sampling segments, the sampling frequency of the analog-to-digital converter, the signal frequency of the sampled signal, and the number of complete cycles comprises: determining the offset of the qth sampling segment as: Δq=F S (q-1)S q -F IN Q, where Δq is the offset of the qth sampling segment, F S is the sampling frequency, q is the sequence number of the sampling segment, S q is the data volume of the qth sampling segment, F IN is the signal frequency, Q is the number of complete cycles, and 1<q≤p.

[0107] Optionally, obtaining the synchronization point of each of the sampling segments includes: each time an interrupt triggered by a comparator in the single-chip microcomputer is received, determining that a synchronization point is obtained, the synchronization point being the triggering moment of the interrupt, obtaining a plurality of synchronization points arranged in order from early to late within a predetermined time length, the predetermined time length being the total time length for sampling the sampled signal to obtain the sampled sample, and the interrupt being triggered by the comparator whenever the voltage value of the sampled signal is equal to a predetermined threshold.

[0108] Optionally, according to the synchronization point of each sampling segment and the offset from the second sampling segment to the pth sampling segment, the analog-to-digital converter is controlled to sample the sampled signal to obtain a sampling segment and the analog-to-digital converter is controlled to stop sampling, the obtained sampling segment is transmitted to the memory, and after the sampling segment stored in the memory is issued, the analog-to-digital converter is continuously controlled to sample the sampled signal until the pth sampling segment is transmitted to the memory, including: a sampling step, when the sampled signal starts to be received and the interrupt is received for the first time, the analog-to-digital converter is controlled to sample the sampled signal, and when the sampling stop condition is met, the analog-to-digital converter is controlled to stop sampling to obtain the first sampling segment. The method comprises the following steps: a sampling segment is selected and the first sampling segment is transmitted to the memory; a timing step is performed, when the q-1th sampling segment stored in the memory has been issued and the interrupt is received for the qth time, the timer is controlled to start timing, and when the timing time reaches the offset corresponding to the qth sampling segment, the analog-to-digital converter is controlled to sample the sampled signal; a stopping step is performed, when the sampling stopping condition is met, the analog-to-digital converter is controlled to stop sampling, the qth sampling segment is obtained, and the qth sampling segment is transmitted to the memory; a looping step is performed, when q is not equal to p, the q+1th sampling segment is determined to be the new qth sampling segment, and the timing step and the stopping step are looped until q is equal to p, so as to obtain all the sampling segments.

[0109] Optionally, according to the synchronization point of each sampling segment and the offset from the second sampling segment to the pth sampling segment, the analog-to-digital converter is controlled to sample the sampled signal to obtain a sampling segment and the analog-to-digital converter is controlled to stop sampling, the obtained sampling segment is transmitted to the memory, and after the sampling segment stored in the memory is issued, the analog-to-digital converter is continuously controlled to sample the sampled signal until the pth sampling segment is transmitted to the memory, including: determining that the actual value of the first sampling segment is the synchronization point of the first sampling segment; calibrating the synchronization point of the qth sampling segment according to the offset of the qth sampling segment to obtain the pth sampling segment. The actual values ​​of q sampling segments, the actual value of the qth sampling segment is the sum of the synchronization point of the qth sampling segment and the offset of the qth sampling segment, wherein 1<q≤p; when the actual value is reached at the moment of receiving the sampled signal, the analog-to-digital converter is controlled to sample the sampled signal to obtain a sampling segment and the analog-to-digital converter is controlled to stop sampling, and the obtained sampling segment is transferred to the memory; after the sampling segment stored in the memory is sent and the moment of receiving the sampled signal reaches the next actual value, the analog-to-digital converter is controlled to continue sampling the sampled signal until the pth sampling segment is transferred to the memory.

[0110] Optionally, obtaining the data volume of multiple sampling segments and the number of sampling segments includes: obtaining the storage capacity, the signal frequency, the sampling frequency and the number of cycles sampled by the sampled signal; determining the number of samples as the product of the signal frequency and the number of cycles divided by the sampling frequency based on the signal frequency, the sampling frequency and the number of cycles sampled by the sampled signal, wherein the sampling samples include multiple samples; determining the data volume of the sampling samples as the product of the number of samples and the number of storage bits occupied by each sample based on the number of samples and the number of storage bits occupied by each sample; determining the number of sampling segments based on the data volume of the sampling samples and the storage capacity of the memory, wherein the number of sampling segments is greater than or equal to the ratio of the data volume of the sampling samples to the storage capacity; determining the data volume of each sampling segment based on the number of sampling segments and the data volume of the sampling samples.

[0111] Optionally, determining the data volume of each sampling segment according to the number of sampling segments and the data volume of the sampling samples includes: when the number of sampling segments is greater than the ratio of the data volume of the sampling samples to the storage capacity, determining, according to the number of sampling segments and the data volume of the sampling samples, that the data volumes of the first sampling segment to the p-1th sampling segment are all first target data volumes, the first target data volume is less than or equal to the storage capacity, and determining the data volume of the pth sampling segment as a second target data volume, the second target data volume is Sp=Ssum-(p-1)S, S sum is the data volume of the sampling sample, S is the first target data volume; when the number of sampling segments is equal to the ratio of the data volume of the sampling sample to the storage capacity, according to the number of sampling segments and the data volume of the sampling sample, it is determined that the data volume of each sampling segment is the ratio of the data volume of the sampling sample to the number of sampling segments.

[0112] The present application also provides a computer program product, including computer instructions, which, when executed by a processor, implement at least the following method steps:

[0113] Step S201, obtaining the data volume and number of sampling segments of a plurality of sampling segments, wherein the data volume of each sampling segment is less than or equal to the storage capacity of the memory, and the plurality of sampling segments are obtained by segmenting the sampling samples of the analog-to-digital converter;

[0114] Specifically, the sampling samples are obtained by the analog-to-digital converter continuously sampling the sampled signal. The number of sampling segments is the total number of sampling segments. The product of the data volume of the sampling segment and the number of sampling segments must be greater than or equal to the minimum sampling sample data volume of the analog-to-digital converter.

[0115] Step S202, determining an offset from the second sampling segment to the pth sampling segment according to the data volume of the plurality of sampling segments, the number of sampling segments, the sampling frequency of the analog-to-digital converter, the signal frequency of the sampled signal, and the number of complete cycles, wherein the offset is the difference between the synchronization point at the start of sampling and the actual value at the start of sampling, the number of complete cycles is the number of complete cycles of the sampled signal contained in the sample, and p is the number of sampling segments;

[0116] Specifically, the number of complete cycles is a positive integer. The sampled signal is a sinusoidal wave signal.

[0117] Step S203, obtaining the synchronization point of each sampling segment, and controlling the analog-to-digital converter to sample the sampled signal according to the synchronization point of each sampling segment and the offset from the second sampling segment to the pth sampling segment, obtaining a sampling segment and controlling the analog-to-digital converter to stop sampling, transmitting the obtained sampling segment to the memory, and continuing to control the analog-to-digital converter to sample the sampled signal after the sampling segment stored in the memory is sent out, until the pth sampling segment is transmitted to the memory.

[0118] Specifically, the memory can send the received sampling segment to a host computer or other large-capacity non-volatile memory. Subsequently, multiple sampling segments in the host computer or other large-capacity non-volatile memory are spliced ​​into a complete sampling sample data file for measuring and evaluating the static parameters DNL and INL, and the dynamic parameters ENOB, SINAD, SNR, etc. of the built-in ADC of the MCU.

[0119] Optionally, determining the offset from the second sampling segment to the pth sampling segment according to the data volume of the plurality of sampling segments, the number of sampling segments, the sampling frequency of the analog-to-digital converter, the signal frequency of the sampled signal, and the number of complete cycles comprises: determining the offset of the qth sampling segment as: Δq=F S (q-1)S q -F IN Q, where Δq is the offset of the qth sampling segment, F S is the sampling frequency, q is the sequence number of the sampling segment, S q is the data volume of the qth sampling segment, F IN is the signal frequency, Q is the number of complete cycles, and 1<q≤p.

[0120] Optionally, obtaining the synchronization point of each of the sampling segments includes: each time an interrupt triggered by a comparator in the single-chip microcomputer is received, determining that a synchronization point is obtained, the synchronization point being the triggering moment of the interrupt, obtaining a plurality of synchronization points arranged in order from early to late within a predetermined time length, the predetermined time length being the total time length for sampling the sampled signal to obtain the sampled sample, and the interrupt being triggered by the comparator whenever the voltage value of the sampled signal is equal to a predetermined threshold.

[0121] Optionally, according to the synchronization point of each sampling segment and the offset from the second sampling segment to the pth sampling segment, the analog-to-digital converter is controlled to sample the sampled signal to obtain a sampling segment and the analog-to-digital converter is controlled to stop sampling, the obtained sampling segment is transmitted to the memory, and after the sampling segment stored in the memory is issued, the analog-to-digital converter is continuously controlled to sample the sampled signal until the pth sampling segment is transmitted to the memory, including: a sampling step, when the sampled signal starts to be received and the interrupt is received for the first time, the analog-to-digital converter is controlled to sample the sampled signal, and when the sampling stop condition is met, the analog-to-digital converter is controlled to stop sampling to obtain the first sampling segment. The method comprises the following steps: a sampling segment is selected and the first sampling segment is transmitted to the memory; a timing step is performed, when the q-1th sampling segment stored in the memory has been issued and the interrupt is received for the qth time, the timer is controlled to start timing, and when the timing time reaches the offset corresponding to the qth sampling segment, the analog-to-digital converter is controlled to sample the sampled signal; a stopping step is performed, when the sampling stopping condition is met, the analog-to-digital converter is controlled to stop sampling, the qth sampling segment is obtained, and the qth sampling segment is transmitted to the memory; a looping step is performed, when q is not equal to p, the q+1th sampling segment is determined to be the new qth sampling segment, and the timing step and the stopping step are looped until q is equal to p, so as to obtain all the sampling segments.

[0122] Optionally, according to the synchronization point of each sampling segment and the offset from the second sampling segment to the pth sampling segment, the analog-to-digital converter is controlled to sample the sampled signal to obtain a sampling segment and the analog-to-digital converter is controlled to stop sampling, the obtained sampling segment is transmitted to the memory, and after the sampling segment stored in the memory is issued, the analog-to-digital converter is continuously controlled to sample the sampled signal until the pth sampling segment is transmitted to the memory, including: determining that the actual value of the first sampling segment is the synchronization point of the first sampling segment; calibrating the synchronization point of the qth sampling segment according to the offset of the qth sampling segment to obtain the pth sampling segment. The actual values ​​of q sampling segments, the actual value of the qth sampling segment is the sum of the synchronization point of the qth sampling segment and the offset of the qth sampling segment, wherein 1<q≤p; when the actual value is reached at the moment of receiving the sampled signal, the analog-to-digital converter is controlled to sample the sampled signal to obtain a sampling segment and the analog-to-digital converter is controlled to stop sampling, and the obtained sampling segment is transferred to the memory; after the sampling segment stored in the memory is sent and the moment of receiving the sampled signal reaches the next actual value, the analog-to-digital converter is controlled to continue sampling the sampled signal until the pth sampling segment is transferred to the memory.

[0123] Optionally, obtaining the data volume of multiple sampling segments and the number of sampling segments includes: obtaining the storage capacity, the signal frequency, the sampling frequency and the number of cycles sampled by the sampled signal; determining the number of samples as the product of the signal frequency and the number of cycles divided by the sampling frequency based on the signal frequency, the sampling frequency and the number of cycles sampled by the sampled signal, wherein the sampling samples include multiple samples; determining the data volume of the sampling samples as the product of the number of samples and the number of storage bits occupied by each sample based on the number of samples and the number of storage bits occupied by each sample; determining the number of sampling segments based on the data volume of the sampling samples and the storage capacity of the memory, wherein the number of sampling segments is greater than or equal to the ratio of the data volume of the sampling samples to the storage capacity; determining the data volume of each sampling segment based on the number of sampling segments and the data volume of the sampling samples.

[0124] Optionally, determining the data volume of each sampling segment according to the number of sampling segments and the data volume of the sampling samples includes: when the number of sampling segments is greater than the ratio of the data volume of the sampling samples to the storage capacity, determining, according to the number of sampling segments and the data volume of the sampling samples, that the data volumes of the first sampling segment to the p-1th sampling segment are all first target data volumes, the first target data volume is less than or equal to the storage capacity, and determining the data volume of the pth sampling segment as a second target data volume, the second target data volume is Sp=Ssum-(p-1)S, S sum is the data volume of the sampling sample, S is the first target data volume; when the number of sampling segments is equal to the ratio of the data volume of the sampling sample to the storage capacity, according to the number of sampling segments and the data volume of the sampling sample, it is determined that the data volume of each sampling segment is the ratio of the data volume of the sampling sample to the number of sampling segments.

[0125] An embodiment of the present application further provides a single chip computer, comprising: an analog-to-digital converter (ADC); a memory; and a controller, for executing any one of the methods described.

[0126] In one embodiment, Figure 5 As shown, the single chip microcomputer (MCU) also includes: a software processing module, a digital-to-analog converter (DAC), an analog comparator (ACMP) and a timer (TIMER).

[0127] Wherein, the memory may be SRAM.

[0128] The sampling process of the present application includes a sampling preprocessing stage and a sampling stage. In the sampling preprocessing stage, ACMP converts the sine wave into a square wave and provides TIMER for period measurement calculation; in the sampling preprocessing stage and the sampling stage, ACMP is used to generate the synchronization point required for the entire sine wave sampling (i.e., the synchronization point at the start of sampling), that is, when the sine wave amplitude is the same as the comparison level, an interrupt is triggered, and the relevant software processing is performed through the software processing module. DAC is used to provide the comparison level of ACMP, and the voltage value of the comparison level is a predetermined threshold. In the sampling preprocessing stage, the square wave output by ACMP is calculated through the capture function of TIMER, and the software processing module is used for software processing; in the sampling stage, the initial sampling point of each sampling segment calculated by the software processing module is delayed compared to the synchronization point of ACMP; in the sampling preprocessing stage, the software processing module is used to calculate the offset value of the starting sampling point of each segmented sub-segment compared to the synchronization point and then store it; in the sampling stage, the software processing module calls the offset value of the current sampling segment before each sampling segment starts sampling, and enables ADC for sampling after counting delay through TIMER. The ADC is used to continuously sample the input sine wave and output the sampled data. The key indicators such as INL and DNL of the ADC are then calculated to evaluate the ADC performance. The memory can be SRAM, which is used to store ADC sampled data. The capacity is generally tens of KB to hundreds of KB.

[0129] also, Figure 5 In the process, the sampled signal is provided by a sine wave signal source, which is generally a dedicated signal source device with adjustable frequency and amplitude.

[0130] The sampling process is as follows: Figure 6As shown, ADC sampling is divided into a sampling preprocessing stage and a sampling stage. The sampling preprocessing stage is used to determine the frequency period of the sine wave to be sampled; and according to the SRAM capacity requirement and the number of sampled samples, the number of sampled samples is divided into several sampling segments, and the number of sampling segments and the capacity of each sampling segment are calculated and recorded (generally, the capacity of each sampling segment is equal, and the size of the last sampling segment may be inconsistent). The data size of each sampling segment meets the capacity requirement of the SRAM; for the divided sampling segments, the initial sampling point of each sampling segment is calculated to coexist with the phase offset of the synchronization point on the continuous sine wave, which is used for the position calibration of the initial sampling point in the sampling stage. In the sampling preprocessing stage, the sine wave input comparator is compared with the established comparison level (which can be achieved by DAC) to output a square wave and then enter the timer to use the capture function to calculate the square wave period to obtain the sine wave period. In the sampling stage, the input sine wave is compared with the comparison level set by the comparator. When the sine wave amplitude reaches the comparison level value, an interrupt is triggered, and it is considered that the current sine wave amplitude is the synchronization point. In the sampling stage, the starting sampling point of each sampling segment is determined, and the offset value between the starting sampling point and the synchronization point of the current sampling segment calculated in the sampling preprocessing stage is called. After the synchronization point triggers an interrupt, the sampling is enabled after the timer delays and waits for the sampling point to move to the target phase position of the sine wave, and the sampling of the current sampling segment begins. In the sampling stage, the ADC sampling data is transferred to SRAM via DMA. After the sampling data of the current sampling segment is completed, the ADC sampling is suspended, and the MCU uploads the SRAM data to the host computer or other large-capacity non-volatile storage. Finally, multiple sampling data are spliced ​​into a complete ADC sampling sample data file for parameter calculation.

[0131] This application divides the continuous sinusoidal periodic signal to be sampled into several sinusoidal sampling segments for sampling, so that the sampling data size of each sampling segment meets the MCU SRAM storage capacity requirements. A synchronization point is set for the sinusoidal sampling, and the synchronization point is used as a reference to calibrate the first ADC sampling point position of the sinusoidal waves of several sampling segments to ensure that the sampling point interval between adjacent sampling segments is consistent with the interval of other sampling points, that is, the segmented sampling frequency is consistent with the ideal continuous sampling frequency.

[0132] Obviously, those skilled in the art should understand that the modules or steps of the present invention described above can be implemented by a general-purpose computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order than herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present invention is not limited to any specific combination of hardware and software.

[0133] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0134] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0135] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0136] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0137] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0138] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0139] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0140] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0141] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A sampling method for an analog-to-digital converter in a single-chip microcomputer, wherein the single-chip microcomputer also includes a memory, characterized in that: The method comprises: Acquire the data volume and number of the sampling segments of the plurality of sampling segments, wherein the data volume of each sampling segment is less than or equal to the storage capacity of the memory, and the plurality of sampling segments are obtained by segmenting the sampling samples of the analog-to-digital converter; Determine the offset from the second sampling segment to the pth sampling segment according to the data volume of the plurality of sampling segments, the number of sampling segments, the sampling frequency of the analog-to-digital converter, the signal frequency of the sampled signal, and the number of complete cycles, wherein the offset is the difference between the synchronization point at the start of sampling and the actual value at the start of sampling, the number of complete cycles is the number of complete cycles of the sampled signal contained in the sampling sample, and p is the number of sampling segments; The synchronization point of each sampling segment is obtained, and according to the synchronization point of each sampling segment and the offset from the second sampling segment to the pth sampling segment, the analog-to-digital converter is controlled to sample the sampled signal to obtain a sampling segment and the analog-to-digital converter is controlled to stop sampling, and the obtained sampling segment is transferred to the memory, and after the sampling segment stored in the memory is sent, the analog-to-digital converter is continuously controlled to sample the sampled signal until the pth sampling segment is transferred to the memory.

2. The method according to claim 1, characterized in that Determining an offset from the second sampling segment to the pth sampling segment according to the data volume of the plurality of sampling segments, the number of the sampling segments, the sampling frequency of the analog-to-digital converter, the signal frequency of the sampled signal, and the number of complete cycles, comprising: According to the data amount of the plurality of sampling segments, the number of the sampling segments, the sampling frequency of the analog-to-digital converter, the signal frequency of the sampled signal, and the number of complete cycles, the offset of the qth sampling segment is determined as: Δq=F S (q-1)S q -F IN Q, Wherein, Δq is the offset of the qth sampling segment, F S is the sampling frequency, q is the sequence number of the sampling segment, S q is the data volume of the qth sampling segment, F IN is the signal frequency, Q is the number of complete cycles, and 1<q≤p.

3. The method according to claim 1, characterized in that Acquiring the synchronization point of each sampling segment includes: Each time an interrupt triggered by a comparator in the single-chip microcomputer is received, a synchronization point is determined to be obtained, and the synchronization point is the triggering moment of the interrupt. A plurality of synchronization points arranged in order from early to late within a predetermined time length are obtained, and the predetermined time length is the total time length for sampling the sampled signal to obtain the sampled sample, and the interrupt is triggered by the comparator whenever the voltage value of the sampled signal is equal to a predetermined threshold value.

4. The method according to claim 3, characterized in that According to the synchronization point of each sampling segment and the offset from the second sampling segment to the pth sampling segment, the analog-to-digital converter is controlled to sample the sampled signal to obtain a sampling segment and the analog-to-digital converter is controlled to stop sampling, the obtained sampling segment is transmitted to the memory, and after the sampling segment stored in the memory is sent, the analog-to-digital converter is continuously controlled to sample the sampled signal until the pth sampling segment is transmitted to the memory, including: A sampling step, when the sampled signal starts to be received and the interrupt is received for the first time, controlling the analog-to-digital converter to sample the sampled signal, and controlling the analog-to-digital converter to stop sampling when a sampling stop condition is met, to obtain the first sampling segment, and transmitting the first sampling segment to the memory; a timing step, when the q-1th sampling segment stored in the memory has been issued and the interrupt is received for the qth time, controlling the timer to start timing, and when the timing duration reaches the offset corresponding to the qth sampling segment, controlling the analog-to-digital converter to sample the sampled signal; a stop step, controlling the analog-to-digital converter to stop sampling when the sampling stop condition is met, obtaining the qth sampling segment, and transmitting the qth sampling segment to the memory; A loop step, when q is not equal to p, determines the q+1th sampling segment as the new qth sampling segment, and loops through the timing step and the stop step until q is equal to p, thereby obtaining all the sampling segments.

5. The method according to claim 1, characterized in that According to the synchronization point of each sampling segment and the offset from the second sampling segment to the pth sampling segment, the analog-to-digital converter is controlled to sample the sampled signal to obtain a sampling segment and the analog-to-digital converter is controlled to stop sampling, the obtained sampling segment is transmitted to the memory, and after the sampling segment stored in the memory is sent, the analog-to-digital converter is continuously controlled to sample the sampled signal until the pth sampling segment is transmitted to the memory, including: Determine the actual value of the first sampling segment as the synchronization point of the first sampling segment; According to the offset of the qth sampling segment, the synchronization point of the qth sampling segment is calibrated to obtain the actual value of the qth sampling segment, and the actual value of the qth sampling segment is the sum of the synchronization point of the qth sampling segment and the offset of the qth sampling segment, wherein 1<q≤p; When the moment when the sampled signal is received reaches the actual value, controlling the analog-to-digital converter to sample the sampled signal to obtain a sampling segment and controlling the analog-to-digital converter to stop sampling, and transmitting the obtained sampling segment to the memory; After the sampling segment stored in the memory is issued and when the moment of receiving the sampled signal reaches the next actual value, the analog-to-digital converter is controlled to continue sampling the sampled signal until the pth sampling segment is transmitted to the memory.

6. The method according to any one of claims 1 to 5, characterized in that Get the data volume and number of sampling segments for multiple sampling segments, including: Acquire the storage capacity, the signal frequency, the sampling frequency, and the number of cycles sampled by the sampled signal; According to the signal frequency, the sampling frequency and the number of cycles sampled by the sampled signal, the number of samples is determined as the product of the signal frequency and the number of cycles divided by the sampling frequency, and the sampled samples include a plurality of the samples; According to the number of samples and the number of storage bits occupied by each sample, determining the data volume of the sampled sample as the product of the number of samples and the number of storage bits; Determine the number of sampling segments according to the data volume of the sample and the storage capacity of the memory, wherein the number of sampling segments is greater than or equal to the ratio of the data volume of the sample to the storage capacity; The data volume of each sampling segment is determined according to the number of sampling segments and the data volume of the sampling samples.

7. The method according to claim 6, characterized in that Determining the data volume of each sampling segment according to the number of sampling segments and the data volume of the sampling samples includes: In the case where the number of sampling segments is greater than the ratio of the data volume of the sampling samples to the storage capacity, according to the number of sampling segments and the data volume of the sampling samples, it is determined that the data volumes of the first sampling segment to the p-1th sampling segment are all the first target data volumes, and the first target data volume is less than or equal to the storage capacity, and the data volume of the pth sampling segment is determined to be the second target data volume, and the second target data volume is Sp=Ssum-(p-1)S, S sum is the data volume of the sampled samples, and S is the first target data volume; When the number of sampling segments is equal to the ratio of the data volume of the sampling samples to the storage capacity, the data volume of each sampling segment is determined based on the number of sampling segments and the data volume of the sampling samples, which is the ratio of the data volume of the sampling samples to the number of sampling segments.

8. A computer program product comprising computer instructions, characterized in that: When the computer instructions are executed by a processor, the method according to any one of claims 1 to 7 is implemented.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored program, wherein when the program is executed, the device where the computer-readable storage medium is located is controlled to execute the method according to any one of claims 1 to 7.

10. A single chip microcomputer, characterized in that: include: Analog-to-digital converters; Memory; A controller for executing the method according to any one of claims 1 to 7.

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