Compressed data bit splicing method and device, equipment and storage medium
By performing multiple interleaving and shifting operations on compressed data, combined with logic or operations, the problem of low bit splicing efficiency in the prior art is solved, and efficient vector processing and splicing of compressed data bits is realized.
Patent Information
- Application Number
- CN202411985334.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-30
- Publication Date
- 2025-04-29
AI Technical Summary
In the prior art, in the process of data compression and transmission, bit splicing efficiency is low, resulting in an extended data transmission time.
By obtaining each group of compressed data, determining its common index, forming compressed blocks, and performing multiple interleaving and shifting operations on these blocks, finally obtaining the bit splicing result of the compressed data through logic or operations.
This method can vectorize the bit of compressed data, significantly improve the bit splicing efficiency and shorten the data transmission time.
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Figure CN119906435A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of data compression technology, and in particular to a compressed data bit splicing method, device, equipment, and storage medium. Background Art
[0002] In order to improve data transmission efficiency, data needs to be compressed before transmission and decompressed after receiving the data.
[0003] During compression, according to different data bit width requirements, after compressing the data to a certain bit width, each bit of the compressed data needs to be arranged according to certain rules before it can be transmitted.
[0004] Efficient bit splicing can reduce data compression time and allow data to enter the transmission process as quickly as possible. Therefore, how to improve the efficiency of bit splicing has become one of the key research directions. Summary of the invention
[0005] In order to solve one of the above-mentioned technical defects, the present application provides a compressed data bit splicing method, device, equipment, and storage medium.
[0006] In a first aspect of the present application, a compressed data bit splicing method is provided, the method comprising:
[0007] Obtain each group of compressed data; wherein each group of compressed data is obtained by compressing each group of original data, the amount of data in each group of original data is fixed, and all groups of original data constitute the data to be compressed;
[0008] Determine the public index corresponding to each group of compressed data;
[0009] According to each group of compressed data and the corresponding public index, a compressed block corresponding to each group of compressed data is formed;
[0010] Performing multiple processing on each compressed block; wherein each processing includes an interleaving operation and a shift operation;
[0011] The results of multiple processing of each compression block are logically ORed to obtain the compressed data bit concatenation result of each compression block.
[0012] Optionally, forming a compressed block corresponding to each group of compressed data according to each group of compressed data and a corresponding public index includes:
[0013] For any group of compressed data, the public index corresponding to any group of compressed data is used as the first byte data of the corresponding compressed block, and any group of compressed data is used as the non-first byte data of the corresponding compressed block to form a compressed block corresponding to any group of compressed data;
[0014] Among them, each bit in the compressed block is arranged tightly.
[0015] Optionally, any group of compressed data includes an in-phase component and a quadrature component, and the quadrature component is arranged before the in-phase component.
[0016] Optionally, the interleaving operation in any one of the processing operations includes: selecting a plurality of bytes of processing data by an interleaver;
[0017] The shift operation in any processing includes: performing a shift operation on each byte of the processed data through a multiplier.
[0018] In a second aspect of the present application, a compressed data bit splicing device is provided, the device comprising:
[0019] An acquisition module is used to acquire each group of compressed data; wherein each group of compressed data is obtained by compressing each group of original data, the amount of data in each group of original data is fixed, and all groups of original data constitute the data to be compressed;
[0020] A determination module, used to determine the public index corresponding to each group of compressed data obtained by the acquisition module;
[0021] A forming module, used for forming a compressed block corresponding to each group of compressed data according to each group of compressed data acquired by the acquiring module and the corresponding public index determined by the determining module;
[0022] A first processing module, configured to perform multiple processing on each compressed block formed by the forming module; wherein each processing includes an interleaving operation and a shifting operation;
[0023] The second processing module is used to perform a logical OR operation on the results of multiple processing of each compressed block obtained by the first processing module to obtain a compressed data bit splicing result of each compressed block.
[0024] Optionally, a forming module is used for, for any group of compressed data, using the public index corresponding to any group of compressed data as the first byte data of the corresponding compressed block, and using any group of compressed data as the non-first byte data of the corresponding compressed block, to form a compressed block corresponding to any group of compressed data;
[0025] Among them, each bit in the compressed block is arranged tightly.
[0026] Optionally, any group of compressed data includes an in-phase component and a quadrature component, and the quadrature component is arranged before the in-phase component.
[0027] Optionally, the interleaving operation in any one of the processing operations includes: selecting a plurality of bytes of processing data by an interleaver;
[0028] The shift operation in any processing includes: performing a shift operation on each byte of the processed data through a multiplier.
[0029] In a third aspect of the present application, an electronic device is provided, including:
[0030] Memory;
[0031] Processor; and
[0032] Computer programs;
[0033] The computer program is stored in the memory and is configured to be executed by the processor to implement the method as described in the first aspect above.
[0034] In a fourth aspect of the present application, a computer-readable storage medium is provided, on which a computer program is stored; the computer program is executed by a processor to implement the method described in the first aspect above.
[0035] The present invention relates to a method, device, equipment and storage medium for bit splicing of compressed data, the method comprising: obtaining each group of compressed data; wherein each group of compressed data is obtained by compressing each group of original data, the number of data in each group of original data is fixed, and all groups of original data constitute the data to be compressed; determining the public index corresponding to each group of compressed data; forming a compressed block corresponding to each group of compressed data according to each group of compressed data and the corresponding public index; performing multiple processing on each compressed block; wherein each processing includes an interleaving operation and a shift operation; performing a logical or operation on the results of the multiple processing of each compressed block to obtain the compressed data bit splicing result of each compressed block. The method provided by the present application can perform vector processing on the bits of compressed data to improve the efficiency of bit splicing. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:
[0037] Figure 1 A flowchart of a compressed data bit splicing method provided in an embodiment of the present application;
[0038] Figure 2 A schematic diagram of a compression block provided in an embodiment of the present application;
[0039] Figure 3 A schematic diagram of the arrangement of 9-bit compressed data specified in the communication protocol provided in an embodiment of the present application;
[0040] Figure 4 A schematic diagram of compressed data provided in an embodiment of the present application;
[0041] Figure 5 A schematic diagram of multiple processing and logical or operation of a compression block provided in an embodiment of the present application;
[0042] Figure 6 A schematic diagram of a compressed data bit splicing result of a compressed block provided in an embodiment of the present application;
[0043] Figure 7 A schematic diagram of the structure of a BBU delay measurement system provided in an embodiment of the present application;
[0044] Figure 8 A schematic diagram of the structure of a compressed data bit splicing device provided in an embodiment of the present application;
[0045] Fig. 9 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0046] In order to make the technical solutions and advantages in the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.
[0047] In the process of implementing the present application, the inventors found that in order to improve the transmission efficiency of data, the data needs to be compressed before transmission and then decompressed after receiving the data. During compression, according to different data bit width requirements, after compressing the data to a certain bit width, each bit of the compressed data needs to be arranged according to certain rules before it can be transmitted. Highly efficient bit splicing can reduce data compression time and allow data to enter the transmission process as quickly as possible. Therefore, how to improve the efficiency of bit splicing has become one of the key research directions.
[0048] In view of the above research direction, the embodiments of the present application provide a compressed data bit splicing method, device, equipment, and storage medium, the method comprising: obtaining each group of compressed data; wherein each group of compressed data is obtained by compressing each group of original data, the number of data in each group of original data is fixed, and all groups of original data constitute the data to be compressed; determining the public index corresponding to each group of compressed data; forming a compressed block corresponding to each group of compressed data according to each group of compressed data and the corresponding public index; performing multiple processing on each compressed block; wherein each processing includes an interleaving operation and a shift operation; performing a logical or operation on the results of the multiple processing of each compressed block to obtain the compressed data bit splicing result of each compressed block. The method provided by the present application can perform vector processing on the bits of compressed data to improve the efficiency of bit splicing.
[0049] A method for bit splicing of compressed data is provided, which splices the bits of compressed data. In the data compression stage, the data to be compressed are grouped, each group including a fixed amount of original data. The original data of each group is then compressed using an existing compression scheme to obtain each group of compressed data. Subsequently, each group of compressed data is bit spliced using the method provided in this embodiment.
[0050] See also Figure 1 The implementation process of the compressed data bit splicing method provided in this embodiment is as follows:
[0051] 101, obtain each group of compressed data.
[0052] Each group of compressed data is obtained by compressing each group of original data. The amount of data in each group of original data is fixed, and all groups of original data constitute the data to be compressed.
[0053] For example, before executing the compressed data bit concatenation method provided in this embodiment, the data to be compressed are grouped, each group contains a fixed amount of data, and then each group of original data is compressed to obtain each group of compressed data. In step 101, each group of compressed data is obtained.
[0054] 102, determine the public index corresponding to each group of compressed data.
[0055] For example, the public exponent corresponding to each group of compressed data is calculated using an existing method.
[0056] 103 , forming a compression block corresponding to each group of compressed data according to each group of compressed data and the corresponding public index.
[0057] For any group of compressed data, the public index corresponding to any group of compressed data is used as the first byte data of the corresponding compressed block, and any group of compressed data is used as the non-first byte data of the corresponding compressed block to form a compressed block corresponding to any group of compressed data.
[0058] Among them, each bit in the compressed block is arranged tightly.
[0059] In addition, any set of compressed data includes an in-phase component and a quadrature component, and the quadrature component is arranged before the in-phase component.
[0060] Taking 9-bit width as an example, the bits in the compressed block are arranged as follows Figure 2 shown. Figure 2Each row in represents 1 byte of storage space, consisting of 8 bits. udCompParam represents the public index of the compressed block. I_(bitwidth-1)…I_0, Q_(bitwidth-1)…Q_0, bitwidth=9 represent 1 bit of the in-phase component and quadrature component of a group of compressed data respectively. The arrangement rule of each compressed block is that the first byte is the public index of the current compressed block, and each byte after that is closely arranged for each 1 bit of all compressed data in the current compressed block.
[0061] 104, perform multiple processing on each compressed block.
[0062] Each processing includes an interleaving operation and a shifting operation.
[0063] The interleaving operation in any processing includes: selecting multiple bytes of processing data through an interleaver. For example, for any compressed block, the compressed data of the compressed block is loaded into the interleaver. Since the bit arrangement of each compressed block has a certain regularity, the interleaving function of the interleaver is used to select the IQ components of the compressed data required for each byte, that is, the processing data.
[0064] The shift operation in any one processing includes: performing a shift operation on each byte of the processed data through a multiplier. For example, after any compression block selects a plurality of bytes of processed data through an interleaver, a multiplier is used to perform a shift operation on each byte of data.
[0065] For any compressed block, the number of times it is processed in step 104 can be determined according to the requirements of the communication protocol, and the number of shift bits in the shift operation during each processing can also be determined according to the requirements of the communication protocol.
[0066] 105 , performing a logical OR operation on the results of multiple processing of each compression block to obtain a compressed data bit concatenation result of each compression block.
[0067] Through steps 104 and 105, each bit can be rearranged according to the bit arrangement rule of each compression block and the characteristics of parallel instructions. When arranging, the bit splicing of the compressed data in each compression block can be processed in parallel, and then the compressed data in each compression block can be vectorized to improve the efficiency of bit splicing.
[0068] Taking the 9-bit width commonly used in communication protocols as an example, the 9-bit compressed data specified in the communication protocol is arranged as follows: Figure 3 As shown, the compressed data of any compression block is placed in the register as follows Figure 4 As shown, its multiple processing and logical OR operation are as follows Figure 5 As shown, we can finally get Figure 6A schematic diagram of the compressed data bit splicing result of any compressed block is shown.
[0069] In order to improve the transmission efficiency of data, the data needs to be compressed before transmission and decompressed after receiving the data. According to different data bit width requirements, after compressing the data to a certain bit width, each bit of the compressed data needs to be arranged according to certain rules before it can be transmitted. The compressed data bit splicing method provided in this embodiment can perform vector processing on the bits of compressed data, can batch process the bit splicing of compressed data, and improve the efficiency of bit splicing.
[0070] In addition, if the data spliced by the method provided in this embodiment will be sent by a BBU (Baseband Unit) transmission module, then before executing the method provided in this embodiment, BBU delay measurement will be performed to obtain configuration parameters and achieve time alignment based on the configuration parameters.
[0071] The BBU delay measurement process is implemented by the BBU delay measurement system consisting of BBU, control station, gateway and signal analyzer. Figure 7 shown.
[0072] 1. Console initialization
[0073] The console initializes the configuration parameters and 1PPS, and sends the configuration parameters and 1PPS to the BBU and the signal analyzer (ie, outputs a stable 1PPS) as a reference clock.
[0074] 2. BBU initializes and enters delay measurement mode
[0075] After receiving 1PPS, the BBU starts to enter the delay measurement mode and continues to send downlink signals to the gateway.
[0076] For example, 1) the BBU starts the delay measurement program after receiving the 1PPS, 2) the delay measurement program performs detection and synchronizes with the 1PPS, 3) the delay measurement program determines the signal delay amount according to the configuration parameters (wherein the initial value of the signal delay amount is 0, and for the downlink signal, the signal delay amount is the advance amount of the downlink signal), 4) the delay measurement program sets a timer according to the signal delay amount (i.e., the advance amount of the downlink signal), and the timer generates a timing interrupt according to the signal delay amount, and 5) when the timer generates a timing interrupt, the delay measurement program sends a downlink signal to the gateway station (i.e., whenever a timing interrupt is generated, the downlink signal is sent to the gateway station in the non-terrestrial network).
[0077] Among them, the content of the downlink signal is a test signal that complies with the 3GPP Test Model, such as: NR-FR1-TM3.1a.
[0078] 3. Console configuration signal analyzer
[0079] After the console initializes the configuration parameters and 1PPS, it sends the configuration parameters and 1PPS to the signal analyzer.
[0080] The signal analyzer continuously acquires the downlink signal from the gateway and determines the time delay of the downlink signal relative to 1PPS. The signal analyzer continuously acquires the downlink signal from the gateway and determines the time delay of the downlink signal relative to 1PPS.
[0081] 4. Console setting time delay
[0082] The console cyclically obtains the time delay of the downlink signal relative to 1PPS from the signal analyzer, calculates the appropriate delay compensation parameters (i.e., updates the configuration parameters) based on the time delay, and sends the updated configuration parameters to the BBU and signal analyzer, continuously looping to achieve time alignment.
[0083] 5. When the delay measurement program exit condition is met and the downlink measurement process is completed, the configuration parameters at this time are saved.
[0084] The BBU delay measurement process can quickly measure the downlink signal transmission and processing delay, realize the downlink signal transmission and processing delay, and then make time compensation for the uplink signal according to the aforementioned delay to achieve uplink and downlink time alignment.
[0085] The present embodiment provides a method for bit splicing of compressed data, obtaining each group of compressed data; wherein each group of compressed data is obtained by compressing each group of original data, the number of data in each group of original data is fixed, all groups of original data constitute the data to be compressed, and the fixed number is determined based on the communication protocol; determining the public index corresponding to each group of compressed data; forming a compressed block corresponding to each group of compressed data according to each group of compressed data and the corresponding public index; performing multiple processing on each compressed block; wherein each processing includes an interleaving operation and a shift operation; performing a logical or operation on the results of the multiple processing of each compressed block to obtain the compressed data bit splicing result of each compressed block. The method provided in the present embodiment can perform vector processing on the bits of compressed data to improve the efficiency of bit splicing.
[0086] In the above step 103, after forming compressed blocks corresponding to each group of compressed data according to each group of compressed data and the corresponding public index, the compressed blocks corresponding to each group of compressed data are decompressed. The decompression process includes:
[0087] Input the compressed block into a pre-configured decompression module, and determine a compression factor correction value according to N compression factors input into the decompression module, wherein the N compression factors correspond to N frames of compressed signals;
[0088] According to the compression factor correction value, the compressed signal bit width and the target output bit width of the signal after decompression, the N compression factors are corrected to obtain N corrected compression factors;
[0089] For each frame of compressed signal, the frame compressed signal is decompressed according to the corresponding corrected compression factor to obtain a decompressed signal.
[0090] In an optional embodiment of the present application, the step of determining the compression factor correction value according to the N compression factors input to the decompression module includes:
[0091] Search for the maximum compression factor among the N compression factors input to the decompression module;
[0092] The maximum value of the compression factor is determined as the compression factor correction value.
[0093] In an optional embodiment of the present application, the step of correcting the N compression factors according to the compression factor correction value, the compressed signal bit width, and the target output bit width after signal decompression to obtain N corrected compression factors includes:
[0094] For each of the compression factors, calculating a first difference between the target output bit width of the signal after decompression and the bit width of the compressed signal;
[0095] calculating a second difference between the compression factor and the compression factor correction value;
[0096] The sum of the first difference and the second difference is determined as the corrected compression factor.
[0097] In an optional embodiment of the present application, before the step of determining the compression factor correction value according to the N compression factors input to the decompression module, the method further includes:
[0098] Determining whether the bit width of an original signal corresponding to the compressed signal is greater than or equal to the target output bit width;
[0099] If yes, after receiving the compressed signal, the step of determining the compression factor correction value according to the N compression factors input to the decompression module is performed.
[0100] In an optional embodiment of the present application, the target output bit width is 16 bits.
[0101] Based on the same inventive concept of the compressed data bit splicing method, this embodiment provides a compressed data bit splicing device, such as Figure 8 As shown, the device comprises:
[0102] The acquisition module 801 is used to acquire each group of compressed data, wherein each group of compressed data is obtained by compressing each group of original data, the number of data in each group of original data is fixed, and all groups of original data constitute the data to be compressed.
[0103] The determination module 802 is used to determine the public index corresponding to each group of compressed data obtained by the obtaining module 801.
[0104] The forming module 803 is used to form a compressed block corresponding to each group of compressed data according to each group of compressed data obtained by the obtaining module 801 and the corresponding public index determined by the determining module 802.
[0105] The first processing module 804 is used to perform multiple processing on each compressed block formed by the forming module 803. Each processing includes an interleaving operation and a shifting operation.
[0106] The second processing module 805 is used to perform a logical OR operation on the results of multiple processing of each compressed block obtained by the first processing module 804 to obtain a compressed data bit splicing result of each compressed block.
[0107] Among them, the formation module 803 is used to use the public index corresponding to any group of compressed data as the first byte data of the corresponding compressed block, and use any group of compressed data as the non-first byte data of the corresponding compressed block to form a compressed block corresponding to any group of compressed data.
[0108] Among them, each bit in the compressed block is arranged tightly.
[0109] Any set of compressed data includes an in-phase component and an orthogonal component, and the orthogonal component is arranged before the in-phase component.
[0110] The interleaving operation in any one processing includes: selecting a plurality of bytes of processing data through an interleaver.
[0111] The shift operation in any processing includes: performing a shift operation on each byte of the processed data through a multiplier.
[0112] This embodiment provides a compressed data bit splicing device, wherein the acquisition module acquires each group of compressed data; the determination module determines the public index corresponding to each group of compressed data; the formation module forms a compressed block corresponding to each group of compressed data according to each group of compressed data and the corresponding public index; the first processing module processes each compressed block multiple times; the second processing module performs a logical OR operation on the results of the multiple processing of each compressed block to obtain the compressed data bit splicing result of each compressed block. The device provided by this embodiment can perform vector processing on the bits of compressed data to improve the efficiency of bit splicing.
[0113] Based on the same inventive concept of the compressed data bit splicing method, this embodiment provides an electronic device, the electronic device such as Fig. 9 As shown, it includes: a memory 901, a processor 902, and a computer program.
[0114] The computer program is stored in the memory 901 and is configured to be executed by the processor 902 to implement the above-mentioned compressed data bit splicing method.
[0115] Specifically,
[0116] Obtain each group of compressed data, wherein each group of compressed data is obtained by compressing each group of original data, the number of data in each group of original data is fixed, and all groups of original data constitute the data to be compressed.
[0117] Determine the public exponent corresponding to each group of compressed data.
[0118] According to each group of compressed data and the corresponding public index, a compressed block corresponding to each group of compressed data is formed.
[0119] Each compressed block is processed multiple times, wherein each processing includes an interleaving operation and a shift operation.
[0120] The results of multiple processing of each compression block are logically ORed to obtain the compressed data bit concatenation result of each compression block.
[0121] Optionally, forming a compressed block corresponding to each group of compressed data according to each group of compressed data and a corresponding public index includes:
[0122] For any group of compressed data, the public index corresponding to any group of compressed data is used as the first byte data of the corresponding compressed block, and any group of compressed data is used as the non-first byte data of the corresponding compressed block to form a compressed block corresponding to any group of compressed data.
[0123] Among them, each bit in the compressed block is arranged tightly.
[0124] Optionally, any group of compressed data includes an in-phase component and a quadrature component, and the quadrature component is arranged before the in-phase component.
[0125] Optionally, the interleaving operation in any one processing includes: selecting a plurality of bytes of processing data through an interleaver.
[0126] The shift operation in any processing includes: performing a shift operation on each byte of the processed data through a multiplier.
[0127] The electronic device provided by the present embodiment has a computer program executed by a processor to obtain each group of compressed data; determine the public index corresponding to each group of compressed data; form a compressed block corresponding to each group of compressed data according to each group of compressed data and the corresponding public index; perform multiple processing on each compressed block; perform a logical OR operation on the results of the multiple processing of each compressed block to obtain the bit splicing result of the compressed data of each compressed block, thereby improving the bit splicing efficiency.
[0128] Based on the same inventive concept of the compressed data bit splicing method, this embodiment provides a computer-readable storage medium, and a computer program is stored thereon. The computer program is executed by a processor to implement the compressed data bit splicing method.
[0129] Specifically,
[0130] Obtain each group of compressed data, wherein each group of compressed data is obtained by compressing each group of original data, the number of data in each group of original data is fixed, and all groups of original data constitute the data to be compressed.
[0131] Determine the public exponent corresponding to each group of compressed data.
[0132] According to each group of compressed data and the corresponding public index, a compressed block corresponding to each group of compressed data is formed.
[0133] Each compressed block is processed multiple times, wherein each processing includes an interleaving operation and a shift operation.
[0134] The results of multiple processing of each compression block are logically ORed to obtain the compressed data bit concatenation result of each compression block.
[0135] Optionally, forming a compressed block corresponding to each group of compressed data according to each group of compressed data and a corresponding public index includes:
[0136] For any group of compressed data, the public index corresponding to any group of compressed data is used as the first byte data of the corresponding compressed block, and any group of compressed data is used as the non-first byte data of the corresponding compressed block to form a compressed block corresponding to any group of compressed data.
[0137] Among them, each bit in the compressed block is arranged tightly.
[0138] Optionally, any group of compressed data includes an in-phase component and a quadrature component, and the quadrature component is arranged before the in-phase component.
[0139] Optionally, the interleaving operation in any one processing includes: selecting a plurality of bytes of processing data through an interleaver.
[0140] The shift operation in any processing includes: performing a shift operation on each byte of the processed data through a multiplier.
[0141] The computer-readable storage medium provided in this embodiment has a computer program executed by a processor to obtain each group of compressed data; determine the public index corresponding to each group of compressed data; form a compressed block corresponding to each group of compressed data according to each group of compressed data and the corresponding public index; perform multiple processing on each compressed block; perform a logical OR operation on the results of the multiple processing of each compressed block to obtain the bit splicing result of the compressed data of each compressed block, thereby improving the bit splicing efficiency.
[0142] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of complete hardware embodiments, complete software embodiments, or embodiments in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code. The scheme in the embodiments of the present application can be implemented in various computer languages, for example, object-oriented programming language Java and literal scripting language JavaScript, etc.
[0143] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0144] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.
[0145] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.
[0146] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.
[0147] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.
[0148] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.
Claims
1. A compressed data bit splicing method, characterized in that: The method comprises: Obtain each group of compressed data; wherein each group of compressed data is obtained by compressing each group of original data, the amount of data in each group of original data is fixed, and all groups of original data constitute the data to be compressed; Determine the public index corresponding to each group of compressed data; According to each group of compressed data and the corresponding public index, a compressed block corresponding to each group of compressed data is formed; Performing multiple processing on each compressed block; wherein each processing includes an interleaving operation and a shift operation; The results of multiple processing of each compression block are logically ORed to obtain the compressed data bit concatenation result of each compression block.
2. The method according to claim 1, characterized in that: The forming of compressed blocks corresponding to each group of compressed data according to each group of compressed data and the corresponding public index comprises: For any group of compressed data, using the public index corresponding to the any group of compressed data as the first byte data of the corresponding compressed block, and using the any group of compressed data as the non-first byte data of the corresponding compressed block, to form a compressed block corresponding to the any group of compressed data; Among them, each bit in the compressed block is arranged tightly.
3. The method according to claim 1, characterized in that Any one group of compressed data includes an in-phase component and an orthogonal component, and the orthogonal component is arranged before the in-phase component.
4. The method according to claim 3, characterized in that The interleaving operation in any one process includes: selecting a plurality of bytes of processing data by an interleaver; The shift operation in any one of the processings includes: performing a shift operation on each byte of the processed data through a multiplier.
5. A compressed data bit splicing device, characterized in that: The device comprises: An acquisition module is used to acquire each group of compressed data; wherein each group of compressed data is obtained by compressing each group of original data, the amount of data in each group of original data is fixed, and all groups of original data constitute the data to be compressed; A determination module, used to determine the public index corresponding to each group of compressed data acquired by the acquisition module; A forming module, configured to form a compressed block corresponding to each group of compressed data according to each group of compressed data acquired by the acquiring module and the corresponding public index determined by the determining module; A first processing module, configured to perform multiple processing on each compressed block formed by the forming module; wherein each processing includes an interleaving operation and a shifting operation; The second processing module is used to perform a logical OR operation on the results of multiple processing of each compressed block obtained by the first processing module to obtain a compressed data bit splicing result of each compressed block.
6. The device according to claim 5, characterized in that The forming module is used for, for any group of compressed data, using the public index corresponding to the any group of compressed data as the first byte data of the corresponding compressed block, and using the any group of compressed data as the non-first byte data of the corresponding compressed block, to form a compressed block corresponding to the any group of compressed data; Among them, each bit in the compressed block is arranged tightly.
7. The device according to claim 5, characterized in that Any one group of compressed data includes an in-phase component and an orthogonal component, and the orthogonal component is arranged before the in-phase component.
8. The device according to claim 7, characterized in that The interleaving operation in any one process includes: selecting a plurality of bytes of processing data by an interleaver; The shift operation in any one of the processings includes: performing a shift operation on each byte of the processed data through a multiplier.
9. An electronic device, characterized in that: include: Memory; processor; as well as Computer programs; The computer program is stored in the memory and is configured to be executed by the processor to implement the method according to any one of claims 1 to 4.
10. A computer-readable storage medium, characterized in that: A computer program is stored thereon; the computer program is executed by a processor to implement the method according to any one of claims 1 to 4.