Data caching method, network equipment and computer readable medium

Abstract

The invention provides a data caching method. The data caching method comprises the following steps: extracting message feature information from a received service message; according to the message feature information, determining a target queue in which metadata of the service message needs to be stored; metadata of the service message is cached by utilizing a target queue, the target queue comprises at least two queue segments, and each queue segment is located in a memory allocated for the queue segment. The invention further provides network equipment and a computer readable medium.

Description

Technical Field

[0001] The present disclosure relates to the technical field of data caching, and in particular to a data caching method, a network device and a computer-readable medium. Background Art

[0002] With the rapid development of network communication technology, more and more devices are connected to the network, and the network has entered the era of big data transmission. Among these massive amounts of data, there are autonomous driving, remote control, video calls, etc. that have very high requirements for real-time and packet loss; there are also those with low real-time requirements such as images and data storage; there are also forwarding data services that have very high requirements for forwarding performance, such as NAT (Network Address Translation) and NETFLOW (network monitoring function).

[0003] Regardless of the real-time requirements, packet loss requirements, and forwarding performance requirements, all message data needs to be aggregated and forwarded through network devices. This requires the network devices to be able to process these messages in a timely manner. If the real-time performance is not enough, it may not meet the needs of certain services.

[0004] In the existing technical solutions, in order to improve the forwarding performance and real-time performance of network equipment, the common practice is to use the method of sharing on-chip and off-chip memory. When the message flow is small, the on-chip memory is used to enter and exit the queue; when the message flow is large or there is a burst, the off-chip memory is used to cache the message. At the same time, in order to support different services, the chip in the network device will allocate multiple queues during design. The memory management rules of all queues are consistent, and the service plans the use and allocation of queues by itself.

[0005] However, when designing the chip in the network device, it is impossible to determine how many queues will be used by the business. It can only be planned according to the maximum supported number and the on-chip SRAM (Static Random-Access Memory) memory is evenly distributed to the queues. When the number of queues used by the business is small, the on-chip SRAM memory corresponding to the unused queues will be wasted. Summary of the invention

[0006] The embodiments of the present disclosure provide a data caching method, a network device, and a computer-readable medium.

[0007] In a first aspect, an embodiment of the present disclosure provides a data caching method, including:

[0008] Extracting message feature information from received service messages;

[0009] Determine, according to the message characteristic information, a target queue in which the metadata of the service message is to be stored;

[0010] The metadata of the service message is cached by using the target queue, wherein the target queue includes at least two queue segments, and each of the queue segments is located in a memory allocated thereto.

[0011] In a second aspect, an embodiment of the present disclosure provides a network device, including:

[0012] one or more processors;

[0013] A memory having one or more programs stored thereon, when the one or more programs are executed by the one or more processors, the one or more processors implement the data caching method described in the first aspect of the embodiment of the present disclosure.

[0014] In a third aspect, an embodiment of the present disclosure provides a computer-readable medium having a computer program stored thereon, and when the program is executed by a processor, the data caching method described in the first aspect of the embodiment of the present disclosure is implemented.

[0015] The data caching method provided by the embodiment of the present disclosure allocates memory to at least two queue segments of the target queue, and the memory of each queue segment is allocated according to business needs. The target queue is used to cache metadata of business messages, thereby solving the problem that network equipment cannot meet the business needs of business messages, and at the same time improving the utilization rate of on-chip memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A flowchart of a data caching method provided by an embodiment of the present disclosure;

[0017] Figure 2 A schematic diagram of the relationship between a queue and a processing thread provided in an embodiment of the present disclosure;

[0018] Figure 3 A schematic diagram of the relationship between another queue and a processing thread provided in an embodiment of the present disclosure;

[0019] Figure 4 A schematic diagram of the structure of an on-chip memory provided by an embodiment of the present disclosure;

[0020] Figure 5 A schematic diagram of the structure of an off-chip memory provided by an embodiment of the present disclosure;

[0021] Figure 6 A schematic diagram of the structure of a target queue provided in an embodiment of the present disclosure;

[0022] Figure 7 A schematic diagram of the structure of another target queue provided in an embodiment of the present disclosure;

[0023] Figure 8A schematic diagram of the structure of another target queue provided in an embodiment of the present disclosure;

[0024] Fig. 9 A schematic diagram of the structure of a queue management module provided in an embodiment of the present disclosure;

[0025] Fig.10 This is a flowchart of a specific implementation method of step S3 in the embodiment of the present disclosure;

[0026] Fig.11 This is a flowchart of another specific implementation method of step S3 in the embodiment of the present disclosure;

[0027] Fig.12 A schematic diagram of the structure of a network device provided in an embodiment of the present disclosure;

[0028] Fig.13 A schematic diagram of the structure of a computer-readable medium provided in an embodiment of the present disclosure;

[0029] Fig.14 A flowchart of a data caching method provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] In order to enable those skilled in the art to better understand the technical solution of the present disclosure, the data caching method, network device and computer-readable medium of the control provided by the present disclosure are described in detail below with reference to the accompanying drawings.

[0031] Example embodiments will be described more fully below with reference to the accompanying drawings, but the example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, the purpose of providing these embodiments is to make the present disclosure thorough and complete and to enable those skilled in the art to fully understand the scope of the present disclosure.

[0032] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0033] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0034] The terms used herein are only used to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and / or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements and / or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof is not excluded.

[0035] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined as such herein.

[0036] The service messages transmitted in the network have different service requirements. The service messages can be forwarded by network devices (such as routers, switches, base stations, etc.). The network devices can manage service messages through queues. The queues require memory, which includes on-chip memory and off-chip memory. The on-chip memory has high cost but fast storage rate. The off-chip memory has low cost but low storage rate compared to the on-chip memory. In some related technologies, the queue uses a shared on-chip memory and off-chip memory. When the message flow is small, the on-chip memory is used to enter and exit the queue. When the message flow is large or there is a burst, the off-chip memory is used to cache the message. At the same time, in order to support different services, multiple queues will be allocated during chip design. The memory management rules of all queues are consistent, and the service plans the use and allocation of queues by itself. However, this solution has the following disadvantages: because it is not clear how many queues will be used by the service during chip design, it can only be planned according to the maximum supported number, and the on-chip memory is evenly allocated to the queues. When the number of queues used by the service is small, the on-chip memory corresponding to the unused queues will be wasted. Therefore, in order to avoid wasting on-chip memory, segment management for queues is a feasible solution.

[0037] In view of this, firstly, Figure 1 A flowchart of a data caching method provided in an embodiment of the present disclosure, referring to Figure 1 , the present disclosure provides a data caching method, including:

[0038] S1. Extract message feature information from the received service message.

[0039] S2. Determine, according to the message characteristic information, a target queue in which the metadata of the service message is to be stored.

[0040] S3. Utilize the target queue to cache metadata of the service message, wherein the target queue includes at least two queue segments, and each of the queue segments is located in a memory allocated thereto.

[0041] In the embodiments of the present disclosure, it can be applied to the message processing inside the hardware chips such as CPU (Central Processing Unit, central processing unit) accelerator, intelligent network card, DPU (Data Processing Unit, data processor), and the hardware chip can complete the forwarding performance that meets the business requirements according to the software configuration. Extract the message feature information from the received business message, determine the target queue where the metadata of the business message is to be stored, and use the target queue to cache the metadata of the corresponding business message, that is, the metadata enters the target queue from the tail of the queue in turn, and exits from the head of the target queue in the order of entering the target queue. Among them, the target queue is a linear table that allows insertion at one end of the queue (the tail of the queue) and deletion at the other end (the head of the queue). The queue has the characteristics of first-in-first-out, that is, the element that enters the queue first leaves the queue first. The head of the queue refers to the end of the queue that allows deletion operations, and the tail of the queue refers to the end of the queue that allows insertion of elements.

[0042] Each queue is divided into at least two queue segments, each queue segment is located in the same memory, and different queue segments can be located in different memories, that is, each queue segment can independently manage a memory storage allocated to it, and the memory storage can be selected for each queue segment according to business needs. The memory storage corresponding to each queue segment can be an on-chip memory or an off-chip memory. Therefore, by using multiple queue segments of the target queue with the same or different memories allocated according to business needs to cache the metadata of business messages, the problem that network equipment cannot meet the business needs of business messages can be effectively solved. At the same time, the memory of each queue segment is configured according to business needs, and corresponding configuration can be made according to the business to improve the utilization rate of the on-chip memory.

[0043] Among them, a business message is a data packet used by network devices to communicate or complete specific business tasks. In the embodiments of the present disclosure, there is no special limitation on the data information contained in the business message, which may include various types of information, such as requests, instructions, responses, etc.

[0044] Extract message characteristic information from the service message, the message characteristic information is characteristic information about the service message. In some embodiments, the message characteristic information includes at least one of a multiple access channel, a virtual local area network, a port, a starting position of an offset, a mask, an extraction length, a hash value, a message storage location, and a message length. As an exemplary embodiment, MAC, VLAN, and PORT information are extracted according to MAC (Multiple Access Channel, multiple access channel) + MASK (mask), VLAN (Virtual Local Area Network, virtual local area network) + MASK, and PORT (port) of the service message. As another exemplary embodiment, the message information of the specified offset is extracted by OFFSET (starting position of the offset), MASK, and extraction length of the service message. As another exemplary embodiment, a HASH value can also be calculated so that the service message can be queued according to the HASH value.

[0045] Metadata is data to be stored in the target queue, and is the message description information of the business message. The embodiments of the present disclosure do not impose any special limitations on the cached metadata, which may be message feature information, message information extracted based on message feature information, or the business message itself.

[0046] The target queue is a data structure for storing metadata. For the target queue where the metadata of the service message is to be stored, the target queue can be a single queue or multiple queues, and the present disclosure is not limited thereto.

[0047] As an exemplary embodiment, refer to Figure 2 ,When the target queue is a single queue, the metadata of all ,service messages of service 1 are put into a queue a and are processed in turn. The ,processing process is single-threaded and can be applied to the external network port of the ,network device or the interconnection port between different chips inside the ,device.

[0048] As another exemplary embodiment, refer to Figure 3 In the case where the target queue is multiple queues, the metadata of the service message of service 2 is dispersed into multiple queues (queue i, queue i+1...queue i+j-1), and multiple threads (threads 1 to j) are started accordingly. Each thread processes the metadata of the service message of one queue. The threads can be bound to multiple CPU cores to process the metadata cache of the service message in parallel, thereby greatly improving the forwarding performance of the network device. It can be applied to NAT services on telecommunication equipment that may need to process a large amount of data and have very high requirements for forwarding traffic and performance.

[0049] Accordingly, in some embodiments, before S1, the method further includes:

[0050] S0. Allocate memory for each queue segment in the target queue according to business requirements.

[0051] The embodiments of the present disclosure do not specifically limit the service requirements of service messages, which may be latency requirements or traffic size requirements. The memory allocated for queue segmentation includes on-chip memory and off-chip memory. In some embodiments, the on-chip memory is specially designed inside the chip to improve the performance of queue entry and exit, and at the same time facilitate the division of the use of the on-chip memory according to service requirements.

[0052] In some embodiments, reference Figure 4 The on-chip memory is an on-chip SRAM. The on-chip SRAM area includes K memory blocks, namely Buffer 1, ..., Buffer P, ..., Buffer Q, ..., Buffer R, ..., Buffer K. The size of each memory block can be customized and is used to store messages or message description information. Among them, the on-chip SRAM memory has the characteristics of fast access rate, and its access rate is usually several times faster than that of the off-chip DDR. At the same time, the on-chip SRAM memory also has the characteristics of high cost. Therefore, when the queue uses the on-chip memory and the off-chip memory, the memory space configuration of the on-chip SRAM is relatively small. Reference Figure 5 The off-chip memory is an off-chip DDR (Double Data Rate) memory. The off-chip DDR area includes K memory blocks, namely Buffer 1, ..., Buffer A, ..., Buffer B, ..., Buffer C, ..., Buffer M. Among them, the off-chip DDR memory has the characteristic of low cost. Therefore, when the queue uses the on-chip memory and the off-chip memory, the memory space of the off-chip DDR memory will be larger, and the actual use space that can be configured for the queue will also be larger. If the entry and exit performance requirements of the service message are not high or the queue depth is required to be relatively large, the off-chip DDR memory can be used as the queue management memory.

[0053] As an exemplary implementation, for services with high performance requirements, such as NAT service messages, the queue segments of all target queues used by the NAT service can be configured as on-chip memories, which can greatly improve the forwarding performance of the hardware; as another exemplary implementation, for service messages with low performance requirements, such as control plane messages, off-chip memories can be allocated to the queues used by the control plane messages to meet their service needs; as another exemplary implementation, for messages with high latency requirements but low traffic, on-chip memories can be configured for the head and tail segments of their queues, while off-chip memories can be configured for the mid-team segments, so that in most scenarios, messages are transmitted from the tail segment to the head segment, and in the case of message bursts, the off-chip memories of the mid-team segments are used to prevent bursts.

[0054] In some embodiments, the target queue is divided into three queue segments, which are the first queue segment, the second queue segment, and the third queue segment from the entrance to the exit of the target queue.

[0055] In this embodiment, the target queue is a FIFO (First-In-First-Out) queue, wherein when a new element is added to the target queue, it is queued from the end of the target queue (also referred to as the tail), and when an element is removed from the target queue, it is queued from the beginning of the target queue (also referred to as the head). In this embodiment, the first queue segment is the tail segment, and the third queue segment is the head segment.

[0056] In some embodiments, when the target queue includes a first queue segment, a second queue segment, and a third queue segment, the first queue segment is a tail segment, the second queue segment is a middle segment, and the third queue segment is a head segment. According to business requirements, allocating memory to the first queue segment, the second queue segment, and the third queue segment includes at least one of the following situations:

[0057] 1)Reference Figure 6 For business requirements with low performance but high latency, on-chip memory is allocated to the first queue segment and the third queue segment, and the on-chip memory is on-chip SRAM, and off-chip memory is allocated to the second queue segment, and the off-chip memory is off-chip DDR.

[0058] 2)Reference Figure 7 , the performance and latency requirements corresponding to the business needs are relatively high, and an on-chip memory is allocated to the first queue segment, the second queue segment, and the third queue segment. The on-chip memory is an on-chip SRAM.

[0059] 3)Reference Figure 8, the performance and latency requirements corresponding to the business needs are relatively low, and an off-chip memory is allocated to the first queue segment, the second queue segment, and the third queue segment. The off-chip memory is an off-chip DDR.

[0060] Among them, it is worth mentioning that when the first queue segment, the second queue segment and the third queue segment are all located in the on-chip memory, the target queue has high entry and exit performance and low latency. When the metadata of the service message is cached through the target queue, the metadata can be directly queued from the first queue segment (tail segment), the metadata in the first queue segment is queued into the second queue segment (middle segment), the metadata in the second queue segment is queued into the third queue segment (head segment), and the metadata is dequeued from the third queue segment.

[0061] In some embodiments, N queues (including the target queue) can be managed by the queue management module, where N is a positive integer. The value of N can be determined according to the actual needs of the chip used for caching. For example, N can be 128, 256, 512, etc. The value of N is the maximum number of queues supported by the chip, not the number of queues actually used. The number of queues actually used is determined by the business. At the same time, unused queues will not occupy on-chip memory and off-chip memory. Each queue includes at least two queue segments, and the queue management module sets the management of each queue segment according to the actual performance needs (business needs) of the business. Each queue segment allocates on-chip memory or off-chip memory according to business needs to ensure that business messages with different performance use different queue memory combinations to meet their own business needs. In some embodiments, it is only necessary to allocate on-chip memory or off-chip memory for the target queue actually used, and it is not necessary to allocate memory for all queues.

[0062] As an exemplary embodiment, refer to Fig. 9 The target queue includes a first queue segment (tail segment), a second queue segment (middle segment) and a third queue segment (head segment). The queue management module sets up head segment management, middle segment management and tail segment management.

[0063] As another exemplary implementation, the target queue may also be divided into two queue segments, which are the fourth queue segment and the fifth queue segment. From the entrance to the exit of the target queue are the fourth queue segment and the fifth queue segment.

[0064] As another exemplary implementation, when the target queue includes a first queue segment (tail segment), a second queue segment (middle segment) and a third queue segment (head segment), and a descriptor address (metadata) of a service message can be stored in every 4 bytes, the queue management module allocates memory to the target queue according to service requirements as follows:

[0065] Confirm the memory size of the allocable on-chip memory, divide the total memory size by 4 to get the total number of descriptor addresses that the on-chip memory can store. When using it, specify the head address and tail address for the first queue segment, the second queue segment, and the third queue segment of the target queue. The head and tail address range memory must be physically continuous. The queue management module will automatically calculate the number of 4-byte descriptors that can be stored based on the head and tail addresses of the memory block. At the same time, the first queue segment, the second queue segment, and the third queue segment that allocate the on-chip memory will be marked with an on-chip memory mark to facilitate identification of whether the memory is on-chip memory or off-chip memory.

[0066] Specifically, refer to Fig. 9 , each 4-byte space is defined as a Buffer, then Buffer 1~P can be allocated to the third queue segment, P+1~Q can be allocated to the second queue segment of the queue, and Q+1~R can be allocated to the first queue segment of the queue. This is only an exemplary allocation method. The queue management module 112 can also be allocated with an off-chip memory. The configuration method is similar to the allocation method of the on-chip memory. For queues with low performance requirements or some queues that require a large amount of Buffer buffering, an off-chip memory can be allocated for them. The off-chip memory has the advantages of large memory and can configure the depth of the queue to be deeper. Similarly, when the off-chip memory is configured for use by the queue segment, the physical address must also be continuous. It is worth noting that since the memory actually used by the queue management module may be greater than its maximum memory threshold (such as 4G), when the configured memory is greater than the maximum memory threshold, the SMMU (System Memory Management Units, memory management unit) page table must be configured to realize the conversion of virtual and real addresses, that is, the physical address or virtual physical address within the maximum memory threshold is actually configured for the queue management module.

[0067] Accordingly, in some embodiments, reference Fig.10 , when the first queue segment and the third queue segment are located in an on-chip memory, and the second queue segment is located in an off-chip memory, S3 includes:

[0068] S31. Enqueue the metadata from the first queue segment of the target queue.

[0069] S32. When there is no backlog metadata in the first queue segment or the data volume of the backlog metadata is less than a preset threshold value, the metadata is directly dequeued from the third queue segment; when there is backlog metadata in the first queue segment and the data volume of the backlog metadata is greater than or equal to the preset threshold value, the metadata queued in the first queue segment enters the first buffer, the metadata in the first buffer enters the second queue segment, and the metadata in the second queue segment is dequeued from the third queue segment.

[0070] In this embodiment, metadata is directly enqueued from the first queue segment (tail segment) of the target queue.

[0071] When there is no backlog metadata in the first queue segment or the amount of backlog metadata is less than the preset threshold value, it means that the current business message traffic is small and / or the business processing performance is high. The metadata in the first queue segment can be directly dequeued through the third queue segment (head segment) without passing through the second queue segment (mid-queue segment). At this time, the delay of the target queue caching metadata is small.

[0072] When there is backlog metadata in the first queue segment and the amount of backlog metadata is greater than or equal to the preset threshold value, it indicates that the current service message flow is large and / or the service processing performance is low. The metadata in the first queue segment is buffered to the first buffer zone. The first buffer zone is a buffer FIFO. The first buffer zone has the function of preventing bursts or caching messages, which can be used to solve the problem of mismatch between the entry and exit rates of the first queue segment and the second queue segment, so as to avoid the slow entry rate of the second queue segment, which may lead to the blocking of the first queue segment or other queues. Then the metadata in the first buffer zone enters the second queue segment, and the metadata in the second queue segment is dequeued from the third queue segment.

[0073] Accordingly, in some embodiments, when the first buffer is full, S3 further includes:

[0074] The metadata most recently entered into the first buffer is discarded.

[0075] In this embodiment, when the first buffer is full, it means that no new metadata can enter the first buffer, and the first buffer can discard the latest metadata, that is, perform packet loss processing. In some embodiments, when a packet is lost, the metadata message is first sent to the FREE FIFO (buffer FIFO for release), and then the description information address of the message and the message storage address are released to the POOL (memory pool). The buffer FIFO for release is used to solve the rate mismatch problem in packet loss processing.

[0076] In some embodiments, reference Fig.11, when the first queue segment, the second queue segment and the third queue segment are located in an off-chip memory, S3 includes:

[0077] S31', storing the metadata in a second buffer.

[0078] S32′: After metadata in the second buffer is enqueued from the first queue segment of the target queue, it is dequeued in sequence through the second queue segment and the third queue segment.

[0079] In this embodiment, when the first queue segment, the second queue segment, and the third queue segment are all located in the off-chip memory, the target queue has low entry and exit performance and large latency, and can generally be used in business scenarios where performance requirements are not high, latency is not sensitive, or a large amount of metadata needs to be cached. The metadata requires a second buffer, which is a buffer FIFO, and then queues to the first queue segment. The second buffer has the function of preventing bursts or caching messages, which can be used to solve the problem of rate mismatch. After the metadata in the second buffer is queued from the first queue segment, it is dequeued through the second queue segment and the third queue segment in turn.

[0080] Accordingly, in some embodiments, when the second buffer is full, S3 further includes:

[0081] The metadata most recently entered into the second buffer is discarded.

[0082] In this embodiment, when the second buffer is full, it means that there are too many metadata in the target queue at this time, that is, the message traffic is too large, and the second buffer cannot enter new metadata. The second buffer can discard the latest metadata, that is, perform packet loss processing. In some embodiments, when a packet is lost, the metadata message is first sent to the FREE FIFO, and then the description information address and the message storage address of the message are released to the POOL. The FREE FIFO is used to solve the rate mismatch problem in packet loss processing.

[0083] As an exemplary implementation, the memory corresponding to the first buffer and / or the second buffer is an on-chip memory.

[0084] In some embodiments, the enqueue rules of the business message can be configured through the enqueue management module, the business message can be received, the message feature information can be extracted according to the business message, and the metadata of the business message can be enqueued into the corresponding target queue according to the message feature information.

[0085] As an exemplary implementation, the entry to the exit of the queue managed by the enqueue management module are the first queue segment (tail segment), the second queue segment (middle segment) and the third queue segment (head segment) respectively. When the enqueue management module caches the service message to the target queue, if the tail segment of the target queue is SRAM memory (i.e., on-chip memory), it can be directly enqueued. If the tail segment of the target queue is DDR memory area (i.e., off-chip memory), a buffer FIFO is added to solve the problems of large delay and rate mismatch in the off-chip memory area of ​​the target queue. The message is then sent to the tail segment of the off-chip DDR memory by the buffer FIFO, thereby avoiding affecting other on-chip memories. At the same time, if the message flow in the DDR area of ​​the write queue is too large and causes the buffer FIFO to be full, the packet can be dropped at the buffer FIFO to avoid affecting the data enqueuing of other queues.

[0086] The step division of the above various methods is only for clear description. When implemented, they can be combined into one step or some steps can be split and decomposed into multiple steps. As long as they include the same logical relationship, they are all within the protection scope of this disclosure. Adding insignificant modifications to the algorithm or process or introducing insignificant designs without changing the core design of the algorithm and process are all within the protection scope of this disclosure.

[0087] Second, refer to Fig.12 , an embodiment of the present disclosure provides a network device, comprising:

[0088] One or more processors 1201.

[0089] The memory 1202 stores one or more programs. When the one or more programs are executed by one or more processors, the one or more processors implement any one of the above data caching methods.

[0090] One or more I / O interfaces 1203 are connected between the processor and the memory and are configured to implement information exchange between the processor and the memory.

[0091] Among them, the processor 1201 is a device with data processing capabilities, including but not limited to a central processing unit (CPU); the memory 1202 is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH); the I / O interface (read-write interface) 1203 is connected between the processor 1201 and the memory 1202, and can realize information interaction between the processor 1201 and the memory 1202, including but not limited to a data bus (Bus), etc.

[0092] In some embodiments, the network equipment is a product that has high requirements for network acceleration performance, can facilitate product design of flexible packet receiving rules, relatively balanced traffic load, and has high requirements for sending and receiving message rates. It can be a router, switch, base station, server, smart network card, DPU, etc.

[0093] Thirdly, refer to Fig.13 The embodiment of the present disclosure provides a computer-readable medium on which a computer program is stored. When the program is executed by a processor, any of the above-mentioned data caching methods is implemented.

[0094] In order to enable those skilled in the art to more clearly understand the technical solutions provided by the embodiments of the present disclosure, the technical solutions provided by the embodiments of the present disclosure are described in detail below through specific embodiments:

[0095] Example 1: Reference Fig.14 , the metadata caching process of business messages is:

[0096] First, according to the forwarding performance of the service, the queues to be used are planned and the on-chip memory or off-chip memory is planned for each queue segment of the corresponding queue (including the head segment, the middle segment, and the tail segment), and then all queues to be used are initialized uniformly. At the same time, all on-chip SRAM memory needs to be planned and used to avoid waste.

[0097] More specifically, for the kernel network port with a smaller message volume, the first queue is allocated to it, and the head segment and the tail segment of the first queue are allocated on-chip SRAM, and the middle segment of the first queue is allocated off-chip DDR; for the NAT service with high performance requirements, multiple queues are allocated to it, including the second queue, the third queue, the fourth queue, etc., and the head segment, middle segment, and tail segment of all queues use on-chip SRAM to improve the performance of message entry and exit, thereby improving the forwarding performance of messages; for the DPI (Deep Packet Inspection) service that requires a large number of cached messages, the fifth queue is allocated to it, and the head segment, middle segment, and tail segment of the fifth queue are allocated off-chip DDR.

[0098] Furthermore, the message receiving module receives the service message on the network and extracts the message characteristic information of the service message, or calculates the HASH value of the service message according to the message characteristic information. The specific parsing rules can be configured by the service. At the same time, the service message is stored. The physical first address (or virtual physical address) corresponding to the service message and the characteristic information and HASH value of the message are passed to the queue management module.

[0099] The enqueue management module automatically matches and compares the message feature information and HASH value to be identified with the queue number QID, and caches the metadata of the business message that passes the comparison to the corresponding target queue. If the business message fails the comparison, it can be sent to a default queue or directly discarded.

[0100] The process of caching the metadata of the service message to the corresponding target queue is as follows:

[0101] When the head segment and the tail segment are located in the on-chip memory and the middle segment is located in the off-chip memory, the metadata is queued from the tail segment; when there is no backlog metadata in the tail segment or the amount of backlog metadata is less than a preset threshold value, the metadata is directly dequeued from the head segment; when there is backlog metadata in the tail segment and the amount of backlog metadata is greater than or equal to the preset threshold value, the metadata of the queued tail segment enters the first buffer, the metadata in the first buffer enters the middle segment, and the metadata in the middle segment is dequeued from the head segment.

[0102] When the head segment, the middle segment, and the tail segment are all located in the on-chip memory, the metadata is queued from the tail segment, then enters the middle segment, and finally exits the queue through the head segment.

[0103] When the head segment, middle segment and tail segment are all located in the off-chip memory, the metadata first enters the second buffer, and the metadata in the second buffer is queued from the tail segment, then enters the middle segment, and finally exits the queue through the head segment.

[0104] The metadata of the service message has been sent to the target queue, and the service can fetch packets from the target queue for processing. The way of fetching packets can be evaluated based on the actual service performance. It can be interruption or polling. During polling, the CPU core is bound and packets are received in a loop to improve the performance of fetching packets.

[0105] During the caching process of the above metadata, each target queue is divided into a head segment, a middle segment, and a tail segment, so that the business can set the on-chip memory or off-chip memory corresponding to the queue segment according to performance and latency requirements, which can increase the utilization of the on-chip memory and, to a certain extent, improve the product forwarding performance and reduce the message entry and exit latency. At the same time, adding a buffer FIFO before the off-chip memory can solve the rate mismatch problem caused by direct writing to the off-chip memory, and will not block other queues or memory release when packets are lost.

[0106] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0107] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly noted, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A data caching method, comprising: Extracting message feature information from received service messages; Determine, according to the message characteristic information, a target queue in which the metadata of the service message is to be stored; The metadata of the service message is cached by using the target queue, wherein the target queue includes at least two queue segments, and each of the queue segments is located in a memory allocated thereto.

2. The data caching method according to claim 1, wherein: The message characteristic information includes at least one of a multiple access channel, a virtual local area network, a port, a starting position of an offset, a mask, an extraction length, a hash value, a message storage location, and a message length.

3. The data caching method according to claim 1, wherein: Before extracting message feature information from the received service message, the following steps are also included: According to business requirements, memory is allocated to each of the queue segments in the target queue.

4. The data caching method according to claim 1, wherein: The target queue is divided into three queue segments, which are the first queue segment, the second queue segment and the third queue segment from the entrance to the exit of the target queue.

5. The data caching method according to claim 4, wherein: In a case where the first queue segment and the third queue segment are located in an on-chip memory, and the second queue segment is located in an off-chip memory, using the target queue to cache metadata of the service message includes: enqueue the metadata from the first queue segment of the target queue; In the case that there is no backlog metadata in the first queue segment or the amount of the backlog metadata is less than a preset threshold value, the metadata is directly dequeued from the third queue segment; When there is backlog metadata in the first queue segment and the data volume of the backlog metadata is greater than or equal to a preset threshold value, the metadata enqueued in the first queue segment enters the first buffer, the metadata in the first buffer enters the second queue segment, and the metadata in the second queue segment is dequeued from the third queue segment.

6. The data caching method according to claim 5, wherein: When the first buffer is full, caching the metadata of the service message to the target queue further includes: The metadata most recently entered into the first buffer is discarded.

7. The data caching method according to claim 4, wherein: In a case where the first queue segment, the second queue segment, and the third queue segment are located in an off-chip memory, using the target queue to cache metadata of the service message includes: storing the metadata in a second buffer; After metadata in the second buffer is enqueued from the first queue segment of the target queue, it is dequeued in sequence through the second queue segment and the third queue segment.

8. The data caching method according to claim 7, wherein: When the second buffer is full, caching the metadata of the service message to the target queue further includes: The metadata most recently entered into the second buffer is discarded.

9. A network device comprising: one or more processors; A memory having one or more programs stored thereon, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the data caching method according to any one of claims 1 to 8.

10. A computer-readable medium having a computer program stored thereon, wherein the program, when executed by a processor, implements the data caching method according to any one of claims 1 to 8.

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