Semiconductor device including vertical channel transistor

Abstract

A semiconductor device including a vertical channel transistor is disclosed. The semiconductor device includes: a molded insulating pattern on a substrate; an upper lead extending in a first horizontal direction on the substrate; a channel structure including a vertical channel portion facing a side surface of the upper conductive line and contacting a first sidewall of the molded insulation pattern, in which the vertical channel portion extends in a vertical direction; a first gate dielectric layer at least partially surrounding a surface of the channel structure; and a second gate dielectric layer between the upper conductive line on the channel structure and the first gate dielectric layer, in which the molded insulation pattern includes a body and a protrusion, in which the body extends in a first horizontal direction and the protrusion protrudes in a second horizontal direction intersecting the first horizontal direction.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0145936 filed on October 27, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Embodiments of the inventive concept relate to semiconductor devices. More particularly, embodiments of the inventive concept relate to semiconductor devices including vertical channel transistors. Background Art

[0003] The size reduction of semiconductor devices is progressing rapidly, and therefore, in order to reduce leakage current through a channel region, a vertical channel transistor having a channel layer including an oxide semiconductor material is being developed. Summary of the invention

[0004] According to an embodiment conceived in the present invention, a semiconductor device includes: a molded insulating pattern located on a substrate; an upper conductive line extending in a first horizontal direction on the substrate; a channel structure including a vertical channel portion, the vertical channel portion facing a side surface of the upper conductive line and contacting a first side wall of the molded insulating pattern, wherein the vertical channel portion extends in a vertical direction; a first gate dielectric layer at least partially surrounding a surface of the channel structure; and a second gate dielectric layer located between the upper conductive line on the channel structure and the first gate dielectric layer, wherein the molded insulating pattern includes a body and a protrusion, wherein the body extends in the first horizontal direction and the protrusion protrudes in a second horizontal direction intersecting the first horizontal direction.

[0005] According to an embodiment of the present invention, a semiconductor device includes: a plurality of lower conductive lines located on a substrate and arranged in parallel with each other; a mold insulating pattern located on the plurality of lower conductive lines and extending in a first horizontal direction, wherein the mold insulating pattern defines a transistor region; a plurality of channel structures arranged in the transistor region along the first horizontal direction, wherein each of the plurality of channel structures includes a vertical channel portion facing a sidewall of the mold insulating pattern; a first gate dielectric layer overlapping the sidewalls of the plurality of channel structures; a plurality of upper conductive lines located on the plurality of channel structures in the transistor region and including a vertical channel portion facing the sidewalls of the mold insulating pattern; The molded insulating pattern is provided with a first gate dielectric layer disposed between the plurality of channel structures and the plurality of upper conductive lines, and a second gate dielectric layer disposed between the plurality of channel structures and the plurality of upper conductive lines; and a plurality of conductive contact patterns, each of the plurality of conductive contact patterns being connected to the vertical channel portion of each of the plurality of channel structures, wherein a first portion of the molded insulating pattern facing the vertical channel portion has a width in the second horizontal direction greater than a second portion of the molded insulating pattern not facing the vertical channel portion, and wherein the second horizontal direction intersects the first horizontal direction.

[0006] According to an embodiment of the present invention, a semiconductor device includes: a printed circuit region located on a substrate and including a plurality of printed circuits; a lower conductive line located on the printed circuit region and connected to the plurality of printed circuits; a molded insulating pattern located on the lower conductive line and including a sidewall defining a transistor region; a channel structure located in the transistor region and including a lower surface and a vertical portion, wherein the lower surface of the channel structure contacts an upper surface of the lower conductive line, and the vertical channel portion of the channel structure faces the sidewall of the molded insulating pattern; a first gate dielectric layer and a second gate dielectric layer covering the channel structure in the transistor region; an upper conductive line located on the first gate dielectric layer and the second gate dielectric layer in the transistor region and including a sidewall facing the vertical channel portion of the channel structure; and a conductive contact pattern connected to the vertical channel portion of the channel structure, wherein the channel structure includes an oxide semiconductor layer, and the molded insulating pattern includes a protrusion protruding in a direction intersecting a direction in which the molded insulating pattern extends, wherein the protrusion of the molded insulating pattern has a preset thickness and contacts the vertical channel portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The above and other aspects of the present inventive concept will become more apparent by describing in detail embodiments of the present inventive concept with reference to the accompanying drawings, in which: Figure 1 is a plan layout diagram showing components of a semiconductor device according to an embodiment of the inventive concept; Figure 2A yes Figure 1 A cross-sectional view taken along line AA'; Figure 2B yes Figure 1 A cross-sectional view taken along line BB'; Figure 3 yes Figure 1 An enlarged cross-sectional view of a portion indicated by "EX" in FIG. Figure 4A , Figure 4B , Figure 4C , Figure 5A , Figure 5B , Figure 5C , Fig. 6A , Figure 6B , Figure 6C , Fig. 7A , Figure 7B , Figure 7C , Fig. 8A , Figure 8B , Figure 8C , Fig. 9 , Fig.10 and Fig.11 A sequential process of a method for manufacturing a semiconductor device according to an embodiment of the inventive concept is shown, wherein: Figure 4A , Figure 5A , Fig. 6A , Fig. 7A and Fig. 8A It is shown according to the manufacturing Figure 1 A method of sequentially processing a semiconductor device with a planar layout of some components, Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9 , Fig.10 and Fig.11 It shows that Figure 1 A cross-sectional view of a sequential process of a region corresponding to a cross-section taken along line AA', and Figure 4C , Figure 5C , Figure 6C , Figure 7C and Figure 8C It shows that Figure 1 A cross-sectional view of a sequential process of a region corresponding to a cross-sectional view taken along line BB'. DETAILED DESCRIPTION

[0008] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the same components are assigned the same reference numerals throughout the specification and the drawings, and overlapping descriptions of the same components will be omitted or briefly discussed.

[0009] The embodiments of the present invention are subject to various modifications and have various forms, and the embodiments of the present invention are shown in the drawings and described in detail below. However, it should be understood that the scope of the present invention is not limited to the embodiments discussed herein, but includes all modifications, equivalents and replacements within the spirit and technical scope of the present invention.

[0010] Figure 1 is a plan layout illustrating components of a semiconductor device 100 according to an embodiment of the inventive concept. Figure 2A yes Figure 1 A cross-sectional view taken along line AA'. Figure 2B yes Figure 1 A cross-sectional view taken along line BB', and Figure 3 yes Figure 1 An enlarged cross-sectional view of the portion indicated by “EX” in FIG.

[0011] Reference Figure 1 , Figure 2A , Figure 2B and Figure 3 , the semiconductor device 100 may include a substrate 102, a printed circuit assembly PCA located on the substrate 102 and including a plurality of printed circuits, a plurality of bit lines BL arranged on the printed circuit assembly PCA, and a plurality of shielding lines SL.

[0012] According to an embodiment of the present inventive concept, the substrate 102 may include silicon (e.g., single crystal silicon, polycrystalline silicon, or amorphous silicon). According to an embodiment of the present inventive concept, the substrate 102 may include at least one of germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). According to an embodiment of the present inventive concept, the substrate 102 may include a conductive region (e.g., a well doped with impurities or a structure doped with impurities).

[0013] Each of the plurality of bit lines BL may be connected to at least one printed circuit among the plurality of printed circuits included in the printed circuit assembly PCA. Each of the plurality of shielding lines SL may be floated. The plurality of bit lines BL may be insulated from the plurality of shielding lines SL by the insulating interlayer 106F, respectively. The plurality of shielding lines SL may be covered by the insulating interlayer 106G, and the plurality of bit lines BL may penetrate the insulating interlayers 106F and 106G in the vertical direction (Z direction). The plurality of bit lines BL may be connected to the printed circuit included in the printed circuit assembly PCA through a portion selected from the plurality of conductive plugs P1, P2, and P3 and the plurality of wiring layers M1 and M2 included in the printed circuit assembly PCA.

[0014] The printed circuit assembly PCA may include a plurality of core circuits 104. The plurality of core circuits 104 may include a first conductive pattern C1 and a second conductive pattern C2 sequentially located on the substrate 102. The first conductive pattern C1 and the second conductive pattern C2 may constitute various circuit elements for controlling functions of a semiconductor device located on the printed circuit assembly PCA. According to an embodiment of the inventive concept, the printed circuit assembly PCA may also include various active elements (such as transistors) and various passive elements (such as capacitors, resistors, inductors, etc.).

[0015] According to an embodiment of the inventive concept, a plurality of printed circuits included in the printed circuit assembly PCA may include a sub-word line driver block SWD, a sense amplifier block S / A, and / or a control logic, but the inventive concept is not limited thereto. A plurality of printed circuits included in the printed circuit assembly PCA may include an n-channel metal oxide semiconductor (NMOS) transistor and a p-channel metal oxide semiconductor (PMOS) transistor. The plurality of printed circuits may be electrically connected to conductive lines (e.g., a plurality of bit lines BL) located on the printed circuit assembly PCA through a plurality of conductive plugs P1, P2, and P3 and a plurality of wiring layers M1 and M2.

[0016] In the printed circuit assembly PCA, some parts of the plurality of core circuits 104, the plurality of conductive plugs P1, P2, and P3, and the plurality of wiring layers M1 and M2 may be maintained at a predetermined insulation distance by the plurality of insulating interlayers 106A, 106B, 106C, 106D, and 106E. For example, each of the plurality of insulating interlayers 106A, 106B, 106C, 106D, and 106E may be formed of an oxide layer, a nitride layer, or a combination thereof, but is not limited thereto.

[0017] According to an embodiment of the inventive concept, the printed circuit assembly PCA on the substrate 102 may be omitted. In this case, the printed circuit assembly PCA may be located on the substrate 102 and may be located on the substrate 102. Figure 2A and Figure 2B According to an embodiment of the inventive concept, the printed circuit assembly PCA may be located in a region spaced apart from the cell array region including the transistor region TRR in a side direction.

[0018] The plurality of bit lines BL may be spaced apart from the plurality of shielding lines SL in a first horizontal direction (X direction) on the substrate 102, respectively, and the plurality of bit lines BL and the plurality of shielding lines SL may extend in a second horizontal direction (Y direction) substantially perpendicular to the first horizontal direction (X direction). The plurality of bit lines BL and the plurality of shielding lines SL may extend parallel to each other in the second horizontal direction (Y direction). According to an embodiment of the inventive concept, the plurality of bit lines BL may be formed of at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), ruthenium (Ru), tungsten (W), tungsten nitride (WN), cobalt (Co), nickel (Ni), titanium silicon (TiSi), titanium silicon nitride (TiSiN), tungsten silicon (WSi), tungsten silicon nitride (WSiN), tantalum silicon (TaSi), tantalum silicon nitride (TaSiN), ruthenium titanium nitride (RuTiN), cobalt silicon (CoSi), nickel silicon (NiSi), polysilicon, and combinations thereof, but the inventive concept is not limited thereto. In this specification, the bit line BL may also be referred to as a lower conductive line. According to an embodiment of the inventive concept, each of the plurality of shielding lines SL may be formed of at least one of tungsten (W), aluminum (Al), copper (Cu), and a combination thereof, but the inventive concept is not limited thereto. According to an embodiment of the inventive concept, each of the plurality of shielding lines SL may include a conductive layer formed of W, Al, Cu, or a combination thereof, and an air gap or void formed inside the conductive layer.

[0019] The mold insulating pattern 110 may be located on the plurality of bit lines BL and the plurality of shield lines SL. The mold insulating pattern 110 may extend in a first horizontal direction (X direction). For example, the mold insulating pattern 110 may be formed of at least one of a silicon oxide layer, a silicon nitride layer, and a combination thereof.

[0020] like Figure 1 and Figure 2A As shown in , the channel structure 120 may be aligned along the first horizontal direction (X direction) in the transistor region TRR. The channel structure 120 may include a vertical channel portion VC and a horizontal channel portion HC. The vertical channel portion VC may face the sidewall of the mold insulation pattern 110, and the horizontal channel portion HC may contact the upper surface of the bit line BL.

[0021] In each of the plurality of channel structures 120 , the vertical channel portion VC may be in contact with a sidewall of the mold insulation pattern 110 , and may extend from the horizontal channel portion HC in a vertical direction (Z direction).

[0022] The channel structure 120 may contact the upper surface of the bit line BL among the plurality of bit lines BL. According to an embodiment of the inventive concept, the channel structure 120 may be formed of an oxide semiconductor layer. In the drawings, the channel structure 120 is shown as a single layer, however, this is only an example. The inventive concept is not limited thereto, and the channel structure 120 may include a multilayer including two or more layers.

[0023] According to an embodiment of the inventive concept, the oxide semiconductor layer included in the channel structure 120 may be formed of at least one of indium gallium zinc oxide (InGaZnO; IGZO), Sn-IGZO, indium tungsten oxide (InWO; IWO), indium zinc oxide (InZnO; IZO), zinc tin oxide (ZnSnO; ZTO), zinc oxide (ZnO), yttrium-doped zinc oxide (YZO), indium gallium silicon oxide (InGaSiO; IGSO), indium oxide (InO), tin oxide (SnO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), silicon indium zinc oxide (SiInZnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), and combinations thereof. For example, the channel structure 120 may be formed of IGZO.

[0024] like Figure 1 and Figure 2A As shown in FIG, the first gate dielectric layer 131 and the second gate dielectric layer 132 covering the channel structure 120 and the plurality of word lines WL covering the first gate dielectric layer 131 and the second gate dielectric layer 132 may be located in the transistor region TRR. The plurality of word lines WL may extend in a first horizontal line (X direction) and may be arranged parallel to each other. Figure 1 and Figure 2A 1 shows a configuration in which two word lines WL are arranged in the transistor region TRR. In this specification, the word line WL may also be referred to as an upper conductive line. In the transistor region TRR, the word line WL may contact the second gate dielectric layer 132, and the word line WL may face the plurality of channel structures 120 in the second horizontal direction (Y direction), wherein the first gate dielectric layer 131 and the second gate dielectric layer 132 are disposed between the word line WL and the plurality of channel structures 120.

[0025] like Figure 1As shown in , each of the plurality of word lines WL may include a first portion and a second portion. The first portion of each of the plurality of word lines WL faces the channel structure 120, wherein the first gate dielectric layer 131 and the second gate dielectric layer 132 are disposed between the first portion of the plurality of word lines WL and the channel structure 120. The second portion of each of the plurality of word lines WL faces the mold insulating pattern 110, wherein the second gate dielectric layer 132 is disposed between the second portion of the plurality of word lines WL and the mold insulating pattern 110 without being disposed between the channel structure 120 and the first gate dielectric layer 131. In each of the plurality of word lines WL, the second portion may be closer to the mold insulating pattern 110 than the first portion in the second horizontal direction (Y direction).

[0026] like Figure 2A As shown in , each bit line BL may be spaced apart from each word line WL in the vertical direction (Z direction), wherein the channel structure 120 and the first gate dielectric layer 131 and the second gate dielectric layer 132 are disposed between each bit line BL and each word line WL. For example, the bit line BL may have an upper surface in contact with the channel structure 120.

[0027] In the transistor region TRR, the channel structure 120 may face one side surface of each of the two word lines WL located in the transistor region TRR. The first gate dielectric layer 131 and the second gate dielectric layer 132 may include portions in contact with the plurality of channel structures 120. In one embodiment, the first gate dielectric layer 131 may at least partially surround the surface of the channel structure 120. The second gate dielectric layer 132 may include a portion in contact with the sidewall of the mold insulation pattern 110. The first gate dielectric layer 131 and the second gate dielectric layer 132 may include a portion located between one side surface of each of the two word lines WL and the vertical channel portion VC of the channel structure 120, and a portion located between the lower surface of each of the two word lines WL and the horizontal channel portion HC of the channel structure 120.

[0028] The first and second gate dielectric layers 131 and 132 may be between the channel structure 120 and the word lines WL. A top surface of the channel structure 120 may be closer to the substrate 102 than top surfaces of the first and second gate dielectric layers 131 and 132 , the plurality of word lines WL, and the mold insulation pattern 110 .

[0029] According to an embodiment of the inventive concept, each of the first gate dielectric layer 131 and the second gate dielectric layer 132 may be formed of a high dielectric layer having a dielectric constant greater than that of a silicon oxide layer. According to an embodiment of the inventive concept, the first gate dielectric layer 131 may have the same composition as that of the second gate dielectric layer 132. According to an embodiment of the inventive concept, the first gate dielectric layer 131 may have a composition different from that of the second gate dielectric layer 132. According to an embodiment of the inventive concept, the first gate dielectric layer 131 and the second gate dielectric layer 132 may be formed of at least one of hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconate titanate (PZT), strontium bismuth tantalate (STB), bismuth iron oxide (BFO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO). For example, each of the plurality of word lines WL may be formed of Ti, TiN, Ta, TaN, Mo, Ru, W, WN, TiSiN, WSiN, polysilicon, or a combination thereof. In one embodiment, the mold insulation pattern 110 may include a low-k material having a dielectric constant smaller than each of a dielectric constant of the first gate dielectric layer 131 and a dielectric constant of the second gate dielectric layer 132.

[0030] The lower insulating partition wall 142 may be located on the channel structure 120 between the two word lines WL “located in the transistor region TRR”. The upper surfaces of the two word lines WL and the upper surfaces of the lower insulating partition wall 142 may be covered by the upper insulating partition wall 144. In the second horizontal direction (Y direction), the width of the upper insulating partition wall 144 may be greater than the width of the lower insulating partition wall 142. For example, in the second horizontal direction (Y direction), the width of the upper insulating partition wall 144 may be greater than the width of each of the two word lines WL. For example, each of the lower insulating partition wall 142 and the upper insulating partition wall 144 may be formed of a silicon oxide layer, a silicon nitride layer, or a combination thereof.

[0031] A plurality of conductive contact patterns 150P may be located on the plurality of channel structures 120. Each of the plurality of conductive contact patterns 150P may be connected to a channel structure 120 among the plurality of channel structures 120. For example, each conductive pattern 150P may be disposed on the upper insulating partition wall 144 and the mold insulating pattern 110.

[0032] like Figure 1As shown in FIG. 1 , a plurality of conductive contact patterns 150P may be regularly disposed at constant intervals in a first horizontal direction (X direction) and a second horizontal direction (Y direction). Figure 1 An example is shown in which a plurality of conductive contact patterns 150P are arranged in a matrix structure on a plane (e.g., an XY plane) on the substrate 102. However, the inventive concept is not limited thereto. For example, a plurality of conductive contact patterns 150P may be arranged in a honeycomb structure on a plane (e.g., an XY plane) on the substrate 102. The plurality of conductive contact patterns 150P may be insulated from each other by a separation insulating layer 160.

[0033] The channel structure 120 may be spaced apart from a portion of the conductive contact pattern 150P. Each of the plurality of conductive contact patterns 150P may have a surface contacting the channel structure 120 .

[0034] The plurality of conductive contact patterns 150P may be spaced apart from the word lines WL, wherein the first gate dielectric layer 131 and the second gate dielectric layer 132 are disposed between the plurality of conductive contact patterns 150P and the word lines WL.

[0035] Each of the plurality of conductive contact patterns 150P may be formed of a metal layer. According to an embodiment of the inventive concept, the plurality of conductive contact patterns 150P may be formed of Ti, TiN, Ta, TaN, Mo, Ru, W, WN, TiSiN, WSiN, or a combination thereof. For example, the plurality of conductive contact patterns 150P may be a stacked structure of a conductive barrier layer formed of TiN and a conductive layer formed of W.

[0036] The semiconductor device 100 may include a plurality of capacitor structures CAP located on a plurality of conductive contact patterns 150P. An etch stop layer 162 and an insulating interlayer 170 may be sequentially disposed on the plurality of conductive contact patterns 150P and the separation insulating layer 160. The plurality of capacitor structures CAP may penetrate the insulating interlayer 170 and the etch stop layer 162 in a vertical direction (Z direction) and may be connected to the conductive contact patterns 150P among the plurality of conductive contact patterns 150P. For example, the etch stop layer 162 may be a silicon nitride layer, and the insulating interlayer 170 may be a silicon oxide layer.

[0037] Figure 3 yes Figure 1 An enlarged cross-sectional view of the portion indicated by “EX” in FIG.

[0038] Refer to Figure 3 and Figure 1, the mold insulation pattern 110 may include a body extending in a first horizontal direction (X direction) and a protrusion protruding in a second horizontal direction (Y direction). According to an embodiment of the inventive concept, the protrusion may be a plurality of protrusions having a mirror-symmetrical shape with respect to the body of the mold insulation pattern 110 and spaced apart from each other. According to an embodiment of the inventive concept, the protrusion may have a rectangular shape from a plan view.

[0039] Since the mold insulating pattern 110 includes a body and a protrusion, the mold insulating pattern 110 may have different widths in the second horizontal direction (Y direction). The sidewall 110H2 of the protrusion may protrude from the sidewall (110H1) of the body by a preset distance D1. For example, the length of the side of the protrusion having a rectangular shape in a plan view in the second horizontal direction (Y direction) may be the preset distance D1. In one embodiment, the sidewall 110H2 of the protrusion may protrude from the sidewall (110H1) of the body by a preset distance D1. Figure 1In a plan view of FIG. 1 , the width (or referred to as the maximum width) of the first portion of the mold insulating pattern 110 facing the vertical channel portion VC in the second horizontal direction (Y direction) is greater than the width (or referred to as the minimum width) of the second portion of the mold insulating pattern 110 not facing the vertical channel portion VC in the second horizontal direction, and the difference between the width of the first portion in the second horizontal direction (Y direction) and the width of the second portion in the second horizontal direction (Y direction) (e.g., the difference between the maximum width and the minimum width) may be two or more times the specific distance D2 (e.g., the thickness of the second gate dielectric layer 132). According to an embodiment of the inventive concept, the preset distance D1 may be substantially equal to the thickness of the second gate dielectric layer 132. In this case, the difference between the maximum width and the minimum width of the mold insulating pattern 110 in the second horizontal direction (Y direction) may be at least twice the specific distance D2 (i.e., at least twice the thickness of the second gate dielectric layer 132). According to an embodiment of the inventive concept, in one embodiment, the preset distance D1 may be greater than the minimum width of the mold insulating pattern 110 in the second horizontal direction (Y direction), however, the embodiment is not limited thereto, and in another embodiment, the preset distance D1 may be less than or equal to the minimum width of the mold insulating pattern 110 in the second horizontal direction (Y direction). According to an embodiment of the inventive concept, the preset distance D1 may be greater than the thickness of the second gate dielectric layer 132. In this case, the difference between the maximum width and the minimum width of the mold insulating pattern 110 in the second horizontal direction (Y direction) may be more than twice the specific distance D2 (i.e., more than twice the thickness of the second gate dielectric layer 132). In one embodiment, the thickness of the second gate dielectric layer 132 is greater than the minimum width of the mold insulating pattern 110 in the second horizontal direction (Y direction), and the embodiment is not limited thereto, and in another embodiment, the thickness of the second gate dielectric layer 132 may be less than or equal to the minimum width of the mold insulating pattern 110 in the second horizontal direction (Y direction). The mold insulating pattern 110 may be a pattern obtained by partially etching the sidewall of the mold insulating pattern 110 after forming the mold insulating pattern 110. The inventive concept may obtain a final structure in which the word line WL surrounds three sides of the channel structure 120 including the oxide semiconductor layer by adding a process of partially etching the sidewall of the mold insulating pattern 110. Therefore, a gate characteristic improvement effect of a semiconductor device including a vertical channel semiconductor may be provided.

[0040] FIG. 4A to FIG. 11 1 shows a sequential process of a method for manufacturing a semiconductor device according to an embodiment of the inventive concept. More specifically, Figure 4A , Figure 5A , Fig. 6A , Fig. 7A and Fig. 8A It is shown according to the manufacturing Figure 1A method for sequentially processing a planar layout of components of a semiconductor device. Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9 , Fig.10 and Fig.11 It shows that Figure 1 A cross-sectional view of a sequential process of a region corresponding to a cross section taken along AA'. Figure 4C , Figure 5C , Figure 6C , Figure 7C and Figure 8C It shows that Figure 1 A cross-sectional view of a sequential process of a region corresponding to a cross section taken along line BB'. FIG. 4A to FIG. 11 In the same reference numerals (such as Figure 1 , Figure 2A , Figure 2B and Figure 3 ) denote the same elements and, therefore, overlapping descriptions thereof will be omitted or briefly discussed.

[0041] Reference Figure 4A , Figure 4B and Figure 4C , a plurality of printed circuits including a plurality of core circuits 104, a plurality of conductive plugs P1, P2, and P3, and a plurality of wiring layers M1 and M2 may be formed on the substrate 102 to form a printed circuit assembly PCA on the substrate 102. Thereafter, a plurality of shielding lines SL penetrating the insulating interlayer 106F and a plurality of bit lines BL penetrating the insulating interlayers 106F and 106G may be formed on the printed circuit assembly PCA.

[0042] Reference Figure 5A , Figure 5B and Figure 5C , can be formed in the plurality of bit lines BL Figure 4A , Figure 4B and Figure 4C A mold insulating pattern 110 having a plurality of openings 110H is formed on the obtained structure. For example, the mold insulating pattern 110 may be formed on the bit lines BL. Some regions of the plurality of bit lines BL may be exposed through the plurality of openings 110H. Each of the plurality of openings 110H formed in the mold insulating pattern 110 may be provided with a transistor region TRR (see Figure 1 According to an embodiment of the inventive concept, a width of each mold insulation pattern 110 extending in the first horizontal direction (X direction) in the second horizontal direction (Y direction) may be W1.

[0043] Reference Fig. 6A , Figure 6B and Figure 6C , a channel layer 120L may be formed in a plurality of openings 110H formed in the mold insulating pattern 110, and a first gate dielectric layer 131L may be formed to conformally cover an exposed surface of the channel layer 120L. For example, the channel layer 120L may be formed on regions of a plurality of bit lines BL exposed by the plurality of openings 110H. The channel layer 120L may be formed of, for example, an oxide semiconductor layer. The oxide semiconductor layer may be formed of, for example, IGZO (InGaZnO), Sn-IGZO, InWO (IWO), InZnO (IZO), ZnSnO (ZTO), ZnO, yttrium-doped zinc oxide (YZO), InGaSiO (IGSO), InO, SnO, TiO, ZnON, MgZnO, ZrInZnO, HfInZnO, SnInZnO, SiInZnO, GaZnSnO, ZrZnSnO, or a combination thereof. For example, the channel layer 120L may be formed of IGZO.

[0044] According to an embodiment of the inventive concept, the channel layer 120L may be formed by at least one of a chemical vapor deposition (CVD) process, a low pressure CVD process, a plasma enhanced CVD process, a metal organic CVD (MOCVD) process, and an atomic layer deposition (ALD) process. According to an embodiment of the inventive concept, the channel layer 120L may be formed with a thickness of about 1 nm to about 50 nm; however, the inventive concept is not limited thereto.

[0045] Reference Fig. 7A , Figure 7B and Figure 7C , available in Fig. 6A , Figure 6B and Figure 6C A sacrificial pattern SM1 covering the channel layer 120L and the first gate dielectric layer 131L is formed on the obtained structure, and the channel layer 120L and the first gate dielectric layer 131L may be etched by using the sacrificial pattern SM1 as an etching mask to divide the channel layer 120L into a plurality of channel structures 120. For example, the sacrificial pattern SM1 may be formed on the first gate dielectric layer 131L in the plurality of openings 110H. The insulating interlayer 106G may be exposed between the plurality of channel structures 120 in the plurality of openings 110H.

[0046] In addition, both sides of each mold insulating pattern 110 may be additionally etched to further reduce the width of the mold insulating pattern 110 in the second horizontal direction (Y direction). Fig. 7A The width W2 of the mold insulation pattern 110 may become smaller than Fig. 6A The width W1 of the mold insulation pattern 110 is 0. Fig. 6A The width W1 of the mold insulation pattern 110 is Fig. 7AThe width difference between the width W2 of the mold insulation pattern 110 in the second gate dielectric layer 132 (see FIG. 8A to FIG. 8C ), the second gate dielectric layer 132 is deposited later and has a thickness of twice or more than Fig. 6A The mold insulating pattern 110 is etched to a thickness smaller than the width W1 of the mold insulating pattern 110. For example, the mold insulating pattern 110 may be etched to a thickness of the second gate dielectric layer 132 (see FIG. 8A to FIG. 8C ) is twice or more the thickness of the Figure 3 , Fig. 6A The width W1 of the mold insulation pattern 110 is Fig. 7A The width difference between the width W2 of the mold insulation pattern 110 in the embodiment may be twice the preset distance D1, which is less than Fig. 6A The width W1 of the mold insulation pattern 110 is 0.

[0047] Reference Fig. 8A , Figure 8B and Figure 8C , which can be obtained by Fig. 7A , Figure 7B and Figure 7C The sacrificial pattern SM1 is removed from the obtained structure to expose the upper surfaces of the multiple channel structures 120, and then, multiple second gate dielectric layers 132 and multiple word lines WL that sequentially cover “the multiple channel structures 120 and the first gate dielectric layer 131 located on the upper surfaces of the multiple channel structures 120” can be formed in the multiple openings 110H of the mold insulation pattern 110.

[0048] According to an embodiment of the inventive concept, in order to form a plurality of second gate dielectric layers 132 and a plurality of word lines WL, after exposing the upper surfaces of the plurality of channel structures 120 and the first gate dielectric layer 131, the second gate dielectric layer 132 may be first formed to conformally cover the exposed surfaces of the plurality of channel structures 120, the first gate dielectric layer 131, and the insulating interlayer 106G. Then, a plurality of word lines WL may be formed on the second gate dielectric layer 132. During the patterning process for forming the plurality of word lines WL, a portion of the second gate dielectric layer 132 located between two word lines WL in the opening 110H may be removed. The upper surface of the channel structure 120 may be exposed between the two word lines WL in the opening 110H.

[0049] Thereafter, a lower insulating partition wall 142 filling a space between two word lines WL in the opening 110H may be formed in the opening 110H. Then, an upper insulating partition wall 144 covering upper surfaces of the two word lines WL and the lower insulating partition wall 142 may be formed in the opening 110H. Upper surfaces of the upper insulating partition wall 144, the first gate dielectric layer 131, the second gate dielectric layer 132, the word lines WL, and the mold insulating pattern 110 may form a substantially flat surface.

[0050] Reference Fig. 9 , can be removed Fig. 8A , Figure 8B and Figure 8C The process of removing a portion of the upper portion of each of the plurality of channel structures 120 in the obtained structure is performed to lower the height of the plurality of channel structures 120. As a result, a plurality of contact spaces CTH defined by the sidewalls of the first gate dielectric layer 131 and the mold insulating pattern 110 may be formed above the plurality of channel structures 120. For example, the process of removing a portion of the upper portion of each of the plurality of channel structures 120 may be performed by a wet process, a dry process, or a combination thereof.

[0051] Reference Fig.10 , can form "in Fig. 9 A conductive layer 150 is formed by filling a plurality of contact spaces CTH in the obtained structure and covering the upper surface of the mold insulating pattern 110, the first gate dielectric layer 131, the second gate dielectric layer 132, and the upper insulating partition wall 144. The conductive layer 150 may be formed of, for example, Ti, TiN, Ta, TaN, Mo, Ru, W, WN, TiSiN, WSiN, polysilicon, or a combination thereof. For example, the conductive layer 150 may be a stacked structure of a conductive barrier layer formed of TiN and a conductive layer formed of W.

[0052] Reference Fig.11 , can be etched Fig.10 Some regions of the conductive layer 150 in the obtained structure are formed to form separation spaces exposing the upper insulating partition walls 144, and a plurality of conductive contact patterns 150P may be formed by etching the conductive layer 150. Thereafter, a separation insulating layer 160 filling the separation spaces may be formed.

[0053] Afterwards, if Figure 2A and Figure 2B As shown in FIG. 1 , an etch stop layer 162 and an insulating interlayer 170 may be formed on the obtained structure on which a plurality of conductive contact patterns 150P are formed. For example, the etch stop layer 162 may be formed on the conductive contact pattern 150P and the separation insulating layer 160, and the insulating interlayer 170 may be formed on the etch stop layer 162. A plurality of capacitor structures CAP penetrating the etch stop layer 162 and the insulating interlayer 170 to be connected to the plurality of conductive contact patterns 150P may be formed.

[0054] Therefore, reference has been made FIG. 4A to FIG. 11 Describes the process used to make Figure 1 , Figure 2A , Figure 2B and Figure 3 However, by applying various modifications and changes within the scope of the inventive concept, semiconductor devices having various structures can be manufactured without departing from the spirit and scope of the inventive concept.

[0055] While the inventive concepts have been described with reference to example embodiments of the inventive concepts, persons skilled in the art will understand that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concepts.

Claims

1. A semiconductor device, comprising: a molded insulating pattern, located on the substrate; An upper conductive line extending in a first horizontal direction on the substrate; a channel structure including a vertical channel portion facing a side surface of the upper conductive line and contacting a first sidewall of the mold insulating pattern, wherein the vertical channel portion extends in a vertical direction; a first gate dielectric layer at least partially surrounding a surface of the channel structure; and A second gate dielectric layer is located between the upper conductive line on the channel structure and the first gate dielectric layer, The molded insulating pattern includes a body and a protrusion, wherein the body extends in a first horizontal direction and the protrusion protrudes in a second horizontal direction intersecting the first horizontal direction.

2. The semiconductor device according to claim 1, wherein The channel structure includes an oxide semiconductor layer.

3. The semiconductor device according to claim 1, wherein A sidewall of the protrusion of the mold insulation pattern corresponds to a first sidewall of the mold insulation pattern.

4. The semiconductor device according to claim 1, wherein: The protrusion of the mold insulation pattern protrudes from the body of the mold insulation pattern by a predetermined distance, which is greater than or equal to a thickness of the second gate dielectric layer.

5. The semiconductor device according to claim 1, wherein The protrusion of the molded insulation pattern has a rectangular shape.

6. The semiconductor device according to claim 1, wherein The protrusion of the molded insulation pattern has a mirror-symmetrical shape with respect to the body of the molded insulation pattern.

7. The semiconductor device according to claim 1, wherein A sidewall of the body of the mold insulation pattern on which no protrusion is located faces the upper conductive line, wherein a second gate dielectric layer is disposed between the sidewall and the upper conductive line.

8. The semiconductor device according to claim 1, wherein The mold insulating pattern includes a low-k material having a dielectric constant smaller than each of a dielectric constant of the first gate dielectric layer and a dielectric constant of the second gate dielectric layer.

9. The semiconductor device according to claim 1, wherein: The vertical channel portion of the channel structure is spaced apart from the body of the mold insulation pattern.

10. The semiconductor device according to claim 1, wherein The channel structure is a multi-layer structure including two or more layers.

11. The semiconductor device according to claim 1, further comprising: The lower conductor is located between the substrate and the channel structure. wherein the lower conductive line is spaced apart from the upper conductive line, wherein the channel structure, the first gate dielectric layer, and the second gate dielectric layer are disposed between the lower conductive line and the upper conductive line, wherein the upper surface of the lower conductive line contacts the horizontal channel portion of the channel structure, and The lower conductive line extends in a second horizontal direction.

12. The semiconductor device according to any one of claims 1 to 11, further comprising: A conductive contact pattern is connected to the channel structure.

13. The semiconductor device according to claim 12, further comprising: A capacitor structure is connected to the conductive contact pattern.

14. A semiconductor device comprising: A plurality of lower conductive lines are located on the substrate and arranged parallel to each other; a molded insulating pattern located on the plurality of lower conductive lines and extending in a first horizontal direction, wherein the molded insulating pattern defines a transistor region; a plurality of channel structures arranged in the transistor region along a first horizontal direction, wherein each of the plurality of channel structures includes a vertical channel portion facing a sidewall of the mold insulation pattern; a first gate dielectric layer overlapping the sidewalls of the plurality of channel structures; a plurality of upper conductive lines located on the plurality of channel structures in the transistor region and including sidewalls facing a vertical channel portion of each of the plurality of channel structures, wherein the plurality of upper conductive lines extend in a first horizontal direction; A second gate dielectric layer is located between the plurality of channel structures and the plurality of upper conductive lines; and a plurality of conductive contact patterns, each of the plurality of conductive contact patterns being connected to a vertical channel portion of each of the plurality of channel structures, wherein a width of a first portion of the mold insulating pattern facing the vertical channel portion in the second horizontal direction is greater than a width of a second portion of the mold insulating pattern not facing the vertical channel portion in the second horizontal direction, The second horizontal direction intersects with the first horizontal direction.

15. The semiconductor device according to claim 14, wherein: The plurality of channel structures include an oxide semiconductor layer.

16. The semiconductor device according to claim 14, wherein: A difference between a width of a first portion of the mold insulating pattern facing the vertical channel portion in the second horizontal direction and a width of a second portion of the mold insulating pattern not facing the vertical channel portion in the second horizontal direction is two or more times the thickness of the second gate dielectric layer.

17. The semiconductor device according to any one of claims 14 to 16, wherein: A plurality of transistors including the plurality of channel structures are located in a transistor region, The plurality of transistors include two transistors facing each other, and The two transistors share a channel structure among the plurality of channel structures.

18. A semiconductor device comprising: a printed circuit region located on the substrate and comprising a plurality of printed circuits; a lower conductor located on the printed circuit area and connected to the plurality of printed circuits; a molded insulating pattern located on the lower conductive line and including a sidewall defining a transistor region; a channel structure located in the transistor region and including a lower surface and a vertical portion, wherein the lower surface of the channel structure contacts the upper surface of the lower conductive line and the vertical channel portion of the channel structure faces a sidewall of the mold insulating pattern; a first gate dielectric layer and a second gate dielectric layer covering the channel structure in the transistor region; an upper conductive line disposed on the first gate dielectric layer and the second gate dielectric layer in the transistor region and including a sidewall facing the vertical channel portion of the channel structure; and A conductive contact pattern connected to the vertical channel portion of the channel structure, Wherein, the channel structure includes an oxide semiconductor layer, and The mold insulating pattern includes a protrusion protruding in a direction intersecting a direction in which the mold insulating pattern extends, wherein the protrusion of the mold insulating pattern has a preset thickness and contacts the vertical channel portion.

19. The semiconductor device according to claim 18, wherein: The preset thickness is greater than or equal to the thickness of the second gate dielectric layer.

20. The semiconductor device according to claim 18 or claim 19, wherein: The protrusion is mirror-symmetrical with respect to the body of the molded insulation pattern and has a rectangular shape.

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