Magnetic random access memory, preparation method thereof, chip packaging body and electronic equipment

Abstract

The invention provides a magnetic random access memory and a preparation method thereof, a chip packaging body and electronic equipment, relates to the technical field of electronics, and is used for improving the performance of the magnetic random access memory, giving consideration to the read-write speed and the data retention capability of the magnetic random access memory and simplifying the preparation process of the magnetic random access memory. The magnetic random access memory comprises a first memory unit and a second memory unit, and the first memory unit comprises a first reference layer, a first barrier layer and a first free layer which are stacked in sequence; the second memory unit comprises a second reference layer, a second barrier layer and a second free layer which are stacked in sequence; the second free layer includes a first portion and a second portion, the first portion is farther from the second barrier layer than the second portion, and a concentration of oxygen ions in the first portion is greater than a concentration of oxygen ions in the second portion and greater than a concentration of oxygen ions in the first free layer. The magnetic random access memory is used for storing data.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a magnetic random access memory and a preparation method thereof, a chip package, and an electronic device. Background Art

[0002] With the continuous development of the digital economy, people have higher and higher requirements for the performance of electronic devices, such as computing performance and power consumption. System on Chip (SoC) is an important component that affects the performance of electronic devices. In order to improve the performance of the system on chip, multi-level caches are usually set up. These caches generally use static random access memory (SRAM), which is composed of multiple transistors. In recent years, although semiconductor technology has been continuously improved, the size of transistors is difficult to reduce significantly, or it costs a very high price to reduce the size of transistors. This results in the area occupied by SRAM on SoC being very large, and even occupies more than half of the area of ​​the entire SoC. In addition, the power consumption of SRAM, especially the static power consumption caused by leakage when idle, is becoming more and more serious as the size of transistors decreases, which also restricts the power consumption optimization space of the entire SoC.

[0003] As a new type of non-volatile memory, magnetic random access memory (MRAM) has advantages over SRAM such as high density and low power consumption, and can be used to replace SRAM. In particular, spin transfer torque magnetic random access memory (STTMRAM) has a relatively mature technology and has received widespread attention. Under the same process, STT-MRAM can achieve 2-3 times the density of SRAM and reduce overall power consumption by 50% or more.

[0004] However, STT-MRAM also has some defects, such as slow reading and writing speeds, so there are still many difficulties to overcome in replacing SRAM with STT-MRAM. Summary of the invention

[0005] The embodiments of the present application provide a magnetic random access memory and a preparation method thereof, a chip package, and an electronic device, which are used to solve the problem of difficulty in balancing the reading and writing speed and data retention of the magnetic random access memory.

[0006] In order to achieve the above objectives, this application adopts the following technical solutions:

[0007] In a first aspect, a magnetic random access memory is provided, comprising: a first storage unit and a second storage unit, wherein the first storage unit comprises a first reference layer, a first barrier layer and a first free layer stacked in sequence; the second storage unit comprises a second reference layer, a second barrier layer and a second free layer stacked in sequence; the second free layer comprises a first part and a second part, the first part is farther away from the second barrier layer than the second part, and the concentration of oxygen ions in the first part is greater than the concentration of oxygen ions in the second part, and greater than the concentration of oxygen ions in the first free layer.

[0008] The storage unit of the magnetic random access memory stores data by stacking a reference layer, a barrier layer and a free layer to form a magnetic tunnel junction. Specifically, the data "0" or "1" is represented by whether the magnetization directions of the reference layer and the free layer are consistent. The magnetization direction of the reference layer remains unchanged, and the magnetization direction of the free layer can be controlled by the direction of the current. The direction of the current includes two directions: the reference layer flows to the free layer and the free layer flows to the reference layer. The current in these two directions can make the magnetization direction of the free layer consistent with or opposite to the magnetization direction of the reference layer.

[0009] The magnetic random access memory provided in this embodiment includes two types of memory cells, namely, a first memory cell and a second memory cell, wherein the first memory cell includes a first reference layer, a first barrier layer and a first free layer stacked in sequence; the second memory cell includes a second reference layer, a second barrier layer and a second free layer stacked in sequence; the second free layer includes a first part and a second part, wherein the first part is farther away from the second barrier layer than the second part, and the concentration of oxygen ions in the first part is greater than the concentration of oxygen ions in the second part, and greater than the concentration of oxygen ions in the first free layer. The concentrations of oxygen ions in the first part and the second part of the second free layer are different, thereby increasing the perpendicular magnetic anisotropy of the second free layer, that is, the magnetization direction of the second free layer is more difficult to change than that of the first free layer, so a larger current needs to be passed, and correspondingly, the time for reading and writing data in the second memory cell is also increased accordingly, but since the magnetization direction of the second free layer is more difficult to change, the data retention capability of the second memory cell is also stronger. On the contrary, the first memory cell has a faster read and write speed and a lower data retention capability, thereby simultaneously realizing fast read and write and high data retention in the same magnetic random access memory.

[0010] In addition, when preparing the magnetic random access memory, the difference between the first storage unit and the second storage unit is only the oxidation degree of the first free layer and the second free layer. Therefore, when preparing the first free layer and the second free layer, a film layer can be deposited, and a mask layer is used to cover the first area where the first free layer is located in the film layer, exposing the second area where the second free layer is located, and the second area is oxidized and then an etching process is performed to form the first free layer and the second free layer. In other words, two types of storage units can be formed by adding only one photolithography step and an oxidation step, which simplifies the preparation process.

[0011] In a possible implementation of the first aspect, the concentration of oxygen ions in the first free layer is less than or equal to one third of the concentration of oxygen ions in the first portion of the second free layer. In this way, the ease of changing the magnetization directions of the first free layer and the second free layer can be significantly different, even if the read and write speeds and data retention capabilities of the two types of storage cells are significantly different, which is beneficial for application in specific usage scenarios.

[0012] In a possible implementation of the first aspect, the concentration of oxygen ions in the first free layer is zero, so that when preparing the magnetic memory, the first free layer does not need to be oxidized, thereby reducing the process flow.

[0013] In a possible implementation of the first aspect, the concentration of oxygen ions in the second portion of the second free layer is equal to the concentration of oxygen ions in the first free layer. In this way, a film layer can be formed by the same deposition process, and then the film layer is formed into the first free layer and the second free layer by photolithography, oxidation, etching, etc.

[0014] In a possible implementation of the first aspect, the magnetic random access memory includes a first storage area and a second storage area, the first storage unit is arranged in the first storage area, and the second storage unit is arranged in the second storage area; the magnetic random access memory is also provided with a first silicon through hole, and the first silicon through hole is arranged near the first storage area; the first storage unit is connected to a bus penetrating the first silicon through hole. In this way, when the magnetic random access memory is read and written through the bus, since the connection distance between the bus and the first storage unit is short, the time consumed on the line when reading and writing the first storage unit can be reduced, and the performance advantage of fast reading and writing of the first storage unit can be better utilized.

[0015] In a possible implementation of the first aspect, there are multiple first TSVs, and the multiple first TSVs surround the first storage area, so as to avoid centrally arranging the first TSVs, which would occupy a large area, thereby reducing restrictions on the layout of each storage area in the magnetic random access memory.

[0016] In a possible implementation of the first aspect, the first storage area is located in the center of the magnetic random access memory, the second storage area surrounds the first storage area, and the plurality of first through silicon vias are located between the first storage area and the second storage area. Thus, when the distance from the first through silicon via to the first storage area is made less than or equal to the distance to the second storage area, the distance from the second storage area to the first through silicon via is balanced.

[0017] In a possible implementation of the first aspect, the magnetic random access memory further comprises a first signal line, and the second storage unit is connected to the bus via the first signal line. Thus, not only the first storage unit but also the second storage unit can be read and written via the bus.

[0018] In the second aspect, the present application provides a chip package, which includes: a stacked processing unit, a magnetic random access memory and a main memory, wherein the magnetic random access memory is arranged between the processing unit and the main memory; the magnetic random access memory includes: a first storage unit and a second storage unit, wherein the first storage unit includes a first reference layer, a first barrier layer and a first free layer stacked in sequence; the second storage unit includes a second reference layer, a second barrier layer and a second free layer stacked in sequence; the second free layer includes a first part and a second part, the first part is farther away from the second barrier layer than the second part, and the concentration of oxygen ions in the first part is greater than the concentration of oxygen ions in the second part, and greater than the concentration of oxygen ions in the first free layer. The magnetic random access memory in the chip package takes into account both the read and write speed and the ability to retain data at a high level, and also simplifies the preparation process.

[0019] In a possible implementation of the second aspect, the magnetic random access memory includes a first storage area and a second storage area, the first storage unit is arranged in the first storage area, and the second storage unit is arranged in the second storage area; a first silicon through via is arranged near the first storage area; the chip package also includes a bus penetrating in the first silicon through via, and the first storage unit is connected to the processing unit through the bus. In this way, when the processing unit performs a read and write operation on the magnetic random access memory through the bus, since the bus penetrates the first silicon through via and the first silicon through via is arranged near the first storage area, the connection distance between the bus and the first storage unit is short, which can reduce the time lost on the line when reading and writing the first storage unit, and can give full play to the performance advantage of fast reading and writing of the first storage unit.

[0020] In a third aspect, the present application also provides a chip package, which includes: a stacked processing unit, a magnetic random access memory, a main memory and a bus, wherein the magnetic random access memory is arranged between the processing unit and the main memory; the magnetic random access memory includes a first storage unit and a second storage unit, the first storage unit is arranged in a first storage area of ​​the magnetic random access memory, and the second storage unit is arranged in a second storage area of ​​the magnetic random access memory; the first storage unit includes a first reference layer, a first barrier layer and a first free layer stacked in sequence; the second storage unit includes a second reference layer, a second barrier layer and a second free layer stacked in sequence; the coercive force of the first free layer is smaller than that of the second free layer; the magnetic random access memory is also provided with a first silicon via near the first storage area; the bus passes through the first silicon via and connects the first storage unit with the main memory.

[0021] The magnetic random access memory in the chip package takes into account both the read and write speed and the high data retention capability. When the processing unit performs read and write operations on the magnetic random access memory through the bus, since the first silicon through via is arranged close to the first storage area and the bus passes through the first silicon through via, the connection distance between the bus and the first storage unit is short, which can reduce the time lost on the line when reading and writing the first storage unit, and can better give play to the performance advantage of fast reading and writing of the first storage unit.

[0022] In a possible implementation of the third aspect, the processing unit includes a first processor, the first storage area is connected to the first processor via a bus, and the geometric center of the first processor coincides with the projection of the geometric center of the first storage area on a reference plane; the reference plane is a plane perpendicular to the stacking direction of the processing unit, the magnetic random access memory, and the main memory. In this way, the length of the bus connection between the first processor and the first storage area can be reduced, thereby improving the reading and writing speed of the processing unit to the first storage area.

[0023] In a possible implementation of the third aspect, there are multiple first through silicon vias, and the multiple first through silicon vias surround the first storage area. This can avoid the first through silicon vias being centrally arranged, which occupies a large area, thereby reducing the restrictions on the layout of each storage area in the magnetic random access memory, and is also beneficial to the connection between the bus and the processing unit during stacking packaging.

[0024] In a possible implementation of the third aspect, the first storage area is located in the center of the magnetic random access memory, the second storage area surrounds the first storage area, and the plurality of first through silicon vias are located between the first storage area and the second storage area, thereby making the distance from the first through silicon via to the first storage area less than or equal to the distance to the second storage area and balancing the distance from the second storage area to the first through silicon via.

[0025] In a possible implementation of the third aspect, the main memory is provided with a second through silicon via, the second through silicon via is connected to the first through silicon via, the bus is also penetrated through the second through silicon via, and the main memory is connected to the bus penetrated through the second through silicon via. In this way, the second through silicon via is aligned with the first through silicon via, and connection through a redistribution layer is avoided during stacked packaging, thereby simplifying the packaging process.

[0026] In a possible implementation of the third aspect, the magnetic random access memory is used as the last level cache. In this way, data that needs to be frequently read and written can be stored in the first storage area, thereby saving costs while ensuring the read and write speed.

[0027] In a fourth aspect, the present application also provides a method for preparing a magnetic random access memory, which includes: providing a substrate; forming a stacked structure on the substrate, the stacked structure including a reference layer, a barrier layer and a free layer stacked in sequence; forming a mask layer on the stacked structure, the mask layer covering a first region of the stacked structure and exposing a second region of the stacked structure; oxidizing a portion of the free layer located in the second region based on the mask layer; etching the stacked structure after removing the mask layer so that the reference layer forms a first reference layer and a second reference layer, the barrier layer forms a first barrier layer and a second barrier layer, and the free layer forms a first free layer and a second free layer; wherein the second free layer includes a first part and a second part, the first part is farther away from the second barrier layer than the second part, and the concentration of oxygen ions in the first part is greater than the concentration of oxygen ions in the second part, and greater than the concentration of oxygen ions in the first free layer.

[0028] Therefore, when preparing the magnetic random access memory, the difference between the first storage unit and the second storage unit is only the oxidation degree of the first free layer and the second free layer. Therefore, when preparing the first free layer and the second free layer, a film layer can be deposited, and a mask layer is used to cover the first area where the first free layer is located in the film layer, and the second area where the second free layer is located is exposed. The second area is oxidized and then an etching process is performed to form the first free layer and the second free layer. In other words, two types of storage units can be formed by adding only one photolithography step and an oxidation step, which simplifies the preparation process.

[0029] In a fifth aspect, the present application also provides an electronic device comprising a printed circuit board and a magnetic random access memory as described above, wherein the magnetic random access memory is connected to the printed circuit board; or comprising a printed circuit board and a chip package as described above, wherein the chip package is connected to the printed circuit board.

[0030] The electronic device provided in this embodiment improves the performance of the device and reduces the cost of the device by adopting the magnetic random access memory in the first aspect and the chip package in the second aspect or the third aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 A schematic diagram of an electronic device provided in an embodiment of the present application;

[0032] Figure 2 A schematic diagram of a storage array of a magnetic random access memory provided in an embodiment of the present application;

[0033] Figure 3 A schematic diagram of the structure of a storage unit provided in an embodiment of the present application;

[0034] Figure 4 A schematic diagram of the structure of a magnetic random access memory provided in an embodiment of the present application;

[0035] Figure 5 A schematic top view of a magnetic random access memory provided by an embodiment of the present application;

[0036] Figure 6 A schematic diagram of a chip package provided by an embodiment of the present application;

[0037] Figure 7 A schematic top view of the main memory provided in an embodiment of the present application;

[0038] Figure 8 A flow chart of a method for preparing a magnetic random access memory provided in an embodiment of the present application;

[0039] Fig. 9 A partial enlarged view of a substrate in the preparation method provided in an embodiment of the present application;

[0040] Fig.10 A schematic diagram of a stacked structure provided on a substrate in a preparation method according to an embodiment of the present application;

[0041] Fig.11 A schematic diagram of a manufacturing method provided in an embodiment of the present application in which a mask layer covers a portion of a stacked structure;

[0042] Fig.12 A schematic diagram of the preparation method provided in an embodiment of the present application after oxidation of a portion of the free layer;

[0043] Fig.13 A schematic diagram of forming a metal hard mask on a stacked structure according to the preparation method provided in an embodiment of the present application;

[0044] Fig.14 A schematic diagram of etching a stacked structure to form a magnetic tunnel junction according to the preparation method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0045] Unless otherwise defined, the technical terms or scientific terms used in this application should be understood by those skilled in the art in the ordinary sense. The terms "first", "second", "third" and similar words used in the specification and claims of this application do not indicate any order, quantity or importance, but are only used to distinguish different components. Thus, the features defined as "first", "second", and "third" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise stated, the meaning of "multiple" is two or more.

[0046] The directional terms such as "left", "right", "up" and "down" are defined relative to the orientation of the device schematically placed in the drawings. It should be understood that these directional terms are relative concepts. They are used for relative description and clarification, and they may change accordingly according to the change of the orientation of the chip or semiconductor packaging structure.

[0047] An electronic device provided in an embodiment of the present application. In some implementations, Figure 1 As shown, the electronic device may be a terminal device 10, such as a personal computer, a mobile phone, a tablet computer, a wearable device, etc. The terminal device 10 includes a printed circuit board (PCB) 11, on which a chip package 12 is arranged, that is, the chip package 12 is connected to the printed circuit board 11. In other embodiments, the electronic device may be a microcontroller unit (MCU) or an application specific integrated circuit (ASIC), the microcontroller unit or the application specific integrated circuit includes a printed circuit board, on which a magnetic random access memory is arranged, that is, the magnetic random access memory is connected to the printed circuit board. The magnetic random access memory specifically refers to a spin transfer torque magnetic random access memory (hereinafter referred to as magnetic random access memory).

[0048] The present application also provides a chip package. Figure 1 The chip package 12 can be used in high-performance computing. The chip package 12 can be a system on chip (SoC). The system on chip can be used to process data, such as processing application data, image data, and caching temporary data. The system on chip includes a processing unit 12a for processing data and a first memory 12b for caching high-speed data. The processing unit 12a and the first memory 12b are stacked and packaged.

[0049] The processing unit 12a may be a central processing unit (CPU) for parsing and executing program instructions, a graphics processing unit (GPU) for processing image data, a neural processing unit (NPU) for neural network calculations, a video processing unit (VPU) for video data processing, or other processors or combinations thereof. For example, the processing unit 12a is a CPU; another example is that the processing unit 12a is a combination of a CPU and a GPU, and the CPU and the GPU share the first memory 12b.

[0050] The first memory 12 b may be a spin transfer torque magnetic random access memory. In this case, the first memory 12 b may be used as a last level cache (LLC) of the system on chip.

[0051] In some embodiments, the system on chip may further include a second memory 12c, the processing unit 12a, the first memory 12b and the second memory 12c are stacked and packaged, and the first memory 12b is arranged between the processing unit 12a and the second memory 12c. The second memory 12c is at least connected to the first memory 12b, so as to realize data interaction with the first memory 12b. The second memory 12c may be a dynamic random access memory (DRAM). The second memory 12c may be used to store volatile data, such as temporary data generated by the system on chip. The storage capacity of the second memory 12c is generally greater than that of the first memory 12b. The second memory 12c may be used as the main memory of the system on chip.

[0052] In addition, the present application also provides a magnetic random access memory, which can be used as the aforementioned first memory 12b, and can also be used in a micro control unit or an application specific integrated circuit. When used in a micro control unit or an application specific integrated circuit, a part of the magnetic random access memory can be used as a cache, and another part can be used to store code.

[0053] Figure 2 Shown is a schematic diagram of a storage array of a magnetic random access memory provided in an embodiment of the present application.

[0054] The magnetic random access memory 13 may include one or more memory arrays, each memory array may include a plurality of memory cells 130 , and each memory cell 130 includes a transistor T and a magnetic tunnel junction (MTJ) element 131 connected to the transistor T.

[0055] The transistor T can be a thin film transistor (TFT) or a MOS (Metal Oxide Semiconductor) or other types of transistors. The transistor T includes a source electrode, a drain electrode, an active layer, a gate barrier layer and a gate electrode, wherein the source electrode and the drain electrode are in contact with the active layer, and the gate barrier layer is disposed between the gate electrode and the active layer.

[0056] The structure of the magnetic random access memory 13 also includes a plurality of word lines (Word Line, WL) arranged in parallel and a plurality of bit lines (Bit Line, BL) arranged in parallel, and the word lines WL and the bit lines BL intersect each other, for example, the word lines WL and the bit lines BL are perpendicular to each other. In some embodiments, the magnetic random access memory 13 also includes a plurality of data lines arranged in parallel, and the data lines can be parallel to the bit lines BL. Among them, the gate of the transistor T is connected to the word line WL, and the source or drain of the transistor T is connected to the data line. Here, the source of the transistor T can be connected to the data line, in which case the data line can also be called a source line (Source Line, SL), or the drain of the transistor T can be connected to the data line. Figure 2 The connection between the source of the transistor T and the source line is taken as an example for illustration.

[0057] In some embodiments, the word line WL is further connected to a word line control circuit, and a high level signal or a low level signal is provided to the word line WL through the word line control circuit to turn on or off the transistor T. When the transistor T is an N-type transistor, the high level signal controls the transistor T to be turned on, and the low level signal controls the transistor T to be turned off. When the transistor T is a P-type transistor, the low level signal controls the transistor T to be turned on, and the high level signal controls the transistor T to be turned off.

[0058] In some implementations, the data line is grounded.

[0059] The MTJ element 131 is disposed on a current transmission path between a source or a drain of the transistor T and the bit line BL.

[0060] like Figure 3 , which is a schematic diagram of the structure of a memory cell 130. The memory cell is formed on a substrate 132. A transistor T is formed on the substrate 132. An MTJ element 131 is formed on a side of the transistor T away from the substrate 132. The MTJ element 131 includes a magnetic tunnel junction MTJ, wherein the magnetic tunnel junction MTJ includes a reference layer 1311, a barrier layer 1312, and a free layer 1313 stacked in sequence; the magnetization direction of the reference layer 1311 (also referred to as the magnetic moment direction, Figure 3 The direction indicated by the arrow in the middle is parallel to the surface of the substrate 132, and the magnetization direction of the reference layer 1311 is fixed.

[0061] It is easy to understand that the MTJ element 131 also includes a first electrode and a second electrode (not shown in the figure), and the stacked structure formed by the reference layer 1311, the blocking layer 1312 and the free layer 1313 is arranged between the first electrode and the second electrode. The first electrode is located on the side of the free layer 1313 away from the reference layer 1311, and the second electrode is located on the side of the reference layer 1311 away from the free layer 1313. The MTJ element 131 is connected to the bit line BL through the first electrode and to the drain or source of the transistor T through the second electrode; or, the MTJ element 131 is connected to the drain or source of the transistor T through the first electrode and to the bit line BL through the second electrode. The following description is based on the connection of the MTJ element 131 to the bit line BL through the first electrode and to the drain or source of the transistor T through the second electrode.

[0062] To facilitate the formation of the reference layer 1311 , in some embodiments, the MTJ element 131 may further include a seed layer disposed between the second electrode and the reference layer 1311 , so that the reference layer 1311 is formed on the seed layer.

[0063] The reference layer 1311 and the free layer 1313 are magnetic layers. By way of example, the materials of the reference layer 1311 and the free layer 1313 include one or more of a cobalt-iron-boron (CoFeB) alloy, a cobalt-iron (CoFe) alloy, or a nickel-iron-cobalt (NiFeCo) alloy.

[0064] The barrier layer 1312 is a non-magnetic layer. For example, the material of the barrier layer 1312 includes one or more of magnesium oxide (MgO) or aluminum oxide (Al 2 O 3 ).

[0065] Based on the structure of the magnetic random access memory 13 described above, the working process of the magnetic random access memory 13 is introduced below by taking a storage unit 130 as an example.

[0066] When the memory cell 130 is written, the transistor T is in the on state. When the current flows from the free layer 1313 to the reference layer 1311, that is, the spin electrons flow from the reference layer 1311 to the free layer 1313, when the spin electrons pass through the reference layer 1311, the electrons in the current are spin polarized along the magnetization direction of the reference layer 1311, and the spin magnetic moment of the electrons is parallel to the magnetization direction of the reference layer 1311. When the electrons pass through the barrier layer 1312 and reach the free layer 1313, the spin electrons will spin the moment ( The free layer 1313 is also called spin angular momentum, or STT, and the magnetization intensity of the free layer 1313 is small due to the spin torque effect. Therefore, the magnetization direction of the free layer 1313 can change freely according to the polarization direction of the spin electrons in the spin current, and finally the magnetization direction of the free layer 1313 is parallel to the magnetization direction of the reference layer 1311, that is, the magnetization direction of the free layer 1313 is the same as that of the reference layer 1311, which can represent the written information "0".

[0067] When the current flows from the reference layer 1311 to the free layer 1313, that is, when the spin electrons flow from the free layer 1313 to the reference layer 1311, the spin electrons exchange-couple with the magnetic moment in the reference layer 1311, so that the electrons with spins parallel to the magnetization direction of the reference layer 1311 pass through, while the electrons with spins antiparallel to the magnetization direction of the reference layer 1311 are reflected, and the reflected electrons pass through the blocking layer 1312 to reach the free layer 1313, and exchange-couple with the magnetic moment of the free layer 1313, so that the magnetization direction of the free layer 1313 rotates in the opposite direction of the magnetization direction of the reference layer 1311, and finally the magnetization direction of the free layer 1313 is antiparallel to the magnetization direction of the reference layer 1311, that is, the magnetization direction of the free layer 1313 is opposite to the magnetization direction of the reference layer 1311, which can represent that the written information is "1". Here, the current direction can be controlled by the voltage provided on the bit line BL and the source line SL. When the voltage provided by the bit line BL is greater than the voltage provided by the source line SL, the current flows from the free layer 1313 to the reference layer 1311; when the voltage provided by the bit line BL is less than the voltage provided by the source line SL, the current flows from the reference layer 1311 to the free layer 1313.

[0068] When the memory cell 130 is read, a constant small current flows from the bit line BL through the MTJ to the drain of the turned-on transistor T, and a potential difference is generated at both ends of the MTJ. According to the magnitude of the potential difference, the resistance of the MTJ can be determined, that is, the relative orientation relationship between the magnetization directions of the free layer 1313 and the reference layer 1311 can be obtained, and then it can be determined whether the information stored in the memory cell 130 is "0" or "1". Specifically, when the MTJ presents low resistance, the magnetization direction of the free layer 1313 is parallel to the magnetization direction of the reference layer 1311, and the information stored in the memory cell 130 is "0"; when the MTJ presents high resistance, the magnetization direction of the free layer 1313 is antiparallel to the magnetization direction of the reference layer 1311, and the information stored in the memory cell 130 is "1".

[0069] It should be understood that when the magnetic random access memory 13 stores and reads information, the word line control circuit operates to provide a selection signal to the word line to turn on the transistors T in the multiple rows of storage cells 130 row by row, so that information can be written or read row by row.

[0070] Based on the working principle of the above-mentioned storage unit 130, the magnetic random access memory 13 provided in the embodiment of the present application can also be called a spin transfer torque magnetic random access memory.

[0071] like Figure 4 , which is a schematic diagram of the structure of a magnetic random access memory 13 provided in an embodiment of the present application. The storage unit 130 of the magnetic random access memory 13 at least includes the transistor T and the MTJ element 131 as described above. It should be understood that in some embodiments, the magnetic random access memory 13 may also include a substrate 132, and the transistor T, the MTJ element 131 and other patterns are all arranged on the substrate 132. Figure 4 Only the MTJ element 131 and the substrate 132 are illustrated.

[0072] More specifically, the memory cell 130 includes a first memory cell 130a and a second memory cell 130b, wherein the MTJ element 131a of the first memory cell 130a includes a first reference layer 1311a, a first barrier layer 1312a and a first free layer 1313a; the MTJ element 131b of the second memory cell 130b includes a second reference layer 1311b, a second barrier layer 1312b and a second free layer 1313b, and the second free layer 1313b includes a first portion 121 and a second portion 122, the first portion 121 is farther away from the second barrier layer 1312b than the second portion 122, the concentration of oxygen ions in the first portion 121 is greater than the concentration of oxygen ions in the second portion 122, and the concentration of oxygen ions in the first portion 121 is also greater than the concentration of oxygen ions in the first free layer 1313a.

[0073] In some embodiments, the second free layer 1313b is oxidized to form a first portion 121 and a second portion 122. Due to the limited degree of oxidation, the thickness of the first portion 121 is small, and the thickness of the first portion 121 may be several angstroms. For example

[0074] The different oxygen ion concentrations of the first part 121 and the second part 122 in the second free layer 1313b will increase the perpendicular magnetic anisotropy of the interface of the second free layer 1313b, that is, the magnetization direction of the second free layer 1313b is more difficult to change, and the difficulty of changing the magnetization direction of the second free layer 1313b is positively correlated with the coercive force of the second free layer 1313b, that is, the greater the coercive force of the second free layer 1313b, the more difficult it is to change the magnetization direction of the second free layer 1313b. Therefore, when the magnetization direction of the second free layer 1313b is to be changed, a larger current is required, that is, the speed of reading and writing data is slower. On the other hand, since it is more difficult to change the magnetization direction of the second free layer 1313b than the first free layer 1313a, the second storage unit 130b has a higher data retention than the first storage unit 130a.

[0075] The ease of changing the magnetization direction of the free layer directly affects the ease of writing data to the storage unit 130, as well as the ability to retain data after writing data. In this embodiment, because the oxygen ion concentration of the first part 121 of the second free layer 1313b in the second storage unit 130b is greater than the oxygen ion concentration of the second part 122, the interface perpendicular magnetic anisotropy of the second free layer 1313b is increased, making the magnetization direction of the second free layer 1313b more difficult to change than the first free layer 1313a, that is, the ability of the second storage unit 130b to retain data after writing data is stronger than that of the first storage unit 130a. From the perspective of writing data, since the magnetization direction of the first free layer 1313a is easier to change than the second free layer 1313b, it is easier to write data to the first storage unit 130a, or the speed of writing data to the first storage unit 130a is faster, that is, the second storage unit 130b has a faster read and write speed than the first storage unit 130a.

[0076] As can be seen from the above description, the material of the free layer 1313 includes one or more of cobalt iron boron (CoFeB) alloy, cobalt iron (CoFe) alloy or nickel iron cobalt (NiFeCo) alloy. Since the first free layer 1313a is not oxidized, the oxygen ion concentration in the first free layer 1313a is zero.

[0077] In some embodiments, the first free layer 1313a may be oxidized during the preparation of the magnetic random access memory 13. For example, after the first free layer 1313a is formed on the substrate 132, the first free layer 1313a may be exposed to an oxygen environment during the transmission process. Therefore, oxygen ions may also exist in the first free layer 1313a.

[0078] It should be understood that in some embodiments, in order to ensure the performance difference between the first storage unit 130a and the second storage unit 130b, the concentration of oxygen ions in the first free layer 1313a should be lower than the concentration of oxygen ions in the first part 121 of the second free layer 1313b. For example, the concentration of oxygen ions in the first free layer 1313a is less than or equal to one third of the concentration of oxygen ions in the first part 121 of the second free layer 1313b, for example, it can be one fifth or one tenth.

[0079] In some embodiments, in order to improve production efficiency, when forming a free layer film, a free layer film may be deposited first, and then the free layer film may be formed into a first free layer 1313a and a second free layer 1313b through subsequent processes. Since the second portion 122 of the second free layer 1313b and the first free layer 1313a are not oxidized, the concentration of oxygen ions in the second portion 122 of the second free layer 1313b is equal to the concentration of oxygen ions in the first free layer 1313a.

[0080] Therefore, in the embodiment of the present application, by changing the coercivity of the free layer of a part of the storage units in the magnetic random access memory 13, the magnetic random access memory 13 has both storage units with fast read and write capabilities and storage units with high data retention. Thus, the magnetic random access memory 13 can be used as the last level cache of the processing unit, wherein the storage unit with fast read and write capabilities can be used to store data that needs to be updated frequently, and the storage unit with high data retention can be used to store data with low update frequency, and this part of the data is not sensitive to the write speed. In addition, the magnetic random access memory 13 can also be used in a microcontroller unit or a dedicated integrated circuit, and the storage unit with fast read and write capabilities of the magnetic random access memory 13 can be used to replace SRAM, and the storage unit with high data retention can be used to replace embedded flash memory eFlash (embedded Flash). By replacing the use of the magnetic random access memory 13, the manufacturing cost of the final chip is greatly reduced, and the power consumption of the system is also reduced.

[0081] like Figure 5 , which is a top view schematic diagram of the magnetic random access memory 13 provided in an embodiment of the present application.

[0082] The magnetic random access memory 13 is divided into a plurality of regions in a plane parallel to the substrate 132, each region is provided with a storage array, and each region is also provided with an address decoder and a read / write circuit corresponding to the storage array provided in the region. Only one storage array may be provided in one region, or multiple storage arrays may be provided in one region, and the multiple storage arrays are connected through a functional circuit, and when data is read, a specific storage array may be selected through the functional circuit for operation. Exemplarily, the functional circuit may be a multiplexer (MUX).

[0083] It should be understood that the magnetic random access memory 13 is also provided with a first signal line 135, and the first signal line 135 interconnects the various regions of the magnetic random access memory 13. When the magnetic random access memory 13 is read and written, the storage cells of the memory array in each region can be read and written through the first signal line 135. The first signal line can be a ring bus.

[0084] In some embodiments, the magnetic random access memory 13 includes a first storage area 13a and a second storage area 13b, wherein the storage array in the first storage area 13a is composed of the first storage unit 130a, and the storage array in the second storage area 13b is composed of the second storage unit 130b. In other words, the first storage unit 130a is arranged in the first storage area 13a, and the second storage unit 130b is arranged in the second storage area 13b. Therefore, the first storage area 13a of the magnetic random access memory 13 has the characteristics of fast reading and writing, and the second storage area 13b has the characteristics of high retention.

[0085] In some embodiments, the number of second storage areas 13b may be multiple, and the multiple second storage areas 13b may be connected to the first signal line 135, that is, the second storage areas 13b are interconnected through the first signal line 135. The first signal line 135 may be formed on the surface of one side of the substrate 132 having the transistor T through a metal interconnection process.

[0086] The magnetic random access memory 13 further includes a first silicon through via 133, which is arranged near the first storage area 13a and penetrates the substrate 132 in a direction perpendicular to the substrate 132. A bus 134 is penetrated in the first silicon through via 133, and the bus 134 includes an address line, a data line, and a control line. The position of the first silicon through via 133 near the first storage area 13a means that the distance from the first silicon through via 133 to the first storage area 13a is less than or equal to the distance to the second storage area 13b. The first storage area 13a and the first signal line 135 are both connected to the bus 134, that is, the first storage area 13a is connected to the bus 134, and the bus 134 is connected to the first signal line 135, so the first storage area 13a and the second storage area 13b are connected through the first signal line 135.

[0087] In some embodiments, the magnetic random access memory 13 is packaged together with the processing unit, and the processing unit can realize the read and write operations of the magnetic random access memory 13 by connecting to the bus 134. And because the first silicon through hole 133 is arranged close to the first storage area 13a, the connection distance between the processing unit and the first storage area 13a is less than the connection distance with the second storage area 13b, therefore, the time consumed by the processing unit when accessing the first storage area 13a due to the connection distance is less than the second storage area 13b. That is, when the read and write speed of the first storage area 13a is the same as the read and write speed of the second storage area 13b, the speed of the processing unit accessing the first storage area 13a is greater than the speed of accessing the second storage area 13b. That is to say, when the first storage area 13a has a faster read and write speed than the second storage area 13b, it is easier to give play to the fast read and write characteristics of the first storage area 13a.

[0088] In some embodiments, the first storage area 13a is directly connected to the bus 134 in the first through silicon via 133, that is, the first storage unit 130a is directly connected to the bus 134 without passing through the first signal line. Thus, the connection distance is further reduced and the read and write speed is improved.

[0089] In some embodiments, the number of first TSVs 133 is proportional to the data storage capacity of the memory array.

[0090] The number of the first TSVs 133 can be multiple, and the multiple first TSVs 133 surround the first storage area 13a. Since the first TSVs 133 are arranged close to the first storage area 13a, that is, the distance from any first TSV 133 to the first storage area 13a is less than or equal to the distance to the second storage area 13b, the fast reading and writing characteristics of the first storage area 13a can be brought into play as much as possible. At the same time, since the multiple first TSVs 133 are arranged around the first storage area 13a, it is possible to avoid centrally arranging the first TSVs 133, which occupies a large area, thereby reducing the restrictions of the first TSVs 133 on the layout of each storage area in the magnetic random access memory 13, and is also conducive to the connection between the bus 134 and other components during stacking packaging.

[0091] Please continue to see Figure 5In some embodiments, the first storage area 13a is located in the center of the magnetic random access memory 13, that is, the geometric center of the magnetic random access memory 13 is located in the first storage area 13a. And the second storage area 13b is arranged around the first storage area 13a, surrounding the first storage area 13a. Since the plurality of first through silicon vias 133 are arranged at a position close to the first storage area 13a, the plurality of first through silicon vias 133 are located between the first storage area 13a and the second storage area 13b. In this way, the connection distance from the second storage area 13b to the bus 134 in the first through silicon via 133 can be optimized as a whole, even if the distance from all the second storage areas 13b to the first through silicon vias 133 is not too large, and the access speed to each second storage area 13b is balanced.

[0092] like Figure 6 , which is a schematic diagram of the structure of a chip package 12 provided in an embodiment of the present application, wherein the first memory 12b adopts any of the magnetic random access memories 13 described above, and the second memory 12c serves as the main memory 14. That is, the chip package 12 includes the magnetic random access memory 13, the main memory 14 and the processing unit 12a, the magnetic random access memory 13, the main memory 14 and the processing unit 12a are stacked, and the magnetic random access memory 13 is arranged between the processing unit 12a and the main memory 14. Figure 6 In the figure, the processing unit 12a is illustrated as a central processing unit (CPU) and the main memory is illustrated as a DRAM.

[0093] In some embodiments, the side with active layer in the processing unit 12a and the magnetic random access memory 13 is both facing the main memory 14, that is, the side of the substrate of the processing unit 12a without forming a device is away from the magnetic random access memory 13, and the side of the substrate of the magnetic random access memory 13 without forming a device is away from the main memory 14. This arrangement can avoid the active layer of the processing unit 12a facing the active layer of the magnetic random access memory 13, that is, avoid the heat generated by the active layer during operation from being difficult to dissipate.

[0094] In some embodiments, the magnetic random access memory 13 includes a first storage unit 130a and a second storage unit 130b, and the first storage unit 130a and the second storage unit 130b are in the same plane perpendicular to the stacking direction of the chip package 12. The first storage unit 130a includes a first reference layer 1311a, a first barrier layer 1312a, and a first free layer 1313a stacked in sequence. The second storage unit 130b includes a second reference layer 1311b, a second barrier layer 1312b, and a second free layer 1313b stacked in sequence. Among them, the ease of changing the magnetization direction of the first free layer 1313a is less than that of the second free layer 1313b, that is, the coercive force of the first free layer 1313a is less than that of the second free layer 1313b. As a result, the first storage unit 130a can retain the stored data for a longer time, that is, it has a high retention force; the second storage unit 130b can quickly access data, that is, it has high-speed reading and writing capabilities.

[0095] In order to differentiate the coercive force of the first free layer 1313a and the second free layer 1313b, in some embodiments, the second free layer includes a first portion 121 and a second portion 122, the first portion 121 is farther away from the second barrier layer 1312b than the second portion 122, and the concentration of oxygen ions in the first portion 121 is greater than the concentration of oxygen ions in the second portion 122, and is also greater than the concentration of oxygen ions in the first free layer 1313a. To change the concentration of oxygen ions in the first portion 121, an oxidation process can be used to oxidize the side of the second free layer 1313b away from the second barrier layer 1312b, and the oxidized portion is the first portion 121. In other embodiments, the concentration of boron ions in the second free layer 1313b can be increased, for example, ion implantation can be used to increase the concentration of boron ions in the second free layer 1313b. In still other embodiments, an oxide layer and a magnetic layer can be stacked in sequence on the side of the second free layer 1313b away from the second barrier layer 1312b, and the oxide layer can be made of the same material as the free layer and have a thickness less than the free layer. In addition, an insertion layer may be further provided in the second free layer 1313 b to change the coercive force of the magnetic layer.

[0096] In some embodiments, the first storage unit 130a of the magnetic random access memory 13 is arranged in the first storage area 13a, and the second storage unit 130b is arranged in the second storage area 13b. That is to say, the first storage area 13a is a fast area capable of quickly reading and writing data, and the second storage area 13b is a high retention area capable of keeping data for a long time. The magnetic random access memory 13 also includes a first silicon through hole 133 and a bus 134 penetrating the first silicon through hole 133. The first silicon through hole 133 is arranged near the first storage area 13a, and the distance between the first silicon through hole 133 and the first storage area 13a is less than the distance between the first silicon through hole 133 and the second storage area 13b. The first silicon through hole 133 simultaneously penetrates the surface of the magnetic random access memory 13 on the side close to the processor 15 and the surface on the side close to the main memory 14. The first silicon through hole 133 can be along the stacking direction of the main memory 14, the magnetic random access memory 13 and the processing unit 12a, or it can be at a certain angle to the stacking direction.

[0097] The bus 134 is arranged through the first silicon through-via 133 and connects the processing unit 12a with the magnetic random access memory 13, so that the processing unit 12a can perform read and write operations on the magnetic random access memory 13. In this way, the length of the bus 134 between the processing unit 12a and the first storage area 13a can be reduced, that is, the read and write speed loss due to the distance can be reduced, and the fast read and write characteristics of the first storage area 13a can be fully utilized.

[0098] In some embodiments, the processing unit 12a includes multiple processors, which may be formed on the same substrate or packaged on a substrate in the form of a package, wherein one of the processors is a first processor, for example Figure 6 CPU5 in. Taking the plane perpendicular to the stacking direction of the processing unit 12a, the magnetic random access memory 13 and the main memory as the reference plane, the projection of the geometric center of the first processor and the geometric center of the first storage area 13a on the reference plane coincides. In this case, the first processor is connected to the first storage area 13a via the bus 134. Since the bus 134 is arranged in the first silicon through-hole via 133 that runs through the magnetic random access memory 13, when the projection of the geometric center of the first processor and the geometric center of the first storage area 13a on the reference plane coincides, the length of the bus 134 between the first processor and the first storage area 13a can be reduced, thereby improving the reading and writing speed of the processing unit 12a to the first storage area 13a.

[0099] In some embodiments, the multiple processors of the processing unit 12a are connected to the bus 134, that is, each processor can be connected to the magnetic random access memory 13 through the bus 134, and the data interaction between the processors can be realized by reading the magnetic random access memory 13. In this embodiment, the magnetic random access memory 13 can be used as the last level cache of the processing unit 12a. Among them, part of the data can be stored in the second storage area 13b, mainly for reading part of the data, so this part of the data is not sensitive to the write speed; at the same time, another part of the data can be stored in the first storage area 13a, this part of the data needs to be frequently updated when used, so this part of the data does not need a high data retention.

[0100] When the processing unit 12a performs a read operation on the magnetic random access memory 13, in order to improve the read speed, a plurality of first silicon through vias 133 may be provided, that is, the bit width of the bus 134 is increased. The plurality of first silicon through vias 133 surround the first storage area 13a, and because the first silicon through vias 133 are provided close to the first storage area 13a, the distance from the first silicon through vias 133 to the first storage area 13a can be made less than or equal to the distance to any second storage area 13b, and such a setting can also give play to the fast reading and writing characteristics of the first storage area 13a; at the same time, the plurality of first silicon through vias 133 surrounding the first storage area 13a can avoid the plurality of first silicon through vias 133 being centrally provided and occupying a larger area, thereby facilitating the reduction of the restrictions on the plane layout of the first storage area 13a and the second storage area 13b, and also facilitating the stacking package with the processing unit 12a.

[0101] In some embodiments, the first storage area 13a is located in the center of the magnetic random access memory 13, that is, the geometric center of the magnetic random access memory 13 is located in the first storage area 13a. In addition, the second storage area 13b is arranged around the first storage area 13a and surrounds the first storage area 13a. Since the plurality of first through silicon vias 133 are arranged at a position close to the first storage area 13a, the plurality of first through silicon vias 133 are located between the first storage area 13a and the second storage area 13b. In this way, the connection distances from all the second storage areas 13b to the bus 134 in the first through silicon vias 133 can be optimized as a whole, and the access speeds to each second storage area 13b can be balanced.

[0102] In some embodiments, the active layers of the main memory 14 and the magnetic random access memory 13 are both located on the side away from the processing unit 12a, that is, the side of the substrate of the main memory 14 where no device is formed is away from the processing unit 12a, and the side of the substrate of the magnetic random access memory 13 where no device is formed is away from the processing unit 12a. This arrangement can prevent the active layer of the main memory from being opposite to the active layer of the magnetic random access memory 13, thereby preventing the heat generated by the active layer from being difficult to dissipate.

[0103] In some embodiments, Figure 7 As shown, the main memory 14 is provided with a second silicon via 143, and the second silicon via 143 penetrates the main memory in the stacking direction of the processing unit 12a, the magnetic random access memory 13 and the main memory 14, and the second silicon via 143 is connected to the first silicon via 133, and the direction of the second silicon via 143 can be the same as the direction of the first silicon via 133. The bus 134 is simultaneously penetrated by the first silicon via 133 and the second silicon via 143, and the bus 134 is connected to the main memory 14. It is easy to understand that the number of the second silicon vias 143 on the main memory 14 is the same as the number of the first silicon vias 133 on the magnetic random access memory 13, and can be multiple.

[0104] In some embodiments, the main memory 14 also has multiple storage areas, such as Figure 7 The DRAM1-DRAM9 in the main memory 14 can correspond to the storage areas in the magnetic random access memory 13 one by one, and the projections of the corresponding storage areas on the reference surface overlap, so that the main memory 14 and the magnetic random access memory 13 are stacked and packaged. The multiple storage areas of the main memory 14 are interconnected through the second signal line 145, and the second signal line 145 is connected to the bus 134, so that the processing unit 12a can access the main memory 14 through the bus 134.

[0105] In addition, the present application also provides a method for preparing a magnetic random access memory, such as Figure 8 As shown, the preparation method comprises the following steps:

[0106] S10, providing a substrate;

[0107] Fig. 9 1 is a partial enlarged view of the substrate. The substrate 132 may be a silicon substrate, or other types of materials, such as germanium. A transistor T is formed on the substrate 132. The transistor T may be a thin film transistor, or other types of transistors such as a MOS tube. The transistor T includes a source, a drain, an active layer, a gate barrier layer, and a gate. The source and the drain are in contact with the active layer, and the gate barrier layer is disposed between the gate and the active layer.

[0108] S20, forming a stacked structure on a substrate, the stacked structure comprising a reference layer, a barrier layer, and a free layer stacked in sequence;

[0109] like Fig.10As shown, a stacked structure 151 is formed on a substrate 132, and a deposition process such as chemical vapor deposition can be used to form the stacked structure 151. The stacked structure 151 includes a reference layer 1511, a barrier layer 1512, and a free layer 1513 that are stacked in sequence; wherein the reference layer 1511 and the free layer 1513 are magnetic layers, and by way of example, the materials of the reference layer 1311 and the free layer 1313 include one or more of a cobalt iron boron (CoFeB) alloy, a cobalt iron (CoFe) alloy, or a nickel iron cobalt (NiFeCo) alloy; the barrier layer 1312 is a non-magnetic layer, and by way of example, the material of the barrier layer 1312 includes one or more of magnesium oxide (MgO) or aluminum oxide (Al2O3).

[0110] Forming the stacked structure 151 on the substrate 132 does not limit the stacked structure 151 to be directly formed on the substrate 132, it only indicates the orientation, for example, since the lattice constants of the reference layer 1511 and the substrate 132 are not compatible, it is necessary to set a cache layer between the reference layer 1511 and the substrate 132. Similarly, the reference layer 1511, the barrier layer 1512 and the free layer 1513 formed by stacking in sequence also only indicate that the barrier layer 1512 is located between the reference layer 1511 and the free layer 1513, and does not limit the barrier layer 1512 to directly contact the reference layer 1511 and the free layer 1513. For example, in order to change the performance of the finally formed magnetic tunnel junction MTJ, other film layers can be set between the film layers.

[0111] S30, forming a mask layer on the stacked structure, wherein the mask layer covers a first region of the stacked structure and exposes a second region of the stacked structure;

[0112] like Fig.11 As shown, a mask layer 152 is formed on the stacked structure 151, and the mask layer 152 covers a portion of the free layer 1513 in the stacked structure 151, that is, the mask layer 152 covers a first region of the stacked structure 151 and exposes a second region of the stacked structure 151; the first region is a region where the first storage unit 130a needs to be formed, and the second region is a region where the second storage unit 130b needs to be formed. The mask layer 152 can be a photoresist, and this step can adopt a photolithography process, that is, firstly coating the entire surface of the stacked structure 151 with the photoresist, and then removing the photoresist above the second region by exposure and development.

[0113] S40, oxidizing the portion of the free layer located in the second region based on the mask layer;

[0114] like Fig.12As shown, after the mask layer 152 exposes the second region of the stacked structure 151, the free layer 1513 of the second region is oxidized. In some embodiments, oxygen or active oxygen species may be introduced into the substrate 132. Since the first region is covered by the mask layer 152 and the second region is not covered by the mask layer 152, only the second region is oxidized.

[0115] After the surface of the free layer 1513 is oxidized, due to the limited degree of oxidation, the free layer 1513 is actually divided into two layers, namely, the first layer 161 containing oxygen ions and the second layer 162 not containing oxygen ions, that is, the concentration of oxygen ions in the first layer 161 is greater than the concentration of oxygen ions in the second layer 162. The thickness of the first layer 161 is relatively small, and the thickness of the first portion 121 can be several angstroms. For example

[0116] S50, after removing the mask layer, etching the stacked structure, so that the reference layer forms a first reference layer and a second reference layer, the barrier layer forms a first barrier layer and a second barrier layer, and the free layer forms a first free layer and a second free layer;

[0117] After the partial area of ​​the free layer is oxidized, the mask layer 152 is removed, and the stacked structure 151 is etched by photolithography and etching processes to form magnetic tunnel junctions in the first area and the second area respectively. The magnetic tunnel junction formed in the first area covered by the mask layer 152 includes the first reference layer 1311a, the first barrier layer 1312a and the first free layer 1313a, and the magnetic tunnel junction formed in the exposed second area includes the second reference layer 1311b, the second barrier layer 1312b and the second free layer 1313b. Since the free layer 1513 in the exposed second area includes the first layer 161 and the second layer 162, the second free layer includes the first part 121 and the second part 122, the first part 121 is farther away from the second barrier layer 1312b than the second part 122, and the concentration of oxygen ions in the first part 121 is greater than the concentration of oxygen ions in the second part 122. Since the first free layer 1313a is not oxidized, the concentration of oxygen ions in the first part 121 is greater than that in the first free layer 1313a.

[0118] It is easy to understand that in order to form a memory cell, an electrode needs to be formed on the free layer. Fig.13 As shown, in some embodiments, before etching the stacked structure 151 to form a magnetic tunnel junction, a metal hard mask 172 and an oxide hard mask 171 may be deposited on the free layer 1513 after removing the mask layer 152, wherein the oxide hard mask 171 is used to form a pattern of a magnetic tunnel junction on the metal hard mask 172, thereby etching the metal hard mask 172 and the stacked structure 151. Then, a magnetic tunnel junction is formed by etching the metal hard mask 172 and the stacked structure 151. The metal hard mask 172 is formed on the magnetic tunnel junction, as shown in FIG. Fig.14 The metal hard mask 172 can be used as an electrode connecting the magnetic tunnel junction, thereby simplifying the process of forming the electrode.

[0119] After forming the magnetic tunnel junction, in order to prepare the magnetic random access memory 13, steps such as forming word lines BL are required, which will not be described in detail in this application.

[0120] The above are only specific implementations of the present application, but the protection scope of the application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A magnetic random access memory, characterized in that: include: A first storage unit includes a first reference layer, a first barrier layer and a first free layer stacked in sequence; A second storage unit includes a second reference layer, a second barrier layer, and a second free layer stacked in sequence; The second free layer includes a first portion and a second portion, the first portion is farther away from the second blocking layer than the second portion, and a concentration of oxygen ions in the first portion is greater than a concentration of oxygen ions in the second portion and greater than a concentration of oxygen ions in the first free layer.

2. The magnetic random access memory according to claim 1, wherein: A concentration of oxygen ions in the first free layer is less than or equal to one third of a concentration of oxygen ions in the first portion of the second free layer.

3. The magnetic random access memory according to claim 1 or 2, characterized in that: The concentration of oxygen ions in the first free layer is zero.

4. The magnetic random access memory according to any one of claims 1 to 3, characterized in that: The concentration of oxygen ions in the second portion of the second free layer is equal to the concentration of oxygen ions in the first free layer.

5. The magnetic random access memory according to any one of claims 1 to 4, characterized in that: The magnetic random access memory comprises a first storage area and a second storage area, wherein the first storage unit is arranged in the first storage area, and the second storage unit is arranged in the second storage area; the magnetic random access memory is further provided with a first through silicon via, and the first through silicon via is arranged close to the first storage area; The first storage unit is connected to a bus penetrating through the first through silicon via.

6. The magnetic random access memory according to claim 5, characterized in that: There are multiple first TSVs, and the multiple first TSVs surround the first storage area.

7. The magnetic random access memory according to claim 6, wherein: The first storage area is located at the center of the magnetic random access memory, the second storage area surrounds the first storage area, and a plurality of the first through silicon vias are located between the first storage area and the second storage area.

8. The magnetic random access memory according to any one of claims 5 to 7, characterized in that: The magnetic random access memory further includes a first signal line, and the second storage unit is connected to the bus via the first signal line.

9. A chip package, characterized in that: include: A processing unit, a magnetic random access memory and a main memory are stacked, wherein the magnetic random access memory is arranged between the processing unit and the main memory; The magnetic random access memory comprises: A first storage unit includes a first reference layer, a first barrier layer and a first free layer stacked in sequence; A second storage unit includes a second reference layer, a second barrier layer, and a second free layer stacked in sequence; The second free layer includes a first portion and a second portion, the first portion is farther away from the second blocking layer than the second portion, and a concentration of oxygen ions in the first portion is greater than a concentration of oxygen ions in the second portion and greater than a concentration of oxygen ions in the first free layer.

10. The chip package according to claim 9, wherein: The magnetic random access memory comprises a first storage area and a second storage area, wherein the first storage unit is arranged in the first storage area, and the second storage unit is arranged in the second storage area; a first through silicon via is arranged near the first storage area; The chip package further includes a bus penetrating through the first through silicon via, and the first storage unit is connected to the processing unit through the bus.

11. A chip package, characterized in that: include: A processing unit, a magnetic random access memory and a main memory are stacked, wherein the magnetic random access memory is arranged between the processing unit and the main memory; The magnetic random access memory comprises: A first storage unit comprises a first reference layer, a first barrier layer and a first free layer stacked in sequence; the first storage unit is arranged in a first storage area of ​​the magnetic random access memory; A second storage unit comprises a second reference layer, a second barrier layer and a second free layer stacked in sequence; the second storage unit is arranged in a second storage area of ​​the magnetic random access memory; The coercivity of the first free layer is smaller than that of the second free layer; A first through silicon via is arranged near the first storage area; the chip package also includes a bus penetrating through the first through silicon via, and the first storage unit is connected to the main memory through the bus.

12. The chip package according to claim 11, wherein: The processing unit includes a first processor, the first storage area is connected to the first processor through the bus, and the geometric center of the first processor coincides with the projection of the geometric center of the first storage area on a reference plane; the reference plane is a plane perpendicular to the stacking direction of the processing unit, the magnetic random access memory and the main memory.

13. The chip package according to claim 11, wherein: There are multiple first TSVs, and the multiple first TSVs surround the first storage area.

14. The chip package according to claim 13, wherein: The first storage area is located at the center of the magnetic random access memory, the second storage area surrounds the first storage area, and a plurality of the first through silicon vias are located between the first storage area and the second storage area.

15. The chip package according to claim 11, wherein: The main memory is provided with a second through silicon via, the second through silicon via is communicated with the first through silicon via, the bus is also penetrated through the second through silicon via, and the main memory is connected to the bus penetrated through the second through silicon via.

16. The chip package according to claim 11, wherein: The magnetic random access memory is used as a last level cache.

17. A method for preparing a magnetic random access memory, characterized in that: include: providing a substrate; forming a stacked structure on the substrate, the stacked structure comprising a reference layer, a barrier layer and a free layer stacked in sequence; forming a mask layer on the stacked structure, wherein the mask layer covers a first region of the stacked structure and exposes a second region of the stacked structure; oxidizing a portion of the free layer located in the second region based on the mask layer; After removing the mask layer, etching the stacked structure, so that the reference layer forms a first reference layer and a second reference layer, the barrier layer forms a first barrier layer and a second barrier layer, and the free layer forms a first free layer and a second free layer; The second free layer includes a first part and a second part, the first part is farther away from the second blocking layer than the second part, and the concentration of oxygen ions in the first part is greater than the concentration of oxygen ions in the second part and greater than the concentration of oxygen ions in the first free layer.

18. An electronic device, characterized in that: comprising a printed circuit board, and a magnetic random access memory according to any one of claims 1 to 8, wherein the magnetic random access memory is connected to the printed circuit board; or The invention comprises a printed circuit board, and a chip package according to any one of claims 9 to 16, wherein the chip package is connected to the printed circuit board.

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