Transistor, electronic equipment and preparation method of transistor

Abstract

The embodiment of the invention provides a transistor, electronic equipment and a preparation method of the transistor. Relates to the technical field of semiconductor devices. A transistor capable of reducing gate leakage current is provided. The transistor comprises a substrate, a channel layer, a barrier layer and a grid electrode, the channel layer is formed on the substrate, the barrier layer is formed on the channel layer and points to the direction of the channel layer from the barrier layer, and the grid electrode penetrates through at least part of the barrier layer; the channel layer comprises a first region corresponding to the position of the grid electrode and a second region located on the periphery of the first region, and the dislocation density of the first region is smaller than or equal to that of the second region. By performing damage repair on the first region below the grid electrode, the dislocation density of the region is reduced, the crystal quality of the region is improved, and the purpose of reducing the leakage current of the grid electrode is achieved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor device technology, and in particular to a transistor, an electronic device including the transistor, and a method for preparing the transistor. Background Art

[0002] With the development of communication technology, the field of radio frequency communication has put forward requirements for semiconductor devices with higher frequency, higher voltage, higher output power and efficiency.

[0003] Semiconductor devices made of compound semiconductor materials, such as gallium nitride (GaN)-based high electron mobility transistor (HEMT), are increasingly being used in high-power radio frequency devices, high-voltage switching devices and other fields due to their excellent physical properties such as wide bandgap, high electron drift rate, radiation resistance and high temperature resistance. For example, they are widely used in radar, wireless communication, navigation, satellite communication, electronic countermeasure equipment and other systems.

[0004] GaN HEMT semiconductor devices include depletion-mode devices and enhancement-mode devices. Depletion-mode GaN HEMT devices require additional negative voltage bias to realize the operation of the device. The additional negative voltage bias circuit increases the power consumption in the non-operating state, which greatly limits the application of depletion-mode devices. In contrast, enhancement-mode GaN HEMT devices with a positive threshold voltage can simplify the circuit structure, reduce costs, and improve the safety and stability of the system.

[0005] However, enhancement-mode GaN HEMT devices have large gate leakage. Large leakage current reduces the gate voltage swing range and gate control capability, affecting the transconductance of the device. For example, when GaN HEMT devices are used as RF devices, they limit the gain of the RF amplifier. Summary of the invention

[0006] The present application provides a transistor, an electronic device including the transistor, and a method for preparing the transistor, with the purpose of providing a transistor capable of reducing gate leakage current.

[0007] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0008] In one aspect, the present application provides a transistor, which may be an enhanced high electron mobility transistor (HEMT).

[0009] The transistor includes a substrate, a channel layer, a barrier layer and a gate, wherein the channel layer is formed on the substrate, the barrier layer is formed on the channel layer, and the gate penetrates at least a portion of the barrier layer in a direction from the barrier layer to the channel layer; the channel layer includes a first region corresponding to the position of the gate, and a second region located around the first region, and the dislocation density of the first region is less than or equal to the dislocation density of the second region.

[0010] When preparing the transistor provided in the present application, it is necessary to use an etching process to etch a groove in the barrier layer, and the groove is used to fill the gate. When etching the groove, a certain degree of lattice damage will be formed on the bottom area after etching (the surface area of ​​the channel layer), resulting in a large density of dislocation outcrops and a large surface roughness. The present application can reduce the dislocation density of this area through repair means, so that the dislocation density of this area is less than or equal to the dislocation density of the surrounding area, thereby improving the crystal quality of this area, thereby achieving the purpose of controlling the gate leakage current.

[0011] In one possible implementation, the dislocation density of the first region is a1×10 8 / cm 2 , the dislocation density in the second region is a2×10 9 / cm 2 , where 1≤a1<10, and 1≤a2<10.

[0012] The dislocation density in the repaired first region is significantly lower than that in the second region by one order of magnitude, which effectively improves the crystal quality of the region and reduces leakage current channels.

[0013] In one possible implementation, an epitaxial layer is disposed on the surface of the first region of the channel layer, and the gate is located on a side of the epitaxial layer away from the first region; the epitaxial layer is used to deplete the two-dimensional electron gas concentration in the heterojunction region below the gate, and the heterojunction region below the gate includes at least the first region.

[0014] In this example, an epitaxial layer is disposed between the gate and the channel layer, and the epitaxial layer can deplete the two-dimensional electron gas under the gate, so that the transistor becomes an enhancement-mode transistor.

[0015] In addition, the epitaxial layer is arranged on the surface of the first region of the channel layer. Since the present application performs a repair process on the first region, the dislocation density in the region is reduced. Thus, when the epitaxial layer is grown, it helps to reduce the extension of the dislocations in the first region in the epitaxial layer, thereby improving the crystallization quality of the epitaxial layer and reducing the occurrence of stress relaxation in the epitaxial layer.

[0016] Therefore, the transistor given in this example can not only reduce the density of dislocation outcrops and reduce the leakage current channel, but also enhance the gate voltage swing, gate control capability and reliability of the transistor under high temperature and high field conditions by improving the growth quality of the epitaxial layer.

[0017] In a possible implementation, the material of the epitaxial layer includes at least one of InGaN, AlGaN, and InAlGaN.

[0018] In one possible implementation, the epitaxial layer includes stacked In x Ga 1-x N layer and Al y Ga 1-y N layers; among them, 0.1≤x≤0.3, 0.15≤y≤0.3.

[0019] In one possible implementation, Al y Ga 1-y N layer compared to In x Ga 1-x The N layer is closer to the channel layer.

[0020] In some embodiments, the channel layer is GaN, and the epitaxial layer includes Al y Ga 1-y N and In x Ga 1-x N. Since the lattice constant relationship between AlGaN, InGaN and GaN is InGaN>GaN>AlGaN, the direction of the piezoelectric polarization induced electric field of InGaN is opposite to that of AlGaN. By limiting the composition of the AlGaN and InGaN epitaxial layers, the polarization induced electric field of the overall device structure of InGaN, AlGaN and GaN can be reduced, and the conduction band energy level at the interface between AlGaN and GaN can be increased to deplete the two-dimensional electron gas in the channel, thereby realizing an enhancement-mode device.

[0021] In one possible implementation, x Ga 1-x N layer thickness d1: 4nm≤d1≤6nm, Al y Ga 1-y The thickness of the N layer d2: 2nm≤d2≤4nm.

[0022] By limiting the thickness of the AlGaN and InGaN epitaxial layers, the polarization-induced electric field of the overall device structure of InGaN, AlGaN, and GaN can be reduced, and the conduction band energy level at the interface of AlGaN and GaN can be increased to deplete the two-dimensional electron gas in the channel, thereby realizing an enhanced device.

[0023] In a possible implementation, the epitaxial layer further includes a GaN layer, and in a direction from the channel layer to the barrier layer, the GaN layer, the Al y Ga 1-y N layer and In x Ga 1-x N layers are stacked in sequence.

[0024] In the growth of Al y Ga 1-y N layer and In x Ga 1-x A GaN layer can be grown before the N layer. The growth of the GaN layer can further reduce surface damage and reduce the scattering effect of the first region on carriers, ensuring that the carrier mobility is basically not affected.

[0025] In one possible implementation, the epitaxial layer includes In z Al w Ga 1-z-w N layers; among them, 0.01≤z≤0.2, 0.6≤w≤0.9.

[0026] In this embodiment, by defining In z Al w Ga 1-z-w The N component can reduce the polarization induced electric field of the overall device structure of InAlGaN and GaN, and increase the conduction band energy level at the interface between InAlGaN and GaN to deplete the two-dimensional electron gas in the channel, thereby realizing an enhanced device.

[0027] In one possible implementation, z Al w Ga 1-z-w The thickness of the N layer d3: 6nm≤d3≤8nm.

[0028] Through In z Al 1-z Ga 0.2 Limiting the thickness of the N epitaxial layer can reduce the polarization induced electric field of the InAlGaN and GaN overall device structure, increase the conduction band energy level at the interface between InAlGaN and GaN, deplete the two-dimensional electron gas in the channel, and thus realize an enhanced device.

[0029] In a possible implementation, the epitaxial layer further includes a GaN layer, and in a direction from the channel layer to the barrier layer, the GaN layer and the In z Al w Ga 1-z-w N layers are stacked in sequence.

[0030] The growth of the GaN layer can further reduce surface damage and reduce the scattering effect of the first region on carriers, ensuring that the carrier mobility is basically not affected.

[0031] In a possible implementation, the transistor further includes a gate dielectric layer, and the gate dielectric layer is disposed between the gate and the interface of the epitaxial layer.

[0032] In a possible implementation manner, the material of the gate dielectric layer may be selected from at least one of Al2O3, HfO2, SiO2, Si3N4, and ZrO2.

[0033] In one possible implementation, the gate interface trap state density is ρ, 5×10 11 eV -1 cm -2 ≤ρ≤5×10 13 eV -1 cm -2 .

[0034] In some process steps, the channel layer is damaged and repaired to reduce the dislocation density in the first region, and the epitaxial layer and the gate dielectric layer are grown, all of which can be performed in the same vacuum equipment. In this way, interface state problems caused by air exposure and environmental contamination can be avoided, thereby reducing the interface trap state density between the gate dielectric layer and the epitaxial layer, and reducing the threshold voltage fluctuation caused by a large number of traps.

[0035] In a possible implementation, the material of the gate includes at least one of nickel Ni, platinum Pt and gold Au, and the work function of nickel Ni is 5.15 eV, and the work function of platinum Pt is 5.65 eV.

[0036] Using high work function metal as the gate can effectively increase the work function difference Φ of the metal-semiconductor contact. B , thereby increasing the threshold voltage to achieve an enhancement-mode device.

[0037] In another aspect, the present application provides a method for manufacturing a transistor, the method comprising:

[0038] A channel layer is formed on the substrate, and a barrier layer is formed on the channel layer;

[0039] Opening a groove, wherein the groove penetrates the barrier layer so that the first region of the channel layer is exposed;

[0040] Repairing damage to the first region so that the dislocation density of the first region of the channel layer is less than or equal to the dislocation density of the second region, and the second region is located around the first region;

[0041] A gate is formed in the groove.

[0042] When preparing transistors using the method provided in the present application, when a groove is opened, for example, when the groove is dry-etched, damage will be caused to the bottom area of ​​the groove, i.e., the first area of ​​the channel layer, thereby destroying the crystal arrangement. The present application can reduce the dislocation density of the first area and improve the crystal quality of the area by repairing the damage, thereby reducing the gate leakage current channel.

[0043] In one possible implementation, damage repair is performed on the first region, including: annealing in a gas atmosphere; wherein the gas includes at least one of hydrogen, silane, ammonia, nitrogen, and trimethylaluminum; annealing time s, s≥30 minutes; annealing temperature t, t≥800°C.

[0044] Under the high temperature annealing, the crystal quality of the first region can be restored, so that the dislocation density of the region is reduced.

[0045] In one possible implementation, annealing is performed in a gas atmosphere, including:

[0046] The first gas is introduced, the temperature is raised to t1 degrees Celsius, and maintained for s1 minutes, 500°C≤t1≤600°C, 5 minutes≤s1≤10 minutes;

[0047] The second gas and the first gas are introduced, the temperature is raised to t2 degrees Celsius, and maintained for s2 minutes, 800°C≤t2≤1000°C, 30 minutes≤s2≤60 minutes;

[0048] The first gas includes nitrogen, and the second gas includes at least one of hydrogen, silane, nitrogen, and trimethylaluminum.

[0049] In one possible implementation, after the first region is damaged and repaired, the dislocation density of the first region is a1×10 8 / cm 2 , the dislocation density in the second region is a2×10 9 / cm 2 , the surface roughness of the first region is less than or equal to 0.2 nm; wherein, 1≤a1<10, and 1≤a2<10.

[0050] In one possible implementation, after the first region is repaired from damage and before the gate is formed in the groove, the preparation method further includes: forming an epitaxial layer in the groove and on the surface of the first region of the channel layer, the epitaxial layer being used to deplete the two-dimensional electron gas concentration at the heterojunction interface below the gate, and the heterojunction interface below the gate includes at least the first region.

[0051] By using the grown epitaxial layer, the device becomes an enhancement mode device.

[0052] In a possible implementation, forming an epitaxial layer in the groove and on the surface of the first region of the channel layer includes: forming a stacked In layer in the groove and on the surface of the first region of the channel layer. x Ga 1-x N layer and Al y Ga 1-y N layers; among them, 0.1≤x≤0.3, 0.15≤y≤0.3.

[0053] Since the lattice constant relationship between AlGaN, InGaN and GaN is InGaN>GaN>AlGaN, the direction of the piezoelectric polarization induced electric field of InGaN is opposite to that of AlGaN. By limiting the composition of the AlGaN and InGaN epitaxial layers, the polarization induced electric field of the overall device structure of InGaN, AlGaN and GaN can be reduced, and the conduction band energy level at the interface between AlGaN and GaN can be increased to deplete the two-dimensional electron gas in the channel, thereby realizing an enhancement-mode device.

[0054] In a possible implementation, forming an epitaxial layer in the groove and on the surface of the first region of the channel layer includes: forming an In z Al w Ga 1-z-w N layers; among them, 0.01≤z≤0.2, 0.6≤w≤0.9.

[0055] In a possible implementation, a stacked In x Ga 1-x N layer and Al y Ga 1-y N layers, or, make In z Al w Ga 1-z-w Before forming the N layer, the preparation method further comprises: forming a GaN layer on the surface of the first region of the channel layer.

[0056] The growth of the GaN layer can further reduce surface damage and reduce the scattering effect of the first region on carriers, ensuring that the carrier mobility is basically not affected.

[0057] In one possible implementation, after forming a gate dielectric layer on the epitaxial layer and before forming a gate on the gate dielectric layer, the preparation method further includes: annealing in a gas atmosphere; wherein the gas includes at least one of hydrogen, silane, ammonia, and nitrogen; annealing time s, s≤30 minutes; annealing temperature t, t≤800°C.

[0058] By utilizing high temperature annealing, the interface state density of the gate dielectric layer and the epitaxial layer can be reduced.

[0059] In a possible implementation, in the same vacuum equipment, the first region is damaged and repaired, an epitaxial layer is formed, and a gate dielectric layer is formed; the interface trap state density of the gate is ρ, 5×10 11 eV -1 cm -2 ≤ρ≤5×10 13 eV -1 cm -2 .

[0060] On the other hand, the present application also provides an electronic device, which includes the transistor in any of the above implementations, and also includes a substrate, and the transistor is arranged on the substrate.

[0061] In the electronic device provided in the present application, since it includes the transistor in any of the above-mentioned implementation methods, in the transistor device, before the gate is manufactured, a repair process can be used to repair the bottom of the groove used to fill the gate, so that when the gate is working, the gate leakage current can be reduced and the gate control capability can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Figure 1 A schematic diagram of a partial structure of a base station provided in an embodiment of the present application;

[0063] Figure 2 An exploded schematic diagram of a partial structure of a mobile phone provided in an embodiment of the present application;

[0064] Figure 3 A partial circuit diagram of a mobile phone provided in an embodiment of the present application;

[0065] Figure 4 A circuit diagram of a radio frequency power amplifier provided in an embodiment of the present application;

[0066] Figure 5 A schematic diagram of a transistor packaging structure provided in an embodiment of the present application;

[0067] Figure 6 A schematic diagram of the structure of a transistor provided in an embodiment of the present application;

[0068] Figure 7 and Figure 8 A partial structural schematic diagram of a transistor manufacturing process provided in an embodiment of the present application;

[0069] Fig. 9A An Atomic Force Microscopy (AFM) measurement image of a damaged area before repair provided in an embodiment of the present application;

[0070] Fig. 9B An Atomic Force Microscopy (AFM) measurement image of a damaged area after repair provided in an embodiment of the present application;

[0071] Fig. 10A A schematic diagram of dislocation before repairing a damaged area provided in an embodiment of the present application;

[0072] Fig. 10B A schematic diagram of a dislocation after repairing a damaged area provided in an embodiment of the present application;

[0073] Fig.11 A process condition diagram for high temperature gas atmosphere annealing provided in an embodiment of the present application;

[0074] Fig.12 A process condition diagram of a high temperature gas atmosphere annealing provided in an embodiment of the present application

[0075] Fig.13 A cross-sectional AFM scan of a groove provided in an embodiment of the present application;

[0076] Fig.14A A heterojunction band diagram of a GaN channel layer and an AlGaN barrier layer provided in an embodiment of the present application;

[0077] Fig. 14B Heterojunction band diagram of GaN channel layer and AlGaN barrier layer provided in the embodiment of the present application

[0078] Fig.15 A schematic diagram of the structure of a transistor provided in an embodiment of the present application;

[0079] Fig.16 A local enlarged view of a transistor provided in an embodiment of the present application;

[0080] Fig.17 Schematic diagram of polarization induction of AlGaN, InGaN and GaN provided in the embodiments of the present application;

[0081] Fig.18 The AlGaN and GaN heterojunction energy band structure diagram provided in the embodiment of the present application;

[0082] Fig.19 A local enlarged view of a transistor provided in an embodiment of the present application;

[0083] Fig. 20 A local enlarged view of a transistor provided in an embodiment of the present application;

[0084] Fig.21 A schematic diagram of polarization induction of InAlGaN and GaN provided in an embodiment of the present application;

[0085] Fig. 22 The InAlGaN and GaN heterojunction energy band structure diagram provided in the embodiment of the present application;

[0086] Fig.23 A local enlarged view of a transistor provided in an embodiment of the present application;

[0087] Fig.24 A partial structural schematic diagram of a transistor manufacturing process provided in an embodiment of the present application;

[0088] Fig.25 A partial structural schematic diagram of a transistor manufacturing process provided in an embodiment of the present application;

[0089] Fig.26 A schematic diagram of the structure of a transistor provided in an embodiment of the present application;

[0090] Fig. 27 A schematic diagram of the structure of a transistor provided in an embodiment of the present application. DETAILED DESCRIPTION

[0091] Before introducing the embodiments involved in the present application, some technical terms related to the embodiments of the present application are first introduced, as follows:

[0092] Dislocation: refers to an internal microscopic defect of a crystal material, a local irregular arrangement of atoms (crystal defect). From a geometric point of view, dislocation is a line defect and can be regarded as the boundary between the slipped part and the non-slipped part of the crystal. There are roughly three types of dislocations: edge dislocation, screw dislocation and mixed dislocation. Mixed dislocation has the characteristics of both the previous two dislocations.

[0093] Dislocation density: There are a large number of dislocations in ordinary crystals, and the amount of these dislocations is expressed by dislocation density. Dislocation density can be defined as the total length of dislocation lines contained in a unit volume of crystal.

[0094] Heterojunction: A junction formed by the contact of two different semiconductor materials. The lattice constants of these two materials are different, so lattice mismatch will occur.

[0095] Interface state: In a heterojunction, in addition to the interface state caused by lattice mismatch at the contact surface of two different semiconductor materials, interface state will also be generated due to interface distortion caused by the mismatch of thermal expansion coefficients of the two materials.

[0096] Interface trap state density: When the energy band structures of two materials do not match, trap states are formed near the interface. The interface trap state density refers to the number of unoccupied electronic states in the energy band present in the material.

[0097] Semiconductor heterojunction energy band diagram: shows the changes in the energy of the conduction band minimum and the valence band maximum on both sides of the heterojunction interface.

[0098] The following describes the solutions involved in the embodiments of the present application in conjunction with the accompanying drawings.

[0099] The embodiment of the present application provides an electronic device, which may include a communication device (e.g., a base station, a mobile phone), a wireless charging device, a medical device, a radar, a navigation device, a radio frequency (RF) plasma lighting device, an RF induction and microwave heating device, etc. The embodiment of the present application does not impose any special restrictions on the specific form of the above electronic devices.

[0100] The above electronic devices basically include radio frequency semiconductor devices, such as power amplifiers (PA). The main function of PA is to amplify radio frequency signals. Taking base stations as an example, Figure 1 A simple structural diagram of a base station is given. The base station includes a control unit. The control unit in the base station includes a wireless transceiver, an antenna and related signal processing circuits, etc. The control unit mainly includes four components: a cell controller, a voice channel controller, a signaling channel controller and a multi-channel terminal interface for expansion. The control unit of the base station usually controls several base transceiver stations. Through remote commands from the transceiver station and the mobile station, the control unit of the base station is responsible for all mobile communication interface management, mainly the allocation, release and management of wireless channels.

[0101] Continue to combine Figure 1 The base station also includes a transmission unit, which is connected to the core network. The control signaling, voice call or data service information on the core network side is sent to the control unit of the base station through the transmission unit, and these services are processed by the control unit.

[0102] Recombination Figure 1 The base station also includes a baseband unit and a radio frequency (RF) unit. The baseband unit is mainly responsible for baseband modulation and demodulation, wireless resource allocation, call processing, power control and soft switching. The RF unit is mainly responsible for the conversion between the air RF channel and the baseband digital channel, and then the signal is amplified by the power amplifier (PA) and then sent to the antenna through the RF feeder for transmission. The terminal equipment, such as mobile phones and tablet computers, receives the radio waves transmitted by the antenna through the wireless channel and then demodulates its own signal.

[0103] Continue to combine Figure 1 The base station also includes a power supply unit, which can be used to supply power to structures such as the transmission unit, the baseband unit, and the control unit.

[0104] Figure 2A structural diagram of another electronic device is given. The electronic device takes a mobile phone as an example. The mobile phone may include a middle frame 11, a rear shell 12, and a display screen 13. The middle frame 11 includes a carrier plate 111 for carrying the display screen 13, and a frame 110 surrounding the carrier plate 111. Figure 3 As shown, the RF power amplifier PA is in the transmitting link in the RF front-end system of the smart terminal and can be set on the carrier board 111. The main function of the RF power amplifier PA is to amplify the modulated RF signal and then transmit it to the outside through the filter, switch and antenna.

[0105] Figure 4 This is a circuit diagram of an RF power amplifier exemplarily given in this application. In this circuit, the RF power amplifier (for example, a GaN HEMT device unit) is the main body, which needs to cooperate with RF signal input, output matching, bias circuit, capacitors, inductors and other electronic components to form a microwave monolithic integrated circuit during operation.

[0106] With the development of mobile communication technology, the functional requirements for the above-mentioned RF semiconductor devices are becoming higher and higher, such as higher frequency, higher voltage, higher output power and efficiency.

[0107] Among the semiconductor materials that can be selected, gallium nitride (GaN) has become a key material for making radio frequency semiconductor devices due to its high thermal conductivity, high breakdown field strength, high saturation electron mobility rate and other characteristics. For example, a high electron mobility transistor (HEMT) based on gallium nitride (GaN) is made of a GaN epitaxial single crystal film grown on a single crystal substrate. The single crystal substrate generally uses materials such as sapphire (Sapphire), silicon carbide (SiC) or silicon (Si) single crystal. For example, when the substrate uses silicon single crystal material, the HEMT obtained can be called a gallium nitride on silicon (GaN-on-Si) HEMT device.

[0108] like Figure 5 As shown, the transistor 300 in the above device is arranged on a substrate 400 , and the transistor 300 is arranged on the substrate 400 through a first electrical connection structure (eg, a metal layer) 500 , so that the transistor 300 can be signal-interconnected with other electronic devices on the substrate 400 .

[0109] The substrate 400 is then disposed on the circuit board 100 via the second electrical connection structure 200. For example, the circuit board 100 may be a printed circuit board (PCB), and the second electrical connection structure 200 may be a ball grid array (BGA) or other electrical connection structures.

[0110] Figure 5 The transistor 300 shown may be Figure 6 The structure shown, Figure 6 1 is a cross-sectional structural diagram of a transistor provided in an embodiment of the present application, and the transistor may include: a substrate 101, a channel layer 103 disposed on the substrate 101, and a barrier layer 105 disposed on the channel layer 103. The transistor also includes a gate 501, a source 502, and a drain 503, and the source 502 and the drain 503 may both be in ohmic contact with the channel layer 103.

[0111] In one achievable manner, the substrate 101 may be silicon, silicon carbide, aluminum oxide, or a composite substrate formed based on the above substrates. The channel layer 103 includes a gallium nitride GaN material. The barrier layer 105 includes an aluminum gallium nitride AlGaN material. For example, the IIIA nitride barrier layer is disposed on top of the IIIA nitride channel layer, and the IIIA nitride barrier layer 105 is used to cooperate with the IIIA nitride channel layer 103 to generate a two-dimensional electron gas (Two Dimensional Electron Gas, 2DEG) through polarization in the region where the IIIA nitride channel layer 103 and the IIIA nitride barrier layer 105 are connected, thereby providing a channel for conducting current.

[0112] In some embodiments, Figure 6 The transistor may further include a buffer layer 102, which is stacked between the substrate 101 and the channel layer 103. The buffer layer 102 may include a group IIIA nitride, such as AlN or AlGaN. The buffer layer 102 is used to buffer the stress between the substrate 101 and the channel layer 103 and improve the quality of the epitaxial growth of the channel layer 103.

[0113] See you next time Figure 6 In some embodiments, an isolation layer 104 may be disposed between the channel layer 103 and the barrier layer 105 . In other examples, the isolation layer 104 may not be disposed between the channel layer 103 and the barrier layer 105 .

[0114] In some structures, such as Figure 6A passivation layer 106 may also be provided on the barrier layer 105. The passivation layer may be at least one layer of SiNx, Al2O3, HfO2, and SiOx. The passivation layer 106 may be used to protect the device.

[0115] like Figure 6 The gate 501 of the transistor penetrates at least a portion of the passivation layer 106 and the barrier layer 105. This gate structure may be referred to as a recessed gate structure.

[0116] The transistor may further include a gate dielectric layer 401, and a gate 501 is formed on the gate dielectric layer 401. The material of the gate dielectric layer 401 may be selected from at least one of Al2O3, HfO2, SiO2, Si3N4, and ZrO2.

[0117] In the preparation Figure 6 When manufacturing the transistor shown in the figure, grooves need to be opened, and when the grooves are opened, some film layer structures will be damaged.

[0118] like Figure 7 As shown, a channel layer 103 is formed on a substrate 101 , a barrier layer 105 is formed on the channel layer 103 , and a passivation layer 106 is formed on the barrier layer 105 .

[0119] The passivation layer 106 may be an amorphous non-crystalline material.

[0120] Among the optional processes, the passivation layer 106 may be grown by using Metal-Organic Chemical Vapor Deposition (MOCVD), Low Pressure Chemical Vapor Deposition (LPCVD), or Plasma-Enhanced Chemical Vapor Deposition (PECVD).

[0121] In other examples, you can Figure 7 Based on the example, some other film structures are added, such as a buffer layer, an isolation layer, etc. In some examples, the Figure 7 A passivation layer 106 is shown.

[0122] like Figure 8 As shown, a groove is formed so that the groove passes through the passivation layer 106 and the barrier layer 105 to the surface of the channel layer 103. When forming the groove, there may be a process error, for example, the etching stop position may be ±0.5 nm from the surface of the channel layer 103.

[0123] In some processes, the surface of the passivation layer 106 can be patterned by photolithography to expose the portion to be etched, and then the passivation layer 106 and the barrier layer 105 are etched in the exposed area. The etching method can be at least one of reactive ion etching (Reactive-Ion Etching, RIE), inductively coupled plasma-reactive ion etching (Inductively Coupled Plasma-Reactive Ion Etching, ICP-RIE), wet potassium hydroxide (KOH) solution, thermal oxidation followed by wet etching, and photo-assisted electrochemical etching.

[0124] For example, when dry etching grooves, physical bombardment will cause a certain degree of lattice damage to the bottom area after etching, such as Figure 8 For example, a damaged region is formed in the region of the dotted line frame of the channel layer 103. Then, in the obtained Figure 6 After the gate 501 shown, the damaged area leads to a large gate leakage current problem. The large leakage current reduces the gate voltage swing range and gate control capability, affects the transconductance of the device, and further limits the gain of the device.

[0125] In order to reduce the gate leakage current, the present application provides some process means. The following is an introduction to how the present application solves the gate leakage current problem in conjunction with the accompanying drawings and process flow.

[0126] In some feasible process steps, Figure 8 After forming the grooves shown, high temperature gas atmosphere annealing can be used to repair the damaged area.

[0127] Wherein, the gas atmosphere includes but is not limited to one or more of hydrogen, silane, ammonia, nitrogen, and trimethylaluminum (TMAl). The annealing temperature t, t≥800°C, for example, 800°C≤t≤1000°C, and the annealing time s, s≥30 minutes, for example, 30 minutes≤s≤60 minutes. After the high-temperature gas atmosphere annealing process step, the damaged area formed after etching can be eliminated, the dislocation density of the damaged area can be reduced, and the crystal quality of the area can be improved, so as to achieve the purpose of controlling the gate leakage current, and improve the gate voltage swing, gate control capability and reliability under high temperature and high field conditions.

[0128] Fig. 9A The AFM (Atomic Force Microscopy) image of the damaged area before repair is shown as an example. Fig. 9B The Atomic Force Microscopy (AFM) image of the damaged area after repair is shown as an example.

[0129] contrast Fig. 9A and Fig. 9B After the groove is opened, the channel layer 103 has a dislocation outcrop phenomenon. Fig. 9A In the process, due to the bombardment of the etching process, the lattice arrangement is destroyed and the dislocation density is large, which is reflected in Fig. 9A In the middle, that is, on the surface after etching, the dislocation density is large, the surface undulation is large, the surface roughness is high, and the pattern is darker. Fig. 9B In the process, due to the damage repair, the lattice arrangement is more neat, which can reduce the dislocation density in the damaged area, and the surface roughness is smaller, which is reflected in Fig. 9B In the middle, that is, on the surface after etching, the pattern is bright because the surface has small undulations and low roughness.

[0130] In some embodiments, after the damaged area is repaired, Figure 8 The dislocation density of the damaged region (which may be called the first region) is less than or equal to the dislocation density of the second region located around the first region.

[0131] For example, the dislocation density in the first region is a1×10 8 / cm 2 The dislocation density of the area around the damaged area (which can be called the second area) is a2×10 9 / cm 2 , wherein 1≤a1<10, and 1≤a2<10. Obviously, after the damaged region is subjected to high temperature gas atmosphere annealing, the dislocation density level of the first region can be made lower than that of the second region, thereby reducing the gate leakage current channel.

[0132] The damaged area (or first area) involved in the embodiment of the present application corresponds to the position of the gate 501, which can be understood as follows: the orthographic projection of the gate 501 on the channel layer 103 overlaps with the boundary of the first area of ​​the channel layer 103, or the orthographic projection of the gate 501 on the channel layer 103 is located within the boundary of the first area of ​​the channel layer 103, or the orthographic projection of the gate 501 on the channel layer 103 overlaps with part of the first area.

[0133] The dislocation density can be obtained by using a transmission electron microscope (TEM). The gate region of the active area of ​​the sample is sliced ​​and sampled using a focused ion beam (FIB). The images below the gate (i.e., the damaged area) and below the barrier layers on both sides (i.e., the original area of ​​the channel layer) are directly observed using the transmission electron microscope TEM. The number of dislocation lines per unit area in the transmission electron microscope TEM image can be counted to directly calculate the dislocation density. Alternatively, multi-photon photoluminescence can be used to perform three-dimensional reconstruction of the dislocation lines in the damaged area and the original area of ​​the channel layer, and the length of the dislocation lines per unit volume can be counted to directly calculate the dislocation density.

[0134] After the damaged area is subjected to high temperature gas atmosphere annealing treatment, not only the dislocation density in the area can be reduced, but also the surface roughness of the area can be reduced, for example Fig. 10A and Fig. 10B As shown, Fig. 10A The dislocation diagram before the damaged area is repaired is shown as an example. Fig. 10B The schematic diagram of the dislocation after the damaged area is repaired is shown as an example.

[0135] exist Fig. 10A The surface roughness RMS of the damaged area is 0.313nm. After annealing in high-temperature gas atmosphere, Fig. 10B In the embodiment, the surface roughness RMS of the repaired damaged area is reduced to less than or equal to 0.2 nm, for example, it can be reduced to 0.189 nm.

[0136] Therefore, after annealing in a high-temperature gas atmosphere, not only can the crystal arrangement of the damaged area be optimized, the dislocation density be reduced, and the leakage current channel be reduced; the surface roughness of the area can also be reduced, providing a better growth environment for the growth of subsequent film layers.

[0137] At least two process flows for performing high temperature gas atmosphere annealing on the damaged area are given below.

[0138] like Fig.11 , Fig.11 An exemplary process condition diagram of high temperature gas atmosphere annealing is shown. Figure 8 The grooved structure shown is placed in a vacuum device, and 5 SLM of N2 is continuously introduced during the entire annealing process; first, the temperature is increased to 550°C-600°C and maintained for 5 min-10 min; then the temperature is increased to 800°C-1000°C and maintained for 30 min-60 min, and 2 SLM of NH3 is introduced during this time period to perform high temperature annealing on the damaged area.

[0139] For example, in some optional embodiments, the temperature is raised to 550° C. in an atmosphere of 5 SLM of N 2 gas flow, and then annealed at 930° C. for 30 min under an atmosphere of 5 SLM of N 2 and 2 SLM of NH 3 gas flow.

[0140] like Fig.12 , Fig.12 Another process condition diagram of high temperature annealing is shown as an example. Figure 8 The grooved structure shown is placed in a vacuum device, and 5 SLM of N2 is continuously introduced during the entire annealing process; first, the temperature is increased to 550°C-600°C and maintained for 5 min-10 min; then the temperature is increased to 800°C-1000°C and maintained for 30 min-60 min, and during this time period, 10-100 sccm of TMAl and 2-10 SLM of NH3 are introduced to anneal the damaged area.

[0141] In the above two examples, SLM and SCCM are both gas mass flow units. SLM (Standard Liter per Minute) and SCCM (Standard Cubic Centimeter per Minute) stand for standard liters per minute and standard milliliters per minute respectively.

[0142] Etching Figure 8 When the groove shown is Fig.13 As shown, Fig.13 The cross-sectional AFM scan of the groove is shown as an example. The sidewall of the groove is approximately vertical, for example, the inclination of the sidewall of the groove is about 89°-91°, for example, the inclination is 89°, 89.2° or 90°. The groove with an approximately vertical sidewall is beneficial to reducing the nonlinear capacitance of the gate, improving the control ability of the gate over the two-dimensional electron gas 2DEG, and improving the transconductance peak of the device.

[0143] When etching the groove, the etching depth of the groove can be designed according to the thickness of the film structure such as the passivation layer and the barrier layer. The present application does not limit the depth of the groove.

[0144] The transistors exemplified in the present application may include depletion-mode transistors and enhancement-mode transistors. Enhancement-mode transistors with a positive threshold voltage are widely used because they can simplify circuit structure, reduce costs, and improve system safety and stability.

[0145] The key to realizing enhancement-mode devices is to deplete the two-dimensional electron gas 2DEG at the heterojunction interface under the gate to control the threshold voltage. Fig.14A As shown, Fig.14A The heterojunction energy band diagram of the GaN channel layer 103 and the AlGaN barrier layer 105 is shown.f is the Fermi level, given by Fig.14A It can be seen that in the heterojunction of the GaN channel layer 103 and the AlGaN barrier layer 105, the conduction band at the heterojunction below the gate is below the Fermi level, that is, the heterojunction has a certain two-dimensional electron gas 2DEG concentration. In order to deplete the two-dimensional electron gas 2DEG concentration at the heterojunction interface under the gate, Fig. 14B As shown in FIG. 1 , the conduction band at the interface between the AlGaN layer and the GaN layer is raised above the Fermi level, the 2D electron gas 2DEG concentration at the channel is reduced, and the effective conduction channel under the gate is pinched off to realize an enhancement mode device, such as Fig.15 As shown, an epitaxial layer 201 may be disposed between the gate 501 and the channel layer 103 , and the epitaxial layer 201 may be used to deplete the concentration of the two-dimensional electron gas 2DEG at the heterojunction interface under the gate.

[0146] As in the above example, after repairing the damaged area caused by etching damage, Fig.15 , the epitaxial layer 201 can be formed on the surface of the repaired repair region 301 . That is, the epitaxial layer 201 is directly stacked on the surface of the repair region 301 .

[0147] Due to the high temperature gas atmosphere annealing treatment, the dislocation density of the repaired area 301 is reduced and the surface roughness of the repaired area 301 is improved. Thus, when the epitaxial layer 201 is grown, the growth quality of the epitaxial layer 201 is improved and the extension of dislocations in the epitaxial layer 201 is weakened, thereby improving the crystal quality of the epitaxial layer 201 and reducing the occurrence of stress relaxation in the epitaxial layer. In this way, the performance of the entire enhanced device can be improved.

[0148] For example, in some examples, the dislocation density of the epitaxial layer 201 can be as low as 10 7 / cm 2 , which is one order of magnitude lower than that without optimization. The reduction of dislocation density can avoid stress relaxation in the epitaxial layer and improve the piezoelectric polarization effect. At the same time, the low dislocation density can reduce the electron scattering effect in the 2DEG channel and improve the carrier mobility, which in turn helps to improve the device saturation current density and power density level.

[0149] In the example of the present application, the epitaxial layer 201 is used to deplete the concentration of the two-dimensional electron gas 2DEG at the heterojunction interface below the gate 501. Since the epitaxial layer 201 is stacked on the surface of the repaired repair region 301, the concentration of the two-dimensional electron gas 2DEG at the heterojunction interface of at least part of the repair region 301 can be suppressed, and the concentration of the two-dimensional electron gas 2DEG in the area surrounding the repair region 301 can also be suppressed.

[0150] Some structures that can be realized by the epitaxial layer 201 provided in the present application are introduced below with reference to the accompanying drawings.

[0151] like Fig.16 , Fig.16 yes Fig.15 In this embodiment, the epitaxial layer 201 includes an InGaN layer 2011 and an AlGaN layer 2012 which are stacked.

[0152] In this example, both the InGaN layer and the AlGaN layer are single crystalline layers.

[0153] In some examples, such as Fig.16 , the AlGaN layer 2012 is closer to the channel layer 103 than the InGaN layer 2011. In some other examples, the InGaN layer 2011 is closer to the channel layer 103 than the AlGaN layer 2012. That is, the positions of the AlGaN layer and the InGaN layer can be interchanged.

[0154] exist Fig.16 In the example shown, the GaN channel layer 103, the AlGaN layer 2012 and the InGaN layer 2011 are stacked. Since the lattice constant relationship between AlGaN, InGaN and GaN is InGaN>GaN>AlGaN, Fig.17 As shown, Fig.17 The diagram shows the polarization induction of AlGaN, InGaN and GaN. The direction of the piezoelectric polarization induced electric field of InGaN is opposite to that of AlGaN. For example, Fig.17 InGaN piezoelectric polarization induced electric field P PE Direction upward, AlGaN piezoelectric polarization induced electric field P PE The direction is downward, so the polarization induced electric field of the epitaxial layer 201 as a whole will be reduced, such as Fig.18 As shown, Fig.18 It shows Fig.17 The energy band structure diagram of AlGaN and GaN heterojunction is shown in Figure 2. Fig.18 It is known that: the present application utilizes stacked AlGaN layers and InGaN layers to improve the conduction band energy level at the interface between AlGaN and GaN and deplete the two-dimensional electron gas in the channel, thereby realizing an enhancement mode device.

[0155] In some embodiments, the polarization induced electric field of the overall device structure of InGaN, AlGaN, and GaN can be reduced by adjusting the composition of the AlGaN layer and the InGaN layer.

[0156] For example, In in the InGaN layer x Ga 1-x N, 0.1≤x≤0.3, for example, the In component can be 18%, that is, In 0.18 Ga 0.82N, or, the In component can be 20%, that is, In 0.2 Ga 0.8 N. Al in AlGaN layer y Ga 1-y N, 0.15≤y≤0.3, for example, the Al component can be 20%, that is, Al 0.2 Ga 0.8 N, or Al composition can be 25%, that is, In 0.25 Ga 0.75 N.

[0157] In some other examples, the polarization induced electric field of the overall device structure of InGaN, AlGaN, and GaN can be reduced by adjusting the thickness of the AlGaN layer and the InGaN layer.

[0158] For example, x Ga 1-x The thickness d1 of the N layer is: 4nm≤d1≤6nm, for example, d1=5nm, or d1=4.5nm. y Ga 1-y The thickness d2 of the N layer: 2nm≤d2≤4nm, illustratively, d2=3nm, or d2=3.5nm.

[0159] Back to Fig.15 Since the epitaxial layer 201 including the AlGaN layer and the InGaN layer is directly stacked on the surface of the repaired repair area 301 of the channel layer 103, when growing the AlGaN layer 2012, the GaN with a smaller dislocation density, a more orderly lattice arrangement, and a flatter GaN surface can promote the more orderly crystal arrangement of AlGaN and improve the crystal quality of AlGaN. Similarly, when growing InGaN on AlGaN, the more orderly crystal arrangement of AlGaN will also improve the crystal quality of InGaN, so that the crystal quality of the entire epitaxial layer 201 is improved, thereby improving the performance of the enhancement mode device.

[0160] Fig.19 2 is a structural diagram of another epitaxial layer 201 provided in an embodiment of the present application. In this embodiment, the epitaxial layer 201 includes not only the AlGaN layer 2012 and the InGaN layer 2011, but also the GaN layer 2013, wherein the GaN layer 2013 is disposed on the surface of the repair region 301 of the channel layer 103, and the AlGaN layer 2012 and the InGaN layer 2011 are stacked on the GaN layer 2013. Fig.19 In the embodiment, the GaN layer 2013, the AlGaN layer 2012 and the InGaN layer 2011 are stacked in sequence.

[0161] Before growing AlGaN and InGaN, Fig.19 As shown, GaN is grown first, and GaN can further reduce the surface damage of the repair area 301, and can also reduce the scattering effect of the area on carriers, ensuring that the carrier mobility is not affected.

[0162] Fig.19 In an example, the thickness of the GaN layer 2013 may be 1 nm to 4 nm, for example, 2 nm.

[0163] Fig. 20 2 is a structural diagram of another epitaxial layer 201 provided in an embodiment of the present application. In this embodiment, the epitaxial layer 201 includes an InAlGaN layer 2014, and the InAlGaN layer 2014 is stacked on the surface of the repair region 301 of the channel layer 103. The InAlGaN layer is a single crystalline layer.

[0164] like Fig.21 As shown, Fig.21 The figure shows the polarization induction diagram of InAlGaN and GaN. The piezoelectric polarization induced electric field P of InAlGaN PE is substantially 0, therefore, the polarization induced electric field of the epitaxial layer 201 as a whole will be reduced, such as Fig. 22 As shown, Fig. 22 It is shown that Fig.21 InAlGaN and GaN heterojunction energy band structure diagram, Fig. 22 It is known that: the present application utilizes stacked InAlGaN layers and GaN layers to improve the conduction band energy level at the interface between InAlGaN and GaN and deplete the two-dimensional electron gas in the channel, thereby realizing an enhancement-mode device.

[0165] In some examples, the polarization induced electric field of the InAlGaN and GaN overall device structure can be reduced by adjusting the InAlGaN component, thereby realizing an enhancement mode device.

[0166] For example, In in the InAlGaN layer z Al w Ga 1-z-w N layer; wherein 0.01≤z≤0.2, 0.6≤w≤0.9. For example, the In component can be 5%, and the Al component can be 75%, that is, In 0.05 Al 0.75 Ga 0.2 N, or the In composition may be 3%, and the Al composition may be 62%.

[0167] In some other examples, the thickness of InAlGaN can be adjusted to reduce the polarization induced electric field of the overall device structure of InAlGaN and GaN, thereby realizing an enhancement mode device.

[0168] For example, z Al w Ga 1-z-w The thickness d3 of the N layer is: 6 nm ≤ d3 ≤ 8 nm. For example, d3 = 7 nm, or d3 = 7.5 nm.

[0169] Fig. 20 In the example, since the InAlGaN layer is directly stacked on the surface of the repaired repair area 301 of the channel layer 103, when growing the InAlGaN layer, GaN with a smaller dislocation density, a more orderly lattice arrangement, and a flatter GaN surface can make the crystal arrangement of InAlGaN more orderly, thereby improving the crystallization quality of InAlGaN.

[0170] Fig.23 2 is a structural diagram of another epitaxial layer 201 provided in an embodiment of the present application. In this embodiment, the epitaxial layer 201 includes not only the InAlGaN layer 2014, but also the GaN layer 2013. The GaN layer 2013 is stacked on the surface of the repair region 301 of the channel layer 103, and the InAlGaN layer 2014 is stacked on the GaN layer 2013. Both the InAlGaN layer and the GaN layer are single crystalline layers.

[0171] Before growing InAlGaN, Fig.23 As shown, GaN is grown first, and GaN can further reduce the surface damage of the repair area 301, and can also reduce the scattering effect of the area on carriers, ensuring that the carrier mobility is not affected.

[0172] like Fig.24 When the epitaxial layer 201 is grown in the groove and on the surface of the repair area 301 , the epitaxial layer 201 is in a single crystalline state. Since the passivation layer 106 is in an amorphous non-crystalline state, the epitaxial layer 202 located on the passivation layer 106 is in an amorphous state.

[0173] like Figure 24 to Figure 25 After the epitaxial layer 201 is grown, a gate dielectric layer 401 may be grown. The material of the gate dielectric layer 401 may be at least one of Al2O3, HfO2, SiO2, Si3N4, and ZrO2.

[0174] In one example, the gate dielectric layer 401 covers the surface of the epitaxial layer 201 and the sidewall surface of the groove. Alternatively, the gate dielectric layer 401 may also be formed on the amorphous epitaxial layer 202 .

[0175] In some process steps, the growth of the gate dielectric layer 401 and the growth of the epitaxial layer 201, as well as damage repair, can be performed in the same vacuum equipment. In this way, interface state problems caused by air exposure and environmental contamination can be avoided, thereby reducing the interface trap state density between the gate dielectric layer 401 and the epitaxial layer 201 and reducing the threshold voltage fluctuation caused by a large number of traps.

[0176] For example, the gate dielectric layer 401 may be fabricated by atomic layer deposition (ALD).

[0177] After the gate dielectric layer 401 is prepared, the gate dielectric layer 401 may be subjected to annealing treatment, and the annealing atmosphere may be, but is not limited to, one or more mixed gases of hydrogen, silane, ammonia, and nitrogen, and the annealing time s, s≤30 minutes, and the annealing temperature t, t≤800° C. In this way, the interface state problem between the gate dielectric layer 401 and the epitaxial layer 201 may be further improved.

[0178] In some process steps, the annealing temperature t is 500° C. ≤ t ≤ 800° C., for example, the annealing temperature may be 600° C. The annealing time s is 2 minutes ≤ s ≤ 30 minutes, for example, the annealing time may be 5 minutes, 10 minutes or 20 minutes.

[0179] After the gate dielectric layer 401 is grown, Fig.26 As shown, a gate electrode 501 can be prepared. In some processes, the gate electrode can be deposited by sputtering or evaporation, and the gate electrode 501 pattern is formed by patterning and etching; and then the source electrode 502 and the drain electrode 503 of the ohmic contact are formed.

[0180] In another achievable manner, the ohmic contact source 502 and the drain 503 may be formed before etching the grooves.

[0181] The optional implementation schemes of the ohmic contact source 502 and drain 503 include high temperature annealing, ion implantation or secondary epitaxy.

[0182] When high temperature annealing is used to make the ohmic contact source 502 and drain 503, the Ti layer, Al layer, Ni layer and Au layer can be prepared in sequence, and the ohmic metal can be subjected to high temperature annealing at 800-900°C to obtain the ohmic contact of the source and drain.

[0183] For the ion implantation ohmic contact solution, the ohmic definition area is firstly subjected to ion implantation, the implanted ions may be at least one of elements such as Si and Ge, and an annealing activation treatment is performed at a high temperature above 1000°C.

[0184] For the production of ohmic contacts using secondary epitaxial growth technology, epitaxial growth can be performed at high temperatures above 1000°C.

[0185] In some examples, Fig.26 In the structure shown, since the amorphous epitaxial layer 202 is grown on the surface of the passivation layer 106 when the epitaxial layer 201 is grown, in the transistor, the amorphous epitaxial layer 202, the gate dielectric layer 401 and the gate 501 are stacked in sequence on the surface of the passivation layer 106.

[0186] In the present application example, since the gate dielectric layer 401 and the growth epitaxial layer 201, as well as the damage repair, can be performed in the same vacuum device, the interface trap state density of the gate can be reduced. For example, in some transistors manufactured, the interface trap state density of the gate is ρ, 5×10 11 eV -1 cm -2 ≤ρ≤5×10 13 eV -1 cm -2 .

[0187] Compared with preparing the epitaxial layer and the gate dielectric layer in different vacuum equipment, the present application can solve the problem of high interface state density of the existing gate. The low interface state density of the gate of the present application can reduce the trap effect, reduce the fluctuation and hysteresis of the threshold voltage, and reduce the design difficulty of the bias power supply circuit, thereby improving the reliability and stability of the application of the enhanced GaN-HEMT device system.

[0188] The interface trap state density can be obtained by performing CV testing (i.e., capacitance-voltage testing) on ​​the gate, source, and drain, and calculating the interface trap state density based on the CV curves at different frequencies.

[0189] Fig. 27 This is a structural diagram of another transistor provided in an embodiment of the present application. The difference between this embodiment and the above-mentioned embodiment includes: in this example, a gate dielectric layer may not be included, and after the epitaxial layer 201 is grown, a gate 501 may be further produced, that is, the gate 501 is directly stacked on the epitaxial layer 201 to form a Schottky gate structure HEMT device, which reduces the gate interface and makes the threshold voltage of the device more consistent.

[0190] In some optional embodiments, the gate 501 is deposited by sputtering or evaporation, and the gate 501 can be a layer of metal, or multiple layers of stacked metals, for example, a stacked Ni layer and Au layer, or a Pt layer and Au layer.

[0191] A metal with a high work function may be used as the gate 501. For example, the work function of Ni may be 5.15 eV, and the work function of Pt may be 5.65 eV. In this way, the work function difference ΦB between the metal gate 501 and the semiconductor epitaxial layer 201 can be effectively increased, thereby increasing the threshold voltage to realize an enhanced HEMT device.

[0192] Fig. 27 In the example, the epitaxial layer 201 may be selected from the above example Fig.16 , Fig.19 , Fig. 20 and Fig.23 For example, the epitaxial layer 201 in this example may include a stacked GaN layer and an InAlGaN layer. In other examples, different epitaxial layer structures may also be used.

[0193] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0194] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A transistor, characterized in that: include: substrate; a channel layer formed on the substrate; a barrier layer formed on the channel layer; A gate, pointing from the barrier layer to the channel layer, the gate penetrating at least a portion of the barrier layer; The channel layer includes: a first region corresponding to the gate position, and a second region located around the first region; The dislocation density of the first region is less than or equal to the dislocation density of the second region.

2. The transistor according to claim 1, characterized in that The dislocation density of the first region is a1×10 8 / cm 2 , the dislocation density of the second region is a2×10 9 / cm 2 , where 1≤a1<10, and 1≤a2<10.

3. The transistor according to claim 1 or 2, characterized in that: An epitaxial layer is disposed on the surface of the first region of the channel layer, and the gate is located on a side of the epitaxial layer away from the first region; The epitaxial layer is used to deplete the two-dimensional electron gas concentration in the heterojunction region under the gate, and the heterojunction region under the gate includes at least the first region.

4. The transistor according to claim 3, characterized in that The material of the epitaxial layer includes at least one of InGaN, AlGaN and InAlGaN.

5. The transistor according to claim 3 or 4, characterized in that: The epitaxial layer includes stacked In x Ga 1-x N layer and Al y Ga 1-y N layers; Among them, 0.1≤x≤0.3, 0.15≤y≤0.

3.

6. The transistor according to claim 5, characterized in that In x Ga 1-x The thickness of the N layer d1: 4nm≤d1≤6nm, the Al y Ga 1-y The thickness of the N layer d2: 2nm≤d2≤4nm.

7. The transistor according to claim 5 or 6, characterized in that: The epitaxial layer also includes a GaN layer. From the channel layer to the barrier layer, the GaN layer, the Al y Ga 1-y N layer and the In x Ga 1-x N layers are stacked in sequence.

8. The transistor according to claim 3 or 4, characterized in that: The epitaxial layer includes In z Al w Ga 1-z-w N layers; among them, 0.01≤z≤0.2, 0.6≤w≤0.

9.

9. The transistor according to claim 8, characterized in that In z Al w Ga 1-z-w The thickness of the N layer d3: 6nm≤d3≤8nm.

10. The transistor according to claim 8 or 9, characterized in that: The epitaxial layer further includes a GaN layer, and in a direction from the channel layer to the barrier layer, the GaN layer and the In z Al w Ga 1-z-w N layers are stacked in sequence.

11. The transistor according to any one of claims 3 to 10, characterized in that: The transistor further comprises a gate dielectric layer, and the gate dielectric layer is arranged between the interface between the gate and the epitaxial layer.

12. The transistor according to any one of claims 1 to 11, characterized in that The interface trap state density of the gate is ρ, 5×10 11 eV -1 cm -2 ≤ρ≤5×10 13 eV -1 cm -2 .

13. A method for preparing a transistor, characterized in that: The preparation method comprises: Forming a channel layer on a substrate, and forming a barrier layer on the channel layer; Opening a groove, wherein the groove passes through the barrier layer so that the first region of the channel layer is exposed; Repairing damage to the first region so that a dislocation density in the first region of the channel layer is less than or equal to a dislocation density in a second region, the second region being located around the first region; A gate is formed in the groove.

14. The method for preparing a transistor according to claim 13, characterized in that: Repairing damage to the first region includes: annealing in a gas atmosphere; Wherein, the gas includes at least one of hydrogen, silane, ammonia, nitrogen, and trimethylaluminum; Annealing time s, s ≥ 30 minutes; Annealing temperature t, t≥800℃.

15. The method for preparing a transistor according to claim 14, characterized in that: The annealing in a gas atmosphere comprises: The first gas is introduced, the temperature is raised to t1 degrees Celsius, and maintained for s1 minutes, 500°C≤t1≤600°C, 5 minutes≤s1≤10 minutes; The second gas and the first gas are introduced, the temperature is raised to t2 degrees Celsius, and maintained for s2 minutes, 800°C≤t2≤1000°C, 30 minutes≤s2≤60 minutes; The first gas includes nitrogen, and the second gas includes at least one of hydrogen, silane, nitrogen, and trimethylaluminum.

16. The method for preparing a transistor according to any one of claims 13 to 15, characterized in that: After the first region is damaged and repaired, the dislocation density of the first region is a1×10 8 / cm 2 , the dislocation density of the second region is a2×10 9 / cm 2 , the surface roughness of the first region is less than or equal to 0.2 nm; wherein 1≤a1<10, and 1≤a2<10.

17. The method for preparing a transistor according to any one of claims 13 to 16, characterized in that: After repairing the damage of the first region and before forming a gate in the groove, the preparation method further includes: An epitaxial layer is formed in the groove and on the surface of the first region of the channel layer, wherein the epitaxial layer is used to deplete the two-dimensional electron gas concentration in the heterojunction region under the gate, and the heterojunction region under the gate includes at least the first region.

18. The method for preparing a transistor according to claim 17, characterized in that: Producing the epitaxial layer in the groove and on the surface of the first region of the channel layer, comprising: In the groove and on the surface of the first region of the channel layer, a stacked In x Ga 1-x N layer and Al y Ga 1-y N layers; Among them, 0.1≤x≤0.3, 0.15≤y≤0.

3.

19. The method for preparing a transistor according to claim 17, characterized in that: Producing the epitaxial layer in the groove and on the surface of the first region of the channel layer, comprising: In the groove and on the surface of the first region of the channel layer, an In z Al w Ga 1-z-w N layers; among them, 0.01≤z≤0.2, 0.6≤w≤0.

9.

20. The method for preparing a transistor according to claim 18 or 19, characterized in that: The stacked In x Ga 1-x N layer and Al y Ga 1-y N layers, or, make In z Al w Ga 1-z-w Before the Nth layer, the preparation method further comprises: A GaN layer is formed on the surface of the first region of the channel layer.

21. The method for preparing a transistor according to any one of claims 17 to 20, characterized in that: After forming the epitaxial layer in the groove and on the surface of the first region of the channel layer and before forming the gate in the groove, the preparation method further includes: Producing a gate dielectric layer on the epitaxial layer; The gate is manufactured on the gate dielectric layer.

22. The method for preparing a transistor according to claim 21, characterized in that: After forming a gate dielectric layer on the epitaxial layer and before forming a gate on the gate dielectric layer, the preparation method further comprises: Annealing in a gas atmosphere; Wherein, the gas includes at least one of hydrogen, silane, ammonia and nitrogen; Annealing time s, s≤30 minutes; Annealing temperature t, t≤800℃.

23. The method for preparing a transistor according to claim 21 or 22, characterized in that: In the same vacuum equipment, repairing the damage of the first region, producing the epitaxial layer, and producing the gate dielectric layer; The interface trap state density of the gate is ρ, 5×10 11 eV -1 cm -2 ≤ρ≤5×10 13 eV -1 cm -2 .

24. An electronic device, characterized in that: include: substrate; A transistor as claimed in any one of claims 1 to 12, or a transistor made by the method for making a transistor as claimed in any one of claims 13 to 23; Wherein, the transistor is arranged on the substrate.

Images