A method for fabricating a low-frequency, low-noise operational amplifier

Abstract

This invention discloses a method for fabricating a low-frequency, low-noise operational amplifier, including the steps of growing an oxide layer on the surface of a silicon substrate, forming a P-well region within the substrate using photolithography, ion implantation, and push-well thermal diffusion, and the following steps: N+ source / drain fabrication, N-channel fabrication, P+ gate region fabrication, BPSG protective film fabrication, metal fabrication, and passivation layer fabrication. This invention utilizes a grid-like JFET gate structure to increase the device gate area and improve JFET transconductance. Simultaneously, the parallel structure of the JFETs effectively reduces gate leakage current and input noise voltage. Furthermore, by fabricating an N+ contact region, the ohmic contact resistance between the source and the metal is reduced, effectively decreasing thermal resistance noise and lowering the device noise voltage.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and more specifically to a junction field-effect transistor low-frequency low-noise operational amplifier. Background Technology

[0002] In situations involving long-range and passive reception, the acoustic signals received by a sonar system are extremely weak, and the electrical signals converted by the sensor are also very weak. Therefore, a low-noise amplifier is needed to pre-amplify them, i.e., a low-noise preamplifier. Since the frequency spectrum of acoustic signals is between 20Hz and 20kHz, a preamplifier with even lower low-frequency noise is required.

[0003] Sonar sensors are high-impedance, so from the perspective of impedance matching, the input impedance of the preamplifier is required to be very high. From the perspective of noise contribution, current noise is dominant at this time, so the input noise current and bias current of the preamplifier are required to be very low. At the same time, considering that the temperature in the ocean is not very high, the JFET input amplifier is a more ideal choice, and its current noise is nearly three orders of magnitude lower than that of the NPN input OP series amplifier.

[0004] One practical way to improve the basic performance of a preamplifier is to combine two standard operational amplifiers or a standard operational amplifier with a discrete transistor; such a combination is called a composite amplifier. Well-designed composite amplifiers typically offer superior performance compared to standard operational amplifiers. This is because composite amplifiers are optimized for specific parameters, which is difficult to achieve in standard amplifiers due to manufacturing limitations.

[0005] To achieve lower input bias current, noise current, and noise voltage, a JFET is chosen as the input stage. JFET transistors typically have a relatively large offset voltage, ranging from a few millivolts to tens of millivolts, thus requiring an offset trimming circuit. Simultaneously, to minimize JFET current drift, leakage current fine-tuning is necessary.

[0006] An input buffer amplifier is constructed using the high input impedance and low noise current characteristics of the NJFET device structure. The second stage can be a general low-noise voltage amplifier. Its bias current must be from the same current source, so the noise is coherent. When the output is a differential signal, the common-mode noise is eliminated. Summary of the Invention

[0007] To address the aforementioned technical problems, this invention provides a method for fabricating a low-frequency, low-noise operational amplifier.

[0008] The present invention adopts the following technical solution:

[0009] A method for fabricating a low-frequency, low-noise operational amplifier includes growing an oxide layer on the surface of a silicon substrate, and forming a P-well region within the substrate using photolithography, ion implantation, and push-well thermal diffusion. The method is characterized by further including the following steps:

[0010] 1) N+ source / drain fabrication: Multiple N+ source / drain regions are formed in the P-trap region using photolithography, ion implantation, and thermal diffusion.

[0011] 2) N-channel fabrication: Using photolithography, ion implantation, and thermal diffusion, an N-channel region is formed in the P-well region, wherein the junction depth of the N+ drain-source region extends beyond the N-channel region;

[0012] 3) P+ gate region fabrication: using photolithography, ion implantation, and thermal diffusion, a grid-like P+ gate region is formed in the N-channel region and P-well region. Each N+ source / drain is located within the grid of the P+ gate region.

[0013] 4) N+ contact region preparation: Using photolithography, ion implantation and thermal diffusion are used to form N+ contact regions in the N-channel region that correspond to the number of N+ drain and source regions. The implantation area of ​​each N+ contact region covers the area of ​​the N+ drain and source regions. The ion concentration of the N+ contact region is higher than that of the N+ source and drain regions.

[0014] 5) Preparation of BPSG protective film: A BPSG protective film is formed on the surface of the oxide layer using CVD chemical vapor deposition process;

[0015] 6) Metal fabrication: using metal sputtering, photolithography, and etching processes, the N+ contact regions of the device are connected in parallel to form the source and drain, and the P+ gate regions are self-connected to form the gate.

[0016] 7) Passivation layer preparation: A dielectric protective film is formed on the surface of the BPSG protective film using CVD chemical vapor deposition process, and the lead ends are exposed to form PAD points.

[0017] Furthermore, the BPSG protective film layer is composed of silicon dioxide, boron ions, and phosphorus ions, wherein phosphorus ions are present in the form of boron ions and phosphorus ions. 31 + The mass ratio is 5%, B 11 + The mass ratio is 2.5%, and the remainder is silicon dioxide.

[0018] Compared with existing technologies, the present invention has the following advantages:

[0019] The purpose of this invention is to provide a technological approach for the production of low-frequency, low-noise operational amplifiers. In terms of manufacturing method, a grid-like JFET gate structure is fabricated to increase the gate area and improve the JFET transconductance. Simultaneously, the grid-like P+ gate region and the corresponding source-drain interconnection in the JFET effectively reduce gate leakage current and input noise voltage. Furthermore, the fabrication of an N+ contact region, which has a higher impurity ion concentration, reduces the ohmic contact resistance between the source and the metal, effectively reducing thermal resistance noise and device voltage noise. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the process flow of an embodiment of the method for manufacturing a low-frequency, low-noise operational amplifier according to the present invention;

[0021] Figures 2 to 12 This is a schematic diagram of the main process steps in the fabrication of a low-frequency, low-noise operational amplifier according to the present invention;

[0022] Figure 13 This is a schematic diagram showing the device at different testing positions on the wafer before cleaving.

[0023] Explanation of reference numerals in the attached figures: 1. Substrate; 2. Oxide layer; 3. P-well region; 4. N+ drain / source region; 5. N-channel; 6. P+ gate region; 7. N+ contact region; 8. BPSG protective film layer; 9. Lead wire; 10. Dielectric protection film. Detailed Implementation

[0024] To make the present invention clearer, a method for manufacturing a low-frequency, low-noise operational amplifier according to the present invention will be further described below with reference to the accompanying drawings. The specific embodiments described herein are only for explaining the present invention and are not intended to limit the present invention.

[0025] A method for fabricating a low-frequency, low-noise operational amplifier. Figure 1 The fabrication process for a low-frequency, low-noise operational amplifier is presented, and the specific steps are as follows:

[0026] 1) Substrate selection

[0027] like Figure 2 As shown, substrate 1 is selected as an N-type (111) 6-inch silicon wafer with a resistivity of 6.5Ω.cm~8Ω.cm and a thickness of 675μm±15μm.

[0028] 2) Cleaning

[0029] Substrate 1 needs to be chemically cleaned using standard RCA cleaning, which can effectively remove impurities and contaminants from the wafer surface and improve the quality of the wafer oxide layer.

[0030] Volume ratio of chemical reagents and ambient temperature during RCA cleaning:

[0031] Name: SC-1, RCA1; Chemical composition: NH4OH:H2O2:H2O; Ratio: 1:2:12.5; Ambient temperature: 65℃.

[0032] Name: SC-2, RCA-2; Chemical composition: HCl:H2O2:H2O; Ratio: 1:2:12.5; Ambient temperature: 65℃.

[0033] Name: SPM, Chemical composition: H2SO4:H2O2, Ratio: 4:1, Ambient temperature: 65℃;

[0034] Name: Diluted HF, Chemical composition: HF:H2O, Ratio: 1:100, Ambient temperature: 23℃.

[0035] 3) Initial oxidation

[0036] Oxidation is carried out in a high-temperature oxidation furnace, such as... Figure 3 As shown, an oxide layer 2 of silicon dioxide is formed on the surface of substrate 1. The oxidation temperature is a key parameter for growing the silicon dioxide oxide layer. Precise temperature control will affect the thickness uniformity. The temperature is controlled at 950±0.5℃.

[0037] The oxidation process uses dry oxygen + DCE (dichloroethylene) + dry oxygen. Dry oxygen refers to the direct feeding of dry oxygen into the oxidation furnace, which produces a dense oxide layer. The oxygen flow rate is 16 L / min. Dichloroethylene is carried into the oxidation furnace by nitrogen gas at a flow rate of 0.2 L / min.

[0038] Oxidation time: 5 min in dry oxygen atmosphere, 30 min in DCE and oxygen atmosphere, and 5 min in dry oxygen atmosphere.

[0039] Oxide layer thickness: 50±5nm.

[0040] 4) P-trap lithography

[0041] Spin coating: Positive photoresist was selected. To ensure the adhesion between the photoresist and the silicon wafer, HMDS (hexamethyldisilazane) was first used to enhance the adhesion of the oxide layer 2 surface, and then the photoresist was spin-coated to a thickness of (1.0±0.1) μm.

[0042] Pre-baking: Place the substrate 1 coated with photoresist on the heat dissipation plate, set the temperature to (100±5)℃, and the time to 1min.

[0043] Exposure: Patterning and exposure are performed on a lithography machine using a photomask with registration. The registration accuracy is ±0.5μm.

[0044] Developing: Developing temperature (20±1)℃; developing time (1±0.1)min. Rinse with deionized water, centrifuge and dry; the resistivity of deionized water is ≥18MΩ.cm.

[0045] Post-baking: Place the developed silicon wafers into a nitrogen-filled oven at (120±5)℃ for (30±2)min.

[0046] 5) P-trap ion implantation and P-trap push-in

[0047] Using ion implantation technology, an implantation energy of 120 keV was used to implant B with a dose of 7E12. 11 + Impurities are injected into substrate 1 through oxide layer 2.

[0048] In an oxidation diffusion furnace at 800℃~1180℃~800℃, a heating process is employed: (N2+O2) heating (800℃) + 10 min O2 (1180℃) + 800 min N2 (1180℃) + N2 cooling (to 800℃). This process redistributes and diffuses the injected boron impurities, forming a certain junction depth, resulting in a product like... Figure 4 P-well region 3 is shown.

[0049] 6) N+ source-drain lithography

[0050] Photolithography is used to form N+ source / drain region patterns on the surface of oxide layer 2, and the areas to be injected are exposed.

[0051] 7) N+ source-drain injection

[0052] Using ion implantation technology, P4E15 was implanted at an implantation energy of 50 keV. 31 ＋ Impurities are injected into the P-well region 3 and the substrate 1 through the oxide layer 1. Specifically, N+ sources and drains are injected into the substrate 1, using the N-type region to isolate the P-type substrate. This effectively isolates devices on the wafer, preventing interference. Furthermore, the N+ sources and drains in the substrate 1 can be connected via leads to serve as grounding points for the JFET, preventing electrostatic discharge (ESD) interference.

[0053] 8) N-channel lithography

[0054] The N-channel region pattern is formed on the surface of oxide layer 2 using photolithography, and the area to be injected is exposed.

[0055] 9) N-channel injection

[0056] Using ion implantation technology, P0.5 with an implantation energy of 150 keV was implanted with a dose of 5E12. 31 ＋ Impurities are injected into the P-trap region 3 through the oxide layer 1.

[0057] 10) Push-in trap

[0058] Under the conditions of oxidation diffusion furnace temperature of 800℃~1130℃~920℃~800℃, the following process was used: (N2+O2) (800℃) heating + 50min N2 (1130℃) + 80min N2 (cooling down to 920℃) + 10min O2 (920℃) + 50min (H2+O2) (920℃) + 10min O2 (920℃) + 15min N2 (920℃) + N2 cooling down (to 800℃). This activated the injected N+ source / drain and N- channel impurities and formed a certain junction depth, creating the N+ drain / source region 4 as shown in Figure 5 and the N+ drain / source region 4 as shown in Figure 5. Figure 6 The N-channel 5 is shown, in which the N+ drain-source region 4 extends beyond the N-channel 5.

[0059] 11) P+ gate lithography

[0060] A grid-like P+ gate pattern is formed on the surface of oxide layer 2 using photolithography, and the areas to be injected are exposed.

[0061] 12) P+ gate region injection

[0062] Using ion implantation technology, an implantation energy of 20 keV was used to implant B with a dose of 1E14. 11 ＋ Impurities are injected into the N-channel 5 and P-trap region 3 through the oxide layer 1.

[0063] 14) N+ contact area photolithography

[0064] The N+ contact area pattern is formed on the surface of oxide layer 2 using photolithography, and the area to be injected is exposed.

[0065] 15) Injection into the N+ contact area

[0066] Using ion implantation technology, P with an implantation energy of 80 keV was implanted with a dose of 3E15. 31 ＋ Impurities are injected into the N-channel 5 through the oxide layer 1, and the injected area of ​​the N+ contact region corresponds to the area of ​​the N+ drain / source region 4. The ion concentration of the N+ contact region is higher than the ion concentration of the N+ source / drain region.

[0067] 16) Main expansion of the fence area

[0068] Under the conditions of 800℃~920℃~800℃ in the oxidation diffusion furnace, the temperature is increased by (N2+O2) (800℃) + 20min by N2 (920℃) and then decreased (to 800℃) to activate the impurities in the injected P+ gate region and N+ contact region and form a certain junction depth. The resulting P+ gate region 6 and the junction as shown in Figure 7 are fabricated. Figure 8 The N+ contact region 7 is shown. In the ion implantation process, the thickness of part of the oxide layer 2 can be reduced by dry etching, facilitating impurity ion implantation.

[0069] 17) BPSG protective film deposition

[0070] like Figure 9 As shown, a 7000-8000 Å BPSG protective film layer 8 was formed on the surface of oxide layer 2 using CVD chemical vapor deposition. BPSG is composed of silicon dioxide, boron ions, and phosphorus ions, wherein phosphorus ions are abundant. 31 + The mass ratio is 5%, B 11 + The mass ratio is 2.5%, with the remainder being silicon dioxide. The purpose of depositing the BPSG protective film is to deposit P 31 + It can absorb mobile charges and effectively reduce the gate leakage current of JFET to below 50pA.

[0071] 18) Hole photolithography

[0072] like Figure 10 As shown, the lead hole pattern is formed using photolithography, and the BPSG thin film 8 and oxide layer 1 in the lead hole area are etched clean.

[0073] 19) Sputtered aluminum

[0074] A pure aluminum film of 1.2–1.5 μm is sputtered on the device surface to connect the N+ contact regions in parallel and the P+ gate regions are self-connected.

[0075] 20) Metal Preparation

[0076] Using photolithography to form aluminum plate patterns, such as Figure 11 The aluminum lead 9 and the pressure point shown form a metal connection between the source, drain, and gate. The source and drain are identical in manufacturing process and structure, and are not distinguished in the above description.

[0077] 21) Passivation

[0078] like Figure 12 As shown, a 10,000 angstrom dielectric protective film 10 is deposited using chemical vapor deposition. The dielectric protective film 10 can be composed of a 650 nm silicon dioxide layer and a 250 nm silicon nitride layer. Then, dry etching is used to expose the lead ends to form PAD points.

[0079] Devices fabricated using this method and those fabricated using conventional methods, under shielded conditions such as electromagnetic noise and light protection, are tested under the same conditions (external power supply voltage 5V). Before dicing, the wafer is divided as follows: Figure 13The five positions shown (top, middle, bottom, left, and right) are grouped and compared sequentially. The test results are shown in the table below:

[0080]

[0081] As shown in the table, the device fabricated by this method can effectively reduce gate leakage current, effectively reduce thermal resistance noise, and effectively reduce device voltage noise.

[0082] The above embodiments of the present invention are merely examples for clearly illustrating the present invention and are not intended to limit the implementation of the present invention. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively describe all embodiments here. However, obvious variations or modifications derived from the essential spirit of the present invention still fall within the protection scope of the present invention.

Claims

1. A method for fabricating a low-frequency, low-noise operational amplifier, comprising the steps of growing an oxide layer on the surface of a silicon substrate, and forming a P-well region within the substrate using photolithography, ion implantation, and push-well thermal diffusion, characterized in that... It also includes the following steps: 1) N+ source / drain fabrication: Multiple N+ source / drain regions are formed in the P-trap region using photolithography, ion implantation, and thermal diffusion. 2) N-channel fabrication: Using photolithography, ion implantation, and thermal diffusion, an N-channel region is formed in the P-well region, wherein the junction depth of the N+ drain-source region extends beyond the N-channel region; 3) P+ gate region fabrication: Using photolithography, ion implantation and thermal diffusion are used to form grid-like P+ gate regions in the N-channel and P-well regions. Each N+ source / drain is located within the grid of the P+ gate region. 4) N+ contact region fabrication: Using photolithography, ion implantation and thermal diffusion are used to form N+ contact regions in the N-channel region corresponding to the number of N+ source / drain regions. The implanted area of ​​each N+ contact region covers the area of ​​the N+ source / drain regions. The ion concentration in the N+ contact region is higher than that in the N+ source / drain regions. 5) Preparation of BPSG protective film: A BPSG protective film is formed on the oxide layer surface using CVD (chemical vapor deposition) technology. The BPSG protective film is composed of silicon dioxide, boron ions, and phosphorus ions, wherein phosphorus ions are abundant. 31 + The mass ratio is 5%, B 11 + The mass ratio is 2.5%, the remainder is silicon dioxide, and the thickness of the BPSG protective film is 7000~8000 angstroms; 6) Metal fabrication: Using metal sputtering, photolithography, and etching processes, the N+ contact regions of the device are interconnected in parallel to form the source and drain, and the P+ gate regions are self-connected to form the gate. 7) Passivation layer preparation: A dielectric protective film is formed on the surface of the BPSG protective film using CVD chemical vapor deposition process, and the lead ends are exposed to form PAD points.

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