Transistor, electronic device and method for manufacturing transistor

Abstract

Embodiments of the present application relate to the technical field of semiconductor devices, provide a transistor, an electronic device and a method for manufacturing a transistor, and provide a transistor capable of reducing gate leakage current. The transistor comprises a substrate, a channel layer, a barrier layer and a gate, wherein the channel layer is formed on the substrate, the barrier layer is formed on the channel layer, and in the direction from the barrier layer to the channel layer, the gate penetrates through at least part of the barrier layer; and the channel layer comprises a first region corresponding to the position of the gate and a second region located on the periphery of the first region, and the dislocation density of the first region is less than or equal to that of the second region. Damage of the first region below the gate is repaired, such that the dislocation density of the region is reduced, and the crystal quality of the region is improved, thereby achieving the objective of reducing gate leakage current.

Description

Transistor, electronic device, and method for manufacturing transistor

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on October 24, 2023, with application number 202311390112.8 and invention name “Transistor, electronic device, and method for manufacturing transistor,” the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductor device technology, and in particular to a transistor, an electronic device including the transistor, and a method for manufacturing the transistor. Background Art

[0003] With the development of communication technology, the field of radio frequency communication has put forward demands for higher frequency, higher voltage, higher output power and efficiency for semiconductor devices.

[0004] Semiconductor devices made of compound semiconductor materials, such as gallium nitride (GaN)-based high electron mobility transistors (HEMTs), are increasingly being adopted in high-power radio frequency devices, high-voltage switching devices and other fields due to their excellent physical properties such as wide bandgap, high electron drift rate, radiation resistance, and high temperature resistance. For example, they are widely used in radar, wireless communication, navigation, satellite communication, electronic countermeasure equipment and other systems.

[0005] GaN HEMT semiconductor devices include depletion-mode and enhancement-mode devices. Depletion-mode GaN HEMTs require an additional negative bias voltage to operate. This additional negative bias circuit increases power consumption in the non-operating state, significantly limiting the application of depletion-mode devices. In contrast, enhancement-mode GaN HEMTs with a positive threshold voltage can simplify circuit structure, reduce costs, and improve system safety and stability.

[0006] However, enhancement-mode GaN HEMT devices suffer from large gate leakage. Large leakage current reduces the gate voltage swing range and gate control capability, affecting the transconductance of the device. For example, when GaN HEMT devices are used as RF devices, they limit the gain of the RF amplifier.

[0007] Summary of the Invention

[0008] The present application provides a transistor, an electronic device including the transistor, and a method for manufacturing the transistor, with the purpose of providing a transistor capable of reducing gate leakage current.

[0009] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0010] In one aspect, the present application provides a transistor, which may be an enhanced high electron mobility transistor (HEMT).

[0011] The transistor includes a substrate, a channel layer, a barrier layer and a gate. The channel layer is formed on the substrate, the barrier layer is formed on the channel layer, and the gate penetrates at least a portion of the barrier layer in a direction from the barrier layer to the channel layer. The channel layer includes a first region corresponding to the position of the gate and a second region located around the first region, and the dislocation density of the first region is less than or equal to the dislocation density of the second region.

[0012] When preparing the transistor provided in the present application, an etching process is required to etch a groove in the barrier layer, which is used to fill the gate. When etching the groove, a certain degree of lattice damage will be caused to the bottom area after etching (the surface area of ​​the channel layer), resulting in a high density of dislocation outcrops and a large surface roughness. The present application can reduce the dislocation density in this area through repair means, so that the dislocation density in this area is less than or equal to the dislocation density in the surrounding area, thereby improving the crystal quality of this area, thereby achieving the purpose of controlling the gate leakage current.

[0013] In one possible implementation, the dislocation density of the first region is a1×10 8 / cm 2 , the dislocation density in the second region is a2×10 9 / cm 2 , where 1≤a1<10, and 1≤a2<10.

[0014] The dislocation density in the repaired first region is significantly lower than that in the second region by an order of magnitude, effectively improving the crystal quality of the region and reducing leakage current channels.

[0015] In one possible implementation, an epitaxial layer is provided on the surface of the first region of the channel layer, and the gate is located on a side of the epitaxial layer away from the first region; the epitaxial layer is used to deplete the two-dimensional electron gas concentration in the heterojunction region below the gate, and the heterojunction region below the gate includes at least the first region.

[0016] In this example, an epitaxial layer is provided between the gate and the channel layer. The epitaxial layer can deplete the two-dimensional electron gas under the gate, making the transistor an enhancement-mode transistor.

[0017] In addition, the epitaxial layer is arranged on the surface of the first region of the channel layer. Since the present application repairs the first region, the dislocation density in the region is reduced. In this way, when the epitaxial layer is grown, it helps to reduce the extension of the dislocations in the first region in the epitaxial layer, thereby improving the crystallization quality of the epitaxial layer and reducing the occurrence of stress relaxation in the epitaxial layer.

[0018] Therefore, the transistor given in this example can not only reduce the density of dislocation outcrops and reduce the leakage current channel, but also enhance the gate voltage swing, gate control capability and reliability of the transistor under high temperature and high field conditions by improving the growth quality of the epitaxial layer.

[0019] In one possible implementation, the material of the epitaxial layer includes at least one of InGaN, AlGaN, and InAlGaN.

[0020] In one possible implementation, the epitaxial layer includes stacked In x Ga 1-x N layer and Al y Ga 1-y N layers; among them, 0.1≤x≤0.3, 0.15≤y≤0.3.

[0021] In one possible implementation, Al y Ga 1-y N layer compared to In x Ga 1-x The N layer is closer to the channel layer.

[0022] In some embodiments, the channel layer is GaN, and the epitaxial layer includes Al y Ga 1-y N and In x Ga 1-x N. Since the lattice constant relationship between AlGaN, InGaN and GaN is InGaN>GaN>AlGaN, the direction of the piezoelectric polarization induced electric field of InGaN is opposite to that of AlGaN. By limiting the composition of the AlGaN and InGaN epitaxial layers, the polarization induced electric field of the overall device structure of InGaN, AlGaN and GaN can be reduced, and the conduction band energy level at the interface between AlGaN and GaN can be increased to deplete the two-dimensional electron gas in the channel, thereby realizing an enhancement-mode device.

[0023] In one possible implementation, x Ga 1-x The thickness of the N layer d1: 4nm≤d1≤6nm, Al y Ga 1-y The thickness of the N layer d2: 2nm≤d2≤4nm.

[0024] By limiting the thickness of the AlGaN and InGaN epitaxial layers, the polarization-induced electric field of the overall device structure of InGaN, AlGaN, and GaN can be reduced, and the conduction band energy level at the AlGaN and GaN interfaces can be increased to deplete the two-dimensional electron gas in the channel, thereby realizing an enhancement-mode device.

[0025] In a possible implementation, the epitaxial layer further includes a GaN layer, and in the direction from the channel layer to the barrier layer, the GaN layer, the Al y Ga 1-y N layer and In x Ga 1-x N layers are stacked in sequence.

[0026] In the growth of Al y Ga 1-y N layer and In x Ga 1-x Before the N layer, the GaN layer can be grown first. The growth of the GaN layer can further reduce surface damage and reduce the scattering effect of the first region on carriers, ensuring that the carrier mobility is basically unaffected.

[0027] In one possible implementation, the epitaxial layer includes In z Al w Ga 1-z-w N layers; among them, 0.01≤z≤0.2, 0.6≤w≤0.9.

[0028] In this embodiment, by defining In z Al w Ga 1-z-w The N component can reduce the polarization-induced electric field of the overall device structure of InAlGaN and GaN, increase the conduction band energy level at the interface between InAlGaN and GaN, and deplete the two-dimensional electron gas in the channel, thereby realizing an enhancement-mode device.

[0029] In one possible implementation, z Al w Ga 1-z-w The thickness d3 of the N layer is: 6nm≤d3≤8nm.

[0030] Through In z Al 1-z Ga 0.2 Limiting the thickness of the N epitaxial layer can reduce the polarization-induced electric field of the InAlGaN and GaN overall device structure, increase the conduction band energy level at the interface between InAlGaN and GaN, and deplete the two-dimensional electron gas in the channel, thereby realizing an enhancement-mode device.

[0031] In a possible implementation, the epitaxial layer further includes a GaN layer, and in the direction from the channel layer to the barrier layer, the GaN layer and the In z Al w Ga 1-z-w N layers are stacked in sequence.

[0032] The growth of the GaN layer can further reduce surface damage and reduce the scattering effect of the first region on carriers, ensuring that the carrier mobility is basically not affected.

[0033] In one possible implementation, the transistor further includes a gate dielectric layer, and the gate dielectric layer is provided between the gate and the interface of the epitaxial layer.

[0034] In a possible implementation, the material of the gate dielectric layer may be selected from at least one of Al2O3, HfO2, SiO2, Si3N4, and ZrO2.

[0035] In one possible implementation, the gate interface trap state density is ρ, 5×10 11 eV -1 cm -2 ≤ρ≤5×10 13 eV -1 cm -2 .

[0036] In some process steps, the channel layer is damaged and repaired to reduce the dislocation density in the first region, and the epitaxial layer and gate dielectric layer are grown, all of which can be carried out in the same vacuum equipment. This avoids interface state problems caused by air exposure and environmental contamination, thereby reducing the interface trap state density between the gate dielectric layer and the epitaxial layer, and reducing the threshold voltage fluctuation caused by a large number of traps.

[0037] In one possible implementation, the material of the gate includes at least one of nickel (Ni), platinum (Pt), and gold (Au), and the work function of nickel (Ni) is 5.15 eV, and the work function of platinum (Pt) is 5.65 eV.

[0038] Using high work function metal as gate can effectively increase the work function difference Φ of metal-semiconductor contact B , thereby increasing the threshold voltage to realize an enhancement-mode device.

[0039] In another aspect, the present application provides a method for manufacturing a transistor, the method comprising:

[0040] A channel layer is formed on the substrate, and a barrier layer is formed on the channel layer;

[0041] forming a groove, wherein the groove penetrates the barrier layer so that the first region of the channel layer is exposed;

[0042] Repairing damage to the first region so that a dislocation density in the first region of the channel layer is less than or equal to a dislocation density in a second region, where the second region is located around the first region;

[0043] A gate electrode is formed in the groove.

[0044] When preparing transistors using the method provided in this application, when grooves are opened, for example, when dry etching the grooves, damage will be caused to the bottom area of ​​the grooves, that is, the first area of ​​the channel layer, thereby destroying the crystal arrangement. This application can reduce the dislocation density of the first area and improve the crystal quality of the area by repairing the damage, thereby reducing the gate leakage current channel.

[0045] In one possible implementation, damage repair is performed on the first region, including: annealing in a gas atmosphere; wherein the gas includes at least one of hydrogen, silane, ammonia, nitrogen, and trimethylaluminum; annealing time s, s ≥ 30 minutes; annealing temperature t, t ≥ 800°C.

[0046] Under the high temperature annealing, the crystal quality of the first region can be restored, so that the dislocation density of the region is reduced.

[0047] In one possible implementation, annealing in a gas atmosphere includes:

[0048] Introduce the first gas, raise the temperature to t1 degrees Celsius, and maintain it for s1 minutes, 500°C ≤ t1 ≤ 600°C, 5 minutes ≤ s1 ≤ 10 minutes;

[0049] The second gas and the first gas are introduced, the temperature is raised to t2 degrees Celsius, and maintained for s2 minutes, 800°C ≤ t2 ≤ 1000°C, 30 minutes ≤ s2 ≤ 60 minutes;

[0050] The first gas includes nitrogen, and the second gas includes at least one of hydrogen, silane, nitrogen, and trimethylaluminum.

[0051] In one possible implementation, after the first region is damaged and repaired, the dislocation density of the first region is a1×10 8 / cm 2 , the dislocation density in the second region is a2×10 9 / cm 2 , the surface roughness of the first region is less than or equal to 0.2 nm; wherein, 1≤a1<10, and 1≤a2<10.

[0052] In one possible implementation, after the first region is repaired from damage and before the gate is formed in the groove, the preparation method further includes: forming an epitaxial layer in the groove and on the surface of the first region of the channel layer, the epitaxial layer being used to deplete the two-dimensional electron gas concentration at the heterojunction interface below the gate, and the heterojunction interface below the gate includes at least the first region.

[0053] By using the grown epitaxial layer, the device becomes an enhancement mode device.

[0054] In a possible implementation, forming an epitaxial layer in the groove and on the surface of the first region of the channel layer includes: forming a stacked In layer in the groove and on the surface of the first region of the channel layer. x Ga 1-x N layer and Al y Ga 1-y N layers; among them, 0.1≤x≤0.3, 0.15≤y≤0.3.

[0055] Since the lattice constant relationship between AlGaN, InGaN and GaN is InGaN>GaN>AlGaN, the direction of the piezoelectric polarization induced electric field of InGaN is opposite to that of AlGaN. By limiting the composition of the AlGaN and InGaN epitaxial layers, the polarization induced electric field of the overall device structure of InGaN, AlGaN and GaN can be reduced, and the conduction band energy level at the interface between AlGaN and GaN can be increased to deplete the two-dimensional electron gas in the channel, thereby realizing an enhancement-mode device.

[0056] In a possible implementation, forming an epitaxial layer in the groove and on the surface of the first region of the channel layer includes: forming an In layer in the groove and on the surface of the first region of the channel layer. z Al w Ga 1-z-w N layers; among them, 0.01≤z≤0.2, 0.6≤w≤0.9.

[0057] In one possible implementation, a stacked In layer is formed on the surface of the first region. x Ga 1-x N layer and Al y Ga 1-y N layer, or, make In z Al w Ga 1-z-w Before forming the N layer, the preparation method further includes: forming a GaN layer on the surface of the first region of the channel layer.

[0058] The growth of the GaN layer can further reduce surface damage and reduce the scattering effect of the first region on carriers, ensuring that the carrier mobility is basically not affected.

[0059] In one possible implementation, after forming a gate dielectric layer on the epitaxial layer and before forming a gate on the gate dielectric layer, the preparation method further includes: annealing in a gas atmosphere; wherein the gas includes at least one of hydrogen, silane, ammonia, and nitrogen; annealing time s, s≤30 minutes; annealing temperature t, t≤800°C.

[0060] By utilizing high temperature annealing, the interface state density between the gate dielectric layer and the epitaxial layer can be reduced.

[0061] In one possible implementation, in the same vacuum equipment, the first region is damaged and repaired, an epitaxial layer is formed, and a gate dielectric layer is formed; the interface trap state density of the gate is ρ, 5×10 11 eV -1 cm -2 ≤ρ≤5×10 13 eV -1 cm -2 .

[0062] On the other hand, the present application also provides an electronic device, which includes the transistor in any of the above implementations, and the electronic device also includes a substrate, and the transistor is arranged on the substrate.

[0063] In the electronic device provided in the present application, since it includes a transistor in any of the above-mentioned implementation methods, in the transistor device, before the gate is manufactured, a repair process can be used to repair the bottom of the groove used to fill the gate. In this way, when the gate is in operation, the gate leakage current can be reduced and the gate control capability can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] FIG1 is a schematic diagram of a partial structure of a base station provided in an embodiment of the present application;

[0065] FIG2 is an exploded schematic diagram of a partial structure of a mobile phone provided in an embodiment of the present application;

[0066] FIG3 is a partial circuit diagram of a mobile phone provided in an embodiment of the present application;

[0067] FIG4 is a circuit diagram of a radio frequency power amplifier provided in an embodiment of the present application;

[0068] FIG5 is a schematic diagram of a packaging structure of a transistor provided in an embodiment of the present application;

[0069] FIG6 is a schematic diagram of the structure of a transistor provided in an embodiment of the present application;

[0070] 7 and 8 are partial structural schematic diagrams of a transistor manufacturing process provided in an embodiment of the present application;

[0071] FIG9A is an atomic force microscopy (AFM) image of a damaged area before repair provided in an embodiment of the present application;

[0072] FIG9B is an AFM (Atomic Force Microscopy) image of a damaged area after repair provided in an embodiment of the present application;

[0073] FIG10A is a schematic diagram of a dislocation before repair of a damaged area according to an embodiment of the present application;

[0074] FIG10B is a schematic diagram of a dislocation after repair of a damaged area according to an embodiment of the present application;

[0075] FIG11 is a process condition diagram of a high temperature gas atmosphere annealing according to an embodiment of the present application;

[0076] FIG12 is a diagram showing process conditions for high temperature gas atmosphere annealing according to an embodiment of the present application;

[0077] FIG13 is an AFM scan of a cross section of a groove provided in an embodiment of the present application;

[0078] FIG14A is a heterojunction band diagram of a GaN channel layer and an AlGaN barrier layer provided in an embodiment of the present application;

[0079] FIG14B is a heterojunction band diagram of a GaN channel layer and an AlGaN barrier layer provided in an embodiment of the present application;

[0080] FIG15 is a schematic diagram of the structure of a transistor provided in an embodiment of the present application;

[0081] FIG16 is a partial enlarged view of a transistor provided in an embodiment of the present application;

[0082] FIG17 is a schematic diagram of polarization induction of AlGaN, InGaN, and GaN provided in an embodiment of the present application;

[0083] FIG18 is a diagram of the energy band structure of an AlGaN and GaN heterojunction according to an embodiment of the present application;

[0084] FIG19 is a partial enlarged view of a transistor provided in an embodiment of the present application;

[0085] FIG20 is a partial enlarged view of a transistor provided in an embodiment of the present application;

[0086] FIG21 is a schematic diagram of polarization induction of InAlGaN and GaN provided in an embodiment of the present application;

[0087] FIG22 is a diagram of the energy band structure of an InAlGaN and GaN heterojunction according to an embodiment of the present application;

[0088] FIG23 is a partial enlarged view of a transistor provided in an embodiment of the present application;

[0089] FIG24 is a partial structural diagram of a transistor manufacturing process provided in an embodiment of the present application;

[0090] FIG25 is a partial structural diagram of a transistor manufacturing process provided in an embodiment of the present application;

[0091] FIG26 is a schematic structural diagram of a transistor provided in an embodiment of the present application;

[0092] FIG27 is a schematic diagram of the structure of a transistor provided in an embodiment of the present application. DETAILED DESCRIPTION

[0093] Before introducing the embodiments of the present application, some technical terms related to the embodiments of the present application are introduced as follows:

[0094] Dislocation: A microscopic defect within a crystalline material, a localized irregular arrangement of atoms (a crystal defect). From a geometric perspective, a dislocation is a line defect, thought of as the boundary between the slipped and unslipped portions of a crystal. There are three general types of dislocations: edge dislocations, screw dislocations, and mixed dislocations, which combine the characteristics of the three.

[0095] Dislocation density: A large number of dislocations exist in ordinary crystals, and the amount of these dislocations is expressed by dislocation density. Dislocation density can be defined as the total length of dislocation lines contained in a unit volume of crystal.

[0096] Heterojunction: A junction formed by the contact of two different semiconductor materials. The lattice constants of these two materials are different, resulting in lattice mismatch.

[0097] Interface state: In a heterojunction, in addition to the interface state produced by lattice mismatch at the contact surface of two different semiconductor materials, interface state will also be produced due to interface distortion caused by the mismatch of thermal expansion coefficients of the two materials.

[0098] Interface trap state density: When the band structures of two materials do not match, trap states will form near the interface. The interface trap state density refers to the number of unoccupied electronic states in the energy band present in the material.

[0099] Semiconductor heterojunction energy band diagram: shows the energy changes of the conduction band minimum and valence band maximum on both sides of the heterojunction interface.

[0100] The following describes the solutions involved in the embodiments of the present application in conjunction with the accompanying drawings.

[0101] The present invention provides an electronic device, which may include a communication device (e.g., a base station, a mobile phone), a wireless charging device, a medical device, a radar, a navigation device, a radio frequency (RF) plasma lighting device, an RF induction device, and a microwave heating device. The present invention does not impose any particular restrictions on the specific form of the electronic device.

[0102] The aforementioned electronic devices generally include radio frequency semiconductor devices, such as power amplifiers (PAs). The PA's primary function is to amplify radio frequency signals. Taking a base station as an example, Figure 1 shows a simplified schematic diagram of the structure of a base station. The base station includes a control unit, which includes a wireless transceiver, an antenna, and related signal processing circuits. The control unit primarily comprises four components: a cell controller, a voice channel controller, a signaling channel controller, and a multi-port interface for expansion. The base station's control unit typically controls several base transceiver stations. Through remote commands from the transceiver stations and mobile stations, the base station's control unit manages all mobile communication interfaces, primarily the allocation, release, and management of wireless channels.

[0103] Continuing with Figure 1, the base station also includes a transmission unit, which is connected to the core network. The control signaling, voice call or data service information on the core network side is sent to the control unit of the base station through the transmission unit, and these services are processed by the control unit.

[0104] Referring to Figure 1, the base station also includes a baseband unit (BBU) and a radio frequency (RF) unit. The BBU primarily performs baseband modulation and demodulation, wireless resource allocation, call processing, power control, and soft handoff. The RF unit primarily converts between over-the-air radio frequency channels and baseband digital channels. The signal is then amplified by a power amplifier (PA) and sent to the antenna via an RF feeder for transmission. Terminal devices, such as mobile phones and tablets, receive the radio waves transmitted by the antenna over wireless channels and demodulate their own signals.

[0105] Continuing with FIG1 , the base station further includes a power supply unit, which can be used to supply power to structures such as the transmission unit, the baseband unit, and the control unit.

[0106] Figure 2 shows the structure of another electronic device, taking a mobile phone as an example. The mobile phone can include a middle frame 11, a rear cover 12, and a display screen 13. The middle frame 11 includes a carrier board 111 for supporting the display screen 13, and a frame 110 surrounding the carrier board 111. As shown in Figure 3, the RF power amplifier (PA) is located in the transmit chain of the RF front-end system of the smart terminal and can be installed on the carrier board 111. The RF power amplifier (PA) mainly functions to amplify the modulated RF signal and then transmit it externally through the filter, switch, and antenna.

[0107] Figure 4 is a schematic diagram of a radio frequency power amplifier circuit according to an exemplary embodiment of the present invention. In this circuit, the radio frequency power amplifier (e.g., a GaN HEMT device unit) serves as the main component, which, during operation, must cooperate with radio frequency signal input, output matching, bias circuits, and electronic components such as capacitors and inductors to form a microwave monolithic integrated circuit.

[0108] With the development of mobile communication technology, the functional requirements for the above-mentioned radio frequency semiconductor devices are becoming increasingly higher, such as higher frequency, higher voltage, higher output power and efficiency.

[0109] Among the available semiconductor materials, gallium nitride (GaN) has become a key material for the manufacture of radio frequency semiconductor devices due to its high thermal conductivity, high breakdown field strength, and high saturation electron mobility rate. For example, a high electron mobility transistor (HEMT) based on gallium nitride (GaN) is made of a GaN epitaxial single crystal thin film grown on a single crystal substrate. The single crystal substrate is generally made of materials such as sapphire, silicon carbide (SiC), or silicon (Si) single crystal. For example, when the substrate is made of silicon single crystal material, the resulting HEMT can be called a gallium nitride on silicon (GaN-on-Si) HEMT device.

[0110] As shown in FIG5 , the transistor 300 in the above device is arranged on a substrate 400 , and the transistor 300 is arranged on the substrate 400 through a first electrical connection structure (eg, a metal layer) 500 , so that the transistor 300 can be interconnected with other electronic devices on the substrate 400 for signal interconnection.

[0111] The substrate 400 is then disposed on the circuit board 100 via the second electrical connection structure 200. For example, the circuit board 100 may be a printed circuit board (PCB), and the second electrical connection structure 200 may be a ball grid array (BGA) or other electrical connection structures.

[0112] The transistor 300 shown in FIG5 may have the structure shown in FIG6 , which is a cross-sectional structural diagram of a transistor provided in an embodiment of the present application. The transistor may include: a substrate 101, a channel layer 103 disposed on the substrate 101, and a barrier layer 105 disposed on the channel layer 103. The transistor also includes a gate 501, a source 502, and a drain 503. The source 502 and the drain 503 may both be in ohmic contact with the channel layer 103.

[0113] In one achievable embodiment, the substrate 101 may be silicon, silicon carbide, aluminum oxide, or a composite substrate formed based on the above substrates. The channel layer 103 includes a gallium nitride (GaN) material. The barrier layer 105 includes an aluminum gallium nitride (AlGaN) material. For example, a group IIIA nitride barrier layer is disposed on top of a group IIIA nitride channel layer. The group IIIA nitride barrier layer 105 is used to cooperate with the group IIIA nitride channel layer 103 to generate a two-dimensional electron gas (2DEG) through polarization in the region where the group IIIA nitride channel layer 103 and the group IIIA nitride barrier layer 105 meet, thereby providing a channel for conducting current.

[0114] In some embodiments, as shown in FIG6 , the transistor may further include a buffer layer 102 , which is stacked between the substrate 101 and the channel layer 103 . The buffer layer 102 may include a Group IIIA nitride, such as AlN or AlGaN. The buffer layer 102 is used to buffer the stress between the substrate 101 and the channel layer 103 and improve the quality of the epitaxial growth of the channel layer 103 .

[0115] 6 , in some implementations, an isolation layer 104 may be disposed between the channel layer 103 and the barrier layer 105 . In other examples, the isolation layer 104 may not be disposed between the channel layer 103 and the barrier layer 105 .

[0116] In some structures, as shown in FIG6 , a passivation layer 106 may be provided on the barrier layer 105 . The passivation layer may be at least one of SiNx, Al 2 O 3 , HfO 2 , and SiOx. The passivation layer 106 may protect the device.

[0117] 6 , the gate 501 of the transistor passes through at least a portion of the passivation layer 106 and the barrier layer 105. This gate structure may be referred to as a recessed gate structure.

[0118] The transistor may further include a gate dielectric layer 401, and a gate 501 is formed on the gate dielectric layer 401. The material of the gate dielectric layer 401 may be at least one of Al2O3, HfO2, SiO2, Si3N4, and ZrO2.

[0119] When manufacturing the transistor shown in FIG6 , grooves need to be opened. When the grooves are opened, some film layer structures may be damaged.

[0120] As shown in FIG. 7 , a channel layer 103 is formed on a substrate 101 , a barrier layer 105 is formed on the channel layer 103 , and a passivation layer 106 is formed on the barrier layer 105 .

[0121] The passivation layer 106 may be an amorphous non-crystalline material.

[0122] Among the optional processes, the passivation layer 106 may be grown by using Metal-Organic Chemical Vapor Deposition (MOCVD), Low Pressure Chemical Vapor Deposition (LPCVD), or Plasma-Enhanced Chemical Vapor Deposition (PECVD).

[0123] In some other examples, other film layer structures may be added based on the example of FIG7 , such as a buffer layer, an isolation layer, etc. In some examples, the passivation layer 106 shown in FIG7 may also be removed.

[0124] 8 , a groove is formed so as to penetrate the passivation layer 106 and the barrier layer 105 and reach the surface of the channel layer 103. Process errors may occur when forming the groove. For example, the etching stop position may be ±0.5 nm from the surface of the channel layer 103.

[0125] In some processes, photolithography can be used to pattern the surface of the passivation layer 106 to expose the portion to be etched, and then the passivation layer 106 and the barrier layer 105 are etched in the exposed area. The etching method can be reactive ion etching (RIE), inductively coupled plasma-reactive ion etching (ICP-RIE), wet potassium hydroxide (KOH) solution, thermal oxidation followed by wet etching, and photo-assisted electrochemical etching. At least one of the methods.

[0126] For example, when dry etching grooves, physical bombardment will cause a certain degree of lattice damage to the bottom area after etching. As shown in FIG8 , a damaged area is formed in the area of ​​the dotted box of the channel layer 103. Then, after the gate 501 shown in FIG6 is manufactured, the damaged area leads to a large gate leakage current. The large leakage current reduces the gate voltage swing range and gate control capability, affects the transconductance of the device, and further limits the gain of the device.

[0127] In order to reduce the gate leakage current, this application provides some process means. The following describes how this application solves the gate leakage current problem in combination with the accompanying drawings and process flow.

[0128] In some feasible process steps, after the grooves as shown in FIG8 are formed, high-temperature gas atmosphere annealing can be used to repair the damaged area.

[0129] The gas atmosphere includes but is not limited to one or more of hydrogen, silane, ammonia, nitrogen, and trimethylaluminum (TMAl). The annealing temperature t is t≥800°C, for example, 800°C≤t≤1000°C, and the annealing time s is s≥30 minutes, for example, 30 minutes≤s≤60 minutes. After the high-temperature gas atmosphere annealing process step, the damaged area formed after etching can be eliminated, the dislocation density of the damaged area can be reduced, and the crystal quality of the area can be improved, thereby achieving the purpose of controlling the gate leakage current, improving the gate voltage swing, gate control capability and reliability under high temperature and high field conditions.

[0130] FIG9A exemplarily shows an atomic force microscopy (AFM) measurement image of the damaged area before repair, and FIG9B exemplarily shows an atomic force microscopy (AFM) measurement image of the damaged area after repair.

[0131] Comparing Figure 9A and Figure 9B, after the grooves are opened, the channel layer 103 has a dislocation outcrop phenomenon. In Figure 9A, due to the bombardment of the etching process, the lattice arrangement is destroyed and the dislocation density is large, which is reflected in Figure 9A. That is, on the surface after etching, the dislocation density is large, the surface undulations are large, the surface roughness is high, and the pattern is relatively dark. In Figure 9B, due to the damage repair, the lattice arrangement is more orderly, which can reduce the dislocation density in the damaged area. At the same time, the surface roughness is small, which is reflected in Figure 9B. That is, on the surface after etching, the pattern is bright because the surface undulations are small and the roughness is low.

[0132] In some embodiments, after the damaged area is repaired, the dislocation density of the damaged area (which may be called the first area) shown in FIG. 8 is less than or equal to the dislocation density of the second area located around the first area.

[0133] For example, the dislocation density in the first region is a1×10 8 / cm 2 The dislocation density of the area around the damaged area (which can be called the second area) is a2×10 9 / cm 2 , where 1≤a1<10, and 1≤a2<10. Obviously, after the damaged region is subjected to high-temperature gas atmosphere annealing, the dislocation density level of the first region can be made lower than that of the second region, thereby reducing the gate leakage current channel.

[0134] The damaged area (or first area) involved in the embodiment of the present application corresponds to the position of the gate 501. It can be understood as follows: the orthographic projection of the gate 501 on the channel layer 103 overlaps with the boundary of the first area of ​​the channel layer 103, or the orthographic projection of the gate 501 on the channel layer 103 is located within the boundary of the first area of ​​the channel layer 103, or the orthographic projection of the gate 501 on the channel layer 103 overlaps with part of the first area.

[0135] The dislocation density can be obtained by using a transmission electron microscope (TEM) to slice the gate region of the active area of ​​the sample using a focused ion beam (FIB). The TEM is then used to directly observe the images below the gate (i.e., the damaged area) and below the barrier layers on both sides (i.e., the original area of ​​the channel layer). The dislocation density can be directly calculated by counting the number of dislocation lines per unit area in the TEM image. Alternatively, multiphoton photoluminescence can be used to perform three-dimensional reconstruction of the dislocation lines in the damaged area and the original area of ​​the channel layer, and the length of the dislocation lines per unit volume can be counted to directly calculate the dislocation density.

[0136] After the damaged area is subjected to high-temperature gas atmosphere annealing treatment, not only the dislocation density in the area can be reduced, but also the surface roughness of the area can be reduced. For example, as shown in Figures 10A and 10B, Figure 10A exemplarily shows a schematic diagram of dislocations before the damaged area is repaired, and Figure 10B exemplarily shows a schematic diagram of dislocations after the damaged area is repaired.

[0137] In FIG10A , the surface roughness RMS of the damaged area is 0.313 nm. After high-temperature gas atmosphere annealing, in FIG10B , the surface roughness RMS of the repaired damaged area drops to less than or equal to 0.2 nm, for example, it can drop to 0.189 nm.

[0138] Therefore, after annealing in a high-temperature gas atmosphere, not only can the crystal arrangement of the damaged area be optimized, the dislocation density be reduced, and the leakage current channel be reduced; the surface roughness of the area can also be reduced, providing a better growth environment for the growth of subsequent film layers.

[0139] At least two process flows for performing high temperature gas atmosphere annealing on the damaged area are given below.

[0140] As shown in Figure 11, Figure 11 exemplarily shows a process condition diagram for high-temperature gas atmosphere annealing. The structure with grooves as shown in Figure 8 is placed in a vacuum device. During the entire annealing process, 5SLM of N2 is continuously introduced. First, the temperature is raised to 550℃-600℃ and maintained for 5min-10min. Then, the temperature is raised to 800℃-1000℃ and maintained for 30min-60min. At the same time, 2SLM of NH3 is introduced during this time period to perform high-temperature annealing treatment on the damaged area.

[0141] For example, in some optional embodiments, the temperature is raised to 550° C. under a 5 SLM N 2 gas flow atmosphere, and then annealed at 930° C. for 30 minutes under a 5 SLM N 2 and 2 SLM NH 3 gas flow atmosphere.

[0142] As shown in Figure 12, Figure 12 exemplifies another process condition diagram for high-temperature annealing. The structure with grooves as shown in Figure 8 is placed in a vacuum device. During the entire annealing process, 5SLM of N2 is continuously introduced. First, the temperature is raised to 550℃-600℃ and maintained for 5min-10min. Then, the temperature is raised to 800℃-1000℃ and maintained for 30min-60min. At the same time, 10-100sccm of TMAl and 2-10SLM of NH3 are introduced during this time period to anneal the damaged area.

[0143] In the two examples above, SLM and SCCM are both gas mass flow units. SLM (Standard Liter per Minute) and SCCM (Standard Cubic Centimeter per Minute) stand for standard liters per minute and standard milliliters per minute, respectively.

[0144] When etching the groove shown in FIG8 , as shown in FIG13 , which illustrates an exemplary AFM scan of a cross-section of the groove, the groove sidewalls are approximately vertical, for example, with a slope of approximately 89°-91°, such as 89°, 89.2°, or 90°. Grooves with approximately vertical sidewalls are beneficial for reducing the nonlinear capacitance of the gate, improving the gate's ability to control the two-dimensional electron gas (2DEG), and increasing the peak transconductance of the device.

[0145] When etching the groove, the etching depth of the groove can be designed according to the thickness of the film structure such as the passivation layer and the barrier layer. This application does not limit the depth of the groove.

[0146] The transistors exemplified in this application may include depletion-mode transistors and enhancement-mode transistors. Enhancement-mode transistors with a positive threshold voltage are widely used because they can simplify circuit structure, reduce costs, and improve system safety and stability.

[0147] The key to achieving an enhancement mode device is to deplete the two-dimensional electron gas (2DEG) at the heterojunction interface under the gate to control the threshold voltage. As shown in FIG14A , FIG14A shows the heterojunction band diagram of the GaN channel layer 103 and the AlGaN barrier layer 105, E f It is the Fermi level. As can be seen from FIG14A , in the heterojunction of the GaN channel layer 103 and the AlGaN barrier layer 105, the conduction band at the heterojunction below the gate is below the Fermi level, that is, the heterojunction has a certain two-dimensional electron gas 2DEG concentration. In order to deplete the two-dimensional electron gas 2DEG concentration at the heterojunction interface below the gate, as shown in FIG14B , the conduction band at the interface between the AlGaN layer and the GaN is raised above the Fermi level, the two-dimensional electron gas 2DEG concentration at the channel is reduced, the effective conduction channel below the gate is pinched off, and an enhancement-mode device is realized. As shown in FIG15 , an epitaxial layer 201 can be provided between the gate 501 and the channel layer 103, and the epitaxial layer 201 is utilized to deplete the two-dimensional electron gas 2DEG concentration at the heterojunction interface below the gate.

[0148] As in the above example, after the damaged area caused by etching is repaired, as shown in FIG15 , the epitaxial layer 201 can be formed on the surface of the repaired area 301. That is, the epitaxial layer 201 is directly stacked on the surface of the repaired area 301.

[0149] The high-temperature gas atmosphere annealing treatment reduces the dislocation density in the repaired region 301 and improves the surface roughness of the repaired region 301. This improves the growth quality of the epitaxial layer 201 during growth, weakens the extension of dislocations in the epitaxial layer 201, and thereby improves the crystallization quality of the epitaxial layer 201 and reduces stress relaxation in the epitaxial layer. This improves the performance of the entire enhancement-mode device.

[0150] For example, in some examples, the dislocation density of the epitaxial layer 201 can be as low as 10 7 / cm 2, an order of magnitude lower than the unoptimized version. Reducing dislocation density can prevent stress relaxation in the epitaxial layer and enhance piezoelectric polarization. At the same time, low dislocation density can reduce electron scattering in the 2DEG channel, increasing carrier mobility and, in turn, helping to improve the device's saturation current density and power density.

[0151] In this example, the epitaxial layer 201 is used to deplete the 2DEG concentration at the heterojunction interface below the gate 501. Since the epitaxial layer 201 is stacked on the surface of the repaired region 301, the 2DEG concentration at the heterojunction interface in at least a portion of the repaired region 301 can be suppressed, as can the 2DEG concentration in the area surrounding the repaired region 301.

[0152] Some structures that can be realized by the epitaxial layer 201 provided in this application are described below with reference to the accompanying drawings.

[0153] As shown in FIG16 , FIG16 is an enlarged view of point A in FIG15 . In this embodiment, the epitaxial layer 201 includes an InGaN layer 2011 and an AlGaN layer 2012 stacked.

[0154] In this example, both the InGaN layer and the AlGaN layer are single-crystalline layers.

[0155] In some examples, as shown in FIG16 , the AlGaN layer 2012 is closer to the channel layer 103 than the InGaN layer 2011. In other examples, the InGaN layer 2011 is closer to the channel layer 103 than the AlGaN layer 2012. In other words, the positions of the AlGaN layer and the InGaN layer can be interchanged.

[0156] In the example shown in FIG16 , the GaN channel layer 103, the AlGaN layer 2012 and the InGaN layer 2011 are stacked. Since the lattice constant relationship between AlGaN, InGaN and GaN is InGaN>GaN>AlGaN, as shown in FIG17 , FIG17 shows a schematic diagram of polarization induction of AlGaN, InGaN and GaN. The direction of the piezoelectric polarization induced electric field of InGaN is opposite to that of AlGaN. For example, in FIG17 , the piezoelectric polarization induced electric field P of InGaN is opposite to that of AlGaN. PE Direction upward, AlGaN piezoelectric polarization induced electric field P PE The direction is downward, so the overall polarization induced electric field of the epitaxial layer 201 will be reduced, as shown in Figure 18. Figure 18 shows the energy band structure diagram of the AlGaN and GaN heterojunction in Figure 17. It can be seen from Figure 18 that the present application utilizes stacked AlGaN layers and InGaN layers to improve the conduction band energy level at the interface between AlGaN and GaN and deplete the two-dimensional electron gas in the channel, thereby realizing an enhancement-mode device.

[0157] In some embodiments, the polarization-induced electric field of the overall device structure of InGaN, AlGaN, and GaN can be reduced by adjusting the composition of the AlGaN layer and the InGaN layer.

[0158] For example, In in the InGaN layer x Ga 1-x N, 0.1≤x≤0.3, for example, the In component can be 18%, that is, In 0.18 Ga 0.82 N, or In composition can be 20%, that is, In 0.2 Ga 0.8 N. Al in AlGaN layer y Ga 1-y N, 0.15≤y≤0.3, for example, the Al component can be 20%, that is, Al 0.2 Ga 0.8 N, or Al composition can be 25%, that is, In 0.25 Ga 0.75 N.

[0159] In other examples, the polarization-induced electric field of the overall device structure of InGaN, AlGaN, and GaN can be reduced by adjusting the thickness of the AlGaN layer and the InGaN layer.

[0160] For example, x Ga 1-x The thickness d1 of the N layer is: 4nm≤d1≤6nm, for example, d1=5nm, or d1=4.5nm. y Ga 1-y The thickness d2 of the N layer is: 2 nm ≤ d2 ≤ 4 nm, for example, d2 = 3 nm, or d2 = 3.5 nm.

[0161] Returning to FIG15 , since the epitaxial layer 201 including the AlGaN layer and the InGaN layer is directly stacked on the surface of the repaired repair area 301 of the channel layer 103, when the AlGaN layer 2012 is grown, the GaN with a smaller dislocation density, a more orderly lattice arrangement, and a flatter GaN surface can promote a more orderly crystal arrangement of the AlGaN, thereby improving the crystallization quality of the AlGaN. Similarly, when InGaN is grown on the AlGaN, the crystallization quality of the InGaN is also improved due to the more orderly crystal arrangement of the AlGaN, thereby improving the crystallization quality of the entire epitaxial layer 201, thereby improving the performance of the enhancement-mode device.

[0162] FIG19 is a structural diagram of another epitaxial layer 201 according to an embodiment of the present application. In this embodiment, the epitaxial layer 201 includes not only the AlGaN layer 2012 and the InGaN layer 2011, but also a GaN layer 2013. The GaN layer 2013 is disposed on the surface of the repair region 301 of the channel layer 103, and the AlGaN layer 2012 and the InGaN layer 2011 are stacked on the GaN layer 2013. For example, in FIG19 , the GaN layer 2013, the AlGaN layer 2012, and the InGaN layer 2011 are stacked in sequence.

[0163] Before growing AlGaN and InGaN, GaN may be grown first as shown in FIG19 . GaN may further reduce the surface damage of the repair region 301 and reduce the scattering effect of the region on carriers, thereby ensuring that the carrier mobility is not affected.

[0164] In the example of FIG. 19 , the thickness of the GaN layer 2013 may be 1 nm to 4 nm, for example, 2 nm.

[0165] 20 is a structural diagram of another epitaxial layer 201 according to an embodiment of the present application. In this embodiment, the epitaxial layer 201 includes an InAlGaN layer 2014, which is stacked on the surface of the repair region 301 of the channel layer 103. The InAlGaN layer is a single crystalline layer.

[0166] As shown in Figure 21, Figure 21 shows the polarization induction diagram of InAlGaN and GaN, and the piezoelectric polarization induced electric field P of InAlGaN PE Basically 0, therefore, the overall polarization induced electric field of the epitaxial layer 201 will be reduced, as shown in FIG22 , which shows the InAlGaN and GaN heterojunction band structure diagram in FIG21 . It can be seen from FIG22 that the present application utilizes stacked InAlGaN layers and GaN layers to increase the conduction band energy level at the interface between InAlGaN and GaN and deplete the two-dimensional electron gas in the channel, thereby realizing an enhancement-mode device.

[0167] In some examples, the polarization-induced electric field of the overall InAlGaN and GaN device structure can be reduced by adjusting the InAlGaN composition, thereby realizing an enhancement-mode device.

[0168] For example, In in the InAlGaN layer z Al w Ga 1-z-w N layer; wherein 0.01≤z≤0.2, 0.6≤w≤0.9. For example, the In component can be 5% and the Al component can be 75%, that is, In 0.05 Al 0.75 Ga0.2 Alternatively, the N composition may be 3% and the In composition may be 62%.

[0169] In other examples, the thickness of InAlGaN can be adjusted to reduce the polarization-induced electric field of the overall device structure of InAlGaN and GaN, thereby realizing an enhancement-mode device.

[0170] For example, z Al w Ga 1-z-w The thickness d3 of the N layer is: 6 nm ≤ d3 ≤ 8 nm, for example, d3 = 7 nm, or d3 = 7.5 nm.

[0171] In the example of FIG20 , since the InAlGaN layer is directly stacked on the surface of the repaired repair region 301 of the channel layer 103 , when the InAlGaN layer is grown, GaN with a smaller dislocation density, a more orderly lattice arrangement, and a flatter GaN surface can promote a more orderly crystal arrangement of the InAlGaN, thereby improving the crystallization quality of the InAlGaN.

[0172] Figure 23 shows the structure of another epitaxial layer 201 according to an embodiment of the present application. In this embodiment, epitaxial layer 201 includes not only an InAlGaN layer 2014 but also a GaN layer 2013. GaN layer 2013 is stacked on the surface of repaired region 301 of channel layer 103, and InAlGaN layer 2014 is stacked on GaN layer 2013. Both the InAlGaN layer and the GaN layer are single crystalline layers.

[0173] Before growing InAlGaN, GaN may be grown first as shown in FIG. 23 . GaN may further reduce surface damage in the repair region 301 and reduce the scattering effect of the region on carriers, thereby ensuring that carrier mobility is not affected.

[0174] As shown in FIG24 , when the epitaxial layer 201 is grown in the groove and on the surface of the repair area 301 , the epitaxial layer 201 is in a single crystalline state. Since the passivation layer 106 is in an amorphous non-crystalline state, the epitaxial layer 202 located on the passivation layer 106 is in an amorphous state.

[0175] 24 and 25 , after the epitaxial layer 201 is grown, a gate dielectric layer 401 may be grown. The gate dielectric layer 401 may be made of at least one of Al2O3, HfO2, SiO2, Si3N4, and ZrO2.

[0176] In one example, the gate dielectric layer 401 covers the surface of the epitaxial layer 201 and the sidewalls of the groove. Alternatively, the gate dielectric layer 401 can also be formed on the amorphous epitaxial layer 202.

[0177] In some process steps, the growth of the gate dielectric layer 401 and the growth of the epitaxial layer 201, as well as damage repair, can be performed in the same vacuum equipment. In this way, interface state problems caused by air exposure and environmental contamination can be avoided, thereby reducing the interface trap state density between the gate dielectric layer 401 and the epitaxial layer 201 and reducing the threshold voltage fluctuation caused by a large number of traps.

[0178] For example, the gate dielectric layer 401 may be formed by atomic layer deposition (ALD).

[0179] After the gate dielectric layer 401 is formed, it can be annealed. The annealing atmosphere can be, but is not limited to, a mixture of one or more gases selected from hydrogen, silane, ammonia, and nitrogen. The annealing time s is ≤ 30 minutes, and the annealing temperature t is ≤ 800° C. This can further improve the interface state between the gate dielectric layer 401 and the epitaxial layer 201.

[0180] In some process steps, the annealing temperature t is 500° C. ≤ t ≤ 800° C., for example, the annealing temperature may be 600° C. The annealing time s is 2 minutes ≤ s ≤ 30 minutes, for example, the annealing time may be 5 minutes, 10 minutes, or 20 minutes.

[0181] After growing the gate dielectric layer 401, a gate 501 can be formed as shown in Figure 26. In some processes, the gate can be deposited by sputtering or evaporation, and the gate 501 pattern is formed by patterning and etching; then the ohmic contact source 502 and drain 503 are formed.

[0182] In another achievable manner, the ohmic contact source 502 and the drain 503 may be formed before etching the grooves.

[0183] The ohmic contact of the source 502 and the drain 503 may be realized by high temperature annealing, ion implantation or secondary epitaxy.

[0184] When high temperature annealing is used to make the ohmic contact source 502 and drain 503, Ti layer, Al layer, Ni layer and Au layer can be prepared in sequence, and the ohmic metal can be subjected to high temperature annealing treatment at 800-900°C to obtain the ohmic contact of the source and drain.

[0185] For the ion implantation ohmic contact solution, the ohmic definition area is first subjected to ion implantation. The implanted ions may be at least one of elements such as Si and Ge, and an annealing activation treatment is performed at a high temperature above 1000°C.

[0186] For the production of ohmic contacts using secondary epitaxial growth technology, epitaxial growth can be performed at high temperatures above 1000°C.

[0187] In some examples, in the structure shown in FIG26 , since an amorphous epitaxial layer 202 is grown on the surface of the passivation layer 106 when the epitaxial layer 201 is grown, in the transistor, an amorphous epitaxial layer 202 , a gate dielectric layer 401 and a gate 501 stacked in sequence are formed on the surface of the passivation layer 106 .

[0188] In the present application, since the gate dielectric layer 401 and the epitaxial layer 201 can be grown and the damage repair can be carried out in the same vacuum equipment, the gate interface trap state density can be reduced. For example, in some transistors manufactured, the gate interface trap state density is ρ, 5×10 11 eV -1 cm -2 ≤ρ≤5×10 13 eV -1 cm -2 .

[0189] Compared with producing epitaxial layers and gate dielectric layers in different vacuum equipment, the present application can solve the problem of high gate interface state density in the existing process. The low interface state density of the gate in the present application can reduce the trap effect, reduce the fluctuation and hysteresis of the threshold voltage, and reduce the design difficulty of the bias power supply circuit, thereby improving the reliability and stability of the application of the enhancement mode GaN-HEMT device system.

[0190] The interface trap state density can be obtained by performing CV testing (i.e., capacitance-voltage testing) on ​​the gate, source, and drain, and calculating the interface trap state density based on the CV curves at different frequencies.

[0191] Figure 27 is a structural diagram of another transistor according to an embodiment of the present application. This embodiment differs from the above embodiments in that, in this example, a gate dielectric layer is not required. After growing the epitaxial layer 201, the gate 501 can be formed. Specifically, the gate 501 is directly stacked on the epitaxial layer 201, forming a Schottky gate HEMT device. This reduces the gate interface and improves the consistency of the device's threshold voltage.

[0192] In some optional embodiments, the gate 501 is deposited by sputtering or evaporation. The gate 501 can be a layer of metal, or multiple layers of stacked metal, for example, a stack of Ni layers and Au layers, or a Pt layer and Au layers.

[0193] A metal with a high work function can be used as the gate 501. For example, the work function of Ni can be 5.15 eV, and the work function of Pt can be 5.65 eV. In this way, the work function difference ΦB between the metal gate 501 and the semiconductor epitaxial layer 201 can be effectively increased, thereby increasing the threshold voltage to realize an enhancement-mode HEMT device.

[0194] In the example of FIG27 , the epitaxial layer 201 can be selected from any of the examples in FIG16 , FIG19 , FIG20 , and FIG23 . For example, the epitaxial layer 201 in this example can include a stacked GaN layer and an InAlGaN layer. In other examples, different epitaxial layer structures can also be used.

[0195] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0196] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A transistor, characterized in that: include: substrate; a channel layer formed on the substrate; a barrier layer formed on the channel layer; A gate, pointing from the barrier layer to the channel layer, the gate penetrating at least a portion of the barrier layer; The channel layer includes: a first region corresponding to the gate position, and a second region located around the first region; The dislocation density of the first region is less than or equal to the dislocation density of the second region.

2. The transistor according to claim 1, characterized in that The dislocation density of the first region is a1×10 8 / cm 2 , the dislocation density of the second region is a2×10 9 / cm 2 , where 1≤a1<10, and 1≤a2<10.

3. The transistor according to claim 1 or 2, characterized in that: An epitaxial layer is disposed on the surface of the first region of the channel layer, and the gate is located on a side of the epitaxial layer away from the first region; The epitaxial layer is used to deplete the two-dimensional electron gas concentration in the heterojunction region under the gate, and the heterojunction region under the gate includes at least the first region.

4. The transistor according to claim 3, characterized in that The material of the epitaxial layer includes at least one of InGaN, AlGaN and InAlGaN.

5. The transistor according to claim 3 or 4, characterized in that: The epitaxial layer includes stacked In x Ga 1-x N layer and Al y Ga 1-y N layers; Among them, 0.1≤x≤0.3, 0.15≤y≤0.

3.

6. The transistor according to claim 5, characterized in that In x Ga 1-x The thickness of the N layer d1: 4nm≤d1≤6nm, the Al y Ga 1-y The thickness of the N layer d2: 2nm≤d2≤4nm.

7. The transistor according to claim 5 or 6, characterized in that: The epitaxial layer also includes a GaN layer. From the channel layer to the barrier layer, the GaN layer, the Al y Ga 1-y N layer and the In x Ga 1-x N layers are stacked in sequence.

8. The transistor according to claim 3 or 4, characterized in that: The epitaxial layer includes In z Al w Ga 1-z-w N layers; among them, 0.01≤z≤0.2, 0.6≤w≤0.

9.

9. The transistor according to claim 8, characterized in that In z Al w Ga 1-z-w The thickness of the N layer d3: 6nm≤d3≤8nm.

10. The transistor according to claim 8 or 9, characterized in that: The epitaxial layer further includes a GaN layer, and in a direction from the channel layer to the barrier layer, the GaN layer and the In z Al w Ga 1-z-w N layers are stacked in sequence.

11. The transistor according to any one of claims 3 to 10, characterized in that: The transistor further comprises a gate dielectric layer, and the gate dielectric layer is arranged between the interface between the gate and the epitaxial layer.

12. The transistor according to any one of claims 1 to 11, characterized in that The interface trap state density of the gate is ρ,5×10 11 house -1 cm -2 ≤ρ≤5×10 13 house -1 cm -2 。 13. A method for preparing a transistor, characterized in that: The preparation method comprises: Forming a channel layer on a substrate, and forming a barrier layer on the channel layer; Opening a groove, wherein the groove passes through the barrier layer so that the first region of the channel layer is exposed; Repairing damage to the first region so that a dislocation density in the first region of the channel layer is less than or equal to a dislocation density in a second region, the second region being located around the first region; A gate is formed in the groove.

14. The method for preparing a transistor according to claim 13, characterized in that: Repairing damage to the first region includes: annealing in a gas atmosphere; Wherein, the gas includes at least one of hydrogen, silane, ammonia, nitrogen, and trimethylaluminum; Annealing time s, s ≥ 30 minutes; Annealing temperature t, t≥800℃.

15. The method for preparing a transistor according to claim 14, characterized in that: The annealing in a gas atmosphere comprises: The first gas is introduced, the temperature is raised to t1 degrees Celsius, and maintained for s1 minutes, 500°C≤t1≤600°C, 5 minutes≤s1≤10 minutes; The second gas and the first gas are introduced, the temperature is raised to t2 degrees Celsius, and maintained for s2 minutes, 800°C≤t2≤1000°C, 30 minutes≤s2≤60 minutes; The first gas includes nitrogen, and the second gas includes at least one of hydrogen, silane, nitrogen, and trimethylaluminum.

16. The method for preparing a transistor according to any one of claims 13 to 15, characterized in that: After the first region is damaged and repaired, the dislocation density of the first region is a1×10 8 / cm 2 , the dislocation density of the second region is a2×10 9 / cm 2 , the surface roughness of the first region is less than or equal to 0.2 nm; wherein 1≤a1<10, and 1≤a2<10.

17. The method for preparing a transistor according to any one of claims 13 to 16, characterized in that: After repairing the damage of the first region and before forming a gate in the groove, the preparation method further includes: An epitaxial layer is formed in the groove and on the surface of the first region of the channel layer, wherein the epitaxial layer is used to deplete the two-dimensional electron gas concentration in the heterojunction region under the gate, and the heterojunction region under the gate includes at least the first region.

18. The method for preparing a transistor according to claim 17, characterized in that: Producing the epitaxial layer in the groove and on the surface of the first region of the channel layer, comprising: In the groove and on the surface of the first region of the channel layer, a stacked In x Ga 1-x N layer and Al y Ga 1-y N layers; Among them, 0.1≤x≤0.3, 0.15≤y≤0.

3.

19. The method for preparing a transistor according to claim 17, characterized in that: Producing the epitaxial layer in the groove and on the surface of the first region of the channel layer, comprising: In the groove and on the surface of the first region of the channel layer, an In z Al w Ga 1-z-w N layers; among them, 0.01≤z≤0.2, 0.6≤w≤0.

9.

20. The method for preparing a transistor according to claim 18 or 19, characterized in that: The stacked In x Ga 1-x N layer and Al y Ga 1-y N layers, or, make In z Al w Ga 1-z-w Before the Nth layer, the preparation method further comprises: A GaN layer is formed on the surface of the first region of the channel layer.

21. The method for preparing a transistor according to any one of claims 17 to 20, characterized in that: After forming the epitaxial layer in the groove and on the surface of the first region of the channel layer and before forming the gate in the groove, the preparation method further includes: Producing a gate dielectric layer on the epitaxial layer; The gate is manufactured on the gate dielectric layer.

22. The method for preparing a transistor according to claim 21, characterized in that: After forming a gate dielectric layer on the epitaxial layer and before forming a gate on the gate dielectric layer, the preparation method further comprises: Annealing in a gas atmosphere; Wherein, the gas includes at least one of hydrogen, silane, ammonia and nitrogen; Annealing time s, s≤30 minutes; Annealing temperature t, t≤800℃.

23. The method for preparing a transistor according to claim 21 or 22, characterized in that: In the same vacuum equipment, repairing the damage of the first region, producing the epitaxial layer, and producing the gate dielectric layer; The interface trap state density of the gate is ρ, 5×10 11 eV -1 cm -2 ≤ρ≤5×10 13 eV -1 cm -2 .

24. An electronic device, characterized in that: include: substrate; A transistor as claimed in any one of claims 1 to 12, or a transistor made by the method for making a transistor as claimed in any one of claims 13 to 23; Wherein, the transistor is arranged on the substrate.

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