High electron mobility transistor device and manufacturing method thereof

Abstract

The invention provides a high electron mobility transistor device and a manufacturing method thereof. The high electron mobility transistor device comprises a substrate, a gate structure, a source structure, a drain structure and a Schottky diode. The substrate has a gallium nitride layer. The gate structure is disposed over the substrate. The source electrode structure and the drain electrode structure are arranged on the two sides of the gate electrode structure. The Schottky diode includes a first Schottky contact metal layer and an ohmic contact metal layer. The first Schottky contact metal layer is adjacent to the source structure and is electrically coupled with the gate structure. The ohmic contact metal layer is adjacent to the first Schottky contact metal layer and is electrically coupled with the source structure.

Description

Technical Field

[0001] The present application relates to semiconductor manufacturing technology, and more particularly to a high electron mobility transistor device and a manufacturing method thereof. Background Art

[0002] A high electron mobility transistor (HEMT) is a field effect transistor that includes semiconductor materials with different energy gaps and generates a two-dimensional electron gas (2DEG) at the interface formed by the different semiconductor materials. Since the two-dimensional electron gas has high mobility, the high electron mobility transistor can have advantages such as high breakdown voltage, high electron mobility, low on-resistance and low input capacitance, and is therefore suitable for high power devices.

[0003] In an ideal situation, when a high electron mobility transistor device is in an on state, the gate voltage is 0. However, in actual operation, there may be voltage surges. Such voltage surges may cause characteristic changes and are difficult to monitor. Therefore, there is a need to further improve high electron mobility transistor devices and methods for manufacturing the same. Summary of the invention

[0004] According to some embodiments of the present application, a high electron mobility transistor device is provided. The high electron mobility transistor device includes a substrate, a gate structure, a source structure, a drain structure, and a Schottky diode. The substrate has a gallium nitride layer. The gate structure is disposed above the substrate. The source structure and the drain structure are disposed on both sides of the gate structure. The Schottky diode includes a first Schottky contact metal layer and an ohmic contact metal layer. The first Schottky contact metal layer is adjacent to the source structure and electrically coupled to the gate structure. The ohmic contact metal layer is adjacent to the first Schottky contact metal layer and electrically coupled to the source structure.

[0005] According to some other embodiments of the present application, a method for manufacturing a high electron mobility transistor device is provided. The method for manufacturing the high electron mobility transistor device includes forming a gate structure on a substrate, wherein the substrate has a gallium nitride layer; forming a source structure and a drain structure on both sides of the gate structure; forming a first Schottky contact metal layer adjacent to the source structure and electrically coupled to the gate structure; and forming an ohmic contact metal layer adjacent to the first Schottky contact metal layer and electrically coupled to the source structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The following detailed description in conjunction with the accompanying drawings can better understand the aspects of the embodiments of the present application. It should be emphasized that, according to standard practices in the industry, many components are not drawn to scale. In fact, in order to clearly discuss, the sizes of various components may be arbitrarily increased or decreased.

[0007] Figure 1A to Figure 1D are cross-sectional views illustrating various stages of forming a high electron mobility transistor device according to some embodiments.

[0008] Figure 2 is a circuit diagram of a high electron mobility transistor device according to some embodiments.

[0009] Figure 3 FIG. 1 is a top view of a high electron mobility transistor device according to some embodiments.

[0010] Figure 4 FIG. 1 is a top view of a high electron mobility transistor device according to some embodiments.

[0011] Figure 5 FIG. 1 is a top view of a high electron mobility transistor device according to some embodiments.

[0012] Figure 6 FIG. 1 is a top view of a high electron mobility transistor device according to some embodiments.

[0013] Explanation of symbols

[0014] 100,300,400,500,600: High Electron Mobility Transistor Devices

[0015] 102: Base

[0016] 104: Isolation Structure

[0017] 106: Gate dielectric layer

[0018] 107,108,109: Ohmic contact metal layer

[0019] 110,114: Schottky contact metal layer

[0020] 112: Interlayer dielectric layer

[0021] 116,124: Intermetallic dielectric layer

[0022] 117,118,119,120,122: Field plate layer

[0023] 126,127,128,129: Metal layer

[0024] 128t: Extension

[0025] 130: Passivation layer

[0026] 302: Quarantine

[0027] 304: Active Zone

[0028] 306: Wiring layer

[0029] D: Drain structure

[0030] G: Gate structure

[0031] S: Source structure

[0032] SBD: Schottky diode

[0033] I-I': line

[0034] +V: Positive voltage surge DETAILED DESCRIPTION

[0035] Some embodiments are summarized below so that those skilled in the art can more easily understand the present application. However, these embodiments are only examples and are not intended to limit the present application. It is understood that those skilled in the art can adjust the embodiments described below as needed, such as changing the process sequence and / or including more or fewer steps than described herein, and these adjustments do not exceed the scope of the present application.

[0036] In addition, other elements may be added based on the embodiments described below. For example, the description of "forming a second element on a first element" may include an embodiment in which the first element is in direct contact with the second element, and may also include an embodiment in which there are other elements between the first element and the second element so that the first element and the second element are not in direct contact, and the upper and lower relationship between the first element and the second element may change as the device is operated or used in different orientations.

[0037] In the following description, the description of "a first element passing through a second element" may include that the first element is disposed in the second element and extends from a first side of the second element to an opposite second side, wherein a surface of the first element may be flush with a surface of the second element, or a surface of the first element may be outside a surface of the second element. In addition, the present application may repeat reference numbers and / or letters in different embodiments, and this repetition is for simplicity and clarity, rather than for indicating the relationship between the different embodiments discussed.

[0038] According to some embodiments of the present application, a high electron mobility transistor device and a method for manufacturing the same are described below, and are particularly applicable to a metal-insulator-semiconductor high-electron-mobility-transistor (MIS-HEMT) device. According to the high electron mobility transistor device of the embodiment of the present application, a Schottky Barrier Diode (SBD) is provided between the source structure and the gate structure, which can guide the positive voltage surge of the gate structure to the source structure, thereby protecting the dielectric layer.

[0039] Figure 1A to Figure 1D 1 is a cross-sectional view of various stages of forming a high electron mobility transistor device 100 according to some embodiments of the present application. Additional components may be added to the high electron mobility transistor device 100. For different embodiments, some components and / or steps described below may be replaced or eliminated. To simplify the drawings, only a portion of the high electron mobility transistor device 100 is shown.

[0040] Reference Figure 1A , providing a substrate 102. The substrate 102 may include any substrate material suitable for a high electron mobility transistor device, and may be a monolithic semiconductor substrate or a composite substrate formed of different materials. One or more semiconductor elements (including active elements and / or passive elements) may be pre-formed on the substrate 102, and in order to simplify the diagram, only a flat substrate 102 is used to represent it. In the description of the present application, the term "substrate" may include elements formed on a semiconductor wafer and various coatings covering the semiconductor wafer. According to some embodiments, the substrate 102 has a gallium nitride layer. The gallium nitride layer may be undoped.

[0041] Then, according to some embodiments, a mask layer (not shown) is disposed above the substrate 102, and then an etching process is performed using the mask layer as an etching mask to etch a groove in the substrate 102. For example, the mask layer may include a photoresist, such as a positive photoresist or a negative photoresist. The mask layer may include a hard mask and may be formed of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide, similar materials, or a combination of the foregoing. The mask layer may be a single layer or a multilayer structure.

[0042] The formation of the mask layer may include a deposition process, a photolithography process, other suitable processes, or a combination thereof. In some embodiments, the deposition process includes spin coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), similar processes, or a combination thereof. For example, the photolithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking (PEB), development, rinsing, drying (e.g., hard baking), other suitable processes, or a combination thereof.

[0043] In some embodiments, the etching process may include a dry etching process, a wet etching process, or a combination thereof. For example, the dry etching process may include reactive ion etching (RIE);

[0044] The wet etching process may be RIE, inductively-coupled plasma (ICP) etching, neutral beam etch (NBE), electron cyclotron resonance (ERC) etching, similar etching processes, or combinations thereof. For example, the wet etching process may use hydrofluoric acid, ammonium hydroxide, or any suitable etchant.

[0045] Then, according to some embodiments, an insulating material is deposited in the trench to form an isolation structure 104. The deposition of the insulating material may include spin coating, chemical vapor deposition, atomic layer deposition, similar processes, or a combination thereof. The insulating material may include an oxide such as silicon oxide, a nitride such as silicon nitride, similar materials, or a combination thereof. The isolation structure 104 may be a single-layer or multi-layer structure, for example, with a dielectric liner.

[0046] Then, according to some embodiments, a gate dielectric layer 106 is formed over the substrate 102. The gate dielectric layer 106 may be formed by forming a dielectric material using a suitable deposition process. For example, the formation of the gate dielectric layer 106 may include forming silicon nitride by a low pressure chemical vapor deposition (LPCVD) process.

[0047] Then, according to some embodiments, a mask layer (not shown) is disposed above the gate dielectric layer 106, and then an etching process is performed using the mask layer as an etching mask to etch a plurality of trenches through the gate dielectric layer 106. Then, according to some embodiments, an ohmic contact metal material is deposited in the trenches to form ohmic contact metal layers 107, 108, 109. The ohmic contact metal material may include one or more metal materials, such as Ti, Al, Ti / Al / Ni / Au stack, Al / Ti / Pt / Au stack, Pd / Au stack, similar materials, or a combination thereof. The formation of the ohmic contact metal material may use a suitable deposition process, including electroplating, chemical vapor deposition, atomic layer deposition, physical vapor deposition (PVD), similar processes, or a combination thereof.

[0048] Then, a planarization process, such as a chemical mechanical polishing process, may be performed to make the top surfaces of the gate dielectric layer 106 and the ohmic contact metal layers 107 , 108 , 109 substantially coplanar.

[0049] Then, if Figure 1B As shown, according to some embodiments, an interlayer dielectric (ILD) layer 112 is formed on the gate dielectric layer 106. The material of the interlayer dielectric layer 112 may include a low-k dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon nitride carbon, tetraethylorthosilicate (TEOS), fluorinated silicate glass (FSG), similar materials, or a combination thereof. The interlayer dielectric layer 112 may be formed using a suitable deposition process, including spin coating, chemical vapor deposition, atomic layer deposition, similar processes, or a combination thereof.

[0050] Then, according to some embodiments, a mask layer (not shown) is disposed above the interlayer dielectric layer 112, and then an etching process is performed using the mask layer as an etching mask to etch a trench through the gate dielectric layer 106 and the interlayer dielectric layer 112. Then, according to some embodiments, a Schottky contact metal material is deposited in the trench to form the Schottky contact metal layers 110, 114. The Schottky contact metal material may include one or more metal materials, such as aluminum, titanium, molybdenum, gold, nickel, palladium, titanium tungsten (TiW) alloy, tantalum, rhenium (Re), ruthenium, platinum, similar materials, or a combination of the foregoing. The formation of the Schottky contact metal material may use a suitable deposition process, including electroplating, chemical vapor deposition, atomic layer deposition, physical vapor deposition, similar processes, or a combination of the foregoing.

[0051] The Schottky contact metal layer 110 may pass through the interlayer dielectric layer 112 and the gate dielectric layer 106 and may stay on the top surface of the substrate 102. The Schottky contact metal layer 114 may pass through the interlayer dielectric layer 112 and may stay on the top surface of the gate dielectric layer 106.

[0052] Since the substrate 102 includes GaN, an ohmic contact structure and a Schottky contact structure may be simultaneously formed on the substrate 102 by selecting a metal material and / or an interface. Therefore, a Schottky diode may be formed without requiring additional processes.

[0053] In some embodiments, Figure 1B As shown, the thickness of the Schottky contact metal layer 110 is greater than the thickness of the ohmic contact metal layer 107. The present application is not limited thereto. For example, the thickness of the Schottky contact metal layer 110 may be substantially the same as the thickness of the ohmic contact metal layer 107.

[0054] Then, according to some embodiments, an intermetal dielectric (IMD) layer 116 is formed over the interlayer dielectric layer 112. The material of the intermetal dielectric layer 116 may include a low-k dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, tetraethoxysilane (TEOS), fluorosilicate glass (FSG), similar materials, or a combination of the foregoing. The formation of the intermetal dielectric layer 116 may use a suitable deposition process, including spin coating, chemical vapor deposition, atomic layer deposition, similar processes, or a combination of the foregoing. The intermetal dielectric layer 116 may cover the top surface and sidewalls of the Schottky contact metal layers 110 and 114.

[0055] Then, according to some embodiments, a mask layer (not shown) is disposed above the intermetallic dielectric layer 116, and then an etching process is performed using the mask layer as an etching mask to etch a plurality of grooves through the interlayer dielectric layer 112 and the intermetallic dielectric layer 116. Then, according to some embodiments, a metal material is deposited in the grooves to form field plate layers 117, 118, 119, 120, 122. The metal material may include TiN, Ti, Al, AlCu, Cu, similar materials, or a combination thereof. The formation of the metal material may use a suitable deposition process, including electroplating, chemical vapor deposition, atomic layer deposition, physical vapor deposition, similar processes, or a combination thereof.

[0056] The field plate layers 117, 118, 119 may contact the ohmic contact metal layers 107, 108, 109, respectively, and may be electrically coupled to the ohmic contact metal layers 107, 108, 109, respectively. The field plate layer 120 may contact the Schottky contact metal layer 110, and may be electrically coupled to the Schottky contact metal layer 110. The field plate layer 122 may be disposed above the Schottky contact metal layer 114, and may be electrically coupled to the Schottky contact metal layer 114 or the field plate layer 118.

[0057] Then, if Figure 1C As shown, according to some embodiments, an intermetallic dielectric layer 124 is formed on the intermetallic dielectric layer 116. The intermetallic dielectric layer 124 can be made of the same material and formation process as described above for the intermetallic dielectric layer 116, so it will not be described again. The intermetallic dielectric layer 124 can cover the top surface and sidewalls of the field plate layers 117, 118, 119, 120, and 122.

[0058] Then, according to some embodiments, a mask layer (not shown) is disposed above the intermetallic dielectric layer 124, and then an etching process is performed using the mask layer as an etching mask to etch a plurality of grooves in the intermetallic dielectric layer 124. Then, according to some embodiments, a metal material is deposited in the grooves to form metal layers 126, 127, 128, and 129. The metal material may include TiN, Ti, Al, AlCu, Cu, similar materials, or a combination thereof. The formation of the metal material may use a suitable deposition process, including electroplating, chemical vapor deposition, atomic layer deposition, physical vapor deposition, similar processes, or a combination thereof.

[0059] Metal layer 126 may contact field plate layer 117 and may be electrically coupled with field plate layer 117. Metal layer 127 may contact field plate layer 120 and may be electrically coupled with field plate layer 120. Metal layer 128 may contact field plate layer 118 and may be electrically coupled with field plate layer 118. Metal layer 129 may contact field plate layer 119 and may be electrically coupled with field plate layer 119.

[0060] According to some embodiments, the metal layer 128 has an extension portion 128t extending above the field plate layer 122 toward the metal layer 129. The extension portion 128t can serve as a source field plate. The extension portion 128t can extend beyond the edge of the field plate layer 122. The extension portion 128t is optional, and according to other embodiments, the metal layer 128 does not have the extension portion 128t.

[0061] Then, if Figure 1DAs shown, according to some embodiments, a passivation layer 130 is formed over the intermetallic dielectric layer 124. The material of the passivation layer 130 may include a low dielectric constant dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, tetraethoxysilane (TEOS), fluorosilicon glass (FSG), similar materials, or a combination of the foregoing. The formation of the passivation layer 130 may use a suitable deposition process, including spin coating, chemical vapor deposition, atomic layer deposition, similar processes, or a combination of the foregoing. The passivation layer 130 may cover the top surface and sidewalls of the metal layers 126, 127, 128, and 129.

[0062] Then, according to some embodiments, a mask layer (not shown) is disposed above the passivation layer 130, and then an etching process is performed using the mask layer as an etching mask to etch a contact opening in the passivation layer 130. The contact opening is electrically coupled with the metal layers 126, 127, 128, and 129 to form a source structure S, a drain structure D, a gate structure G, and a Schottky diode SBD. The source structure S may include an ohmic contact metal layer 108, a field plate layer 118, and a metal layer 128. The drain structure D may include an ohmic contact metal layer 109, a field plate layer 119, and a metal layer 129. The gate structure G may include a Schottky contact metal layer 114. The field plate layer 122 may be a part of the source structure S or the gate structure G.

[0063] The Schottky diode SBD may include an ohmic contact metal layer 107, a field plate layer 117, a metal layer 126, a Schottky contact metal layer 110, a field plate layer 120, and a metal layer 127. The ohmic contact metal layer 107, the field plate layer 117, and the metal layer 126 are electrically coupled to the source structure S. The Schottky contact metal layer 110, the field plate layer 120, and the metal layer 127 are electrically coupled to the gate structure G. Therefore, as Figure 2 As shown, the excessive positive voltage surge +V passing through the gate structure G can be guided to the source structure S via the Schottky diode SBD to protect the gate dielectric layer 106 , especially the area directly below the Schottky contact metal layer 114 .

[0064] Figure 3 FIG. 1 is a top view of a high electron mobility transistor device 300 according to some embodiments of the present application. Figure 1D The high electron mobility transistor device 100 may be along Figure 3 To simplify the diagram, only a portion of the high electron mobility transistor device 300 is shown.

[0065] According to some embodiments, Figure 3 As shown, the high electron mobility transistor device 300 includes an isolation region 302 and an active region 304. The location of the isolation region 302 may correspond to Figure 1DThe isolation structure 104 is located in the middle. The Schottky contact metal layer 110 of the Schottky diode SBD and the plurality of gate structures G are electrically coupled via the wiring layer 306. The high electron mobility transistor device 300 includes a wiring layer (not shown) electrically coupling the ohmic contact metal layer 107 of the Schottky diode SBD and the plurality of source structures S, and another wiring layer (not shown) electrically coupling the plurality of drain structures D.

[0066] Figure 4 4 is a cross-sectional view of a high electron mobility transistor device 400 according to some embodiments of the present application. Additional components may be added to the high electron mobility transistor device 400. For different embodiments, some components described below may be replaced or eliminated. It should be noted that the high electron mobility transistor device 400 may include Figure 3 The same or similar components as those of the HEMT device 300 are not discussed in detail for simplicity. In the following embodiments, the HEMT device 400 includes gate structures with different configurations.

[0067] According to some embodiments, Figure 4 As shown, the gate structure G is disposed to surround the source structure S, thereby avoiding the influence of the contact surface between the active region 304 and the isolation region 302. The gate structure G can be electrically coupled to the Schottky contact metal layer 110 of the Schottky diode SBD via the wiring layer 306.

[0068] Figure 5 1 is a cross-sectional view of a high electron mobility transistor device 500 according to some embodiments of the present application. Additional components may be added to the high electron mobility transistor device 500. For different embodiments, some components described below may be replaced or eliminated. It should be noted that the high electron mobility transistor device 500 may include Figure 3 The same or similar components as those of the HEMT device 300 are shown, and will not be discussed in detail for simplicity. In the following embodiments, the HEMT device 500 includes Schottky diodes of different configurations.

[0069] According to some embodiments, Figure 5 As shown, the Schottky diode SBD is arranged in the same row as a source structure S and is electrically coupled to the gate structure G via the wiring layer 306. The isolation region 302 may be arranged to surround the Schottky diode SBD to be separated from the source structure S and the drain structure D. Therefore, the occupied area of ​​the high electron mobility transistor device 500 may be reduced.

[0070] Specifically, the isolation region 302 may have a first portion 302a and a second portion 302b, wherein the first portion 302a may be disposed between the Schottky diode SBD and a source structure S, and the second portion 302b may be disposed between the Schottky diode SBD and the drain structure D. Figure 5 As shown, the first portion 302a and the second portion 302b may extend in different directions. For example, the extension direction of the first portion 302a may be substantially perpendicular to the extension direction of the second portion 302b.

[0071] Figure 6 6 is a cross-sectional view of a high electron mobility transistor device 600 according to some embodiments of the present application. Additional components may be added to the high electron mobility transistor device 600. For different embodiments, some components described below may be replaced or eliminated. It should be noted that the high electron mobility transistor device 600 may include Figure 3 The same or similar components as those of the HEMT device 300 are shown and will not be discussed in detail for simplicity. In the following embodiments, the HEMT device 600 includes active regions with different configurations.

[0072] According to some embodiments, Figure 6 As shown, the active region 304 is retracted to the bottom of the source structure S and the drain structure D, so that the Schottky diode SBD can be separated from other components without an additional isolation structure. Specifically, the source structure S and the drain structure D can cover the edge of the isolation region 302. Therefore, the occupied area of ​​the high electron mobility transistor device 600 can be reduced.

[0073] In addition, the number of Schottky diodes SBD can be adjusted. Figure 6 As shown, the high electron mobility transistor device 600 may have Schottky diodes SBD on both sides. The embodiment of the present application is not limited thereto, and the high electron mobility transistor device 600 may have more or fewer Schottky diodes SBD. Similarly, the aforementioned high electron mobility transistor devices 100, 300, 400, 500 may also have more Schottky diodes SBD.

[0074] In summary, the high electron mobility transistor device provided by the embodiment of the present application can guide the positive voltage surge of the gate structure to the source structure to protect the dielectric layer by setting a Schottky diode between the source structure and the gate structure. In addition, the Schottky diode can be formed during the formation of the high electron mobility transistor device without the need for additional processes.

[0075] The above summarizes the components of several embodiments so that those skilled in the art can better understand the multiple aspects of the embodiments of the present application. Those skilled in the art should understand that they can easily design or modify other processes and structures based on the embodiments of the present application to achieve the same purpose and / or advantages as the embodiments introduced herein. Those skilled in the art should also understand that such equivalent structures do not deviate from the spirit and scope of the embodiments of the present application, and they can make various changes, substitutions and adjustments without violating the spirit and scope of the embodiments of the present application.

Claims

1. A high electron mobility transistor device, characterized in that: include: a substrate having a gallium nitride layer; a gate structure disposed above the substrate; A source structure and a drain structure are arranged on both sides of the gate structure; as well as A Schottky diode, comprising: a first Schottky contact metal layer adjacent to the source structure and electrically coupled to the gate structure; as well as An ohmic contact metal layer is adjacent to the first Schottky contact metal layer and is electrically coupled to the source structure.

2. The high electron mobility transistor device according to claim 1, wherein: The gate structure comprises: a second Schottky contact metal layer, disposed between the source structure and the drain structure; and A field plate layer is disposed above the second Schottky contact metal layer.

3. The high electron mobility transistor device according to claim 2, characterized in that: The source structure includes a source field plate extending above the field plate layer.

4. The high electron mobility transistor device according to claim 1, wherein: In a top view, the gate structure surrounds the source structure.

5. The high electron mobility transistor device according to claim 1, wherein: Also includes: An isolation area, including: a first portion disposed between the Schottky diode and the source structure; as well as a second portion, disposed between the Schottky diode and the drain structure, In a top view, the first portion and the second portion extend in different directions.

6. The high electron mobility transistor device according to claim 1, wherein: In a top view, the source structure and the drain structure cover an edge of an isolation region.

7. A method for manufacturing a high electron mobility transistor device, characterized in that: include: forming a gate structure on a substrate, wherein the substrate has a gallium nitride layer; forming a source structure and a drain structure on both sides of the gate structure; forming a first Schottky contact metal layer adjacent to the source structure and electrically coupled to the gate structure; as well as An ohmic contact metal layer is formed adjacent to the first Schottky contact metal layer and electrically coupled to the source structure.

8. The method for manufacturing a high electron mobility transistor device according to claim 7, wherein: The ohmic contact metal layer is formed during the formation of the source structure and the drain structure.

9. The method for manufacturing a high electron mobility transistor device according to claim 7, wherein: Also includes: During the formation of the first Schottky contact metal layer, a second Schottky contact metal layer is formed between the source structure and the drain structure.

10. The method for manufacturing a high electron mobility transistor device according to claim 7, wherein: Also includes: An isolation structure is formed in the substrate, wherein the first Schottky contact metal layer and the source structure are arranged on both sides of the isolation structure.

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