Transistor and preparation method thereof

Abstract

The invention discloses a transistor and a preparation method thereof, and belongs to the technical field of semiconductors. The transistor comprises a substrate layer, and a bonding layer, a gate electrode layer, a gate dielectric layer, a channel layer and a source and drain electrode layer which are sequentially stacked on the substrate layer, wherein the gate dielectric layer is made of single crystal lithium tantalate, and the thickness range of the gate dielectric layer is [200 nm, 600 nm]. The technical scheme of the invention aims to provide the transistor capable of realizing broadband response and multi-mode sensing.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a transistor and a method for manufacturing the same. Background Art

[0002] At present, in terms of material selection, the transistors provided in the related art use polymers with poor temperature stability or single crystals that are difficult to prepare in large sizes (for example, PMN-PT, STO) as substrate materials; and use two-dimensional thin films and ferroelectric materials that are difficult to prepare in large sizes as channel layer materials. The material selection of the substrate and the channel layer restricts the large-area integration and preparation of transistors. In terms of transistor performance, the transistors provided by the related art are difficult to achieve color perception of optical signals in continuous bands, and the excitation response is weak.

[0003] Therefore, there is an urgent need for a transistor that can achieve wide-band response and multimodal sensing. Summary of the invention

[0004] The present application provides a transistor and a method for preparing the same, aiming to provide a transistor that can achieve wide-band response and multi-modal perception.

[0005] In a first aspect, the present application provides a transistor, comprising:

[0006] A substrate layer, and a bonding layer, a gate electrode layer, a gate dielectric layer, a channel layer, and a source-drain electrode layer stacked in sequence on the substrate layer;

[0007] The material of the gate dielectric layer includes single crystal lithium tantalate, and the thickness of the gate dielectric layer is in the range of [200nm, 600nm].

[0008] In some embodiments, the material of the channel layer includes: indium gallium zinc oxide;

[0009] Wherein, the thickness range of the channel layer is [10nm, 50nm].

[0010] In some embodiments, the material of the channel layer includes: at least one of molybdenum disulfide, bismuth oxyselenide, and indium selenide;

[0011] Wherein, the thickness range of the channel layer is [1nm, 5nm].

[0012] In some embodiments, the material of the bonding layer includes at least one of organic glue, resin glue, and silicon dioxide film.

[0013] In some embodiments, the source-drain electrode layer comprises a transparent ITO electrode;

[0014] The thickness range of the source-drain electrode layer is [100 nm, 300 nm].

[0015] In some embodiments, the gate electrode layer includes a first metal electrode and a second metal electrode stacked together;

[0016] The combined material of the first metal electrode and the second metal electrode includes a group consisting of Cr and Au, Ti and Au, Cr and Pt, and Ti and Pt.

[0017] In some embodiments, the gate electrode layer has a thickness in the range of [100 nm, 200 nm].

[0018] In some embodiments, the material of the substrate layer includes at least one of silicon, glass, and single-crystal lithium tantalate.

[0019] In some embodiments, a through hole is disposed on the substrate layer.

[0020] On the other hand, the present application also provides a method for preparing a transistor, the method comprising:

[0021] Using an electron beam evaporation process, a gate electrode layer is evaporated on a side of the single crystal lithium tantalate layer close to the substrate layer;

[0022] Bonding the gate electrode layer to the substrate layer via a bonding layer;

[0023] Using Smart-Cut or mechanical thinning process, thinning the single crystal lithium tantalate layer to form a gate dielectric layer;

[0024] forming a through hole on the substrate layer by dry etching or wet etching process;

[0025] A channel layer and a source-drain electrode layer are sequentially formed on the gate dielectric layer by using a magnetron sputtering method or an atomic layer deposition method. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0027] Figure 1 A schematic diagram of the structure of a transistor provided in this application.

[0028] Figure 2 A schematic flow chart of a method for manufacturing a transistor provided in the present application.

[0029] FIG. 3A to FIG. 3F A schematic diagram of a process of manufacturing a transistor provided in the present application. DETAILED DESCRIPTION

[0030] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0031] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, ie, meaning "including, but not limited to."

[0032] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0033] When describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. For example, when describing some embodiments, the term "connection" may be used to indicate that two or more components are in direct physical or electrical contact with each other.

[0034] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0035] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0036] Exemplary embodiments are described herein with reference to cross-sectional views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include deviations in shape due to, for example, manufacturing. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0037] Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0038] With the continuous and rapid development of modern information technology, computer systems have entered the era of "cloud computing" and "big data". The information processing mode of the traditional von Neumann architecture can no longer meet the needs of unstructured data analysis and processing such as massive image recognition and semantic understanding, and the power consumption control of the underlying computing hardware has become one of the problems that need to be solved urgently. In contrast, the biological brain has the advantages of high efficiency, low power consumption, parallel computing, and autonomous cognition. Therefore, the emerging brain-like architecture based on the integration of sensing, storage and computing is expected to break the limitation of frequent data transmission between the processing unit and the external memory in the traditional von Neumann architecture, and is a frontier cross-field for the development of intelligent computers.

[0039] Inspired by the human nervous system, neuromorphic computing systems built based on high-performance artificial electronic synapses and neurons can already realize simple human brain perception functions.

[0040] However, for traditional multimodal sensing devices, the need to deploy multiple sensors in the system significantly increases the complexity of the system and seriously restricts its application in brain-like sensing systems. Therefore, the development of new multimodal sensing and integrated sensing, storage and computing brain-like sensing devices is currently a key frontier direction in the field of neuromorphic research.

[0041] The team led by Associate Professor Zhang Min from the Shenzhen Graduate School of Peking University used a stack of polyvinyl alcohol and silicon dioxide (PVA / SiO2) as the gate dielectric layer and semiconductor single-walled carbon nanotubes as the channel layer to prepare a neuromorphic array with a transistor structure, realizing the preparation of multimodal neuromorphic electronic skin with pressure, temperature sensing and memory functions.

[0042] The research team led by Zheng Renkui from Shanghai Institute of Ceramics, Chinese Academy of Sciences, the research team led by Professor Chai Yang from Hong Kong Polytechnic University, and the research team led by Professor Zhang Tao from Guangzhou University introduced Pb(Mg 1 / 3 Nb 2 / 3 )O3-PbTiO3 (PMN-PT) single crystal is used as the substrate to epitaxially grow two-dimensional Bi2O2Se thin film. The prepared transistor can realize the coincidence detection of infrared light (980nm) and visible light (405nm).

[0043] Although researchers can now realize multimodal sensing functions in a single device (for example, a transistor), it still has obvious limitations. For example, in terms of material selection, there are problems such as poor temperature stability of polymers, difficulty in preparing large-scale uniform two-dimensional films and PMN-PT single crystals. In terms of device performance, there are many problems such as the inability to realize color perception of continuous-band optical signals, difficulty in storing dual-modal information in a single device, and weak excitation response.

[0044] In summary, the transistors provided by the relevant technology are currently used in transistor-type neuromorphic devices, but cannot achieve wide-band response and multimodal perception, which limits the application of transistors provided by the relevant technology in neuromorphic computing systems.

[0045] In order to solve at least one of the above problems, the present application provides a transistor and a method for preparing the same, aiming to provide a transistor that can achieve wide-band response and multi-modal perception.

[0046] Figure 1 A schematic diagram of the structure of a transistor provided in this application, such as Figure 1 As shown, in the first aspect, the present application provides a transistor, which includes: a substrate layer 1, and a bonding layer 2, a gate electrode layer 3, a gate dielectric layer 4, a channel layer 5, and a source-drain electrode layer 6 stacked in sequence on the substrate layer 1.

[0047] The material of the gate dielectric layer 4 includes single crystal lithium tantalate, and the thickness of the gate dielectric layer 4 ranges from [200 nm to 600 nm]. For example, the thickness of the gate dielectric layer 4 can be 200 nm, 250 nm, 300 nm, 360 nm, 390 nm, 420 nm, 480 nm, 500 nm, 560 nm, and 600 nm.

[0048] Furthermore, single-crystal lithium tantalate refers to lithium tantalate (LiTaO3, Lithium Tantalate) having a single crystal structure.

[0049] The present application effectively regulates the carrier transport characteristics in the channel layer 5 by utilizing the pyroelectric effect and ferroelectric polarization effect of single-crystal lithium tantalate (LiTaO3, LT) and the visible light response of the channel layer 5, thereby realizing the preparation of transistors with wide-band response (for example, infrared, ultraviolet) and multi-modal perception (signal perception of light, electricity, and temperature).

[0050] In addition, compared with traditional optoelectronic neuromorphic transistors in related technologies, the present application has temperature sensing capabilities, which can significantly improve the integration and functionality of related neuromorphic computing systems and broaden the application scenarios of single-crystal lithium tantalate-based transistors in fields such as artificial intelligence and the Internet of Things.

[0051] In some embodiments, the material of the channel layer 5 includes: Indium Gallium Zinc Oxide (IGZO).

[0052] Further, the thickness of the channel layer 5 is in the range of [10nm, 50nm]. For example, the thickness of the channel layer 5 can be 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, or 50nm. When the material of the channel layer 5 is indium gallium zinc oxide, when the thickness of the channel layer 5 is in the range of [10nm, 50nm], the performance and stability of the transistor can be improved.

[0053] In some other embodiments, the material of the channel layer 5 may include: one of molybdenum disulfide, bismuth oxyselenide, and indium selenide. For example, the material of the channel layer 5 may be molybdenum disulfide (MoS2), bismuth oxyselenide (Bi2O2Se), or indium selenide (In2Se3).

[0054] Further, the thickness of the channel layer 5 is in the range of [1 nm, 5 nm]. For example, the thickness of the channel layer 5 can be 1 nm, 2 nm, 3 nm, 4 nm, or 5 nm. This configuration can improve the performance and stability of the transistor.

[0055] In some embodiments, the material of the bonding layer 2 includes: organic glue, resin glue, silicon dioxide film. For example, in one example, when the material of the bonding layer 2 is organic glue, the organic glue has good viscosity, which can ensure the close bonding between the substrate layer 1 and the gate electrode layer 3 in the transistor, thereby improving the stability and reliability of the transistor.

[0056] In some embodiments, the source-drain electrode layer 6 includes a transparent ITO electrode, and the thickness of the source-drain electrode layer 6 ranges from [100 nm, 300 nm]. For example, the thickness of the source-drain electrode layer 6 can be 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 180 nm, 200 nm, 230 nm, 250 nm, 280 nm, or 300 nm.

[0057] In some embodiments, the gate electrode layer 3 includes a first metal electrode and a second metal electrode which are stacked.

[0058] Among them, metal electrodes usually have good thermal stability and can withstand higher operating temperatures, thereby improving the thermal stability and reliability of transistors.

[0059] In the embodiment of the present application, by stacking metal electrodes, the electric field distribution under the gate can be more effectively controlled, thereby improving the switching speed of the transistor. The stacked metal electrode structure helps to form a thicker gate insulation layer while maintaining good gate control capability, greatly reducing gate leakage current and reducing static power consumption.

[0060] In addition, the stacked structure of metal electrodes can optimize the work function matching of gate materials, reduce carrier scattering at the interface, and thus improve carrier mobility. And by optimizing the gate electrode structure, the on-current of the transistor can be increased, improving the current driving capability of the device.

[0061] The combined material of the first metal electrode and the second metal electrode includes a group consisting of Cr and Au, Ti and Au, Cr and Pt, and Ti and Pt.

[0062] In the embodiment of the present application, by using metals such as Cr and Ti as the bottom electrode, a good ohmic contact can be formed with the semiconductor material, thereby reducing the contact resistance; by using metals such as Au and Pt as the top electrode, the top electrode has a lower resistivity and good conductivity, which helps to improve the overall electrical performance of the gate electrode.

[0063] In addition, the stacking arrangement can enhance the adhesion between the metal electrode and the semiconductor material, improve the mechanical strength of the gate electrode, and prevent it from falling off or being damaged during subsequent processes or use.

[0064] Of course, in the embodiments of the present application, the performance of the transistor can be further optimized to meet different application requirements by adjusting the number of layers, thickness and material combination of the metal electrode.

[0065] In some embodiments, the thickness of the gate electrode layer 3 is in the range of [100 nm, 200 nm]. For example, the thickness of the gate electrode layer 3 can be 100 nm, 110 nm, 130 nm, 150 nm, 160 nm, 180 nm, 200 nm.

[0066] In some embodiments, the material of the substrate layer 1 includes: one of silicon, glass, and single-crystal lithium tantalate. For example, in one example, the substrate layer 1 can be a silicon substrate, a glass substrate, or a single-crystal lithium tantalate substrate.

[0067] In some embodiments, a through hole V is provided on the substrate layer 1 to dissipate heat from the transistor, thereby ensuring that the transistor can operate stably and reliably.

[0068] In the embodiment of the present application, by reasonably designing the number, size and position of the heat dissipation through holes V, the thermal management of the transistor can be optimized to ensure that the heat can be dissipated evenly and quickly.

[0069] Figure 2 A schematic diagram of a process for preparing a transistor provided in this application, FIG. 3A to FIG. 3F A schematic diagram of a process of manufacturing a transistor provided in this application, such as Figure 2 and FIG. 3A to FIG. 3F As shown, the method includes:

[0070] S1. Using an electron beam evaporation process, a gate electrode layer 3 is deposited on a side of the single crystal lithium tantalate layer close to the substrate layer 1 .

[0071] Among them, electron beam evaporation (Electron Beam Evaporation) is a form of physical vapor deposition (PVD). The principle of electron beam evaporation is to use a high-energy electron beam from a charged tungsten filament to bombard the target material used to prepare the gate electrode layer 3.

[0072] In the embodiment of the present application, the gate electrode layer 3 includes a first metal electrode and a second metal electrode stacked together, and a combination material of the first metal electrode and the second metal electrode includes a group selected from Cr and Au, Ti and Au, Cr and Pt, and Ti and Pt.

[0073] Therefore, the target material for preparing the gate electrode layer 3 may be any one of Cr and Au, Ti and Au, Cr and Pt, and Ti and Pt.

[0074] When the electron beam hits the target material, its energy is converted into heat energy, causing the target material to evaporate and convert it into a gaseous state. In a high vacuum chamber, these evaporated atoms or molecules are then deposited on the substrate to form a gate electrode layer 3.

[0075] S2 , bonding the gate electrode layer 3 to the substrate layer 1 through the bonding layer 2 .

[0076] Furthermore, the material of the bonding layer 2 includes at least one of organic glue, resin glue, and silicon dioxide film.

[0077] In the embodiment of the present application, the gate electrode layer 3 is bonded to the substrate layer 1 through the bonding layer 2. This arrangement can firmly bond the gate electrode layer 3 to the substrate layer 1, thereby ensuring that the gate electrode layer 3 and the substrate layer 1 are tightly bonded.

[0078] S3. Using Smart-Cut or mechanical thinning process, the single crystal lithium tantalate layer is thinned to form a gate dielectric layer 4.

[0079] Among them, the Smart-Cut process can be used to prepare a high-quality and high-flatness gate dielectric layer 4; the mechanical thinning process can remove the excess portion of the surface of the single-crystal lithium tantalate layer through mechanical processing to achieve the purpose of reducing the thickness. Among them, the mechanical thinning process mainly uses physical methods to remove materials, such as mechanical grinding, polishing, etc.

[0080] S4. Form a through hole V on the substrate layer 1 by using a dry etching or wet etching process.

[0081] It should be noted that dry etching is a technology that uses plasma to etch thin films. The reaction gas is activated into active particles through a high-frequency glow discharge reaction. These active particles react with the etched material (substrate layer 1) to form volatile products and are removed. Wet etching is a purely chemical etching method that removes materials through a chemical reaction between a chemical solution and the unmasked substrate layer 1.

[0082] S5 . Form a channel layer 5 and a source-drain electrode layer 6 on the gate dielectric layer 4 in sequence by using a magnetron sputtering method or an atomic layer deposition method.

[0083] For example, in one example, a target material 1 is selected from materials such as molybdenum disulfide (MoS), bismuth oxyselenide (Bi2O2Se), or indium selenide (InSe) to form the channel layer 5.

[0084] In the magnetron sputtering device, the gate dielectric layer 4 is used as a substrate and placed in a sputtering chamber.

[0085] The deposition rate and thickness of the sputtered atoms or molecules on the gate dielectric layer 4 are controlled by adjusting the sputtering parameters, such as the sputtering voltage, current, gas pressure and the distance between the target material and the substrate.

[0086] During the sputtering process, atoms of the target material are sputtered by ion bombardment and deposited on the gate dielectric layer 4 to form a channel layer 5 .

[0087] After the channel layer 5 is formed, a target material 2 is selected from materials such as copper, aluminum, and gold to form the source-drain electrode layer 6 .

[0088] Similarly, in the magnetron sputtering device, the gate dielectric layer 4 on which the channel layer 5 has been deposited is used as a substrate for sputtering deposition.

[0089] By precisely controlling the sputtering parameters and deposition time, it is ensured that the thickness and uniformity of the source-drain electrode layer 6 meet the design requirements.

[0090] Based on the above embodiments, the present application also provides a specific embodiment as follows:

[0091] Step S100, providing single crystal lithium tantalate as the material of the gate dielectric layer 4, using acetone, alcohol, and deionized water to ultrasonically clean the single crystal lithium tantalate with a thickness of 500 μm for 5-15 minutes, and then using a nitrogen gun to blow dry the single crystal lithium tantalate. The blown-dried single crystal lithium tantalate is placed in a sample stage of a magnetron sputtering device (the sample stage is set in a vacuum chamber of the magnetron sputtering device), and the vacuum degree of the vacuum chamber is first pumped to below 10Pa using a mechanical pump, and then the vacuum degree of the vacuum chamber is pumped to below 10Pa-4Pa using a molecular pump.

[0092] Argon gas is introduced into the vacuum chamber to make the pressure reach 1Pa; the DC power supply power is set to 45W; the sample stage speed is 15 rpm; the deposition thickness of the single crystal lithium tantalate is monitored by a film thickness meter, and 100nm of chromium and 100nm of gold are sequentially evaporated as the gate electrode layer 3. The gate electrode layer 3 includes a first metal electrode and a second metal electrode stacked, and the materials of the first metal electrode and the second metal electrode can be any one of Cr / Au, Ti / Au, Cr / Pt, and Ti / Pt.

[0093] Step S200, spin-coating an organic glue on the lower surface of the gate electrode layer 3 and the upper surface of the substrate layer 1 to prepare a bonding layer 2, and bonding the single crystal lithium tantalate with the gate electrode layer 3 to the substrate layer 1 by bonding, and then curing the organic glue by light. The material of the bonding layer 2 includes at least one of an organic glue, a resin glue, and a SiO2 film; the material of the substrate layer 1 includes at least one of silicon, glass, and single crystal lithium tantalate.

[0094] Step S300: Use a thinning machine and a 1000-mesh coarse grinding wheel to quickly thin the single-crystal lithium tantalate from 500 μm to 20 μm, and then use a 300-mesh fine grinding wheel to thin the single-crystal lithium tantalate to 1 μm. The thinned single-crystal lithium tantalate is stage-annealed at 150 degrees Celsius for 30 minutes to remove the residual stress of the single-crystal lithium tantalate, thereby improving the yield rate.

[0095] Select an acid wash solution, immerse the single crystal lithium tantalate completely in the acid wash solution, or evenly spray the acid wash solution on the surface of the single crystal lithium tantalate, and determine the duration of immersion or spraying. Use an alkaline solution or a large amount of clean water to rinse the surface of the single crystal lithium tantalate to remove acidic residues. Finally, dry the single crystal lithium tantalate to remove the moisture remaining in the single crystal lithium tantalate to prevent re-oxidation or contamination, and finally obtain a lithium tantalate single crystal film (that is, the gate dielectric layer 4).

[0096] Step S400: Use a lift-off process to protect the surface of the silicon substrate layer 1 away from the bonding layer 2 with a photoresist mask, and use a potassium hydroxide solution wet etching method to anisotropically etch the surface of the silicon substrate layer 1 away from the bonding layer 2 to obtain a through hole V. The through hole V is used to improve the thermal insulation of the transistor.

[0097] Step S500, perform metal mask processing on the surface of the gate dielectric layer 4, and prepare the channel layer 5 on the gate dielectric layer 4 by magnetron sputtering. First, use a mechanical pump to evacuate the vacuum degree of the vacuum chamber to below 10Pa, and then use a molecular pump to evacuate the vacuum degree of the vacuum chamber to below 10Pa-4Pa. Adjust the ratio of oxygen and argon to 1.1:10. Keep the pressure in the vacuum chamber at 2Pa; set the RF power supply power to 80W; control the sample stage speed at 8-15 rpm to ensure uniform growth of the channel layer 5, and deposit a 30nm thick indium gallium zinc oxide film (IGZO), that is, the channel layer 5.

[0098] Step S600: Prepare transparent ITO electrodes as source and drain electrodes on the channel layer 5 by photolithography and magnetron sputtering, and control the channel width and channel length of the transistor by controlling the spacing and size of the source and drain electrodes. The thickness range of the ITO electrode is [100nm, 300nm], the channel length range is [10μm, 200μm], and the channel width range is [1μm, 20μm].

[0099] Based on the above steps S100 to S600 , the transistor based on the single crystal lithium tantalate gate dielectric layer 4 is completed.

[0100] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can think of within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A transistor, characterized in that: include: A substrate layer, and a bonding layer, a gate electrode layer, a gate dielectric layer, a channel layer, and a source-drain electrode layer stacked in sequence on the substrate layer; The material of the gate dielectric layer includes single crystal lithium tantalate, and the thickness of the gate dielectric layer is in the range of [200nm, 600nm].

2. The transistor according to claim 1, characterized in that The material of the channel layer includes: indium gallium zinc oxide; Wherein, the thickness range of the channel layer is [10nm, 50nm].

3. The transistor according to claim 1, characterized in that The material of the channel layer includes: at least one of molybdenum disulfide, bismuth oxyselenide, and indium selenide; Wherein, the thickness range of the channel layer is [1nm, 5nm].

4. The transistor according to claim 1, characterized in that The material of the bonding layer includes at least one of organic glue, resin glue and silicon dioxide film.

5. The transistor according to claim 1, characterized in that The source-drain electrode layer includes a transparent ITO electrode; The thickness of the ITO electrode is in the range of [100nm, 300nm].

6. The transistor according to claim 1, characterized in that The gate electrode layer includes a first metal electrode and a second metal electrode stacked in layers; The combined material of the first metal electrode and the second metal electrode includes a group consisting of Cr and Au, Ti and Au, Cr and Pt, and Ti and Pt.

7. The transistor according to claim 1, characterized in that The thickness of the gate electrode layer is in the range of [100 nm, 200 nm].

8. The transistor according to claim 1, characterized in that The material of the substrate layer includes at least one of silicon, glass, and single crystal lithium tantalate.

9. The transistor according to claim 1, characterized in that The substrate layer is provided with through holes.

10. A method for preparing a transistor, characterized in that: The method comprises: Using an electron beam evaporation process, a gate electrode layer is evaporated on a side of the single crystal lithium tantalate layer close to the substrate layer; Bonding the gate electrode layer to the substrate layer via a bonding layer; Using Smart-Cut or mechanical thinning process, thinning the single crystal lithium tantalate layer to form a gate dielectric layer; forming a through hole on the substrate layer by dry etching or wet etching process; A channel layer and a source-drain electrode layer are sequentially formed on the gate dielectric layer by using a magnetron sputtering method or an atomic layer deposition method.

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