Short-channel mixed contact thin film transistor, preparation method thereof and related device

Abstract

The invention provides a short-channel mixed contact thin film transistor, a preparation method thereof and a related device, and relates to the technical field of semiconductors. The first source-drain electrode layer and the second source-drain electrode layer are sequentially prepared on the substrate, so that the first source electrode layer and the first drain electrode layer which are included in the first source-drain electrode layer are mutually spaced, and the second source electrode layer and the second drain electrode layer which are included in the second source-drain electrode layer are mutually spaced; the side surfaces of the first source electrode layer and the second source electrode layer are aligned and the side surfaces of the first drain electrode layer and the second drain electrode layer are aligned, and then preparing a channel semiconductor film layer, a gate dielectric layer and a gate electrode layer in sequence, so that the channel semiconductor film layer and the second source / drain electrode layer respectively form ohmic contact or quasi-ohmic contact; and a depletion region is formed in a local region in direct contact with the first source / drain layer, so that the short-channel effect of the transistor device is remarkably inhibited by using the depletion region.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a short channel hybrid contact thin film transistor and a preparation method and related devices thereof. Background Art

[0002] With the continuous advancement of technology, the related technical requirements of many high-tech technologies such as high-resolution active matrix display technology, dynamic random access memory (DRAM) technology and flexible integrated circuit technology are driving the development of thin film transistors towards short channel, high mobility and high stability. Among them, oxide thin film transistors (TFTs) using metal oxides (for example, indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO) or rare earth-doped indium zinc oxide (Ln-IZO)) as channel materials have the characteristics of high mobility, extremely low off-state current, large-area uniform preparation, good stability and compatibility with low-temperature processes. At present, they have become one of the key research objects in the semiconductor field.

[0003] However, as the channel size decreases, oxide thin-film transistors tend to exhibit short channel effects similar to silicon-based transistors (for example, significant negative drift of the threshold voltage, drain-induced barrier reduction, etc.), resulting in the electrical characteristics of the transistor being unable to meet the needs of practical applications. In order to weaken the short channel effect of oxide thin-film transistors, the current mainstream in the industry usually adopts measures such as thinning the oxide channel layer and crystallizing the oxide channel layer to suppress the short channel effect of the transistor. However, it is worth noting that the thinning of the oxide channel layer will cause the device electrical characteristics to be more sensitive to changes in the channel layer thickness, changes in the channel passivation layer material, and changes in the channel passivation layer preparation process, and the crystallization of the oxide channel layer will also cause the device electrical characteristics to be significantly affected by the grain boundaries. These short channel effect suppression measures are not conducive to achieving uniformity of device electrical characteristics when oxide thin-film transistors are prepared on a large scale. Summary of the invention

[0004] In view of this, the purpose of the present application is to provide a short channel hybrid contact thin film transistor and a preparation method thereof, a dynamic random access memory and a display panel, which can form an ohmic contact or a quasi-ohmic contact between a channel semiconductor film layer and a group of source / drain layers by preparing two source layers and two drain layers, and form a depletion region in a local semiconductor region of the channel semiconductor film layer that is in direct contact with another group of source / drain layers, so as to utilize the formed depletion region to effectively reduce the carrier concentration of the channel semiconductor film layer, and easily achieve a channel pinch-off effect, thereby significantly suppressing the short channel effect of the transistor device, without the need to adopt measures such as channel layer thinning or channel layer crystallization, and facilitating the improvement of the uniformity of device electrical characteristics during large-scale preparation of transistors.

[0005] In order to achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:

[0006] In a first aspect, the present application provides a short channel hybrid contact thin film transistor, the thin film transistor comprising:

[0007] substrate;

[0008] A first source-drain electrode layer and a second source-drain electrode layer are sequentially stacked on one side of the substrate, wherein the first source-drain electrode layer includes a first source electrode layer and a first drain electrode layer spaced apart from each other, the second source-drain electrode layer includes a second source electrode layer and a second drain electrode layer spaced apart from each other, the first source electrode layer is aligned with the second source layer side surface, and the first drain electrode layer is aligned with the second drain layer side surface;

[0009] a channel semiconductor film layer grown along the sidewalls of the respective separation spaces between the first source-drain electrode layer and the second source-drain electrode layer, wherein the channel semiconductor film layer partially covers the outer surface of the second source-drain electrode layer away from the substrate, the second source electrode layer and the second drain electrode layer respectively form an ohmic contact or a quasi-ohmic contact with the channel semiconductor film layer, a local area of ​​the channel semiconductor film layer directly contacting the first source electrode layer and the first drain electrode layer forms a depletion region, and a projection area of ​​the channel semiconductor film layer on the substrate covers a projection area of ​​the separation space;

[0010] A gate dielectric layer covering the outer surface areas of the channel semiconductor film layer and the second source-drain electrode layer that are not blocked by the channel semiconductor film layer, and a gate layer at least partially covering the gate dielectric layer, wherein the projection area of ​​the gate layer on the substrate at least covers the projection area of ​​the separation space.

[0011] In an optional embodiment, the thin film transistor further comprises an insulating layer, the insulating layer is made of any one of silicon dioxide and silicon nitride or a stack of two materials, and the thickness of the insulating layer is in the range of 5-1000 nm;

[0012] The insulating layer is disposed between the substrate and the first source-drain electrode layer, and the channel semiconductor film layer covers a local surface area of ​​the insulating layer that is not blocked by the first source-drain electrode layer.

[0013] In an optional embodiment, the thin film transistor further includes:

[0014] A source wiring layer electrically connected to the second source layer via the gate dielectric layer, and a drain wiring layer electrically connected to the second drain layer via the gate dielectric layer, wherein the source wiring layer and the drain wiring layer are each made of any one of aluminum, molybdenum, titanium, chromium, tungsten, nickel, platinum, gold, indium tin oxide material, and aluminum-doped zinc oxide material, and the thickness of each of the source wiring layer and the drain wiring layer is in the range of 1-1000nm.

[0015] In an optional embodiment, the thickness of the first source-drain electrode layer is in the range of 1-1000 nm, the thickness of the second source-drain electrode layer is in the range of 5-1000 nm, wherein the width of the interval space in the same source-drain electrode layer is greater than or equal to 5 nm;

[0016] The thickness of the channel semiconductor film layer is in the range of 1-100 nm;

[0017] The thickness of the gate dielectric layer is in the range of 1-1000 nm;

[0018] The thickness of the gate layer is in the range of 1-1000 nm.

[0019] In an optional embodiment, the second source-drain electrode layer and the gate layer are each made of any one of aluminum, molybdenum, titanium, chromium, tungsten, nickel, platinum, gold, indium tin oxide material, and aluminum-doped zinc oxide material;

[0020] The gate dielectric layer is made of a stack of any one or more materials selected from silicon dioxide, silicon nitride, aluminum oxide, hafnium oxide, and zirconium oxide;

[0021] When the material of the channel semiconductor film layer is an N-type semiconductor material, the material of the first source-drain electrode layer is a P-type conductor material, a P-type semiconductor material, or a metal material having a corresponding work function greater than that of the N-type semiconductor material, wherein the N-type semiconductor material includes at least one of N-type doped silicon, N-type doped germanium, indium gallium zinc oxide, indium zinc oxide, indium zinc tin oxide, rare earth-doped indium zinc oxide, indium tin oxide, aluminum-doped zinc oxide, indium gallium oxide, zinc oxide, gallium oxide, indium oxide, and tin oxide, and the material of the first source-drain electrode layer includes at least one of tellurium, telluride, P-type doped silicon, P-type doped germanium, copper iodide, cuprous oxide, stannous oxide, copper, molybdenum, cobalt, titanium, nickel, tungsten, chromium, gold, silver, platinum, and palladium;

[0022] When the material for preparing the channel semiconductor film layer is a P-type semiconductor material, the material for preparing the first source and drain electrode layer is an N-type conductor material, an N-type semiconductor material, or a metal material having a corresponding work function smaller than that of the P-type semiconductor material, wherein the P-type semiconductor material includes at least one of tellurium, telluride, P-type doped silicon, P-type doped germanium, copper iodide, cuprous oxide, and stannous oxide, and the material for preparing the first source and drain electrode layer includes at least one of N-type doped silicon, N-type doped germanium, indium gallium zinc oxide, indium zinc oxide, indium zinc tin oxide, rare earth-doped indium zinc oxide, indium tin oxide, aluminum-doped zinc oxide, indium gallium oxide, zinc oxide, gallium oxide, indium oxide and tin oxide, aluminum, scandium, barium, bismuth, yttrium, and hafnium.

[0023] In a second aspect, the present application provides a method for preparing a short channel hybrid contact thin film transistor, the preparation method comprising:

[0024] providing a substrate;

[0025] A first source-drain electrode layer and a second source-drain electrode layer are sequentially stacked on one side of the substrate to obtain an intermediate stage device, or an insulating layer, a first source-drain electrode layer and a second source-drain electrode layer are sequentially stacked on one side of the substrate to obtain an intermediate stage device; wherein the first source-drain electrode layer includes a first source electrode layer and a first drain electrode layer spaced from each other, the second source-drain electrode layer includes a second source electrode layer and a second drain electrode layer spaced from each other, the first source layer is aligned with the second source layer side, and the first drain layer is aligned with the second drain layer side;

[0026] A channel semiconductor film layer, a gate dielectric layer and a gate layer are sequentially prepared on the outer surface of the intermediate stage device away from the substrate; wherein the channel semiconductor film layer simultaneously covers the side walls of the separation space between the first source-drain electrode layer and the second source-drain electrode layer, and partially covers the outer surface of the second source-drain electrode layer away from the substrate; the second source layer and the second drain layer respectively form ohmic contact or quasi-ohmic contact with the channel semiconductor film layer, and a local area of ​​the channel semiconductor film layer directly in contact with the first source layer and the first drain layer forms a depletion region; the projection area of ​​the channel semiconductor film layer on the substrate covers the projection area of ​​the separation space, and the projection area of ​​the gate layer on the substrate at least covers the projection area of ​​the separation space.

[0027] In an optional embodiment, the insulating layer is grown by chemical vapor deposition;

[0028] The first source-drain electrode layer and the second source-drain electrode layer are both obtained by patterning the source-drain electrode film layer by photolithography, wherein the source-drain electrode film layer is prepared by magnetron sputtering, atomic layer deposition or thermal evaporation;

[0029] The channel semiconductor film layer is obtained by subjecting the semiconductor film patterned by photolithography to a thermal annealing treatment at 100-800° C., wherein the semiconductor film is deposited by a magnetron sputtering method or an atomic layer deposition method;

[0030] The gate dielectric layer is grown by chemical vapor deposition or atomic layer deposition;

[0031] The gate layer is obtained by photolithography-patterning a gate electrode film layer, wherein the gate electrode film layer is prepared by magnetron sputtering, atomic layer deposition or evaporation.

[0032] In an optional embodiment, the preparation method further comprises:

[0033] Before preparing the gate layer, the prepared gate dielectric layer is patterned by photolithography, so that the gate dielectric layer forms a first via hole partially exposing the second source electrode layer and a second via hole partially exposing the second drain electrode layer;

[0034] During the preparation of the gate layer, the gate film layer to which the gate layer belongs is photolithographically patterned to obtain the gate layer, the source wiring layer electrically connected to the second source layer through the first via hole, and the drain wiring layer electrically connected to the second drain layer through the second via hole.

[0035] In a third aspect, the present application provides a dynamic random access memory, which includes a plurality of short-channel hybrid-contact thin-film transistors as described in any one of the aforementioned embodiments, and the plurality of short-channel hybrid-contact thin-film transistors cooperate with each other to realize a dynamic data storage function.

[0036] In a fourth aspect, the present application provides a display panel, comprising a pixel unit array and a plurality of short-channel hybrid-contact thin film transistors as described in any one of the preceding embodiments, wherein the plurality of short-channel hybrid-contact thin film transistors cooperate with each other to form a driving circuit for the pixel unit array.

[0037] In this case, the beneficial effects of the embodiments of the present application may include the following:

[0038] The present application sequentially prepares a first source-drain electrode layer and a second source-drain electrode layer on a substrate, so that the first source electrode layer and the first drain electrode layer included in the first source-drain electrode layer are spaced apart from each other, and the second source electrode layer and the second drain electrode layer included in the second source-drain electrode layer are spaced apart from each other, so that the first source electrode layer is aligned with the side of the second source electrode layer and the first drain electrode layer is aligned with the side of the second drain electrode layer, and then prepares a channel semiconductor film layer that contacts the first source-drain electrode layer and the second source-drain electrode layer at the same time, so that the channel semiconductor film layer can form an ohmic contact or a quasi-ohmic contact with the second source / drain electrode layer, and A depletion region is formed in the local area where the first source / drain layer is in direct contact, and then a gate dielectric layer and a gate layer are sequentially prepared on the channel semiconductor film layer, so as to utilize the formed depletion region to effectively reduce the carrier concentration of the channel semiconductor film layer, and easily achieve the channel pinch-off effect under the coordinated control of the gate voltage and the drain voltage, so as to significantly suppress the short channel effect of the transistor device, without the need to adopt measures such as channel layer thinning or channel layer crystallization, which is convenient for improving the uniformity of device electrical characteristics during the large-scale preparation of transistors, and is beneficial for preparing ultra-short channel high-performance transistor devices. Among them, the projection area of ​​the prepared channel semiconductor film layer on the substrate covers the projection area of ​​the space between the first source and drain electrode layer and the second source and drain electrode layer, and the projection area of ​​the prepared gate layer on the substrate at least covers the projection area of ​​the aforementioned space.

[0039] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0041] Figure 1 One of the schematic diagrams of the composition of the first short channel hybrid contact thin film transistor provided in the embodiment of the present application;

[0042] Figure 2 The second schematic diagram of the composition of the first short channel hybrid contact thin film transistor provided in the embodiment of the present application;

[0043] Figure 3 The third schematic diagram of the composition of the second short channel hybrid contact thin film transistor provided in the embodiment of the present application;

[0044] Figure 4 A fourth schematic diagram of the composition of the second short channel hybrid contact thin film transistor provided in an embodiment of the present application;

[0045] Figure 5 One of the schematic flow charts of the first method for preparing a short channel hybrid contact thin film transistor provided in an embodiment of the present application;

[0046] Figure 6 For Figure 5 Schematic diagram of the fabrication of the corresponding intermediate stage device;

[0047] Figure 7 Based on Figure 5 Corresponding intermediate stage device preparation Figure 1 The schematic diagram of manufacturing the first short channel mixed contact thin film transistor is shown;

[0048] Figure 8 A second schematic flow chart of a method for preparing a first short channel hybrid contact thin film transistor provided in an embodiment of the present application;

[0049] Fig. 9 Based on Figure 5 Corresponding intermediate stage device preparation Figure 2 The schematic diagram of manufacturing the first short channel mixed contact thin film transistor is shown;

[0050] Fig.10 One of the schematic flow charts of the second method for preparing a short channel hybrid contact thin film transistor provided in an embodiment of the present application;

[0051] Fig.11 For Fig.10 Schematic diagram of the fabrication of the corresponding intermediate stage device;

[0052] Fig.12 Based on Fig.10 Corresponding intermediate stage device preparation Figure 3 The schematic diagram of manufacturing the second short channel mixed contact thin film transistor is shown;

[0053] Fig.13 A second schematic flow chart of a second method for preparing a short channel hybrid contact thin film transistor provided in an embodiment of the present application;

[0054] Fig.14 Based on Fig.10 Corresponding intermediate stage device preparation Figure 4 The schematic diagram of the fabrication of the second short channel mixed contact thin film transistor is shown.

[0055] Icon: 10-short channel hybrid contact thin film transistor; 11-substrate; 12-first source-drain electrode layer; 121-first source layer; 122-first drain layer; 13-second source-drain electrode layer; 131-second source layer; 132-second drain layer; 14-channel semiconductor film layer; 15-gate dielectric layer; 16-gate layer; 17-depletion region; 181-first via; 182-second via; 183-source routing layer; 184-drain routing layer; 19-insulating layer. DETAILED DESCRIPTION

[0056] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0057] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0058] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0059] In the description of the present application, it should be understood that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the product of the application is conventionally placed when in use, or are the orientations or positional relationships conventionally understood by those skilled in the art. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0060] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0061] In addition, in the description of the present application, it is understood that the relational terms such as the term "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements that are not clearly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the sentence "comprise one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood by specific circumstances.

[0062] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0063] Please refer to Figure 1 , Figure 1 It is one of the composition schematic diagrams of the first short channel hybrid contact thin film transistor 10 provided in the embodiment of the present application. In the embodiment of the present application, the short channel hybrid contact thin film transistor 10 provided in the present application can form an ohmic contact or a quasi-ohmic contact between the channel semiconductor film layer and a group of source / drain layers respectively by setting two source layers and two drain layers, and form a depletion region in the local semiconductor region of the channel semiconductor film layer that is in direct contact with another group of source / drain layers, so as to effectively reduce the carrier concentration of the channel semiconductor film layer by utilizing the formed depletion region, and can easily achieve the channel pinch-off effect under the coordinated control of the gate voltage and the drain voltage, thereby significantly suppressing the short channel effect of the transistor device, without the need to adopt measures such as channel layer thinning or channel layer crystallization, which is convenient for improving the uniformity of device electrical characteristics in the large-scale preparation process of transistors, and is beneficial for preparing ultra-short channel high-performance transistor devices.

[0064] In the embodiments of the present application, Figure 1The short channel hybrid contact thin film transistor 10 shown may include a substrate 11 , a first source-drain electrode layer 12 , a second source-drain electrode layer 13 , a channel semiconductor film layer 14 , a gate dielectric layer 15 and a gate layer 16 .

[0065] In the embodiment of the present application, the first source-drain electrode layer 12 is disposed on the substrate 11, and the second source-drain electrode layer 13 is disposed on a surface of the first source-drain electrode layer 12 away from the substrate 11. The first source-drain electrode layer 12 includes a first source layer 121 and a first drain layer 122 spaced apart from each other, and the second source-drain electrode layer 13 includes a second source layer 131 and a second drain layer 132 spaced apart from each other, the first source layer 121 and the second source layer 131 are in contact with and electrically connected to each other, the first drain layer 122 and the second drain layer 132 are in contact with and electrically connected to each other, and the first source layer 121 and the second source layer 131 are combined to serve as the transistor source of the short-channel hybrid contact thin film transistor 10, and the first drain layer 122 and the second drain layer 132 are combined to serve as the transistor drain of the short-channel hybrid contact thin film transistor 10; the first drain layer 122 and the second drain layer 132 are aligned sideways, and the first drain layer 122 and the second drain layer 132 are aligned sideways. At this time, for the first source-drain electrode layer 12, the spacing space corresponding to the first source-drain electrode layer 12 is the space region between the first source layer 121 and the first drain layer 122, and the side wall of the spacing space corresponding to the first source-drain electrode layer 12 is composed of the two side walls facing the first source layer 121 and the first drain layer 122; and for the second source-drain electrode layer 13, the spacing space corresponding to the second source-drain electrode layer 13 is the space region between the second source layer 131 and the second drain layer 132, and the side wall of the spacing space corresponding to the second source-drain electrode layer 13 is composed of the two side walls facing the second source layer 131 and the second drain layer 132.

[0066] In the embodiment of the present application, the channel semiconductor film layer 14 grows along the sidewalls of the spaces between the first source-drain electrode layer 12 and the second source-drain electrode layer 13, and partially covers the outer surface of the second source-drain electrode layer 13 away from the substrate 11 (that is, the outer surfaces of the second source layer 131 and the second drain layer 132 away from the substrate 11), and the projection area of ​​the channel semiconductor film layer 14 on the substrate 11 also covers the projection area of ​​the spaces between the first source-drain electrode layer 12 and the second source-drain electrode layer 13 on the substrate 11 (for example, Figure 1The channel semiconductor film layer 14 in the substrate 11 covers the local surface area of ​​the substrate 11 not blocked by the first source-drain electrode layer 12). The channel semiconductor film layer 14 is in direct contact with the respective facing side walls of the second source layer 131 and the second drain layer 132 to achieve ohmic contact or quasi-ohmic contact between the second source layer 131 and the second drain layer 132 and the channel semiconductor film layer 14, wherein the second source layer 131 can independently undertake the task of injecting all or most of the carriers into the channel semiconductor film layer 14 based on the ohmic contact or quasi-ohmic contact.

[0067] In an embodiment of the present application, the gate dielectric layer 15 is used to cover the outer surface areas of the channel semiconductor film layer 14 and the second source-drain electrode layer 13 that are not blocked by the channel semiconductor film layer 14, and the gate layer 16 at least partially covers the gate dielectric layer 15. At the same time, the projection area of ​​the gate layer 16 on the substrate 11 at least simultaneously covers the projection area of ​​the spacing spaces between the first source-drain electrode layer 12 and the second source-drain electrode layer 13 on the substrate 11, so that the gate layer 16 can serve as the transistor gate of the short channel hybrid contact thin film transistor 10.

[0068] In the embodiment of the present application, the carrier conductivity type of the first source-drain electrode layer 12 is different from the carrier conductivity type of the channel semiconductor film layer 14 (for example, if the preparation material of the channel semiconductor film layer 14 is an N-type semiconductor material, the preparation material of the first source-drain electrode layer 12 is a P-type conductor material, a P-type semiconductor material, or a metal material whose corresponding work function is greater than that of the N-type semiconductor material; and if the preparation material of the channel semiconductor film layer 14 is a P-type semiconductor material, the preparation material of the first source-drain electrode layer 12 is an N-type conductor material, an N-type semiconductor material, or a metal material whose corresponding work function is less than that of the P-type semiconductor material), so that Figure 1 When the short channel hybrid contact thin film transistor 10 shown in the figure works in a saturation state, the channel semiconductor film layer 14 will form a depletion region 17 in a local semiconductor region directly in contact with the first source layer 121, and at the same time, a depletion region 17 will be formed in a local semiconductor region directly in contact with the first drain layer 122; wherein the depletion region 17 corresponding to the first source layer 121 will extend from the side where the second source layer 131 realizes ohmic (quasi-ohmic) contact to the side where the first drain layer 122 is located, and touch the interlayer interface between the channel semiconductor film layer 14 and the gate dielectric layer 15 on the side of the first drain layer 122 (see Figure 1Meanwhile, the depletion region 17 corresponding to the first drain layer 122 will expand from the bottom side of the first drain layer 122 to the side where the second drain layer 132 achieves ohmic (quasi-ohmic) contact, and will not touch the interlayer interface between the channel semiconductor film layer 14 and the gate dielectric layer 15 on the side close to the second drain layer 132 (see Figure 1 The expansion distribution of the depletion region 17 on the right side of the MOSFET is shown in FIG. 1 ), thereby achieving the pinch-off effect of the channel. Figure 1 The saturated output current of the short-channel mixed-contact thin-film transistor 10 shown is mainly controlled by the extension degree of the depletion region 17 corresponding to the first source layer 121. The depletion region 17 corresponding to the first source layer 121 can adaptively adjust the actual transport intensity of the injected carriers from the transistor source to the transistor drain under the coordinated control of the gate voltage and the drain voltage.

[0069] In the embodiment of the present application, the substrate 11 can be a rigid substrate such as glass, silicon dioxide, etc., or a flexible organic polymer substrate such as polyimide, polyethylene naphthalate, etc. It is understood that the actual type of the substrate 11 includes but is not limited to the above examples, and any substrate material that can be used to prepare a conventional oxide thin film transistor device falls within the protection scope of the present application.

[0070] In an embodiment of the present application, the thickness range of the first source-drain electrode layer 12 is 1-1000nm, and the thickness range of the second source-drain electrode layer 13 is 5-1000nm, wherein the spacing width in the same source-drain electrode layer (i.e., the spacing distance between the first source layer 121 and the first drain layer 122, or the spacing distance between the second source layer 131 and the second drain layer 132) is greater than or equal to 5nm; the thickness range of the channel semiconductor film layer 14 is 1-100nm; the thickness range of the gate dielectric layer 15 is 1-1000nm; and the thickness range of the gate layer 16 is 1-1000nm.

[0071] In the embodiment of the present application, the second source-drain electrode layer 13 and the gate layer 16 are each made of a metal, an alloy or a transparent conductive oxide material, and the gate dielectric layer 15 is made of a stack of any one or more materials selected from silicon dioxide, silicon nitride, aluminum oxide, hafnium oxide and zirconium oxide. In one implementation of the present embodiment, the second source-drain electrode layer 13 and the gate layer 16 are each made of any one of aluminum, molybdenum, titanium, chromium, tungsten, nickel, platinum, gold, indium tin oxide material and aluminum-doped zinc oxide material.

[0072] In the embodiment of the present application, when the material of the channel semiconductor film layer 14 is an N-type semiconductor material, the material of the first source-drain electrode layer 12 is a P-type conductor material, a P-type semiconductor material, or a metal material whose corresponding work function is greater than that of the N-type semiconductor material. The N-type semiconductor material includes at least one of semiconductor materials with electrons as majority carriers, such as N-type doped silicon, N-type doped germanium, indium gallium zinc oxide, indium zinc oxide, indium zinc tin oxide, rare earth doped indium zinc oxide, indium tin oxide, aluminum doped zinc oxide, indium gallium oxide, zinc oxide, gallium oxide, indium oxide, and tin oxide; the P-type conductor material or semiconductor material includes but is not limited to tellurium, telluride, P-type doped silicon, P-type doped germanium, copper iodide, cuprous oxide, tin oxide, and other conductor materials or semiconductor materials with holes as majority carriers, and the metal material with a work function greater than that of the N-type semiconductor material includes but is not limited to copper, molybdenum, cobalt, titanium, nickel, tungsten, chromium, gold, silver, platinum, palladium, and other metals or alloy materials. In one implementation of this embodiment, the preparation material of the first source-drain electrode layer 12 includes at least one of tellurium, telluride, P-type doped silicon, P-type doped germanium, copper iodide, cuprous oxide, stannous oxide, copper, molybdenum, cobalt, titanium, nickel, tungsten, chromium, gold, silver, platinum, and palladium.

[0073] In the embodiment of the present application, when the material of the channel semiconductor film layer 14 is a P-type semiconductor material, the material of the first source-drain electrode layer 12 is an N-type conductor material, an N-type semiconductor material, or a metal material with a corresponding work function smaller than that of the P-type semiconductor material. The P-type semiconductor material includes at least one of semiconductor materials with holes as majority carriers, such as tellurium, telluride, P-type doped silicon, P-type doped germanium, copper iodide, cuprous oxide, stannous oxide, etc.; the N-type conductor material or semiconductor material includes but is not limited to N-type doped silicon, N-type doped germanium, indium gallium zinc oxide, indium zinc oxide, indium zinc tin oxide, rare earth doped indium zinc oxide, indium tin oxide, aluminum doped zinc oxide, indium gallium oxide, zinc oxide, gallium oxide, indium oxide, tin oxide, etc., and the metal material with a work function smaller than that of the P-type semiconductor material includes but is not limited to aluminum, scandium, barium, bismuth, yttrium, hafnium, etc., and other metal or alloy materials. In one implementation of this embodiment, the preparation material of the first source-drain electrode layer 12 includes at least one of N-type doped silicon, N-type doped germanium, indium gallium zinc oxide, indium zinc oxide, indium zinc tin oxide, rare earth-doped indium zinc oxide, indium tin oxide, aluminum-doped zinc oxide, indium gallium oxide, zinc oxide, gallium oxide, indium oxide and tin oxide, aluminum, scandium, barium, bismuth, yttrium and hafnium.

[0074] Optionally, see Figure 2 , Figure 2 FIG. 2 is a second schematic diagram of the composition of the first short channel hybrid contact thin film transistor 10 provided in the embodiment of the present application. Figure 1Compared with the short channel hybrid contact thin film transistor 10 shown, Figure 2 The short channel hybrid contact thin film transistor 10 shown may further include a source wiring layer 183 and a drain wiring layer 184 .

[0075] In the embodiment of the present application, the gate dielectric layer 15 is provided with a first via 181 that partially exposes the second source layer 131, and the gate dielectric layer 15 is provided with a second via 182 that partially exposes the second drain layer 132; the source wiring layer 183 and the drain wiring layer 184 are both deployed on the outer surface of the gate dielectric layer 15 away from the substrate 11, the source wiring layer 183 is electrically connected to the second source layer 131 through the first via 181, and the drain wiring layer 184 is electrically connected to the second drain layer 132 through the second via 182, and the source wiring layer 183 and the drain wiring layer 184 are both spaced apart from the gate layer 16.

[0076] In the embodiment of the present application, the source wiring layer 183 and the drain wiring layer 184 are each made of any one of aluminum, molybdenum, titanium, chromium, tungsten, nickel, platinum, gold, indium tin oxide material, and aluminum-doped zinc oxide material, and the thickness of the source wiring layer 183 and the drain wiring layer 184 is in the range of 1-1000nm. In one implementation of the present embodiment, the source wiring layer 183, the drain wiring layer 184 and the gate layer 16 can be prepared using the same material, and the source wiring layer 183, the drain wiring layer 184 and the gate layer 16 can be obtained by photolithography patterning the same electrode film layer (i.e., the gate film layer).

[0077] Optionally, see Figure 3 , Figure 3 FIG. 3 is a third schematic diagram of the composition of the second short channel hybrid contact thin film transistor 10 provided in the embodiment of the present application. Figure 1 Compared with the short channel hybrid contact thin film transistor 10 shown, Figure 3 The short channel hybrid contact thin film transistor 10 shown may further include an insulating layer 19 .

[0078] In the embodiment of the present application, the insulating layer 19 is disposed between the substrate 11 and the first source-drain electrode layer 12, and the channel semiconductor film layer 14 covers the local surface area of ​​the insulating layer 19 that is not blocked by the first source-drain electrode layer 12, so that the projection area of ​​the channel semiconductor film layer 14 on the substrate 11 corresponds to the projection area of ​​the spacing space between the first source-drain electrode layer 12 and the second source-drain electrode layer 13 on the substrate 11. The thickness of the insulating layer 19 is in the range of 5-1000 nm, and the material of the insulating layer 19 is any one of insulating materials such as silicon dioxide and silicon nitride, or a stack of two materials.

[0079] Optionally, see Figure 4 , Figure 4 FIG. 4 is a fourth schematic diagram of the composition of the second short channel hybrid contact thin film transistor 10 provided in the embodiment of the present application. Figure 3 Compared with the short channel hybrid contact thin film transistor 10 shown, Figure 4 The short channel hybrid contact thin film transistor 10 shown may further include a source wiring layer 183 and a drain wiring layer 184 .

[0080] In the embodiment of the present application, the gate dielectric layer 15 is provided with a first via 181 that partially exposes the second source layer 131, and the gate dielectric layer 15 is provided with a second via 182 that partially exposes the second drain layer 132; the source wiring layer 183 and the drain wiring layer 184 are both deployed on the outer surface of the gate dielectric layer 15 away from the substrate 11, the source wiring layer 183 is electrically connected to the second source layer 131 through the first via 181, and the drain wiring layer 184 is electrically connected to the second drain layer 132 through the second via 182, and the source wiring layer 183 and the drain wiring layer 184 are both spaced apart from the gate layer 16.

[0081] In the embodiment of the present application, the source wiring layer 183 and the drain wiring layer 184 are each made of any one of aluminum, molybdenum, titanium, chromium, tungsten, nickel, platinum, gold, indium tin oxide material, and aluminum-doped zinc oxide material, and the thickness of the source wiring layer 183 and the drain wiring layer 184 is in the range of 1-1000nm. In one implementation of the present embodiment, the source wiring layer 183, the drain wiring layer 184 and the gate layer 16 can be prepared using the same material, and the source wiring layer 183, the drain wiring layer 184 and the gate layer 16 can be obtained by photolithography patterning the same electrode film layer (i.e., the gate film layer).

[0082] Therefore, the application provides Figure 1 , Figure 2 , Figure 3 or Figure 4 The short channel hybrid contact thin film transistor 10 shown is able to form an ohmic contact or a quasi-ohmic contact between the channel semiconductor film layer 14 and a group of source / drain layers respectively by setting two source layers and two drain layers, and form a depletion region 17 in the local semiconductor region of the channel semiconductor film layer 14 that is in direct contact with the other group of source / drain layers, so as to utilize the formed depletion region 17 to effectively reduce the carrier concentration of the channel semiconductor film layer 14, and can easily achieve the channel pinch-off effect under the coordinated control of the gate voltage and the drain voltage, thereby significantly suppressing the short channel effect of the transistor device, without the need to adopt measures such as channel layer thinning or channel layer crystallization, which is convenient for improving the uniformity of device electrical characteristics during large-scale preparation of transistors, and is beneficial for preparing ultra-short channel high-performance transistor devices.

[0083] In this application, to ensure Figure 1 or Figure 2 The first short channel hybrid contact thin film transistor 10 shown can be prepared and formed quickly and orderly. The embodiment of the present application provides a preparation method for the first short channel hybrid contact thin film transistor 10 to achieve the above-mentioned function.

[0084] Please refer to Figure 5 , Figure 5 This is one of the flow diagrams of the first method for preparing a short channel hybrid contact thin film transistor provided in the embodiment of the present application. In the embodiment of the present application, Figure 5 The preparation method shown may include steps S210 to S230 to prepare Figure 1 A first short channel hybrid contact thin film transistor 10 is shown.

[0085] Step S210, providing a substrate.

[0086] Step S210, a first source-drain electrode layer and a second source-drain electrode layer are stacked in sequence on one side of the substrate to obtain an intermediate stage device, wherein the first source-drain electrode layer includes a first source layer and a first drain layer spaced apart from each other, the second source-drain electrode layer includes a second source layer and a second drain layer spaced apart from each other, the first source layer is aligned with the side of the second source layer, and the first drain layer is aligned with the side of the second drain layer.

[0087] Optionally, in an implementation manner of this embodiment, a photoresist film layer may be deposited on one side of the substrate 11, and the deposited photoresist film layer may be patterned into a photoresist layer to obtain Figure 6 (a) shows the device structure, and then Figure 6 The device structure shown in (a) is formed by sequentially preparing a first source-drain electrode film layer and a second source-drain electrode film layer (i.e., corresponding to the outer surface of the substrate 11 away from the substrate 11) by magnetron sputtering, atomic layer deposition or thermal evaporation. Figure 6 (b)), then the second source-drain electrode film layer and the first source-drain electrode film layer are patterned by a Lift-Off process (including removing the photoresist layer), so as to pattern the second source-drain electrode film layer into a second source-drain electrode layer 13 including a second source electrode layer 131 and a second drain electrode layer 132, and pattern the first source-drain electrode film layer into a first source-drain electrode layer 12 including a first source electrode layer 121 and a first drain electrode layer 122, so as to obtain Figure 6 (c) The intermediate stage device shown.

[0088] Optionally, in an implementation manner of the present embodiment, a first source-drain electrode film layer and a second source-drain electrode film layer can be sequentially prepared by directly using a magnetron sputtering method, an atomic layer deposition method or a thermal evaporation method on one side of the substrate 11, and then the second source-drain electrode film layer and the first source-drain electrode film layer are sequentially photolithographically patterned by a photolithography process combined with a dry or wet etching process, so that the second source-drain electrode film layer is patterned into a second source-drain electrode layer 13 including a second source layer 131 and a second drain layer 132, and the first source-drain electrode film layer is patterned into a first source-drain electrode layer 12 including a first source layer 121 and a first drain layer 122, so as to obtain the following. Figure 6 (c) The intermediate stage device shown.

[0089] Step S230, sequentially preparing a channel semiconductor film layer, a gate dielectric layer and a gate layer on the outer surface of the intermediate stage device away from the substrate, wherein the channel semiconductor film layer simultaneously covers the side walls of the separation space between the first source-drain electrode layer and the second source-drain electrode layer, and partially covers the outer surface of the second source-drain electrode layer away from the substrate, the projection area of ​​the channel semiconductor film layer on the substrate covers the projection area of ​​the separation space, and the projection area of ​​the gate layer on the substrate at least covers the projection area of ​​the separation space.

[0090] In this embodiment, the second source layer 131 and the second drain layer 132 respectively form ohmic contact or quasi-ohmic contact with the channel semiconductor film layer 14 , and a local area of ​​the channel semiconductor film layer 14 that is in direct contact with the first source layer 121 and the first drain layer 122 forms a depletion region 17 .

[0091] In this embodiment, by Figure 6 (c) The intermediate stage device is formed by depositing a semiconductor film on the outer surface of the device away from the substrate 11 by magnetron sputtering or atomic layer deposition, and then the semiconductor film is patterned into the general shape of the channel semiconductor film layer 14 by photolithography combined with dry or wet etching, and the patterned semiconductor film is subjected to thermal annealing at 100-800°C, so as to Figure 6The channel semiconductor film layer 14 is prepared and formed on the intermediate stage device shown in (c), and the Figure 7 (a) shows the device structure.

[0092] Then, you can Figure 7 The device structure shown in (a) is formed by growing the gate dielectric layer 15 on the outer surface away from the substrate 11 by chemical vapor deposition or atomic layer deposition, so as to obtain Figure 7 (b) shows the device structure.

[0093] Then, you can Figure 7 The device structure shown in (b) is formed by using magnetron sputtering, atomic layer deposition or evaporation to form a gate electrode film layer on the outer surface away from the substrate 11, and the gate electrode film layer is directly patterned into the gate layer 16 by using a photolithography process combined with a dry or wet etching process, so as to obtain a gate electrode layer 16 as shown in FIG. Figure 7 (c) shows the device structure. Figure 7 The device structure shown in (c) is Figure 1 A first short channel hybrid contact thin film transistor 10 is shown.

[0094] Optionally, see Figure 8 , Figure 8 This is the second flow chart of the first method for preparing a short channel hybrid contact thin film transistor provided in the embodiment of the present application. Figure 5 Compared with the preparation method shown, Figure 8 The preparation method shown may also include steps S240 to S250 to prepare Figure 2 A first short channel hybrid contact thin film transistor 10 is shown.

[0095] Step S240, before preparing the gate layer, photolithography patterning is performed on the prepared gate dielectric layer, so that the gate dielectric layer forms a first via hole partially exposing the second source layer and a second via hole partially exposing the second drain layer.

[0096] In this embodiment, Figure 6 In the intermediate stage device shown in (c), the channel semiconductor film layer 14 and the gate dielectric layer 15 are sequentially prepared on the outer surface of the device away from the substrate 11, and the device is obtained as shown in FIG. Figure 7 (b) or Fig. 9 Based on the device structure shown in (a), a photolithography process combined with a dry or wet etching process is used to Fig. 9 The gate dielectric layer 15 in the device structure shown in (a) is patterned to form the first via hole 181 and the second via hole 182, as shown in FIG. Fig. 9 (b) shows the device structure.

[0097] Then, in Fig. 9 The device structure shown in (b) is formed on the outer surface away from the substrate 11 by magnetron sputtering, atomic layer deposition or evaporation to form a gate electrode film layer, as shown in FIG. Fig. 9 (c) shows the device structure.

[0098] Step S250, during the process of preparing the gate layer, the gate film layer to which the gate layer belongs is patterned by photolithography to obtain the gate layer, the source wiring layer electrically connected to the second source layer through the first via hole, and the drain wiring layer electrically connected to the second drain layer through the second via hole.

[0099] In this embodiment, a photolithography process can be combined with a dry or wet etching process to Fig. 9 The gate electrode film layer in the device structure shown in (c) is directly patterned to form the gate layer 16, the source wiring layer 183 and the drain wiring layer 184, as shown in FIG. Fig. 9 (d) shows the device structure. Fig. 9 The device structure shown in (d) is Figure 2 A first short channel hybrid contact thin film transistor 10 is shown.

[0100] In this application, to ensure Figure 3 or Figure 4 The second short channel hybrid contact thin film transistor 10 shown can be prepared and formed quickly and orderly. The embodiment of the present application provides a preparation method for the second short channel hybrid contact thin film transistor 10 to achieve the above functions.

[0101] Please refer to Fig.10 , Fig.10 This is one of the flow diagrams of the second method for preparing a short channel mixed contact thin film transistor provided in the embodiment of the present application. In the embodiment of the present application, Fig.10 The preparation method shown may include steps S310 to S330 to prepare Figure 3 A second short channel hybrid contact thin film transistor 10 is shown.

[0102] Step S310, providing a substrate.

[0103] Step S320, an insulating layer, a first source-drain electrode layer and a second source-drain electrode layer are sequentially stacked on one side of the substrate to obtain an intermediate stage device, wherein the first source-drain electrode layer includes a first source layer and a first drain layer spaced apart from each other, the second source-drain electrode layer includes a second source layer and a second drain layer spaced apart from each other, the first source layer is aligned with the side of the second source layer, and the first drain layer is aligned with the side of the second drain layer.

[0104] In this embodiment, the insulating layer 19 can be grown on one side of the substrate 11 by using a chemical vapor deposition method to obtain Fig.11 (a) shows the device structure, and then Fig.11 The device structure shown in (a) is formed by sequentially preparing a first source-drain electrode film layer and a second source-drain electrode film layer (i.e., corresponding to the outer surface of the substrate 11 away from the substrate 11) by magnetron sputtering, atomic layer deposition or thermal evaporation. Fig.11 (b)), then the second source-drain electrode film layer and the first source-drain electrode film layer are patterned by photolithography process combined with dry or wet etching process, so as to pattern the second source-drain electrode film layer into a second source-drain electrode layer 13 including a second source electrode layer 131 and a second drain electrode layer 132, and pattern the first source-drain electrode film layer into a first source-drain electrode layer 12 including a first source electrode layer 121 and a first drain electrode layer 122, so as to obtain Fig.11 (c) The intermediate stage device shown.

[0105] Step S330, sequentially preparing a channel semiconductor film layer, a gate dielectric layer and a gate layer on the outer surface of the intermediate stage device away from the substrate, wherein the channel semiconductor film layer simultaneously covers the side walls of the separation space between the first source-drain electrode layer and the second source-drain electrode layer, and partially covers the outer surface of the second source-drain electrode layer away from the substrate, the projection area of ​​the channel semiconductor film layer on the substrate covers the projection area of ​​the separation space, and the projection area of ​​the gate layer on the substrate at least covers the projection area of ​​the separation space.

[0106] In this embodiment, the second source layer 131 and the second drain layer 132 respectively form ohmic contact or quasi-ohmic contact with the channel semiconductor film layer 14 , and a local area of ​​the channel semiconductor film layer 14 that is in direct contact with the first source layer 121 and the first drain layer 122 forms a depletion region 17 .

[0107] In this embodiment, by Fig.11 (c) The intermediate stage device is formed by depositing a semiconductor film on the outer surface of the device away from the substrate 11 by magnetron sputtering or atomic layer deposition, and then the semiconductor film is patterned into the general shape of the channel semiconductor film layer 14 by photolithography combined with dry or wet etching, and the patterned semiconductor film is subjected to thermal annealing at 100-800°C, so as to Fig.11 The channel semiconductor film layer 14 is prepared and formed on the intermediate stage device shown in (c), and the Fig.12 (a) shows the device structure.

[0108] Then, you can Fig.12 The device structure shown in (a) is formed by growing the gate dielectric layer 15 on the outer surface away from the substrate 11 by chemical vapor deposition or atomic layer deposition, so as to obtain Fig.12 (b) shows the device structure.

[0109] Then, you can Fig.12 The device structure shown in (b) is formed by using magnetron sputtering, atomic layer deposition or evaporation to form a gate electrode film layer on the outer surface away from the substrate 11, and the gate electrode film layer is directly patterned into the gate layer 16 by using a photolithography process combined with a dry or wet etching process, so as to obtain a gate electrode layer 16 as shown in FIG. Fig.12 (c) shows the device structure. Fig.12 The device structure shown in (c) is Figure 3 A second short channel hybrid contact thin film transistor 10 is shown.

[0110] Optionally, see Fig.13 , Fig.13 FIG. 2 is a flow chart of a second method for preparing a short channel hybrid contact thin film transistor provided in an embodiment of the present application. Fig.10 Compared with the preparation method shown, Fig.13 The preparation method shown may also include steps S340 to S350 to prepare Figure 4 A second short channel hybrid contact thin film transistor 10 is shown.

[0111] Step S340, before preparing the gate layer, photolithography patterning is performed on the prepared gate dielectric layer, so that the gate dielectric layer forms a first via hole partially exposing the second source layer and a second via hole partially exposing the second drain layer.

[0112] In this embodiment, Fig.11 In the intermediate stage device shown in (c), the channel semiconductor film layer 14 and the gate dielectric layer 15 are sequentially prepared on the outer surface of the device away from the substrate 11, and the device is obtained as shown in FIG. Fig.12 (b) or Fig.14 Based on the device structure shown in (a), a photolithography process combined with a dry or wet etching process is used to Fig.14 The gate dielectric layer 15 in the device structure shown in (a) is patterned to form the first via hole 181 and the second via hole 182, as shown in FIG. Fig.14 (b) shows the device structure.

[0113] Then, in Fig.14 The device structure shown in (b) is formed on the outer surface away from the substrate 11 by magnetron sputtering, atomic layer deposition or evaporation to form a gate electrode film layer, as shown in FIG. Fig.14 (c) shows the device structure.

[0114] Step S250, during the process of preparing the gate layer, the gate film layer to which the gate layer belongs is patterned by photolithography to obtain the gate layer, the source wiring layer electrically connected to the second source layer through the first via hole, and the drain wiring layer electrically connected to the second drain layer through the second via hole.

[0115] In this embodiment, a photolithography process can be combined with a dry or wet etching process to Fig.14 The gate electrode film layer in the device structure shown in (c) is directly patterned to form the gate layer 16, the source wiring layer 183 and the drain wiring layer 184, as shown in FIG. Fig.14 (d) shows the device structure. Fig.14 The device structure shown in (d) is Figure 4 A second short channel hybrid contact thin film transistor 10 is shown.

[0116] In the present application, the embodiment of the present application may also provide a display panel, the display panel includes a pixel unit array and a plurality of any of the above-mentioned short channel hybrid contact thin film transistors 10, and the plurality of short channel hybrid contact thin film transistors 10 cooperate with each other to form a driving circuit for the pixel unit array. The display panel may be, but not limited to, an AMLCD (active matrix liquid crystal display) display panel, an AMOLED (active matrix organic light emitting diode display) display panel, a Mini-LED (mini light emitting diode) display panel, a Micro-LED (micro light emitting diode) display panel, etc.

[0117] In the present application, an embodiment of the present application further provides a dynamic random access memory, the dynamic random access memory comprising a plurality of any of the aforementioned short channel hybrid contact thin film transistors 10, wherein the plurality of the short channel hybrid contact thin film transistors 10 cooperate with each other to realize a data dynamic storage function. In one implementation of the present embodiment, a 2T0C three-dimensional dynamic random access memory unit can be constructed by two of the short channel hybrid contact thin film transistors 10.

[0118] The above are only various implementations of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A short channel mixed contact thin film transistor, characterized in that: The thin film transistor comprises: substrate; A first source-drain electrode layer and a second source-drain electrode layer are sequentially stacked on one side of the substrate, wherein the first source-drain electrode layer includes a first source electrode layer and a first drain electrode layer spaced apart from each other, the second source-drain electrode layer includes a second source electrode layer and a second drain electrode layer spaced apart from each other, the first source electrode layer is aligned with the second source layer side surface, and the first drain electrode layer is aligned with the second drain layer side surface; a channel semiconductor film layer grown along the sidewalls of the respective separation spaces between the first source-drain electrode layer and the second source-drain electrode layer, wherein the channel semiconductor film layer partially covers the outer surface of the second source-drain electrode layer away from the substrate, the second source electrode layer and the second drain electrode layer respectively form an ohmic contact or a quasi-ohmic contact with the channel semiconductor film layer, a local area of ​​the channel semiconductor film layer directly contacting the first source electrode layer and the first drain electrode layer forms a depletion region, and a projection area of ​​the channel semiconductor film layer on the substrate covers a projection area of ​​the separation space; A gate dielectric layer covering the outer surface areas of the channel semiconductor film layer and the second source-drain electrode layer that are not blocked by the channel semiconductor film layer, and a gate layer at least partially covering the gate dielectric layer, wherein the projection area of ​​the gate layer on the substrate at least covers the projection area of ​​the separation space.

2. The thin film transistor according to claim 1, characterized in that: The thin film transistor further comprises an insulating layer, the insulating layer is made of any one of silicon dioxide and silicon nitride or a stack of two materials, and the thickness of the insulating layer is in the range of 5-1000 nm; The insulating layer is disposed between the substrate and the first source-drain electrode layer, and the channel semiconductor film layer covers a local surface area of ​​the insulating layer that is not blocked by the first source-drain electrode layer.

3. The thin film transistor according to claim 1 or 2, characterized in that: The thin film transistor further comprises: A source wiring layer electrically connected to the second source layer via the gate dielectric layer, and a drain wiring layer electrically connected to the second drain layer via the gate dielectric layer, wherein the source wiring layer and the drain wiring layer are each made of any one of aluminum, molybdenum, titanium, chromium, tungsten, nickel, platinum, gold, indium tin oxide material, and aluminum-doped zinc oxide material, and the thickness of each of the source wiring layer and the drain wiring layer is in the range of 1-1000nm.

4. The thin film transistor according to claim 1 or 2, characterized in that: The thickness of the first source-drain electrode layer is in the range of 1-1000 nm, and the thickness of the second source-drain electrode layer is in the range of 5-1000 nm, wherein the width of the interval space in the same source-drain electrode layer is greater than or equal to 5 nm; The thickness of the channel semiconductor film layer is in the range of 1-100 nm; The thickness of the gate dielectric layer is in the range of 1-1000 nm; The thickness of the gate layer is in the range of 1-1000 nm.

5. The thin film transistor according to claim 1 or 2, characterized in that: The second source-drain electrode layer and the gate layer are each made of any one of aluminum, molybdenum, titanium, chromium, tungsten, nickel, platinum, gold, indium tin oxide material, and aluminum-doped zinc oxide material; The gate dielectric layer is made of a stack of any one or more materials selected from silicon dioxide, silicon nitride, aluminum oxide, hafnium oxide, and zirconium oxide; When the material of the channel semiconductor film layer is an N-type semiconductor material, the material of the first source-drain electrode layer is a P-type conductor material, a P-type semiconductor material, or a metal material having a corresponding work function greater than that of the N-type semiconductor material, wherein the N-type semiconductor material includes at least one of N-type doped silicon, N-type doped germanium, indium gallium zinc oxide, indium zinc oxide, indium zinc tin oxide, rare earth-doped indium zinc oxide, indium tin oxide, aluminum-doped zinc oxide, indium gallium oxide, zinc oxide, gallium oxide, indium oxide, and tin oxide, and the material of the first source-drain electrode layer includes at least one of tellurium, telluride, P-type doped silicon, P-type doped germanium, copper iodide, cuprous oxide, stannous oxide, copper, molybdenum, cobalt, titanium, nickel, tungsten, chromium, gold, silver, platinum, and palladium; When the material for preparing the channel semiconductor film layer is a P-type semiconductor material, the material for preparing the first source and drain electrode layer is an N-type conductor material, an N-type semiconductor material, or a metal material having a corresponding work function smaller than that of the P-type semiconductor material, wherein the P-type semiconductor material includes at least one of tellurium, telluride, P-type doped silicon, P-type doped germanium, copper iodide, cuprous oxide, and stannous oxide, and the material for preparing the first source and drain electrode layer includes at least one of N-type doped silicon, N-type doped germanium, indium gallium zinc oxide, indium zinc oxide, indium zinc tin oxide, rare earth-doped indium zinc oxide, indium tin oxide, aluminum-doped zinc oxide, indium gallium oxide, zinc oxide, gallium oxide, indium oxide and tin oxide, aluminum, scandium, barium, bismuth, yttrium, and hafnium.

6. A method for preparing a short channel mixed contact thin film transistor, characterized in that: The preparation method comprises: providing a substrate; A first source-drain electrode layer and a second source-drain electrode layer are sequentially stacked on one side of the substrate to obtain an intermediate stage device, or an insulating layer, a first source-drain electrode layer and a second source-drain electrode layer are sequentially stacked on one side of the substrate to obtain an intermediate stage device; wherein the first source-drain electrode layer includes a first source electrode layer and a first drain electrode layer spaced from each other, the second source-drain electrode layer includes a second source electrode layer and a second drain electrode layer spaced from each other, the first source layer is aligned with the second source layer side, and the first drain layer is aligned with the second drain layer side; A channel semiconductor film layer, a gate dielectric layer and a gate layer are sequentially prepared on the outer surface of the intermediate stage device away from the substrate; wherein the channel semiconductor film layer simultaneously covers the side walls of the separation space between the first source-drain electrode layer and the second source-drain electrode layer, and partially covers the outer surface of the second source-drain electrode layer away from the substrate; the second source layer and the second drain layer respectively form ohmic contact or quasi-ohmic contact with the channel semiconductor film layer, and a local area of ​​the channel semiconductor film layer directly in contact with the first source layer and the first drain layer forms a depletion region; the projection area of ​​the channel semiconductor film layer on the substrate covers the projection area of ​​the separation space, and the projection area of ​​the gate layer on the substrate at least covers the projection area of ​​the separation space.

7. The preparation method according to claim 6, characterized in that: The insulating layer is grown by chemical vapor deposition; The first source-drain electrode layer and the second source-drain electrode layer are both obtained by patterning the source-drain electrode film layer by photolithography, wherein the source-drain electrode film layer is prepared by magnetron sputtering, atomic layer deposition or thermal evaporation; The channel semiconductor film layer is obtained by subjecting the semiconductor film patterned by photolithography to a thermal annealing treatment at 100-800° C., wherein the semiconductor film is deposited by a magnetron sputtering method or an atomic layer deposition method; The gate dielectric layer is grown by chemical vapor deposition or atomic layer deposition; The gate layer is obtained by photolithography and patterning a gate electrode film layer, wherein the gate electrode film layer is prepared by magnetron sputtering, atomic layer deposition or evaporation.

8. The preparation method according to claim 7, characterized in that: The preparation method further comprises: Before preparing the gate layer, the prepared gate dielectric layer is patterned by photolithography, so that the gate dielectric layer forms a first via hole partially exposing the second source electrode layer and a second via hole partially exposing the second drain electrode layer; During the preparation of the gate layer, the gate film layer to which the gate layer belongs is photolithographically patterned to obtain the gate layer, the source wiring layer electrically connected to the second source layer through the first via hole, and the drain wiring layer electrically connected to the second drain layer through the second via hole.

9. A dynamic random access memory, characterized in that: The memory comprises a plurality of short channel hybrid contact thin film transistors as described in any one of claims 1 to 5, and the plurality of short channel hybrid contact thin film transistors cooperate with each other to realize a data dynamic storage function.

10. A display panel, characterized in that: The display panel comprises a pixel unit array and a plurality of short channel hybrid contact thin film transistors as described in any one of claims 1 to 5, wherein the plurality of short channel hybrid contact thin film transistors cooperate with each other to form a driving circuit for the pixel unit array.

Images