Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. According to the display panel, a driving circuit layer comprises a plurality of light-emitting control lines, a plurality of reset control lines, a plurality of light-emitting patch cords and a plurality of reset patch cords, one light-emitting patch cord is connected with one light-emitting control line, one reset patch cord is connected with one reset control line, and at least one light-emitting patch cord is provided with a fracture; and / or at least one reset patch cord is provided with a fracture; therefore, the impedance of the light-emitting control line and the reset control line is small, and static electricity is dispersed on a plurality of parts of the light-emitting patch cord. And / or static electricity is dispersed on a plurality of parts of the reset patch cord, so that static electricity accumulation is avoided, the risk of electrostatic explosion caused by point discharge is reduced, and the yield of the display panel is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] OLED (Organic Light-Emitting Diode) display devices are widely used due to their advantages such as self-luminescence, wide color gamut, low power consumption, and flexible display. OLED display devices are driven by pixel driving circuits, but in the use of OLED display devices, it is found that the impedance of some signal lines is large, which easily leads to large signal delays, which in turn leads to problems such as insufficient pixel charging or mischarging, resulting in poor display. In order to reduce the impedance of the signal line, some signal lines will adopt a double-layer design, that is, two parts of the signal line are formed by two film layers to reduce the impedance of the signal line. However, in actual use, it is found that since the edge of the signal line is relatively thin, after static electricity accumulates on the signal line, it is easy to cause tip discharge between the edge of the signal line and the active layer, and then turn on the active layer and the signal line, so that the transistor cannot be turned off, and bright spots appear on the display panel, resulting in abnormal display.

[0003] Therefore, the existing display device has a technical problem that a tip discharge occurs between the edge of the signal line and the active layer, resulting in abnormal display. Summary of the invention

[0004] Embodiments of the present application provide a display panel and a display device, which are used to solve the technical problem of abnormal display caused by tip discharge between the edge of a signal line and an active layer in existing display devices.

[0005] In order to achieve the above objective, according to a first aspect of the present application, a display panel is provided, the display panel comprising:

[0006] substrate;

[0007] A driving circuit layer is arranged on one side of the substrate, the driving circuit layer includes a plurality of light-emitting control lines, a plurality of reset control lines, a plurality of light-emitting adapter lines and a plurality of reset adapter lines, one of the light-emitting adapter lines is connected to one of the light-emitting control lines, and one of the reset adapter lines is connected to one of the reset control lines;

[0008] Among them, at least one of the light-emitting adapter wires is provided with a break; and / or at least one of the reset adapter wires is provided with a break.

[0009] According to a second aspect of the present application, a display device is provided, comprising a display panel as described in any one of the above embodiments.

[0010] The embodiments of the present application provide a display panel and a display device; the display panel includes a driving circuit layer including multiple light-emitting control lines, multiple reset control lines, multiple light-emitting adapter lines and multiple reset adapter lines, a light-emitting adapter line is connected to a light-emitting control line, a reset adapter line is connected to a reset control line, wherein at least one light-emitting adapter line is provided with a break; and / or at least one reset adapter line is provided with a break; the impedance of the light-emitting control line and the reset control line can be made smaller, and the static electricity is dispersed on multiple parts of the light-emitting adapter line; and / or the static electricity is dispersed on multiple parts of the reset adapter line, thereby avoiding static electricity accumulation, reducing the risk of static electricity injury caused by tip discharge, and improving the yield of the display panel.

[0011] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0013] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same figure numbers represent the same parts in the following description.

[0014] Figure 1 A schematic cross-sectional view of a comparative display device provided in an embodiment of the present application.

[0015] Figure 2 A schematic plan view of a display panel provided in an embodiment of the present application.

[0016] Figure 3 A first cross-sectional schematic diagram of a display panel provided in an embodiment of the present application.

[0017] Figure 4 A second cross-sectional schematic diagram of a display panel provided in an embodiment of the present application.

[0018] Figure 5 A circuit diagram of a pixel driving circuit of a display panel provided in an embodiment of the present application.

[0019] Figure 6 A stacking diagram of various film layers of a pixel unit of a display panel provided in an embodiment of the present application.

[0020] Figure 7 for Figure 6 An exploded view of the active layer of a display panel.

[0021] Figure 8 for Figure 6 An exploded view of the first gate layer of the display panel in FIG.

[0022] Fig. 9 for Figure 6 An exploded view of the second gate layer of the display panel in FIG.

[0023] Fig.10 for Figure 6 An exploded view of the first source-drain layer of the display panel in FIG.

[0024] Fig.11 for Figure 6 An exploded view of the second source-drain layer of the display panel in FIG.

[0025] Fig.12 for Figure 6 Exploded view of the pixel electrode layer of the display panel.

[0026] Fig.13 for Figure 6 A stacking diagram of the active layer and the first gate layer of the display panel in FIG.

[0027] Fig.14 for Figure 6 A stacking diagram of an active layer, a first gate layer and a second gate layer of a display panel in FIG.

[0028] Fig.15 for Figure 6 A stacked diagram of an active layer, a first gate layer, a second gate layer and a first source and drain layer of a display panel in FIG.

[0029] Fig.16 for Figure 6 A stacking diagram of an active layer, a first gate layer, a second gate layer, a first source-drain electrode layer, and a second source-drain electrode layer of a display panel in FIG.

[0030] Fig.17 for Figure 6 Schematic diagram of the A1-A2 cross-section of the display panel. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0032] In order to illustrate the principle of the technical problem of the embodiment of the present application, the embodiment of the present application provides a comparative display device. It can be understood that the comparative display device cannot be used as the prior art of the embodiment of the present application. Specifically, the comparative display device includes a plurality of sub-pixel units, each sub-pixel unit includes a pixel driving circuit and a light-emitting device, the pixel driving circuit includes a light-emitting control line and a reset control line, the light-emitting control line is connected to the light-emitting control transistor, and the reset control line is connected to the reset transistor. In order to reduce the impedance of the light-emitting control line and the reset control line, the light-emitting control line and the reset control line are double-layered.

[0033] like Figure 1 As shown, the comparative display device includes a substrate 111, a semiconductor film layer 112, a first insulating film layer 113, a first gate film layer 114, a second insulating film layer 115 and a first source-drain film layer 116. The light-emitting control line includes a first light-emitting control line arranged in the first gate film layer 114 and a second light-emitting control line located in the first source-drain film layer 116, and the reset control line includes a first reset control line arranged in the first gate film layer 114 and a second reset control line located in the first source-drain film layer 116. Since the light-emitting control line is a double-layer line, the first light-emitting control line and the second light-emitting control line are both long lines, static electricity 117 is easy to accumulate on the light-emitting control line, and the second light-emitting control line is staggered with the first light-emitting control line, the capacitance between the second light-emitting control line and the semiconductor film layer 112 will be relatively large, further increasing the capacitance between the light-emitting control line and the semiconductor film layer 112. The first light-emitting control line is relatively close to the semiconductor film layer 112, and the edge of the first light-emitting control line is relatively thin. The first light-emitting control line is prone to tip discharge with the semiconductor film layer 112, resulting in electrostatic damage, causing the light-emitting control line to be turned on with the active pattern of the light-emitting transistor. The light-emitting control line controls the light-emitting transistor, which causes the light-emitting transistor to be turned on all the time, so that the sub-pixel unit is always lit, resulting in bright spots, resulting in poor display. Similarly, the first reset control line and the second reset control line are long lines, and static electricity is easily accumulated in the reset control line. The first reset control line is relatively close to the semiconductor film layer 112, and the edge of the first reset control line is relatively thin. The first reset control line is prone to tip discharge with the semiconductor film layer 112, resulting in electrostatic damage, causing the reset control line to be turned on with the active pattern of the reset transistor. The reset control line controls the reset transistor, which causes the reset transistor to be turned on all the time, and also causes abnormal display of the sub-pixel unit. Therefore, the existing display device has a technical problem of tip discharge between the edge of the signal line and the active layer, resulting in abnormal display.

[0034] In view of the above technical problems, the embodiments of the present application provide a display panel and a display device to solve the above technical problems.

[0035] Figure 2 A schematic plan view of a display panel provided in an embodiment of the present application. Figure 3 A first cross-sectional schematic diagram of a display panel provided in an embodiment of the present application. Figure 4 A second cross-sectional schematic diagram of a display panel provided in an embodiment of the present application. Figure 5 A circuit diagram of a pixel driving circuit of a display panel provided in an embodiment of the present application. Figure 6 A stacking diagram of various film layers of a pixel unit of a display panel provided in an embodiment of the present application. Figure 7 for Figure 6 An exploded view of the active layer of a display panel. Figure 8 for Figure 6 An exploded view of the first gate layer of the display panel in FIG. Fig. 9 for Figure 6 An exploded view of the second gate layer of the display panel in FIG. Fig.10 for Figure 6 An exploded view of the first source-drain layer of the display panel in FIG. Fig.11 for Figure 6 An exploded view of the second source-drain layer of the display panel in FIG. Fig.12 for Figure 6 Exploded view of the pixel electrode layer of the display panel. Fig.13 for Figure 6 A stacking diagram of the active layer and the first gate layer of the display panel in FIG. Fig.14 for Figure 6 A stacking diagram of an active layer, a first gate layer and a second gate layer of a display panel in FIG. Fig.15 for Figure 6 A stacked diagram of an active layer, a first gate layer, a second gate layer and a first source and drain layer of a display panel in FIG. Fig.16 for Figure 6 A stacking diagram of an active layer, a first gate layer, a second gate layer, a first source-drain electrode layer, and a second source-drain electrode layer of a display panel in FIG. Fig.17 for Figure 6 Schematic diagram of the A1-A2 cross-section of the display panel.

[0036] like Figures 2 to 17 As shown, an embodiment of the present application provides a display panel, the display panel 2 includes a substrate 21 and a driving circuit layer 22, the driving circuit layer 22 is arranged on one side of the substrate 21, the driving circuit layer 22 includes a plurality of light-emitting control lines EM, a plurality of reset control lines Reset-A, a plurality of light-emitting adapter lines SL4 and a plurality of reset adapter lines SL3, one of the light-emitting adapter lines SL4 is connected to one of the light-emitting control lines EM, and one of the reset adapter lines SL3 is connected to one of the reset control lines Reset-A;

[0037] Among them, at least one of the light-emitting adapter wires SL4 is provided with a break 311; and / or at least one of the reset adapter wires SL3 is provided with a break.

[0038] An embodiment of the present application provides a display panel, which includes a driving circuit layer including multiple light-emitting control lines, multiple reset control lines, multiple light-emitting adapter lines and multiple reset adapter lines, wherein a light-emitting adapter line is connected to a light-emitting control line, and a reset adapter line is connected to a reset control line, wherein at least one of the light-emitting adapter lines is provided with a break; and / or at least one of the reset adapter lines is provided with a break; thereby, the impedance of the light-emitting control line and the reset control line can be made smaller, and static electricity can be dispersed on multiple parts of the light-emitting adapter line; and / or static electricity can be dispersed on multiple parts of the reset adapter line, thereby avoiding static electricity accumulation, reducing the risk of static electricity injury caused by tip discharge, and improving the yield of the display panel.

[0039] Specifically, the light-emitting control line EM and the light-emitting adapter line SL4 are arranged at different layers; the reset adapter line SL3 and the reset control line Reset-A are arranged at different layers.

[0040] In some embodiments, Figures 2 to 17 As shown, the display panel 2 includes a plurality of pixel units 240, each of which includes a plurality of sub-pixel units (e.g., a first sub-pixel unit 240a, a second sub-pixel unit 240b, and a third sub-pixel unit 240c), and the light-emitting adapter line SL4 includes a plurality of light-emitting connecting lines EM-L, and the break 311 is provided between two adjacent light-emitting connecting lines EM-L, and each of the light-emitting connecting lines EM-L is provided corresponding to a sub-pixel unit. By providing each light-emitting connecting line corresponding to a sub-pixel unit, each light-emitting connecting line can drive each transistor, so that each sub-pixel unit works normally. At the same time, the light-emitting adapter line is divided into a plurality of light-emitting connecting lines, so as to further disperse static electricity, avoid static electricity accumulation, reduce the risk of static electricity explosion caused by tip discharge, and improve the yield of the display panel.

[0041] In some embodiments, Figures 2 to 17As shown, the display panel 2 includes a plurality of pixel units 240, each of the pixel units 240 includes a plurality of sub-pixel units (e.g., a first sub-pixel unit 240a, a second sub-pixel unit 240b, and a third sub-pixel unit 240c), and the reset adapter line SL4 includes a plurality of reset connection lines RL, and there is a break between two adjacent reset connection lines RL, and each reset connection line RL is set corresponding to one of the sub-pixel units. By setting each reset connection line corresponding to one of the sub-pixel units, each reset connection line can drive a transistor, so that each sub-pixel unit works normally. At the same time, the reset adapter line is divided into a plurality of reset connection lines, so as to further disperse static electricity, avoid static electricity accumulation, reduce the risk of static electricity explosion caused by tip discharge, and improve the yield of the display panel.

[0042] The above embodiment is described by taking the example of a break being set between two sub-pixel units, but the embodiments of the present application are not limited to this. The break can be set within a sub-pixel unit so that the break avoids the active pattern of each transistor, that is, the break does not overlap with the projection of the active pattern of each transistor on the substrate.

[0043] In some embodiments, Figures 2 to 17 As shown, the display panel 2 includes a plurality of pixel units 240, each of which includes a plurality of sub-pixel units (e.g., a first sub-pixel unit 240a, a second sub-pixel unit 240b, and a third sub-pixel unit 240c), the light-emitting adapter SL4 includes a plurality of light-emitting connecting lines EM-L, a break 311 is provided between two adjacent light-emitting connecting lines EM-L, and each light-emitting connecting line EM-L is provided corresponding to one sub-pixel unit; the reset adapter SL4 includes a plurality of reset connecting lines RL, a break is provided between two adjacent reset connecting lines RL, and each reset connecting line RL is provided corresponding to one sub-pixel unit. By making each light-emitting connecting line corresponding to one sub-pixel unit, and each reset connecting line corresponding to one sub-pixel unit, each light-emitting connecting line can drive each transistor, and each reset connecting line can drive a transistor, so that each sub-pixel unit works normally. At the same time, the light-emitting adapter is divided into a plurality of light-emitting connecting lines, and the reset adapter is divided into a plurality of reset connecting lines, so as to further disperse static electricity, avoid static electricity accumulation, reduce the risk of static electricity explosion caused by tip discharge, and improve the yield of the display panel. Specifically, each light-emitting connection line is connected to a light-emitting control line, and each reset connection line is connected to a reset control line.

[0044] In some embodiments, Figures 2 to 17As shown, the driving circuit layer 22 includes a first gate layer 224 and a first source-drain layer 228, the first gate layer 224 is arranged between the substrate 21 and the first source-drain layer 228, the first gate layer 224 includes the light-emitting connection line EM-L and the reset connection line RL, and the first source-drain layer 228 includes the light-emitting control line EM and the reset control line Reset-A. By arranging the light-emitting connection line and the reset connection line in the first gate layer, the light-emitting control line and the reset control line in the first source-drain layer, and the light-emitting connection line is connected to the light-emitting control line, and the reset connection line is connected to the reset control line, the impedance of the light-emitting control line and the reset control line can be reduced, and multiple light-emitting connection lines connected to the same light-emitting control line are disconnected, and multiple reset connection lines connected to the same reset control line are disconnected, which can avoid static electricity accumulation, reduce the risk of static electricity explosion caused by tip discharge, and improve the yield of the display panel.

[0045] like Figures 2 to 17 As shown, an embodiment of the present application provides a display panel, the display panel 2 includes a plurality of pixel units 240, each of the pixel units 240 includes a plurality of sub-pixel units (for example, a first sub-pixel unit 240a, a second sub-pixel unit 240b and a third sub-pixel unit 240c), the display panel 2 includes a substrate 21 and a driving circuit layer 22, the driving circuit layer 22 is arranged on one side of the substrate 21, the driving circuit layer 22 includes a first gate layer 224 and a first source-drain layer 228, the first gate layer 224 is arranged between the substrate 21 and the first source-drain layer 228, the first gate layer 224 includes a plurality of light-emitting connection lines EM-L and a plurality of reset connection lines RL, the first source-drain layer 228 includes a light-emitting control line EM and a reset control line Reset-A, the light-emitting connection line EM-L is connected to the light-emitting control line EM, and the reset connection line RL is connected to the reset control line Reset-A;

[0046] In two adjacent sub-pixel units (eg, the first sub-pixel unit 240a and the second sub-pixel unit 240b), two adjacent light-emitting connection lines EM-L are disconnected, and / or two adjacent reset connection lines RL are disconnected.

[0047] An embodiment of the present application provides a display panel, which includes a first gate layer 224 including a plurality of light-emitting connection lines EM-L and a plurality of reset connection lines RL, and a first source-drain layer 228 including a light-emitting control line EM and a reset control line Reset-A. The light-emitting connection line EM-L is connected to the light-emitting control line EM, and the reset connection line RL is connected to the reset control line Reset-A. In two adjacent sub-pixel units, two adjacent light-emitting connection lines EM-L are disconnected, and / or two adjacent reset connection lines RL are disconnected, so that the impedance of the light-emitting control line and the reset control line is small, and static electricity is dispersed on the plurality of light-emitting connection lines; and / or static electricity is dispersed on the plurality of reset connection lines, so as to avoid static electricity accumulation, reduce the risk of static electricity injury caused by tip discharge, and improve the yield of the display panel.

[0048] Specifically, there is a slope at the edges of the light-emitting connection line and the reset connection line.

[0049] Specifically, in the first direction, in two adjacent sub-pixel units, two adjacent light-emitting connection lines are disconnected, and / or two adjacent reset connection lines are disconnected.

[0050] Specifically, it can be understood that in the pixel driving circuit, each transistor has a gate, a first electrode, and a second electrode. However, in the actual preparation process, in order to reduce the space occupied by the transistor, some transistor electrodes are not separately set, but the electrodes and signal lines of each transistor are directly connected. For example, in the pixel driving circuit, the first electrode of the driving transistor T1 and the second electrode of the switching transistor T2 are connected to the first node A. When preparing the driving transistor and the switching transistor, there is no need to separately set the first electrode of the driving transistor and the second electrode of the switching transistor. The active pattern of the driving transistor is directly connected to the active pattern of the switching transistor. The connection between the active pattern of the driving transistor and the active pattern of the switching transistor can be regarded as the first node A, thereby reducing the electrodes of the transistor and reducing the space occupied by the transistor. In another example, the first electrode of the compensation transistor is connected to the second electrode of the initialization transistor, but in actual design, there is no need to separately set the first electrode of the compensation transistor and the second electrode of the initialization transistor. The active pattern of the compensation transistor and the active pattern of the initialization transistor are directly connected together. The connection between the active pattern of the compensation transistor and the active pattern of the initialization transistor can be regarded as a point connected to the Q point, or as the Q point, thereby reducing the electrodes of the transistor and reducing the occupied space of the transistor. Similarly, other structures not marked in the film layer diagram also adopt the above design, which can be referred to the above description and will not be repeated in the following embodiments.

[0051] Specifically, in the actual preparation process, in order to reduce the space occupied by the transistor, another way is to make the electrodes of multiple transistors share, or the electrodes of the transistors and the signal lines share the same structure, for example, the gate of the driving transistor is connected to one plate of the storage capacitor, and there is no need to separately set the gate of the driving transistor and one plate of the storage capacitor, and one structure can be used as the gate of the driving transistor and one plate of the storage capacitor. Similarly, for other cases where the same structure is used as the electrodes and / or signal lines of multiple transistors, please refer to the above description, and no further description will be given in the following embodiments.

[0052] Specifically, the display panel includes a plurality of repeating units, and one repeating unit may include a pixel unit, such as the attached pixel unit in the embodiment of the present application. Figure 6 The pixel unit shown is, or a pixel unit in which the reset connection line is electrically connected to the first electrode of the initialization transistor. A repeating unit may also include two pixel units, the difference between the two pixel units is that the reset connection line in one pixel unit is electrically connected to the first electrode of the initialization transistor, and the first electrode of the initialization transistor is connected to the initialization signal line, thereby reducing the voltage drop of the initialization signal line, and the reset connection line in the other pixel unit is electrically connected to the reset signal line, thereby reducing the voltage drop of the reset signal line, and for other parts, the two pixel units may be the same. The following embodiment is described by taking a repeating unit including a pixel unit as an example.

[0053] Specifically, the display panel may include multiple pixel units 240, each pixel unit 240 may include multiple sub-pixel units, the multiple sub-pixel units may include a first sub-pixel unit 240a, a second sub-pixel unit 240b and a third sub-pixel unit 240c, the first sub-pixel unit 240a, the second sub-pixel unit 240b and the third sub-pixel unit 240c all include a pixel driving circuit 220 and a light-emitting device LED, the design of the light-emitting devices of the first sub-pixel unit 240a, the second sub-pixel unit 240b and the third sub-pixel unit 240c may be different, specifically, the light-emitting colors of the light-emitting devices of the first sub-pixel unit 240a, the second sub-pixel unit 240b and the third sub-pixel unit 240c may be different, and / or the areas of the light-emitting devices may be different, and / or the thicknesses of the light-emitting devices may be different.

[0054] Specifically, the light-emitting colors of the first sub-pixel unit, the second sub-pixel unit, and the third sub-pixel unit may be red, green, and blue, respectively, but the embodiments of the present application are not limited thereto. For example, the light-emitting colors of the first sub-pixel unit, the second sub-pixel unit, and the third sub-pixel unit may be red, blue, and green, respectively, or the light-emitting colors of the first sub-pixel unit, the second sub-pixel unit, and the third sub-pixel unit may be blue, green, and red, respectively.

[0055] Specifically, in the embodiments of the present application, it should be noted that, except for the differences explicitly described, the design of all pixel units can refer to the design of the pixel unit provided in the embodiments of the present application. Similarly, the design of all pixel driving circuits can refer to the design of the pixel driving circuit in the embodiments of the present application. For example, the difference between two pixel driving circuits is that the high potential power line of one pixel driving circuit is different from the high potential power line in the other pixel driving circuit, while the other designs of the two pixel driving circuits are the same. In describing the design of the pixel driving circuit, it can be considered that except for the difference in the high potential power line, the other designs of the two pixel driving circuits are the same. Similarly, the differences and the same designs of the pixel units can be determined, and they will not be repeated in the following embodiments.

[0056] Specifically, Figure 2 As shown, the display panel 2 includes a display area AA and a non-display area NA, and the pixel unit is arranged in the display area AA.

[0057] Specifically, Figure 3 , Figure 4 As shown, the display panel 2 includes a substrate 21 , a driving circuit layer 22 , a light-emitting functional layer 24 and an encapsulation layer 25 .

[0058] Specifically, the driving circuit layer 22 includes a buffer layer 221, an active layer 222, a first gate insulating layer 223, a first gate layer 224, a second gate insulating layer 225, a second gate layer 226, an interlayer insulating layer 227, a first source and drain layer 228, a passivation layer 229, a first planarization layer 231, a second source and drain layer 232, a second planarization layer 233 and a third planarization layer 234. The buffer layer 221 is arranged on one side of the substrate 21, the active layer 222 is arranged on a side of the buffer layer 221 away from the substrate 21, the first gate insulating layer 223 is arranged on a side of the active layer 222 away from the buffer layer 221, the first gate layer 224 is arranged on a side of the first gate insulating layer 223 away from the active layer 222, and the second gate insulating layer 225 is arranged on a side of the first gate layer 224 away from the first gate insulating layer 223. The second gate layer 226 is arranged on the side of the second gate insulating layer 225 away from the first gate layer 224, the interlayer insulating layer 227 is arranged on the side of the second gate layer 226 away from the second gate insulating layer 225, the first source and drain layer 228 is arranged on the side of the interlayer insulating layer 227 away from the second gate layer 226, the passivation layer 229 is arranged on the side of the first source and drain layer 228 away from the interlayer insulating layer 227, the first planarization layer 231 is arranged on the side of the passivation layer 229 away from the first source and drain layer 228, the second source and drain layer 232 is arranged on the side of the first planarization layer 231 away from the passivation layer 229, the second planarization layer 233 is arranged on the side of the second source and drain layer 232 away from the first planarization layer 231, and the third planarization layer 234 is arranged on the side of the second planarization layer 233 away from the second source and drain layer 232.

[0059] Specifically, the light-emitting functional layer 24 includes a pixel electrode layer 241, a pixel definition layer 242, a light-emitting material layer 243 and a common electrode layer 244. The pixel definition layer 242 is arranged on the side of the pixel electrode layer 241 away from the driving circuit layer 22, the light-emitting material layer 243 is arranged on the side of the pixel definition layer 242 away from the pixel electrode layer 241, and the common electrode layer 244 is arranged on the side of the light-emitting material layer 243 away from the pixel definition layer 242.

[0060] Specifically, the pixel definition layer 242 may include a first pixel definition layer 242 a and a second pixel definition layer 242 b , but the embodiment of the present application is not limited thereto, and the pixel definition layer may also be a single-layer design.

[0061] Specifically, the encapsulation layer 25 includes a first inorganic layer, an organic layer and a second inorganic layer.

[0062] Specifically, the light emitting functional layer 24 includes a light emitting device LED, and the pixel electrode layer 241 in the light emitting functional layer 24 includes an anode ANO of the light emitting device LED.

[0063] Specifically, since the embodiments of the present application describe the display panel from the perspective of the circuit, film layer structure, and design of each film layer of the display panel, some structures may belong to both one structure and another structure. This is because they are defined from different angles. For example, the pixel driving circuit belongs to the driving circuit layer. This is considered from the film layer structure. The pixel driving circuit is formed by the structure in the driving circuit layer. In addition, the pixel unit includes a pixel driving circuit. This is considered from the design of the pixel unit. Each pixel unit needs to be driven by a corresponding pixel driving circuit. It can be understood that the pixel driving circuits belonging to the two structures of the driving circuit layer and the pixel unit are the same pixel driving circuit. Similarly, other similar defined descriptions can be found in the above descriptions and will not be repeated in the following embodiments.

[0064] In some embodiments, in any two of the sub-pixel units, two adjacent light-emitting connection lines are disconnected. By disconnecting two adjacent light-emitting connection lines in any two sub-pixel units, static electricity can be dispersed on multiple light-emitting connection lines, thereby reducing the risk of tip discharge between the light-emitting connection lines and the active layer, and improving the yield of the display panel.

[0065] Specifically, compared to the comparative display device, the first light-emitting control line is a long line, and static electricity will accumulate on the first light-emitting control line. In addition, since there is a slope at the edge of the first light-emitting control line and the thickness of the edge is relatively small, it is easy for the slope of the first light-emitting control line to have tip discharge with the semiconductor film layer. The embodiment of the present application can disperse the static electricity to multiple light-emitting connecting lines for release by disconnecting two adjacent light-emitting connecting lines, thereby avoiding the problem of static electricity breakdown between the light-emitting connecting lines and the active pattern caused by static electricity accumulation, thereby reducing the risk of tip discharge between the light-emitting connecting lines and the active layer and improving the yield of the display panel.

[0066] In some embodiments, in any two of the sub-pixel units, two adjacent reset connection lines are disconnected. By disconnecting two adjacent reset connection lines in any two sub-pixel units, static electricity can be dispersed on multiple reset connection lines, thereby reducing the risk of tip discharge between the reset connection line and the active layer, and improving the yield of the display panel.

[0067] Specifically, compared to the comparative display device, the first reset control line is a long line, static electricity will accumulate on the first reset control line, and because there will be a slope at the edge of the first reset control line and the thickness of the edge is relatively small, it is easy for the slope of the first reset control line to have a tip discharge with the semiconductor film layer. In the embodiment of the present application, by disconnecting two adjacent reset connection lines, the static electricity can be dispersed to multiple reset connection lines for release, thereby avoiding the problem of static electricity breakdown between the reset connection line and the active pattern due to static electricity accumulation, thereby reducing the risk of tip discharge between the reset connection line and the active layer and improving the yield of the display panel.

[0068] In some embodiments, Figures 6 to 15 As shown, in any two of the sub-pixel units, two adjacent light-emitting connection lines EM-L are disconnected, and two adjacent reset connection lines RL are disconnected. By making two adjacent light-emitting connection lines disconnected and two adjacent reset connection lines disconnected in any two sub-pixel units, static electricity can be dispersed on multiple light-emitting connection lines, and static electricity can be dispersed on multiple reset connection lines, thereby reducing the risk of tip discharge between the light-emitting connection line and the active layer, reducing the risk of tip discharge between the reset connection line and the active layer, and improving the yield of the display panel.

[0069] Specifically, compared with the comparative display device, the first light-emitting control line is a long line, and the first reset control line is a long line. Static electricity will accumulate on the first light-emitting control line and the first reset control line. Moreover, since there will be a slope at the edges of the first light-emitting control line and the first reset control line, and the thickness of the edge is relatively small, it is easy for the first light-emitting control line and the first reset control line to have a tip discharge with the semiconductor film layer at the slope. In the embodiment of the present application, by disconnecting two adjacent light-emitting connecting lines and two adjacent reset connecting lines, the static electricity can be dispersed to multiple light-emitting connecting lines and multiple reset connecting lines for release, thereby avoiding the problem of static electricity accumulation causing static electricity breakdown between the light-emitting connecting line and the active pattern, and avoiding the problem of static electricity accumulation causing static electricity breakdown between the reset connecting line and the active pattern, thereby reducing the risk of tip discharge between the light-emitting connecting line and the reset connecting line and the active layer, and improving the yield of the display panel.

[0070] In some embodiments, Figures 6 to 16 As shown, the light-emitting control line EM and the light-emitting connecting line EM-L are arranged along the first direction X, the projection of the light-emitting connecting line EM-L on the substrate 21 overlaps with the projection of the light-emitting control line EM on the substrate 21, and the width H1 of the light-emitting connecting line EM-L in the second direction Y is greater than or equal to the width H2 of the light-emitting control line EM in the second direction Y; wherein, in the overlapping area of ​​the light-emitting connecting line EM-L and the light-emitting control line EM, the projection of the light-emitting control line EM on the substrate 21 is located within the projection of the light-emitting connecting line EM-L on the substrate, and the angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90 degrees. By making the projection of the light-emitting connecting line EM-L on the substrate 21 overlap with the projection of the light-emitting control line EM on the substrate 21, the width of the light-emitting connecting line EM-L in the second direction Y is greater than or equal to the width of the light-emitting control line EM in the second direction Y. In the overlapping area between the two, the projection of the light-emitting control line EM on the substrate is located within the projection of the light-emitting connecting line EM-L on the substrate, so that the light-emitting connecting line EM-L can block the light-emitting control line, avoiding the formation of capacitance between the light-emitting control line EM-L and the active pattern, reducing the capacitance between the light-emitting control line and the active pattern, reducing the risk of tip discharge between the light-emitting connecting line and the active layer, and improving the yield of the display panel.

[0071] Specifically, compared with the first light-emitting control line and the second light-emitting control line in the comparative display device, the first light-emitting control line and the second light-emitting control line will respectively form coupling capacitance with the active pattern, which makes it easy for the first light-emitting control line to have tip discharge with the active pattern, resulting in electrostatic damage. In the embodiment of the present application, by making the width of the light-emitting connecting line in the second direction greater than or equal to the width of the light-emitting control line in the second direction, in the overlapping area of ​​the two, the projection of the light-emitting control line on the substrate is located within the projection of the light-emitting connecting line on the substrate, and the light-emitting connecting line can cover the light-emitting control line, thereby reducing or even eliminating the coupling capacitance between the light-emitting control line and the active pattern, thereby reducing the risk of tip discharge between the light-emitting connecting line and the active pattern, and improving the yield of the display panel.

[0072] Specifically, in the setting area corresponding to the active pattern, the projection of the light-emitting control line on the substrate is located within the projection of the light-emitting connection line on the substrate.

[0073] In some embodiments, Figures 6 to 16 As shown, the reset control line Reset-Q and the reset connection line RL are arranged along the first direction X, the projection of the reset connection line RL on the substrate 21 overlaps with the projection of the reset control line Reset-Q on the substrate 21, and the width H3 of the reset connection line RL in the second direction Y is greater than or equal to the width H4 of the reset control line Reset-Q in the second direction Y; wherein, in the overlapping area of ​​the reset connection line RL and the reset control line Reset-Q, the projection of the reset control line Reset-Q on the substrate 21 is located within the projection of the reset connection line RL on the substrate 21, and the angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees. By making the projection of the reset connection line RL on the substrate 21 overlap with the projection of the reset control line Reset-Q on the substrate 21, the width of the reset connection line RL in the second direction Y is greater than or equal to the width of the reset control line Reset-Q in the second direction Y. In the overlapping area between the two, the projection of the reset control line Reset-Q on the substrate 21 is located within the projection of the reset connection line RL on the substrate 21, so that the reset connection line RL can block the reset control line Reset-Q, avoiding the formation of capacitance between the reset control line Reset-Q and the active pattern, reducing the capacitance between the light-emitting control line and the active pattern, reducing the risk of tip discharge between the light-emitting connection line and the active layer, and improving the yield of the display panel.

[0074] Specifically, compared with the first reset control line and the second reset control line in the comparative display device, the first reset control line and the second reset control line will form coupling capacitance with the active pattern respectively, which makes it easy for the first reset control line to have tip discharge with the active pattern, resulting in electrostatic damage. In the embodiment of the present application, by making the width of the reset connection line in the second direction greater than or equal to the width of the reset control line in the second direction, in the overlapping area of ​​the two, the projection of the reset control line Reset-Q on the substrate 21 is located within the projection of the reset connection line RL on the substrate 21, and the reset connection line can cover the reset control line, thereby reducing or even eliminating the coupling capacitance between the reset control line and the active pattern, thereby reducing the risk of tip discharge between the reset connection line and the active pattern, and improving the yield of the display panel.

[0075] Specifically, in the arrangement area corresponding to the active pattern, the projection of the reset control line on the substrate is located within the projection of the reset connection line on the substrate.

[0076] Specifically, Figure 1 , Fig.17 As shown, it can be seen that the embodiment of the present application reduces or even eliminates the coupling capacitance between the light emitting control line and the active pattern by making the light emitting connecting line cover the light emitting control line in the overlapping area between the light emitting connecting line and the light emitting control line, and by making the reset connecting line cover the reset control line in the overlapping area between the reset connecting line and the reset control line, thereby reducing or even eliminating the coupling capacitance between the reset control line and the active pattern.

[0077] In some embodiments, Figures 6 to 16 As shown, the driving circuit layer 22 includes a first via hole 301, the light emitting control line EM passes through the first via hole 301 to be connected to the light emitting connection line EM-L, and the light emitting control line EM is symmetrically arranged with respect to the first via hole 301. By making the light emitting control line pass through the first via hole to be connected to the light emitting connection line, and the light emitting control line is symmetrically arranged with respect to the first via hole, the light emitting connection line can have a better shielding effect on the light emitting control line, avoid the light emitting control line and the active pattern being directly arranged opposite to each other to form a coupling capacitor, reduce the coupling capacitor between the light emitting control line and the active pattern, reduce the risk of tip discharge between the light emitting connection line and the active pattern, and improve the yield of the display panel.

[0078] Specifically, the light-emitting connecting wires are symmetrically arranged about the first via hole.

[0079] Specifically, compared to the comparative display device in which the connection between the first light-emitting control line and the second light-emitting control line is arranged near the lower side of the first light-emitting control line, the embodiment of the present application arranges the light-emitting control line symmetrically about the first via hole, which can reduce the risk of tip discharge between the light-emitting connecting line and the active pattern and improve the yield of the display panel.

[0080] Specifically, the first via hole 301 penetrates the interlayer insulating layer 227 and the second gate insulating layer 225 .

[0081] In some embodiments, Figures 6 to 16 As shown, the driving circuit layer 22 further includes a pixel driving circuit 220, an active layer 222, a first source-drain electrode layer 228 and a second via 302, the pixel driving circuit 220 includes a reset transistor T7, the active layer 222 includes an active pattern T7A of the reset transistor T7, and the first source-drain electrode layer 228 further includes a reset signal line VI-A;

[0082] The second via hole 302 is arranged corresponding to the reset signal line VI-A, the second via hole 302 is arranged corresponding to the active pattern T7A of the reset transistor T7, and the reset signal line VI-A is connected to the active pattern T7A of the reset transistor T7 through the second via hole 302. By arranging the reset signal line in the first source-drain layer, and the second via hole is arranged corresponding to the active pattern of the reset transistor and the reset signal line, the part of the reset signal line located in the active layer can be removed, so as to avoid occupying the space of the active layer and improve the aperture ratio.

[0083] Specifically, compared to the comparative display device, which uses a semiconductor film layer and a first source-drain film layer to form two parts of the reset signal line respectively, the embodiment of the present application takes into account that the semiconductor film layer has little effect on the impedance of the reset signal line, and removes the part of the reset signal line located in the active layer, so that the reset signal line adopts a single-layer design, avoids occupying the space of the active layer, and avoids the reduction of yield due to complex process. By setting the second via hole corresponding to the active pattern of the reset transistor and the reset signal line, the reset signal line can be directly connected to the active pattern of the reset transistor through the second via hole, without adding a transfer line, reducing process steps and reducing occupied space.

[0084] Specifically, the second via hole 302 penetrates the interlayer insulating layer 227 , the second gate insulating layer 225 , and the first gate insulating layer 223 .

[0085] In some embodiments, Figures 6 to 16 As shown, the driving circuit layer 22 further includes a pixel driving circuit 220, an active layer 222, a first source-drain electrode layer 228 and a third via hole 303, the pixel driving circuit 220 includes an initialization transistor T4, the active layer 222 includes an active pattern T4A of the initialization transistor T4, and the first source-drain electrode layer 228 further includes an initialization signal line VI-Q;

[0086] The third via hole 303 is arranged corresponding to the initialization signal line VI-Q, the third via hole 303 is arranged corresponding to the active pattern T4A of the initialization transistor T4, and the initialization signal line VI-Q is connected to the active pattern T4A of the initialization transistor T4 through the third via hole 303. By arranging the initialization signal line in the first source-drain layer, and the third via hole being arranged corresponding to the active pattern of the initialization transistor and the initialization signal line, the initialization signal line can be changed from a part of the active layer and the second gate layer to a part of the first source-drain layer, thereby reducing impedance, avoiding occupying the space of the active layer, and improving the aperture ratio.

[0087] Specifically, compared to the comparative display device in which the semiconductor film layer and the second gate film layer are used to form the two parts of the initialization signal line respectively, the embodiment of the present application takes into account that the impedance of the semiconductor film layer and the second gate film layer is relatively large, and the impedance of the initialization signal line is reduced by using the first source and drain layer to form the initialization signal line, so that the initialization signal line adopts a single-layer design to avoid occupying the space of the active layer and avoid the reduction of yield due to complex process. By setting the third via hole corresponding to the active pattern of the initialization transistor and the initialization signal line, the initialization signal line can be directly connected to the active pattern of the initialization transistor through the third via hole, without adding a transfer line, reducing the process steps and reducing the occupied space.

[0088] Specifically, the third via hole 303 penetrates the interlayer insulating layer 227 , the second gate insulating layer 225 and the first gate insulating layer 223 .

[0089] Specifically, the impedance of the first source-drain electrode layer is smaller than the impedance of the second gate electrode layer, and the impedance of the first source-drain electrode layer is smaller than the impedance of the active layer.

[0090] In some embodiments, Figures 6 to 16 As shown, the driving circuit layer 22 further includes a data line Data, and a distance exists between the projection of the light-emitting connection line EM-L on the substrate 21 and the projection of at least part of the data line Data on the substrate 21. By making the projection of the light-emitting connection line EM-L on the substrate 21 and the projection of at least part of the data line Data on the substrate 21 have a distance, each light-emitting connection line EM-L can be disconnected, the coupling capacitance between each light-emitting control line EM and the data line Data is small, and the total capacitance of at least part of the data line is reduced, which can prevent crosstalk caused by insufficient pixel charging time or even charging error, improve display uniformity, and improve display effect.

[0091] Specifically, compared to the comparative display device, in which the first light-emitting control wiring and the second light-emitting control wiring both overlap with the data lines, the embodiment of the present application disconnects a plurality of light-emitting connecting lines, retains portions of the light-emitting connecting lines that serve as gates of the first light-emitting control transistor and the second light-emitting control transistor, and the projections of the light-emitting connecting lines on the substrate do not overlap with at least portions of the data lines, thereby reducing the coupling capacitance between the light-emitting control lines and at least portions of the data lines.

[0092] In some embodiments, Figures 6 to 16 As shown, the driving circuit layer 22 further includes a data line Data, and a distance exists between the projection of the reset connection line RL on the substrate 21 and the projection of the data line Data on the substrate 21. By making a distance exist between the projection of the reset connection line RL on the substrate 21 and the projection of the data line Data on the substrate 21, each reset connection line RL can be disconnected, and the coupling capacitance between each reset control line Reset-A and the data line Data is small, thereby reducing the total capacitance of the data line, preventing crosstalk caused by insufficient pixel charging time or even wrong charging, improving display uniformity, and improving display effect.

[0093] Specifically, compared to the comparative display device, in which both the first reset control line and the second reset control line overlap with the data line, the embodiment of the present application disconnects a plurality of reset connection lines, retains a portion of the reset connection line that serves as the gate of the reset transistor, and a projection of the reset connection line on the substrate does not overlap with the data line, thereby reducing the coupling capacitance between the reset control line and at least the data line.

[0094] In some embodiments, Figures 3 to 16 As shown, the driving circuit layer 22 further includes a first gate layer 224, a first source-drain layer 228 and a second source-drain layer 232, wherein the second source-drain layer 232 is disposed on a side of the first source-drain layer 228 away from the first gate layer 224, and the second source-drain layer 232 includes a high potential power line VDD;

[0095] The first gate layer 224 further includes an initialization connection line SL2, the first source-drain layer further includes an initialization control line Reset-Q, the initialization connection line SL2 includes a first connection portion SL2a and a second connection portion SL2b, the first connection portion SL2a connects the initialization control line Reset-Q and the second connection portion SL2b, and there is a gap between the projection of one end of the first connection portion SL2a on the substrate 21 and the projection of one end of the high potential power line VDD on the substrate 21. By making the projection of one end of the first connection portion on the substrate and the projection of one end of the high potential power line on the substrate have a gap, the coupling capacitance between the high potential power line and the initialization control line can be reduced, the display uniformity can be improved, and the display effect can be improved.

[0096] Specifically, it can be seen that the initialization control line is connected to one end of the first connection portion SL2a through the via hole, and there is a gap between the projection of the other end of the first connection portion SL2a on the substrate and the projection of one end of the high potential power line VDD on the substrate.

[0097] In some embodiments, Figures 3 to 16 As shown, the driving circuit layer 22 further includes a first gate layer 224, a second gate layer 226, a first source-drain layer 228, and a second source-drain layer 232, the second gate layer 226 is arranged between the first gate layer 224 and the first source-drain layer 228, the second source-drain layer 232 is arranged on a side of the first source-drain layer 228 away from the second gate layer 226, the second gate layer 226 includes a first high-potential power connection line VDD-L1, the first source-drain layer 228 includes a second high-potential power connection line VDD-L2, and the second source-drain layer 232 includes a high-potential power line VDD;

[0098] The second high potential power connection line VDD-L2 connects the first high potential power connection line VDD-L1 and the high potential power line VDD, the driving circuit layer 22 further includes a fourth via hole 304, the second high potential power connection line VDD-L2 passes through the fourth via hole 304 to connect the first high potential power connection line VDD-L1, and the lower end of the fourth via hole 304 and the lower end of the second high potential power connection line VDD-L2 are located on the same straight line. By making the lower end of the fourth via hole and the lower end of the second high potential power connection line located on the same straight line, the fourth via hole can be far away from the active pattern of the driving transistor, so as to avoid the fourth via hole affecting the electrical properties of the active pattern of the driving transistor, thereby affecting the electrical properties of the driving transistor, and improving the electrical stability of the driving transistor.

[0099] Specifically, Figure 5As shown, the pixel driving circuit 220 includes a switching transistor T2, a driving transistor T1, a compensation transistor T3 and an initialization transistor T4, the gate of the switching transistor T2 is connected to the switching control line Scan(n), the first electrode of the switching transistor T2 is connected to the data line Data, and the second electrode of the switching transistor T2 is connected to the first electrode of the driving transistor T1 at a first node A; the gate of the compensation transistor T3 is connected to the switching control line Scan(n), the first electrode of the compensation transistor T3 is connected to the gate of the driving transistor T1 at a second node Q, and the second electrode of the compensation transistor T3 is connected to the second electrode of the driving transistor T1 at a third node B; the gate of the initialization transistor T4 is connected to the initialization control line Reset-Q, the first electrode of the initialization transistor T4 is connected to the initialization signal line VI-Q, and the second electrode of the initialization transistor T4 is connected to the gate of the driving transistor T1 at a second node Q.

[0100] Specifically, Figure 5 As shown, the pixel driving circuit 220 further includes:

[0101] a first light emission control transistor T5, wherein a gate of the first light emission control transistor T5 is connected to the light emission control line EM, a first electrode of the first light emission control transistor T5 is connected to the high potential power line VDD, and a second electrode of the first light emission control transistor T5 is connected to the first electrode of the driving transistor T1 and a first node A;

[0102] A second light emission control transistor T6, wherein a gate of the second light emission control transistor T6 is connected to the light emission control line EM, and a first electrode of the second light emission control transistor T6 and a second electrode of the driving transistor T1 are connected to a third node B;

[0103] A reset transistor T7, wherein the gate of the reset transistor T7 is connected to the reset control line Reset-A, the first electrode of the reset transistor T7 is connected to the reset signal line VI-A, the second electrode of the reset transistor T7 and the second electrode of the second light emitting control transistor T6 are connected to a fourth node C, and the second electrode of the reset transistor T7 and the anode of the light emitting device LED are connected to the fourth node C;

[0104] A storage capacitor Cst, one plate of the storage capacitor Cst is connected to the high potential power line VDD, and the other plate of the storage capacitor Cst is connected to the gate of the driving transistor T1 at a second node Q.

[0105] Specifically, Figure 5 As shown, the cathode of the light emitting device LED is connected to the low potential power line VSS.

[0106] Specifically, it can be understood that the display panel includes a plurality of switch control lines, each of which can drive a row of pixel units, the switch control line Scan(n) is the nth switch control line among the plurality of switch control lines, n is greater than or equal to 1, and n is a positive integer, the switch control line Scan(n) can be connected to a gate drive circuit, and a signal can be input through the gate drive circuit, or a signal can be directly input through a driver chip. Similarly, the display panel can include a plurality of initialization control lines, a plurality of reset control lines, and a plurality of light-emitting control lines, each of which drives a row of pixel units, the initialization control line, the light-emitting control line, and the reset control line can also be connected to the gate drive circuit or input a signal through a driver chip, and the gate drive circuit to which the initialization control line, the light-emitting control line, and the reset control line are connected can be the same as the gate drive circuit to which the switch control line is connected, or can be different from the gate drive circuit to which the switch control line is connected.

[0107] Specifically, it is understandable that since each via hole is filled with a structure and each film layer is stacked, the position of each via hole cannot be seen. It is understandable that the position of each via hole can be determined according to the position of each structure.

[0108] In some embodiments, Figures 3 to 16 As shown, the display panel 2 includes a plurality of pixel units 240 arranged in an array, the pixel unit 240 includes a first sub-pixel unit 240a, a second sub-pixel unit 240b and a third sub-pixel unit 240c, the first sub-pixel unit 240a includes a first light-emitting device 341, the second sub-pixel unit 240b includes a second light-emitting device 342, the third sub-pixel unit 240c includes a third light-emitting device 343, and the areas of the anode ANO1 of the first light-emitting device 341, the anode ANO2 of the second light-emitting device 342 and the anode ANO3 of the third light-emitting device 343 are different from each other. Since the luminous efficiency of different light-emitting devices is different, by making the areas of the anode of the first light-emitting device, the anode of the second light-emitting device and the anode of the third light-emitting device different from each other, the volume of the light-emitting device can be set according to the luminous efficiency of each light-emitting device, so that the luminous brightness of each light-emitting device can be consistent, thereby improving the display effect.

[0109] Specifically, it can be understood that the light emitting device LED includes a first light emitting device, a second light emitting device and a third light emitting device, and the anodes of the light emitting devices include an anode of the first light emitting device, an anode of the second light emitting device and an anode of the third light emitting device.

[0110] Specifically, Figure 3 , Figure 4As shown, the light-emitting material layer 243 includes a first light-emitting material layer 243a, a second light-emitting material layer 243b and a third light-emitting material layer 243c, and the light-emitting colors of the first light-emitting material layer 243a, the second light-emitting material layer 243b and the third light-emitting material layer 243c are different from each other. Specifically, the pixel electrode layer forms the anode of the light-emitting device, the light-emitting material layer forms the light-emitting material of the light-emitting device, and the common electrode forms the cathode of the light-emitting device.

[0111] Specifically, taking the examples where the luminous colors of the first luminescent material layer 243a, the second luminescent material layer 243b and the third luminescent material layer 243c are red, green and blue respectively, since the luminous efficiency of each luminescent material is different, specifically, the luminous efficiency of the blue luminescent material is the smallest, and the luminous efficiency of the red luminescent material is the largest, the area of ​​the anode of the first light-emitting device can be made smaller than the area of ​​the anode of the second light-emitting device, and the area of ​​the anode of the second light-emitting device is smaller than the area of ​​the anode of the third light-emitting device.

[0112] In some embodiments, Figures 2 to 16 As shown, in the first direction X, the width of the anode ANO1 of the first light emitting device 341 is smaller than the width of the anode ANO2 of the second light emitting device 342; the width of the anode ANO2 of the second light emitting device 342 is smaller than the width of the anode ANO3 of the third light emitting device 343, and the first direction X is the same as the extension direction of the light emitting control line. By making the width of the anode of the first light emitting device smaller than the width of the anode of the second light emitting device, and the width of the anode of the second light emitting device smaller than the width of the anode of the third light emitting device, the volume of the light emitting device can be set according to the light emitting efficiency of each light emitting device, so that the light emitting brightness of each light emitting device can be consistent, thereby improving the display effect.

[0113] In some embodiments, Figures 3 to 6 , Figure 7As shown, the driving circuit layer 22 also includes an active layer 222, the display panel 2 includes a plurality of pixel units 240 arranged in an array, each of the pixel units 240 includes three pixel driving circuits 220, in each of the pixel driving circuits 220, the active layer 222 includes an active pattern T1A of a driving transistor T1, an active pattern T2A of a switching transistor T2, a first electrode T2S of the switching transistor T2, an active pattern T3A of a compensation transistor T3, a first electrode T3S of the compensation transistor T3, an active pattern T4A of an initialization transistor T4, a first electrode T4S of the initialization transistor, a second electrode T4D of the initialization transistor, an active pattern T5A of a first light-emitting control transistor T5, a first electrode T5S of the first light-emitting control transistor T5, an active pattern T6A of a second light-emitting control transistor T6, a second electrode T6D of the second light-emitting control transistor T6, an active pattern T7A of a reset transistor T7, a first electrode T7S of the reset transistor T7, a second electrode T7D of the reset transistor T7, a first node A and a third node B, the driving transistor The active pattern T1A of the driving transistor T1 is arranged along a first direction X, the active pattern T2A of the switching transistor T2, the active pattern T4A of the first initialization transistor T4, the active pattern T5A of the first light emission control transistor T5, the active pattern T6A of the second light emission control transistor T6 and the active pattern T7A of the reset transistor T7 are arranged along a second direction Y, the active pattern T3A of the compensation transistor T3 includes a portion arranged along the first direction X and a portion arranged along the second direction Y, the active pattern T1A of the driving transistor T1 is aligned with the active pattern T1A of the switching transistor T2. The active pattern T2A of the body transistor T2, the active pattern T3A of the compensation transistor T3, the active pattern T5A of the first light-emitting control transistor T5 and the active pattern T6A of the second light-emitting control transistor T6 are connected, the active pattern T3A of the compensation transistor T3 is connected to the active pattern T4A of the first initialization transistor T4, the active pattern T6A of the second light-emitting control transistor T6 is connected to the active pattern T7A of the reset transistor T7, and the angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90 degrees.

[0114] Specifically, Figures 6 to 16 The portion of two rows of pixel units is intercepted, so it can be seen that the reset transistor is located below the second light emitting control transistor.

[0115] In some embodiments, Figures 3 to 6 , Figure 8As shown, the driving circuit layer 22 also includes a first gate layer 224. In each of the pixel driving circuits 220, the first gate layer 224 includes a gate T1G of the driving transistor T1, a gate T2G of the switching transistor T2, a gate T3G of the compensation transistor T3, a gate T4G of the initialization transistor T4, a gate T5G of the first light-emitting control transistor T5, a gate T6G of the second light-emitting control transistor T6, a gate T7G of the reset transistor T7, a first electrode Cst1 of the storage capacitor Cst, a light-emitting connection line EM-L, a switch connection line SL1, an initialization connection line SL2 and a reset connection line RL. The initialization connection line SL2, the switch connection line SL1, the gate T1G of the driving transistor T1, the light-emitting connection line EM-L and the reset connection line RL are arranged in sequence along the second direction Y.

[0116] Specifically, Figure 6 , Figure 8 As shown, it can be seen that in a row of pixel units, the light-emitting connection line EM-L is disconnected and the reset connection line RL is disconnected.

[0117] Specifically, Figure 8 As shown, the gate T2G of the switching transistor T2 is connected to the gate T3G of the compensation transistor T3.

[0118] Specifically, Figure 8 As shown, it can be seen that some structures are marked with multiple marks. This is because the electrode and the signal line share this structure, and the signals transmitted on the structure are the same (without considering the voltage drop problem). For example, the gate T5G of the first light-emitting control transistor T5 and the light-emitting connecting line EM-L identify the same structure. This is because the portion of the light-emitting connecting line EM-L corresponding to the active pattern of the first light-emitting control transistor T5 serves as the gate T5G of the first light-emitting control transistor T5. Similarly, the meaning of other structures marked with multiple marks can be determined.

[0119] Specifically, Figures 6 to 8 As shown, it can be understood that the gate of each transistor is arranged corresponding to the active pattern of each transistor, for example, the gate T3G of the compensation transistor is arranged corresponding to the active pattern T3A of the compensation transistor T3.

[0120] In some embodiments, Figures 5 to 8 As shown, the gate T3G of the compensation transistor T3 includes a first gate T3Ga and a second gate T3Gb, and the first gate T3Ga is connected to the second gate T3Gb. By making the gate of the compensation transistor a double-gate design, the gate control capability of the display panel can be improved and the leakage current can be reduced.

[0121] In some embodiments, Figures 5 to 8As shown, the gate T4G of the initialization transistor T4 includes a third gate T4Ga and a fourth gate T4Gb, and the third gate T4Ga is connected to the fourth gate T4Gb. By making the gate of the initialization transistor a double-gate design, the gate control capability of the display panel can be improved and the leakage current can be reduced.

[0122] In some embodiments, Figures 3 to 6 , Fig. 9 As shown, the driving circuit layer 22 also includes a second gate layer 226. In each of the pixel driving circuits 220, the second gate layer 226 includes a first high potential power connection line VDD-L1 and a second plate Cst2 of the storage capacitor Cst. The first high potential power connection line VDD-L1 is connected to the second plate Cst2 of the storage capacitor Cst.

[0123] Specifically, Figure 6 , Fig. 9 As shown, it can be seen that the first high-potential power connection line VDD-L1 is connected to the second plate Cst2 of the storage capacitor Cst, a via is provided on the second plate Cst2 of the storage capacitor Cst, the second plate Cst2 of the storage capacitor Cst is arranged corresponding to the first plate Cst1 of the storage capacitor Cst, and the first electrode of the compensation transistor can pass through the via to be connected to the gate of the driving transistor.

[0124] Specifically, the second gate layer may further include a repair line. By setting the repair line in the pixel unit, when an abnormality occurs in the sub-pixel unit or the pixel unit, the connection between the anode of the light-emitting device corresponding to the sub-pixel unit and the pixel driving circuit can be disconnected, and the repair line is directly connected to the anode of the sub-pixel unit to directly drive the sub-pixel unit to avoid dark spots. When the sub-pixel unit or the pixel unit does not have an abnormality, the repair line can be left suspended.

[0125] In some embodiments, Figures 3 to 6 , Fig.10 As shown, the driving circuit layer 22 also includes a first source and drain layer 228. In each of the pixel driving circuits 220, the first source and drain layer 228 includes an initialization signal line VI-Q, an initialization control line Reset-Q, a switch control line Scan(n), a second high potential power connection line VDD-L2, a light emitting control line EM, a reset control line Reset-A, a reset signal line VI-A, a first adapter line KL1, a second adapter line KL2, a third adapter line KL3 and a fourth adapter line KL4; the initialization signal line VI-Q, the initialization control line Reset-Q, the switch control line Scan(n), the first adapter line KL1, the second high potential power connection line VDD-L2, the light emitting control line EM, the third adapter line KL3, the reset control line Reset-A and the reset signal line VI-A are arranged in sequence along the second direction Y.

[0126] Specifically, Figures 6 to 10 As shown, it can be seen that in a row of pixel units, the initialization signal lines VI-Q are continuous, and the initialization signal lines VI-Q are connected to the first electrode T4S of the initialization transistor T4.

[0127] Specifically, Figures 6 to 10 As shown, it can be seen that in a row of pixel units, the initialization control lines Reset-Q are continuous, and the initialization control lines Reset-Q are connected to the initialization connection lines SL2, so that the impedance of the initialization control lines can be reduced.

[0128] Specifically, Figures 6 to 10 As shown, it can be seen that in a row of pixel units, the switch control line Scan(n) is connected, and the switch control line Scan(n) is connected to the switch connection line SL1.

[0129] Specifically, Figures 6 to 10 As shown, it can be seen that in a row of pixel units, the second high potential power connection line VDD-L2 is continuous, and the second high potential power connection line VDD-L2 is connected to the second electrode Cst2 of the storage capacitor Cst, so that the second high potential power connection line VDD-L2 is connected to the first high potential power connection line VDD-L1, reducing the impedance of the high potential power line.

[0130] Specifically, Figures 6 to 10 As shown, it can be seen that in a row of pixel units, the light emitting control lines EM are continuous, and the light emitting control lines EM are connected to the light emitting connection lines EM-L, thereby reducing the impedance of the light emitting control lines.

[0131] Specifically, Figures 6 to 10 As shown, it can be seen that in a row of pixel units, the reset control lines Reset-A are continuous, and the reset control lines Reset-A are connected to the reset connection lines RL, thereby reducing the impedance of the reset control lines.

[0132] Specifically, Figures 6 to 10 As shown, it can be seen that in a row of pixel units, the reset signal line VI-A is continuous, and the reset signal line VI-A is connected to the first electrode T7S of the reset transistor T7.

[0133] Specifically, Figures 6 to 10 As shown, the first adapter wire KL1 is connected to the first electrode T2S of the switching transistor T2, one end of the second adapter wire KL2 is connected to the first electrode T3S of the compensation transistor T3, the other end of the second adapter wire KL2 is connected to the gate T1G of the driving transistor T1, the third adapter wire KL3 is connected to the first electrode T5S of the first light-emitting control transistor T5, and the fourth adapter wire KL4 is connected to the second electrode T6D of the second light-emitting control transistor T6.

[0134] In some embodiments, Figures 3 to 6 , Fig.11 As shown, the driving circuit layer 22 also includes a second source-drain layer 232. In each of the pixel units 240, the second source-drain layer 232 includes three data lines Data, three high potential power lines VDD, one low potential power line VSS, one reset connection line VI-L and three anode connection lines ANO-L. The three data lines Data and the three high potential power lines VDD are alternately arranged along the first direction X, the low potential power line VSS is arranged on the side of the high potential power line VDD away from the data line Data, the reset connection line VI-L is arranged between one of the data lines Data and one of the high potential power lines VDD, each of the anode connection lines ANO-L is arranged between one of the high potential power lines VDD and one of the data lines Data, and the three high potential power lines VDD are connected to one of the second high potential power connection lines VDD-L2.

[0135] Specifically, Figure 6 , Fig.11 As shown, the data line Data, the high potential power line VDD, the low potential power line VSS, the reset connection line VI-L and the anode connection line ANO-L are all arranged along the second direction Y.

[0136] Specifically, Figures 6 to 11 As shown, it can be seen that the data line Data is connected to the first adapter line KL1, the high potential power line VDD is connected to the second high potential power connection line VDD-L2, and the high potential power line VDD is connected to the third adapter line KL3, so that the gridding and signal transmission of the high potential power line VDD can be realized, and the impedance of the high potential power line can be reduced. It can be understood that the signals on the first high potential power connection line and the second high potential power connection line are the signals of the high potential power line, and the first high potential power connection line and the second high potential power connection line can be regarded as part of the high potential power line.

[0137] Specifically, Figures 6 to 11 As shown, the anode connecting line ANO-L can be connected to the fourth switching line KL4.

[0138] In some embodiments, Figures 3 to 6 , Figure 11 to Figure 12 As shown, the light-emitting functional layer 24 includes a pixel electrode layer 241. In each of the pixel units 240, the pixel electrode layer 241 includes three anodes ANO of the light-emitting devices LED. Each anode ANO of the light-emitting device LED is connected to an anode connecting line ANO-L, and an anode connecting line ANO-L is connected to a fourth adapter line.

[0139] Specifically, a projection of the anode of the light-emitting device on the substrate overlaps with a projection of the high-potential power line on the substrate.

[0140] Specifically, Fig.12 As shown, it can be seen that the anode ANO of the light-emitting device LED is arranged along the second direction Y, and the anodes ANO of multiple light-emitting devices LED are arranged at intervals along the first direction X. The anode ANO of each light-emitting device LED is connected to the anode connecting line ANO-L, and the anode connecting line ANO-L is connected to the fourth adapter line KL4. The fourth adapter line KL4 is connected to the second electrode T6D of the second light-emitting control transistor T6, so as to realize the connection between the light-emitting device and the second light-emitting control transistor.

[0141] In some embodiments, Figures 3 to 12 As shown, the display panel 2 includes a plurality of pixel units 240 arranged in an array, the pixel unit 240 includes a first sub-pixel unit 240a, a second sub-pixel unit 240b and a third sub-pixel unit 240c, the first sub-pixel unit 240a includes a first light-emitting device 341, the second sub-pixel unit 240b includes a second light-emitting device 342, the third sub-pixel unit 240c includes a third light-emitting device 343, and the pixel driving circuit 220 includes a first pixel driving circuit 220a electrically connected to an anode of the first light-emitting device 341, an anode of the second light-emitting device 342, and an anode of the third light-emitting device 343, respectively. The second pixel driving circuit 220b and the third pixel driving circuit 220c, the data line Data includes a first data line Data-R, a second data line Data-G and a third data line Data-B electrically connected to the first pixel driving circuit 220a, the second pixel driving circuit 220b and the third pixel driving circuit 220c respectively, and the high potential power line VDD includes a first high potential power line VDD1, a second high potential power line VDD2 and a third high potential power line VDD3 electrically connected to the first pixel driving circuit 220a, the second pixel driving circuit 220b and the third pixel driving circuit 220c respectively.

[0142] Specifically, the first data line Data-R, the second data line Data-G and the third data line Data-B can correspond to the first sub-pixel unit, the second sub-pixel unit and the third sub-pixel unit respectively. It can be understood that when the display panel displays, the brightness of different sub-pixel units can be the same or different. Therefore, there may be a situation where different sub-pixel units are driven by different driving voltages. In this case, different voltages can be input to the first data line Data-R, the second data line Data-G and the third data line Data-B so that each sub-pixel unit displays the corresponding brightness.

[0143] Specifically, the first high potential power line VDD1, the second high potential power line VDD2 and the third high potential power line VDD3 may correspond to the first sub-pixel unit, the second sub-pixel unit and the third sub-pixel unit respectively, and the first high potential power line VDD1, the second high potential power line VDD2 and the third high potential power line VDD3 may be the same or different.

[0144] At the same time, in order to illustrate the relative position of each film layer, Figure 6 , Figures 13 to 16 To explain, from Fig.13 It can be seen from the figure that the relative positions of the structures in the first gate layer 224 and the structures in the active layer 222; Fig.14 The relative positions of the structures in the active layer 222, the first gate layer 224 and the second gate layer 226 can be seen in FIG. Fig.15 The relative positions of the structures in the active layer 222, the first gate layer 224, the second gate layer 226 and the first source and drain layer 228 can be seen in FIG. Fig.16 The relative positions of the structures in the active layer 222, the first gate layer 224, the second gate layer 226, the first source-drain layer 228 and the second source-drain layer 232 can be seen in FIG.

[0145] Specifically, the first electrode of the transistor in the above embodiment is a source, and the second electrode is a drain; or the first electrode of the transistor in the above embodiment is a drain, and the second electrode is a source.

[0146] Specifically, the material of the active layer includes silicon semiconductor material, specifically low-temperature polysilicon; or the material of the active layer includes oxide semiconductor material, specifically metal oxide semiconductor material, more specifically indium gallium zinc oxide.

[0147] Specifically, the driving transistor, the switching transistor, the compensation transistor, the initialization transistor, the first light emission control transistor, the second light emission control transistor and the reset transistor may be P-type transistors or N-type transistors.

[0148] Specifically, it is understood that due to the differences in the cut portions when splitting each film layer, some film layers may have partial structural missing. It is understood that the structure of each film layer in the display panel can be seen in Figure 6 And determine the relative position and size in combination with each figure, for example, Fig.11 In the embodiment, the first data line Data-R in the second source-drain electrode layer 232 is partially missing, and the low potential power line VSS is not shown, but it can be understood that it can be seen from FIG. Figure 6 The positions and sizes of the first data line Data-R and the low potential power line VSS are determined in conjunction with other figures.

[0149] Specifically, the above embodiments describe in detail the display panel from aspects of the circuit of the display panel, the film layer structure, the specific design of each film layer, the connection relationship and the relative relationship between each film layer, etc. It can be understood that when there is no conflict between the embodiments, the embodiments can be combined. For example, the light-emitting control line and the light-emitting connecting line are arranged along a first direction, the projection of the light-emitting connecting line on the substrate overlaps with the projection of the light-emitting control line on the substrate, and the width of the light-emitting connecting line in the second direction is greater than or equal to the width of the light-emitting control line in the second direction; wherein, in the overlapping area between the light-emitting connecting line and the light-emitting control line, the light-emitting The projection of the light control line on the substrate is located within the projection of the light-emitting connection line on the substrate; the reset control line and the reset connection line are arranged along a first direction, the projection of the reset connection line on the substrate overlaps with the projection of the reset control line on the substrate, and the width of the reset connection line in a second direction is greater than or equal to the width of the reset control line in the second direction; wherein, in the overlapping area of ​​the reset connection line and the reset control line, the projection of the reset control line on the substrate is located within the projection of the reset connection line on the substrate, and the angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees.

[0150] At the same time, an embodiment of the present application provides a display device, which includes a display panel as described in any of the above embodiments.

[0151] Specifically, the display panel includes an organic light emitting diode display panel.

[0152] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0153] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0154] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0155] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A display panel, characterized in that: include: substrate; A driving circuit layer is arranged on one side of the substrate, the driving circuit layer includes a plurality of light-emitting control lines, a plurality of reset control lines, a plurality of light-emitting adapter lines and a plurality of reset adapter lines, one of the light-emitting adapter lines is connected to one of the light-emitting control lines, and one of the reset adapter lines is connected to one of the reset control lines; Among them, at least one of the light-emitting adapter wires is provided with a break; and / or at least one of the reset adapter wires is provided with a break.

2. The display panel according to claim 1, characterized in that: The display panel includes a plurality of pixel units, each of the pixel units includes a plurality of sub-pixel units, the light-emitting adapter includes a plurality of light-emitting connecting lines, a break is provided between two adjacent light-emitting connecting lines, and each of the light-emitting connecting lines is provided corresponding to one of the sub-pixel units; The reset adapter line includes a plurality of reset connection lines, and a break is provided between two adjacent reset connection lines. Each of the reset connection lines is arranged corresponding to one of the sub-pixel units.

3. The display panel according to claim 2, characterized in that: The light-emitting control line and the light-emitting connection line are arranged along a first direction, a projection of the light-emitting connection line on the substrate overlaps with a projection of the light-emitting control line on the substrate, and a width of the light-emitting connection line in a second direction is greater than or equal to a width of the light-emitting control line in the second direction; Among them, in the overlapping area of ​​the light-emitting connecting line and the light-emitting control line, the projection of the light-emitting control line on the substrate is located within the projection of the light-emitting connecting line on the substrate, and the angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees.

4. The display panel according to claim 2, characterized in that: The reset control line and the reset connection line are arranged along a first direction, a projection of the reset connection line on the substrate overlaps with a projection of the reset control line on the substrate, and a width of the reset connection line in a second direction is greater than or equal to a width of the reset control line in the second direction; Wherein, in the overlapping area of ​​the reset connection line and the reset control line, the projection of the reset control line on the substrate is located within the projection of the reset connection line on the substrate, and the angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees.

5. The display panel according to any one of claims 2 to 4, characterized in that: The driving circuit layer includes a first gate layer and a first source-drain layer, the first gate layer is arranged between the substrate and the first source-drain layer, the first gate layer includes the light-emitting connection line and the reset connection line, and the first source-drain layer includes the light-emitting control line and the reset control line.

6. The display panel according to any one of claims 2 to 4, characterized in that: The driving circuit layer includes a first via hole, the light-emitting control line passes through the first via hole and is connected to the light-emitting connection line, and the light-emitting control line is symmetrically arranged with respect to the first via hole.

7. The display panel according to any one of claims 2 to 4, characterized in that: The driving circuit layer further includes a pixel driving circuit, an active layer, a first source-drain electrode layer and a second via hole, the pixel driving circuit includes a reset transistor, the active layer includes an active pattern of the reset transistor, and the first source-drain electrode layer further includes a reset signal line; The second via hole is arranged corresponding to the reset signal line, the second via hole is arranged corresponding to the active pattern of the reset transistor, and the reset signal line passes through the second via hole to be connected to the active pattern of the reset transistor.

8. The display panel according to any one of claims 2 to 4, characterized in that: The driving circuit layer further includes a pixel driving circuit, an active layer, a first source-drain electrode layer and a third via hole, the pixel driving circuit includes an initialization transistor, the active layer includes an active pattern of the initialization transistor, and the first source-drain electrode layer further includes an initialization signal line; The third via hole is arranged corresponding to the initialization signal line, the third via hole is arranged corresponding to the active pattern of the initialization transistor, and the initialization signal line passes through the third via hole and is connected to the active pattern of the initialization transistor.

9. The display panel according to any one of claims 2 to 4, characterized in that: The driving circuit layer further comprises a first gate layer, a first source-drain layer, and a second source-drain layer, wherein the second source-drain layer is arranged on a side of the first source-drain layer away from the first gate layer, and the second source-drain layer comprises a high potential power supply line; Among them, the first gate layer also includes an initialization connection line, the first source and drain layer also includes an initialization control line, the initialization connection line includes a first connection part and a second connection part, the first connection part connects the initialization control line and the second connection part, and there is a gap between the projection of one end of the first connection part on the substrate and the projection of one end of the high-potential power line on the substrate.

10. The display panel according to any one of claims 2 to 4, characterized in that: The driving circuit layer further includes a first gate layer, a second gate layer, a first source-drain layer, and a second source-drain layer, wherein the second gate layer is arranged between the first gate layer and the first source-drain layer, the second source-drain layer is arranged on a side of the first source-drain layer away from the second gate layer, the second gate layer includes a first high-potential power connection line, the first source-drain layer includes a second high-potential power connection line, and the second source-drain layer includes a high-potential power line; Among them, the second high-potential power connection line connects the first high-potential power connection line and the high-potential power connection line, the driving circuit layer also includes a fourth via, the second high-potential power connection line passes through the fourth via to connect the first high-potential power connection line, and the lower end of the fourth via is located on the same straight line as the lower end of the second high-potential power connection line.

11. A display device, characterized in that: Comprising the display panel as claimed in any one of claims 1 to 10.

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