Battery management system and monitoring device

Abstract

A monitoring device is provided. The monitoring device comprises one or more circuitry operable to obtain measurements of one or more pins of the battery system, the one or more circuitry comprising at least one circuit for monitoring a current, the at least one circuit used for monitoring current comprises at least one other circuit used for amplifying change, and the at least one other circuit used for amplifying change comprises at least one differential amplifier, a voltage reference electrically connected with a first input end of the differential amplifier; the at least one transconductance component comprises at least one output end electrically connected with the second input end of the differential amplifier and at least one input end electrically connected with the output end of the differential amplifier; at least one current source electrically connected to at least one output of the at least one transconductance member; and an output electrically connected to at least one output of the at least one transconductance member.

Description

Technical Field

[0001] The present disclosure relates to the field of battery technology and energy cells. More specifically, the present disclosure relates to a battery management system and a monitoring device for monitoring a battery cell or a battery cell group and a regulating system used with such a monitoring device. Background Art

[0002] Battery systems comprising a plurality of battery cells are used in a wide range of modern power applications. For example, they are used to power electric vehicles, they are used in industrial power applications, transportation, and in commercial applications, such as powering modern electronic devices. In view of the relatively high power requirements of such applications, battery systems typically include a plurality of battery cells coupled together to achieve the required power output. Battery cells may be coupled together to form a battery pack, and a battery system may include one or more battery packs.

[0003] The battery system is typically connected to a battery management system that is configured to ensure that the battery system operates within its safe operating range. The safe operating area is typically defined as the voltage, temperature, and current conditions under which the battery system is expected to operate without self-destruction.

[0004] To achieve this, a cell monitoring device is typically used to monitor each battery cell in the battery system. The function of the cell monitoring device is to measure signals from the battery cell being monitored, such as the cell terminal voltage, cell current, cell temperature, cell pressure, etc., and then use these signals to determine whether the cell is in a safe state. In some systems, the measurements obtained by the cell monitoring device are collated and transmitted to the battery management system, which processes these measurements to determine the current state of the cell being monitored. Alternatively, the measurements can be collated and processed within each cell monitoring device and reported to the battery management system, so that the battery management system can maintain an overview of the current state of the battery system. Summary of the invention

[0005] One aspect of the present disclosure provides a monitoring device operable to report sensor measurements in a battery system. The monitoring device includes one or more circuit systems operable to obtain measurements of one or more pins of the battery system, and the one or more circuit systems include at least one circuit for monitoring current. The at least one circuit for monitoring current includes: at least one other circuit for amplifying the change, the at least one other circuit for amplifying the change includes at least one differential amplifier, a voltage reference electrically connected to a first input of the differential amplifier, the differential amplifier also including a second input and an output; at least one transconductance member, the at least one transconductance member including at least one output electrically connected to the second input of the differential amplifier and at least one input electrically connected to the output of the differential amplifier; wherein the second input of the differential amplifier and at least one output of the at least one transconductance member are electrically connected to one or more pins of the battery system; at least one current source, the at least one current source is electrically connected to at least one output of at least one of the at least one transconductance members; and an output, the output is electrically connected to at least one output of at least one of the at least one transconductance members; wherein the at least one circuit for monitoring current is operable to detect an interruption or absence of an electrical connection to the sensor connected to the one or more pins by monitoring the current required to cause a change in voltage on the one or more pins.

[0006] One aspect of the present disclosure provides a regulation system for providing a regulated voltage to a cell monitoring device (CMD) of a battery system during a power-on reset. The battery system includes at least one battery pack, each battery pack including a plurality of battery cells, wherein each battery cell is monitored via a corresponding CMD. The regulation system includes a bandgap reference unit, the bandgap reference unit being configured to generate a bandgap reference voltage (VBG) based on a supply voltage (VDD), and further configured to generate a first enable signal once the bandgap reference voltage is stable and at a level suitable for operational safety of the CMD core circuit. The system also includes a voltage regulator unit, the voltage regulator unit being configured to receive the bandgap reference voltage (VBG) and the first enable signal from the bandgap reference unit, and upon receiving the first enable signal, the voltage regulation unit is further configured to generate a regulated voltage (D VDD ), where a regulated voltage (D VDD The system further includes a power-on reset comparator configured to receive a bandgap reference voltage (VBG) from a bandgap reference unit and a regulated voltage (D VDDThe power-on reset comparator is further configured to provide a second enable signal to the CMD core circuit once the value of the regulated voltage is greater than the value of the bandgap reference voltage (VBG), wherein the second enable signal enables the CMD core circuit to access the regulated voltage (D VDD ).

[0007] Another aspect of the present disclosure provides a method in a regulation system for providing a regulated voltage to a cell monitoring device (CMD) of a battery system during a power-on reset. The battery system includes at least one battery pack, each battery pack including a plurality of battery cells, wherein each battery cell is monitored via a corresponding CMD. The method includes generating a bandgap reference voltage (VGB) based on a supply voltage (VDD) via a bandgap reference unit (BG), and also generating a first enable signal once the bandgap reference voltage (VBG) is stable and at a level suitable for operational safety of the CMD core circuit 305. The method also includes receiving the bandgap reference voltage (VBG) and the first enable signal from the bandgap reference unit via a voltage regulator unit 301. After receiving the first enable signal, the method also includes generating a regulated voltage (D VDD ), where a regulated voltage (D VDD The method further includes receiving a bandgap reference voltage (VBG) from a bandgap reference unit and a regulated voltage (D VDD The method further comprises once the voltage (D VDD ) is greater than the bandgap reference voltage (VBG), a second enable signal is provided to the CMD core circuit via the power-on reset comparator, wherein the second enable signal enables the CMD core circuit to access the regulated voltage (D VDD ).

[0008] Further aspects of the present disclosure provide monitoring devices, monitoring systems, controllers, and regulating systems for use in systems such as those described above, and methods relating thereto. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The foregoing will be described in more detail by the following more particular description of example embodiments as illustrated in the accompanying drawings, in which reference numerals refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed on illustrating the example embodiments.

[0010] Figure 1 is a schematic diagram of an exemplary wired battery management system architecture, in which a plurality of cell monitoring devices are connected to a communication controller via a wired harness in the form of a star network;

[0011] Figure 2 is a schematic diagram of an exemplary wired battery management system architecture, in which a plurality of battery cell monitoring devices are connected to a communication controller via a wired harness in the form of a daisy chain network;

[0012] Figure 3 is a schematic diagram of an exemplary battery management system architecture, wherein a plurality of battery cell monitoring devices and a communication controller are connected via a wireless communication network;

[0013] Figure 4 yes Figure 3 A schematic block diagram of an exemplary battery cell monitoring device and a communication controller of a battery management system.

[0014] Figure 5 yes Figure 3 Schematic block diagram of an alternative exemplary battery cell monitoring device and communication controller of a battery management system.

[0015] Figure 6 is a schematic diagram of a circuit for monitoring current of an exemplary sensor operable to obtain measurements of one or more pins of a battery system according to some of the exemplary embodiments described herein.

[0016] Figure 7 is a schematic diagram of first and second circuits for monitoring current of an exemplary sensor operable to obtain measurements of one or more pins of a battery system according to some of the exemplary embodiments described herein.

[0017] Figure 8 is a schematic diagram of a circuit for monitoring current of an exemplary sensor operable to obtain measurements of one or more pins of a battery system according to some of the exemplary embodiments described herein.

[0018] Fig. 9 is a schematic diagram of an exemplary regulation system for providing a regulated voltage to a cell monitoring device during a power-on reset according to some of the exemplary embodiments described herein.

[0019] Fig.10 According to some of the example embodiments described herein Fig. 9 Schematic diagram of an exemplary bandgap reference cell. DETAILED DESCRIPTION

[0020] Reference will now be made in detail to the exemplary embodiments, examples of which are shown in the accompanying drawings. The following description refers to the accompanying drawings, wherein the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations set forth in the following description of the exemplary embodiments do not represent all implementations consistent with the present invention. Instead, they are merely examples of systems, devices, and methods consistent with aspects related to the present invention recited in the appended claims.

[0021] Overview of Battery Management System Architecture

[0022] Figure 1 1 is a diagram of an exemplary wired battery management system architecture, in which a plurality of cell monitoring devices 10 - 1 . . . 10 -N are connected to a communication controller 15 via a wired harness 12 . Figure 1 In the exemplary architecture of FIG. 1 , the wire harness 12 connects the cell monitoring devices 10 - 1 . . . 10 -N to the communication controller 15 in the form of a star network, wherein the communication controller 15 is located at the center. The communication controller 15 is also connected to the battery management unit 20 .

[0023] exist Figure 1 In an example system, each cell monitoring device 10-1...10-N is configured to monitor one or more battery cells 22-1...22-N and obtain measurements of physical characteristics associated with one or more cells 22-1...22-N (such as voltage, current, temperature, pressure, strain, force, etc.) and / or derived measurements, such as state of charge (SoC). These measurements (which may include derived measurements in some examples) are then transmitted from each cell monitoring device 10-1...10-N to a communication controller 15 via a wired harness 12.

[0024] The communication controller 15 can be arranged to aggregate all messages from the cell monitoring devices 10-1...10-N and then pass them to the battery management unit 20, or alternatively, the communication controller 15 can be configured to pass the individual messages directly to the battery management unit 20, which then proceeds to process the received measurements to determine the current state of the battery system.

[0025] Typically, the communication controller 15 will be a separate hardware device from the battery management unit 20. Alternatively, the communication controller 15 and the battery management unit 20 may be integrated into a single hardware device, with the communication controller 15 responsible for coordinating the receipt of data via the wired harness 12 and the battery management unit 20 responsible for analyzing and processing the data.

[0026] Figure 1One disadvantage of the wired battery management system architecture shown is that in this architecture, the communication controller 15 and the wire harness 12 are configured to receive measurements from a predefined number of cell monitoring devices 10-1...10-N. This makes expansion of the system difficult because adding additional cell monitoring devices 10-1...10-N will generally require adding additional circuitry and connectors to the communication controller 15 to connect to the additional cell monitoring devices and modifying the wire harness 12.

[0027] Figure 2 Shows Figure 1 An alternative approach to wired battery management system architecture. Figure 1 Compared with the wired battery management system architecture in which the wired harness 12 connects the cell monitoring devices 10-1...10-N to the communication controller 15 in the form of a star network, Figure 2 In the exemplary architecture of , the cell monitoring devices 10 - 1 . . . 10 -N are connected in a daisy chain network via wiring 25 , wherein consecutive cell monitoring devices 10 - 1 . . . 10 -N are connected in series.

[0028] Figure 2 The operation and Figure 1 The operation of the star network is very similar, except that instead of each cell monitoring device 10-1...10-N communicating directly with the communication controller 15, messages are transmitted to and from the cell monitoring devices 10-1...10-N by relaying up and down along the daisy chain line 25. This means that the operation of each cell monitoring device 10-1...10-N is no longer the same, because the cell monitoring device 10-N directly connected to the communication controller 15 must relay messages from all other cell monitoring devices 10-1...10-N-1, while the cell monitoring device 10-1 at the end of the daisy chain has no message relay requirements. The message latency (how long it takes to travel from the source cell monitoring device to the communication controller 15) varies from cell monitoring device to cell monitoring device and increases as the number of cells / cell monitoring devices increases. In some embodiments, the daisy chain line 25 can be formed into a loop that terminates at the communication controller 15 at both ends. In this case, the delay between the cell monitoring devices 10-1...10-N may be different, depending on the direction in which the message travels around the loop. This variable delay is a disadvantage of daisy-chain wired battery networks.

[0029] Figure 3 Shows Figure 1 A variation of the battery management system architecture of , but instead of using a wired harness 12, the communication is performed wirelessly via a radio network. To this end, each cell monitoring device 10-1 ... 10-N has an antenna 30, and the communication controller 15 also has an antenna. The radio network can use a far-field antenna or near-field coupling.

[0030] Figure 3 The wireless battery management system architecture has the advantages of a wired star network (all battery cell monitoring devices 10-1...10-N are identical, constant latency, etc.). Additionally, when the number of battery cell monitoring devices 10-1...10-N changes, the communication controller 15 and any wired harness 12 do not need to be modified. However, wireless communication may generally be less reliable than a wired network due to the unpredictability of the radio channel and interference with communications by external radio energy sources.

[0031] Structure of communication controller and cell monitoring device

[0032] Now refer to Figure 4 and Figure 5 Describe in more detail Figure 3 The structure of the communication controller 15 and the battery cell monitoring devices 10-1...10-N of the system.

[0033] First go to Figure 4 , in an embodiment, Figure 3 The battery cell monitoring device 10 of the battery management system may include one or more sensors 31, 32, 33. Figure 4 In FIG. 1 , three sensors are shown: a voltage sensor 31, a current sensor 32, and a temperature sensor 33. It should be understood that in other embodiments, the battery cell monitoring device 10 may include more, fewer, or different sensors.

[0034] In this embodiment, the sensors 31, 32, 33 are connected via an analog multiplexer 35 to an analog to digital converter (ADC) 37, which is also connected to a processor 39. In alternative embodiments, the analog multiplexer 35 may be omitted and instead a plurality of ADCs 37 may be provided, with each of the sensors being connected directly to the processor 39 via its own dedicated ADC 37. However, it will be appreciated that providing the analog multiplexer 35 enables duplication of ADCs 37 to be avoided.

[0035] The processor 39 is also connected to a memory 40, which may be a non-volatile random access memory (NVRAM) or a read-only memory (ROM) that stores a program including processing instructions for processing digital signals representing sensor measurements received from the ADC 37. Alternatively, the memory 40 may include a static random access memory (SRAM) so that the program can be stored and subsequently modified. Such an embodiment may facilitate the creation and debugging of a program for storage in the cell monitoring device 10 during development of a battery management system.

[0036] Additionally, processor 39 is also connected to antenna 30 via radio block 45. A clock 47 is provided within cell monitoring device 10 to coordinate the timing of sensor measurements and other processes performed by cell monitoring device 10. In some embodiments, clock 47 may take the form of an oscillator.

[0037] In use, the sensors 31, 32, 33 obtain measurements from one or more battery cells 22 ( Figure 4 Only one battery cell 22 is shown, but generally in embodiments, the monitoring device 10 may be arranged to obtain measurements from a plurality of battery cells (e.g., a group of 12 or more battery cells). The analog measurements from the sensors 31, 32, 33 are passed via an analog multiplexer 35 to an ADC 37, which sends the digitized measurements to a processor 39. The processor 39 then runs a program stored in a memory 40, which converts the received digital signals into physically meaningful measurements (such as volts, amperes, Kelvin, etc.) and packages the data ready for transmission. In embodiments, the packaged digitized measurements may be retained in internal registers within the processor 39 prior to transmission. The radio block 45 is periodically activated, which causes the stored packaged measurements stored internally in registers within the processor 39 to be wirelessly transmitted to the communications controller 15 via the antenna 30.

[0038] The structure of the communication controller 15 is similar to that of the cell monitoring device 10 in that the communication controller 15 also includes an antenna 30, a radio block 45, a processor 39, a memory 40, and a clock 48. However, instead of storing a program for coordinating the capture, packaging, and transmission of sensor measurements from sensors 31, 32, 33, the memory 40 in the communication controller 15 stores a program that enables the processor 39 of the communication controller 15 to coordinate the transmission of measurement data to the battery management unit 20. In some embodiments, the processor 39 of the communication controller 15 can detect errors in the transmission, reception, and / or packaging of sensor measurements before transmitting the measurement data to the battery management unit 20. Such processing can involve checking for error detection or error correction codes contained in the transmission received via the antenna 30. In addition, the communication controller 15 also provides a communication path so that control messages are sent from the battery management unit 20 to the cell monitoring devices 10-1...10-N via the antenna 30 and the wireless communication link. In some embodiments, the communication controller 15 can generate control messages and send the control messages to the cell monitoring devices 10-1...10-N via the antenna 30.

[0039] although Figure 4 The illustrated architecture of the cell monitoring device 10 and the communication controller 15 may be satisfactory for low-risk applications, but such an architecture is not suitable for high-risk applications because there are many unreliable points in the illustrated architecture.

[0040] For example, a fault in the ADC 37 may not be detected. Alternatively, a fault in the software routine may not be detected. "Stuck-at" faults may occur in many locations where a value that should have changed is not updated. If the ADC 37 output value fails to update, the system may not notice that the value failed to change. At the same time, the battery cell may be over-voltage, which may cause danger. The processor software may not update the value sent to the radio block 45, so the communication controller 15 receives a value that appears to be safe but is actually incorrect.

[0041] In view of these problems, in many applications, it is possible to use Figure 5 Alternative architecture shown.

[0042] and Figure 4 Compared with the architecture of Figure 5 In an alternative architecture, a diagnostic source block 50 is included in the cell monitoring device 10, which is arranged to apply a known signal to the analog multiplexer 35. If the processor of the monitoring device 10 or the communication controller 15 subsequently does not see a known value or a predicted value based on a known value, then this may be an indication that something is wrong and a fault will be detected.

[0043] in addition, Figure 5 The architecture replaces ADC 37 with a multiplexer 51 connected to two ADCs 37-1, 37-2. It is unlikely that the two ADCs 37-1, 37-2 will show the same fault at the same time (i.e., the probability is very low). Therefore, the outputs from ADCs 37-1, 37-2 can be compared, and if they are not substantially consistent (i.e., the ADC conversions obtained are substantially corresponding), the fault can be marked. Typically, in this case, if there is an inconsistency between the results of ADCs 37-1, 37-2, it will usually only be possible to determine that one of ADCs 37-1, 37-2 is faulty, but it is impossible to determine which one. However, in some embodiments, a diagnostic source (e.g., a known value from a diagnostic source block 50 or a predicted value based on a known value) can be combined to identify which of ADCs 37-1, 37-2 is in error. Another potential benefit of having two ADCs 37-1, 37-2 is that the outputs of the ADCs 37-1, 37-2 that are substantially consistent (i.e., the values ​​obtained do not differ by more than a threshold amount) can be averaged to obtain an average value of the digitized sensor signal. This can improve the accuracy of the analog-to-digital conversion of the measured analog signal because it will reduce the effects of noise in the measurement and conversion process. In some embodiments, this may be preferred over simply truncating the measurement signal from a single ADC.

[0044] In addition to using a pair of ADCs 37-1, 37-2 and a multiplexer 51 instead of a single ADC 37, Figure 5 In the architecture of , the processor 39 of the monitoring device 10 and the communication controller 15 is also replaced by a dual-core lockstep processor 52. A dual-core lockstep processor 52 (sometimes referred to as a safety processor) is a processor comprising two (or more) processor cores, each of which runs the same software program, but one core has a delay relative to the other core. Apart from this delay, the two cores run in lockstep. This enables the outputs of the cores to be compared (taking into account the delay). Since the cores run the same program on the same data, the results should be exactly the same. Therefore, if one of the software programs on one of the cores is corrupted and the results are inconsistent, a fault can be detected.

[0045] Although Figure 4 These modifications to the architecture improve the ability to confirm that no errors occurred during the conversion of sensor measurements from sensors 31, 32, 33 at the cell monitoring device 10 and their transmission to the battery management unit 20, but the reliability of the data received by the battery management unit 20 can be further enhanced by limiting the processing performed by the dual-core lockstep processor 52.

[0046] More specifically, Applicants have recognized that software processing of data within the communication path between the acquisition of analog measurements by sensors 31, 32, 33 at cell monitoring devices 10-1...10-N and the receipt of the collected data at the battery management unit 20 is a significant potential source of error within the battery management system. Hard-wired data processing, such as that performed by multiplexer 35 and ADC 37-1, 37-2, is inherently deterministic. For example, as described above, because the results of hard-wired data processing are predictable within tolerances, faults or errors can be detected. However, software processing (particularly where it depends on factors external to the processor) is not (e.g., because such external factors can lead to a wide range of results, often leading to results from a variety of possibilities that, in fact, are unpredictable before the processing is actually performed). Examples of such external factors would include any processing based on an interrupt that would change the intended processing by causing a particular process to stop while a second process is being performed. Additionally, operations that rely on non-deterministic external memory access (rather than storing values ​​within the processor's registers) can result in non-deterministic errors, as can the use of a stack, as stack overflow errors can occur at unexpected times. In contrast, when processing is deterministic and does not involve interrupts, external memory access steps, etc., it can be expected that processing will run to completion within a set period of time, and the time required to run the program to completion can be expected to vary relatively little. This would not be the case if the program involved interrupt steps, as such interrupts would necessarily render the time required for the program to run to completion indeterminate, as any interruption would result in the processing being suspended for an unknown period of time and the time at which such an interrupt would be triggered could not be known in advance.

[0047] Although software can be analyzed to "prove" that errors will not occur, such analysis is difficult, time consuming, and expensive. Applicants have recognized that much of the potential unreliability of software processing in the data path between a set of sensors 31, 32, 33 and the battery management unit 20 can be reduced by applying a number of basic principles to the construction of the programs to be run by the processors 39, 52.

[0048] First, as a principle, processing measurements from a set of sensors 31, 32, 33 should be limited to converting the sensor measurements into meaningful digital data (e.g., converting the sensor measurements into digital codes that have physical meaning for measurements such as volts, amperes, kelvins, etc.) and packaging such data (including generating and checking any error detection or error correction codes within the data to be transmitted) so that it can be transmitted to the battery management unit 20 for analysis. Other processes (e.g., non-critical but potentially helpful processing such as generating histogram data representing the time that the cells 22-1...22-N remain in a particular state) should be performed via separate processing paths using separate processors that are not responsible for processing, packaging, and transmitting the sensor measurement data.

[0049] Secondly, the programs to be executed as part of the data transfer path should be designed to avoid the use of any interrupts, external memory access steps involving the storage or access of data in non-deterministic memory, or the use of stacks. The latter principle can be achieved if the programs within the data transfer path are arranged to store data in the internal registers of the processor 39 rather than utilizing external memory during the process of processing sensor data and transmitting it from the sensors 31, 32, 33 to the battery management unit 20, and the scope of the programs to be executed by the processor 39, 52 is such that they must run to completion in a time scale that is smaller than the time scale for obtaining sensor measurements and reporting them to the battery management unit 20.

[0050] The latter criterion can be achieved if the sensor measurements are sampled and reported to the battery management unit 20 according to a predetermined schedule, and the processing power and clock speed of any processor 39, 52 within the data transmission path between the sensors 31, 32, 33 and the battery management unit 20 are such that any program to be executed by such processor 39, 52 within the data path will run to completion in a time scale that is shorter than the time scale for sampling and reporting the data.

[0051] Thus, for example, when cell measurements are sampled and reported at a frequency of several hertz and the processor 39, 52 has a processing speed of the order of several megahertz, the programs to be executed by the processor 39, 52 need to be such that they must run to completion within a number of clock cycles that is less than the ratio between the sampling frequency and the processing speed of the processor 39, 52. While this means that the processing power of the processor 39, 52 will not be fully utilized, this will ensure that each program executed by the processor 39, 52 can be completed and packaged data can be transmitted when required. This, together with the absence of the use of interrupts, external memory accesses, or the use of stacks, causes the processor 39, 52 to operate as a deterministic state machine and will therefore make the processing reliability of the processor 39, 52 comparable to other hard-wired components of the cell monitors 10-1...10-N and the communication controller 15.

[0052] In some examples, the processors 39, 52 may be provided in a system (e.g., designed or manufactured to) not include at least one or all of the following functions: interrupts, external memory access, and / or use of a stack. Alternatively, the processors 39, 52 may be provided in a system having the above functions, but these functions are disabled. However, in other alternative embodiments, the processors 39, 52 are provided in a system having the above functions, but any program to be run thereon is designed to avoid using any of these functions.

[0053] In addition, preferably, the operations performed by the processor 39, 52 within the communication path between the ADC 37 or ADC 37-1, 37-2 and the battery management unit 20 are such that the processing is limited to converting the output of the ADC to data and packaging such data, including creating and attaching any error checking or error correction codes, without storing or modifying the data representing the sensor measurements. Preferably, the processing is limited to processing according to a single set of instructions corresponding to that task. This should help ensure that the processor 39, 52 operation is the same each time the process is performed.

[0054] Interrupted or faulty connection detection using circuits that monitor current flow

[0055] The following description relates to an example circuit system of the present disclosure, the circuit system including at least one circuit for monitoring current (e.g., injected current), wherein the at least one circuit is operable to detect an interruption or failure in a signal communication path that may be caused by, for example, a faulty pin. The interruption or fault detection may take the form of detecting or identifying an open circuit. For example, such an open circuit may occur when a pin or connection between a cell monitoring device (CMD) and a sensor external to the CMD is damaged, resulting in a voltage on the pin in the event of such an open circuit. The interruption or fault detection may take the form of detecting or identifying a short circuit, such as typically between two adjacent pins of the CMD. Such a circuit for monitoring current may be configured to perform an open circuit detection (OCD) or short circuit detection (SCD) process as described below. For example, Figure 6 Circuit 118, Figure 7 The circuits 118a, 118b and Figure 8 Any one or more of the circuits 418 in may form part of an open circuit detection circuit (OCD).

[0056] Previous system

[0057] Previous systems for detecting open or short circuits operate by varying the current and observing the change in voltage. Such systems are similar to those using the circuits described herein for monitoring current (e.g., Figures 6 to 8 For example, under similar conditions with all other variables being the same, the time taken may differ by a factor of about ten. The exemplary embodiments of OCD and / or SCD described herein at least save a significant amount of time in detecting an open or short circuit, which may be an indication of a broken or faulty connection.

[0058] Open Circuit Detection (OCD) According to Some Example Embodiments

[0059] In some examples, the sensor (such as Figures 1 to 5 The connection between the sensors 31, 32, 33) and the analog multiplexer 35 of the exemplary battery management system in FIG. 1 reaches a defined voltage and a current injected into the connection is required to identify an open circuit in the connection. In normal operation, since the impedance of the sensors 31, 32, 33 is too low, any reasonable amount of current cannot force the connection voltage to change much. In the event of an open circuit, such as due to a faulty pin, the connection will present a high impedance and the connection voltage can then be moved or changed by injecting current into the connection.

[0060] Therefore, such a circuit for monitoring injected current can be used on the electrical connection pins of sensors 31, 32, 33, which should have a normal impedance value within the operating impedance range so as to detect an interruption or faulty connection by identifying a fault or error in the connection when the voltage on the electrical connection pin behaves in a specific manner in response to a possibly abnormal injected current or an expected response of a faulty connection.

[0061] In some examples, when such an interruption or faulty connection is detected, the detection is reported to the device or controller using the same process or method as how the measurement data from the sensors 31, 32, 33 is transmitted, for example, as described herein or in Figures 1 to 5 10 -N, a diagnostic source block 50, a communication controller 15, and / or a battery management unit 20 of a battery management system shown in FIG. In some examples, data representing an output signal from a circuit for monitoring current is transmitted to a device or controller using the same process or method as how measurement data from sensors 31, 32, 33 is transmitted, for example, as described herein or in Figures 1 to 5 The battery management system shown in the figure includes a cell monitoring device 10, 10-1...10-N, a diagnostic source block 50, a communication controller 15 and / or a battery management unit 20, so that the device or controller can process the received data to determine whether an interruption or faulty connection is detected. It should be understood that according to some examples, a circuit for monitoring current is implemented using an application specific integrated circuit (ASIC).

[0062] Figures 6 to 8 and the schematic circuits shown therein provide examples of circuits operable in this manner for monitoring current. In some examples, such circuits for monitoring injected current may be part of one or more components (e.g., connected status sensors or those components of a circuit system operable to obtain measurements of one or more pins of a battery system) that are arranged to have one or more electrical connections with another component, such as Figures 1 to 5 Any component of the exemplary battery management system in, such as exemplary battery cell monitoring devices 10-1, 10-2, ..., 10-N, communication controller 15, battery management unit 20, one or more sensors 31, 32, 33, ADC 37, 37-1, 37-2 and / or multiplexers 35, 51.

[0063] Figure 6At least one circuit 118 for monitoring injected current according to some examples described herein is shown. In some examples, the circuit 118 can be a component of a circuit system or a cell monitoring device 10, 10-1...10-N, and can be operated to transmit, communicate and / or report its output (such as interrupt detection, fault detection, or connected state sensor measurement) to a controller (e.g., communication controller 15 or battery management unit 20) in a battery system (not shown).

[0064] Such circuitry, including at least one circuit for monitoring current as described herein, can be operable to obtain measurements (e.g., voltage measurements) of one or more pins 116 of the battery system. In some examples, Figures 1 to 5 The sensors 31, 32, 33 (not shown) of the exemplary battery management system in can include one or more internal circuit systems for obtaining voltage measurements of one or more pins 116, and / or can include connections to measurement points of external circuit systems and battery systems (not shown) via device pins 116. In some examples, the sensors 31, 32, 33 (not shown) are external sensors that can be electrically connected to one or more circuit systems for obtaining voltage measurements of one or more pins 116 via one or more pins 116. One or more pins 116 can be connected to one or more circuits 118, 118a, 118b, 418 via a multiplexer 35, as in Figures 6 to 8 In the example shown, one or more electrical connections may be established to one or more selected pins through one or more circuits 118 , 118 a , 118 b , 418 .

[0065] Figure 6 and Figure 7 The one or more circuit systems shown in the figure include at least one circuit 118, 118a, 118b for monitoring current, and the at least one circuit may include at least one other circuit 117 for amplifying changes, and the at least one other circuit itself may include at least one differential amplifier 112, a voltage reference 219 (or a reference voltage source for providing a reference voltage Vref) electrically connected to the first input terminal 120 of the differential amplifier 112, wherein the differential amplifier 112 also includes a second input terminal 121 and an output terminal 122.

[0066] At least one circuit 118, 118a, 118b (e.g., a circuit for OCD) may further include at least one transconductance member 213a, 213b, which may include at least one output terminal 227a electrically connected to the second input terminal 121 of the differential amplifier 112 and at least one input terminal 228a, 228b electrically connected to the output terminal 122 of the differential amplifier 112. The transconductance members 213a, 213b may be arranged in the circuit 118 for monitoring the injected current so that they convert the voltage on the input terminals 228a, 228b into a current on the output terminals 227a, 227b.

[0067] The second input terminal 121 of the differential amplifier 112 and the at least one output terminal 227a of the at least one transconductance member may also be configured to be electrically connected to one or more pins 116 of the battery system, for example, via a multiplexer 35. The one or more pins 116 may provide an electrical connection to a module or cell of the battery system, and / or may provide an electrical connection to an external measurement point (not shown), for example, an electrical connection to one or more sensors 31, 32, 33. The analog multiplexer 35 may be operable to select at least one of the one or more pins 116 and electrically connect only the selected pin to the at least one output terminal 227a of the at least one transconductance member.

[0068] The at least one circuit 118 for monitoring current may also include at least one current source 214 electrically connected to at least one output terminal 227b of at least one of the at least one transconductance member. Such current source 214 is used to provide a reference current.

[0069] The at least one circuit 118 may also include an output 125 electrically connected to at least one output 227b of at least one of the at least one transconductance member. The at least one circuit 118 for monitoring current may then be operable to detect an interruption or absence of electrical connection to the sensor connected to the one or more pins 116 by monitoring the current required to cause a change in voltage on the one or more pins 116.

[0070] Figure 6 A specific example is shown in which at least one transconductance member includes at least one transistor 213a, 213b. Figure 6In the example shown, at least one transistor 213a, 213b includes a pair of field effect transistors, for example, a first field effect transistor 213a and a second field effect transistor 213b, each field effect transistor itself including a source terminal 226a, 226b, a drain terminal 227a, 227b (serving as an output terminal of the transconductance member) and a gate terminal 228a, 228b (serving as an input terminal of the transconductance member). The first field effect transistor 213a and the second field effect transistor 213b are arranged in parallel so that their respective gate terminals 228a, 228b are electrically connected to each other, and their respective source terminals 226a, 226b are electrically connected to each other.

[0071] The output terminal 122 of the differential amplifier 112 is electrically connected to the gate terminals 228 a and 228 b of the pair of field effect transistors 213 a and 213 b. The drain terminal 227 a of the first field effect transistor 213 a is electrically connected to the second input terminal 121 of the differential amplifier 112 .

[0072] exist Figure 6 In the example shown, at least one current source 214 is electrically connected to the drain terminal 227b of the second field effect transistor 213b. Figure 6 and Figure 7 In the example shown, at least one current source 214, 214a, 214b comprises a variable current source. It should be understood that in other examples, a constant current source or any other type of current source may be used instead, as long as it can provide a reference current for a field effect transistor (such as the second field effect transistor 213b) of a transconductance member.

[0073] The circuit 118 , 118 a , 118 b for monitoring current further comprises at least one output amplifier 229 arranged at the output 125 , 125 a , 125 b of the circuit 118 , 118 a , 118 b for monitoring current, wherein the at least one output amplifier 229 may be implemented as at least one inverter.

[0074] exist Figure 6 and Figure 7 In the example shown, the voltage reference Vref is provided by two resistors 219 arranged in series. The two resistors 219 may act as a voltage divider setting the reference voltage to a defined fraction of the supply voltage.

[0075] In some examples, the pair of field effect transistors 213a, 213b may include at least one pair of p-channel or n-type field effect transistors, also referred to as PMOS (p-channel metal oxide semiconductor) or NMOS (n-type metal oxide semiconductor) transistors, respectively.

[0076] When used as part of an OCD circuit system, exemplary operation of circuit 118 is as follows. Figure 6 In FIG. 1 , the transconductance member is shown as NMOS transistors 213a, 213b. The reference voltage Vref is set to a relatively low value compared to the normal operating range, for example, set to about 10% of the power supply voltage. The multiplexer 35 connects the drain terminal 227a to an external sensor (e.g., sensor 31, 32, 33) via pin 116. Then, the amplifier 112 will try to force or control the gate terminals 228a, 228b so that the voltage at the second input terminal 121 is the same as Vref, thereby actually trying to pull down the voltage on pin 116 ("pull-down test"). If the connection is operating correctly, for example, the signal carried on the connection is not interrupted or disconnected, the voltage on pin 116 will not change too much if it changes (in other words, only a small change in voltage can be observed when monitoring). Therefore, the current in NMOS transistors 213a, 213b will reach a maximum. The maximum current is arranged so that it is higher than the reference current from the current source 214. This means that the input to the one or more amplifiers 229 (which act as a chain of inverters) is pulled low and therefore the output signal at the output terminal 125 is set low. This indicates that there is no fault or interruption in the electrical connection caused by an open circuit.

[0077] However, if there is an open circuit on pin 116, little injected current is needed to move the voltage on pin 116. The current in NMOS transistor 213b is lower because not much current in NMOS transistor 213a is needed to move the voltage at input 121 of amplifier 112, and the input to one or more amplifiers 229 (which act as an inverter chain) is pulled high by the larger reference current from current source 214. The output signal at output 125 is set high, indicating an open circuit fault or interrupt.

[0078] However, if the voltage on pin 116 is normally very small, e.g., close to or at zero volts, then attempting to pull the voltage down as described above will fail because the result of performing a pull-down test cannot be used as a reliable indication of detecting an open circuit. Thus, an open circuit cannot be distinguished from a properly operating connection. In order to test for an open circuit in this situation, the voltage on pin 116 must instead be pulled high (a "pull-up test"). This requires a second circuit that is similar to circuit 118 but is configured differently to source current, rather than sink current. An example of such a second circuit is described below. Figure 7 The circuit 118b shown in FIG.

[0079] Figure 7 Another example of one or more circuit systems operable to obtain measurements of one or more pins includes a first circuit 118a for monitoring current and a second circuit 118b for monitoring current. Figure 6The circuit 118 in FIG. 1 is the same as the circuit 118 in FIG. For example, the reference voltage Vref of the first circuit 118a can be set to a relatively low value compared to the normal operating range, for example, set to about 10% of the power supply voltage. The second circuit 118b operates in a similar manner, but with the following differences, which means that the second circuit performs a pull-up test instead of the pull-down test performed by the first circuit 118a. The reference voltage Vref of the second circuit 118b can be set to a higher value, for example, set to about 90% of the power supply voltage. The transconductance member is implemented as a PMOS transistor that supplies current to pin 116 and supplies input to the amplifier. If there is an open circuit, the connection between the current slot 214b (which can be equivalent to the current source 214a in the first circuit 118a, but now acts as a slot, not a source) and the PMOS transistor is forced to be low. There is only one amplifier used as an inverter, so that the signal at the output terminal 125b is forced to be high when the circuit is open.

[0080] Figure 7 One or more circuit systems in the circuit 118a and the circuit 118b cannot perform pull-up and pull-down tests on the same pin at the same time. Therefore, at any given time, only one of the first circuit 118a and the second circuit 118b is electrically connected to the same pin through the multiplexer 35. It should be noted that when performing pull-up and pull-down tests on the same pin, although Figure 7 1 and 125b are shown as being directly connected to the logic AND element 126 via separate inputs, but the logic AND element 126 will receive signals from the outputs 125a and 125b at different times and will therefore perform an AND operation on the inputs with a time delay therebetween. This may require that the inputs of the logic AND element 126 be latched or that the AND operation be performed by a device (e.g., a processor) having a memory.

[0081] In order to detect an open circuit based solely on the voltage on the pin, the pin must be pulled down and pulled up. Typically, these two tests are performed when the operation of one or more circuit systems does not interfere with other functions of the battery system (e.g., obtaining sensor measurements from one or more external sensors (such as sensors 31, 32, 33) connected to the pin 116). In some examples, one or more controllers described herein can schedule or synchronize such pull-down and pull-up tests so that these tests are not performed when the pin 116 is used to carry signals or data for other functions of the battery system.

[0082] It should be understood that the operation Figure 7For example, the multiplexer 35 may be controlled so that: at a particular moment, the first circuit 118a performs a pull-down test on the first pin, while the second circuit 118b performs a pull-up test on the second pin different from the first pin, and the output signals at the output terminals 125a and 125b are stored in the memory; and at another moment, the first circuit 118a performs a pull-down test on the second pin, while the second circuit 118b performs a pull-up test on the first pin, and the output signals at the output terminals 125a and 125b and the stored output signals from the previous moment are used as inputs to the logic AND element 126 to detect the open circuit. It should be understood that the multiplexer 35 may be used. Figure 7 Still other modifications may be implemented to detect an open circuit using one or more circuit systems in the embodiment.

[0083] exist Figure 7 In the example shown, the first circuit 118a for measuring current and the second circuit 118b for measuring current include a pair of n-type field effect transistors and a pair of p-channel field effect transistors. However, it should be understood that other types of transconductance members can be used in the first circuit 118a and the second circuit 118b depending on the operation that the circuits 118a, 118b are designed to perform (e.g., pull-up or pull-down testing).

[0084] Figure 8 An example of one or more circuit systems 418 is shown, the one or more circuit systems and Figure 7 The example provided in is different in that the first circuit for monitoring current (for pulling the voltage on pin 116 high) and the second circuit for monitoring current (for pulling the voltage on pin 116 low) share the same circuit 417 for amplifying changes. In this example, the first variable current source 214a is electrically connected to the drain terminal of the second field effect transistor 213b, and the second variable current source 214b is electrically connected to the drain terminal of the fourth field effect transistor 413b. Switches 417a, 417b, 417c, 417d are configured to operate one or more circuit systems 418 to pull up or pull down. In Figure 8In the example circuit for monitoring current shown, the drain terminal of the third field effect transistor 413a is electrically connected to the second input terminal 121 of the differential amplifier 112. When the switch 417c is closed, the output terminal 122 of the differential amplifier 112 is electrically connected to the gate terminals of the third field effect transistor 413a and the fourth field effect transistor 413b. When the switch 417b is closed, the output terminal 122 of the differential amplifier 112 is electrically connected to the gate terminals of the first field effect transistor 213a and the second field effect transistor 213b. Therefore, if the first switch 417a and the second switch 417b are closed, the one or more circuit systems 418 pull down the voltage on the pin 116. If the third switch 417c and the fourth switch 417d are closed, the one or more circuit systems 418 pull up the voltage on the pin 116. In some examples, a controller may be provided to control the opening and closing of the switches 417a, 417b, 417c, and 417d to configure the one or more circuit systems 418 to pull up or pull down.

[0085] Short Circuit Detection (SCD) According to Some Exemplary Embodiments

[0086] In some examples, the above open circuit detection process (e.g., pull-up or pull-down test) is performed on a first pin while measuring the voltage on a second pin different from the first pin. When the open circuit detection process is performed on the first pin, the measured value on the second pin can be compared to determine the presence of a short circuit between the first pin and the second pin. If the voltage measurement on the second pin also changes as the voltage of the first pin is pulled up or pulled down, this indicates that there may be a short circuit between these pins.

[0087] Alternatives for transconductance members

[0088] Figures 6 to 8 The transconductance member in the circuit system in the embodiment includes at least one transistor. In some examples, such at least one transistor includes at least one field effect transistor and / or at least one bipolar transistor. Such at least one field effect transistor may include at least one n-type transistor and / or at least one p-type transistor.

[0089] Effects of Impedance on Circuits Used to Monitor Current

[0090] If the above example circuit for monitoring current is connected to a high impedance (e.g., a pin of a pressure sensor), the open circuit detection function of the circuit may have less utility than the short circuit detection function. Alternatively, if such a circuit for monitoring current is electrically connected to a low impedance (such as a pin of a shunt or a cell voltage), the short circuit detection function of the circuit may have less utility than the open circuit detection function of the circuit.

[0091] Methods of enabling open circuit detection or short circuit detection according to some exemplary embodiments

[0092] In some examples of methods for enabling open circuit detection or short circuit detection, at least one circuit for monitoring current is provided in a component of a battery system as described herein, wherein the circuit for monitoring current is operable to provide an output signal for detecting an open circuit or a short circuit, which output signal can then be used to detect an interruption or failure of a signal communication path in the battery system. For example, such an interruption or failure may be caused by a faulty pin. For example, the at least one circuit may be Figures 6 to 8 Any of the circuits 118, 118a, 118b, 418 in.

[0093] The method includes: providing a first element for establishing an electrical connection between a voltage reference and a first input of a different amplifier of at least one other circuit for amplifying a change, wherein the differential amplifier further includes a second input and an output; providing a second element for establishing an electrical connection between the second input of the differential amplifier and at least one output of at least one transconductance member; providing a third element for establishing an electrical connection between at least one input of at least one transconductance member and the output of the differential amplifier, wherein the second input of the differential amplifier and at least one output of at least one transconductance member can be configured to be electrically connected to one or more pins of a battery system; providing a fourth element for establishing an electrical connection between at least one current source and at least one output of at least one of the at least one transconductance members; and providing a fifth element for establishing an electrical connection between the output of at least one circuit for monitoring current and at least one output of at least one of the at least one transconductance members. In some examples, the first element, the second element, the third element, the fourth element, and the fifth element are disposed on a semiconductor material and / or in an integrated circuit (IC) chip. In some examples, at least some of the first element, the second element, the third element, the fourth element, and the fifth element are disposed on a printed circuit board (PCB) or a printed wiring board (PWB). Preferably, the first element, the second element, the third element, the fourth element and the fifth element include a conductive component having an exposed surface for establishing an electrical connection.

[0094] In some examples, the method may also include providing at least one circuit for monitoring current in a monitoring device described herein, wherein the monitoring device is operable to report sensor measurements in the battery system, and wherein the monitoring device includes one or more circuit systems operable to obtain measurements of one or more pins of the battery system, and the one or more circuit systems include at least one circuit for monitoring current.

[0095] In some other examples, the method may also include establishing (e.g., by physically connecting via welding or by controlling one or more switches to establish electrical contact) an electrical connection using the first element, the second element, the third element, the fourth element, and the fifth element, whereby at least one circuit for monitoring current is operable to generate an output signal for detecting an open circuit or a short circuit, which output signal may then be used to detect an interruption or absence of an electrical connection of a sensor connected to one or more pins of the battery system by monitoring the current required to cause a change in voltage on the one or more pins. For example, the output signal may indicate an interruption or absence of an electrical connection of a sensor connected to the one or more pins.

[0096] Power-On Reset

[0097] Circuits on an application specific integrated circuit (ASIC) are typically designed using a library of standard components. For example, an ASIC designer does not have to design a trigger circuit, and the ASIC manufacturer will provide previously verified trigger designs for all designers to use. There will be many such parts, which are combined into a library of standard parts. The selected standard parts are then combined into core circuits by the ASIC designer to perform any function that the ASIC needs to perform, for example, as a processor. For example, the core circuit can be designed or arranged to perform some or all of the functions or functionalities described herein as being performed by a circuit system, device, or processor. In some examples, an ASIC is utilized to implement one or more components of a system or device described herein.

[0098] A standard library will be specified to operate within a well-defined voltage range. For example, the library may be defined to operate within a voltage range of 1.10V to 1.30V. Within this range, the library parts are guaranteed to operate as defined. Outside this range, operation is not guaranteed. For example, if the voltage is too low, the parts may operate too slowly, or an example flip-flop may not hold its state. If the voltage is too high, the parts may switch too quickly, causing timing problems, or the parts may age too quickly.

[0099] Circuits need to operate normally or at least in a predictable manner, especially in safety-critical systems such as those required for functional safety. It is useful to always know the state of the circuit rather than being in an unknown and therefore potentially unsafe state. If the core circuit is to operate correctly, the circuit power supply should deliver a supply voltage within a specified range. To provide certainty or at least predictability, if the voltage is outside the specified range, the core circuit can be forced into a known "reset" state in which it is inoperable but known to be safe.

[0100] The most common situation where this occurs is when the core circuit is powered up. The circuit will start with zero supply voltage. As the voltage increases, the voltage will initially be too low and the circuit must be held in reset. Eventually the voltage will enter the specified range and the circuit may be allowed to leave reset and begin normal operation.

[0101] The function of forcing a reset state is performed by a reset circuit. A reset circuit (often called a power-on reset or POR circuit) sends a signal to the core circuit. When asserted, this signal forces the core circuit to enter a reset state. When deasserted, the core circuit is allowed to leave the reset state in a defined manner. A typical reset circuit measures the supply voltage, and when the supply voltage reaches a sufficiently high level, the reset signal is deasserted.

[0102] Typically, power is applied very quickly, for example, in a time typically much less than a second. The ASIC may have a specification for how quickly the supply voltage must rise, for example, it may specify that the supply voltage must reach a specified range in less than 1 ms.

[0103] Some circuits will start operating as soon as the voltage is high enough, for example, a clock generator or oscillator. The clock generator also needs to be operational before the core circuit can operate normally. The clock generator requires a certain amount of time to stabilize, for example, 10ms. There may be other circuit systems that also require a certain amount of time to stabilize and become fully operational.

[0104] For this reason, the POR circuit typically has a time delay before the reset signal is asserted that is longer than the time required for the slowest circuit to stabilize. In the above case, for example, this time delay can be set to 50ms, giving the clock generator sufficient time to stabilize into normal operation. Therefore, the core circuit is allowed to leave the reset state only when the supply voltage is within the specified range and has been within the range for more than a (predefined) period of time.

[0105] In some examples, a type of ASIC may be utilized to implement the cell monitoring device (CMD) described herein. Such a CMD includes core circuitry built from standard library parts and performs safety functions that require the core circuitry to always be in a known state. A CMD attached to a battery cell will be powered by the battery cell. If the CMD is attached to a cell when the cell voltage is below a minimum specified voltage, the core circuitry on the CMD will remain in reset and remain in reset until the cell voltage rises high enough for the CMD power supply to provide a supply voltage within a specified range.

[0106] Unlike more typical applications where the power is connected, on a CMD attached to a cell, the power is always connected and almost permanently on until the cell is depleted, so the power provided may only change very slowly. Typically, the cell voltage will only increase when the cell is charging.

[0107] A special case is when a CMD is attached to a cell during cell manufacturing. Initially, the cell is at zero volts. The cell then undergoes a "formation charge," where the cell is charged at a rate that allows the necessary electrochemical processes to occur in the cell. A formation charge may take hours or even days to perform.

[0108] Therefore, instead of increasing over 1ms or even 1s, the supply voltage increases over hours. This very slow ramp-up creates problems for normal POR circuits, as the circuit cannot implement a time delay (of any practical length) to ensure that all circuits are within specified ranges and can operate before the POR time delay expires.

[0109] Therefore, some of the example embodiments presented herein involve a regulation system that provides a power-on reset for a CMD core circuit system (e.g., the core circuit system in the cell monitoring devices 10, 10-1, ... 10-N described herein) in a defined state in an efficient manner, thereby eliminating the need for a POR time delay. Fig. 9 An example electronic regulation system for regulating the voltage to be supplied to the core logic of a CMD 305 within a battery system during a power-on reset (POR) is shown. The system includes a voltage regulation unit 301 , a bandgap reference unit (BG), and a power-on reset comparator 303 .

[0110] In operation, once the voltage level supplied to the CMD core circuit system 305 is in the range of, for example, 1.1 volts to 1.3 volts, the CMD can operate. The power supply 307 can be configured to supply a voltage (VDD) in the range of 0 to 5 volts to the regulation system during a power-on reset. The electronic regulation system can generate a regulated voltage (D) based on a bandgap voltage (VBG) reference provided by a bandgap reference unit (BG). VDD ), and once the regulated voltage reaches a threshold (eg, 1.1v to 1.3v) that provides functionality in a safe manner, the core circuitry of CMD 305 is enabled.

[0111] First, the voltage (VDD) supplied by the power supply 307 will activate the bandgap reference unit (BG). The bandgap reference unit (BG) is configured to enable the voltage regulating unit 301 by providing an enable signal (VBG_ok) to the voltage regulating unit 301. The bandgap reference unit (BG) is also configured to supply a stable bandgap voltage reference (VBG) to the voltage regulating unit 301 and the power-on reset comparator 303. Once enabled by the bandgap reference unit (BG), the voltage regulating unit 301 is configured to generate a regulated voltage (D) based on a comparison of the bandgap reference voltage (VBG). VDD The voltage regulation unit 301 is further configured to provide a regulated voltage (D VDD The power-on reset comparator will enable CMD 305 to receive the regulated voltage (D VDD ).

[0112] In some examples, a bandgap reference cell (BG) is a temperature-independent voltage reference circuit that produces a fixed and constant voltage regardless of variations caused by power supply, temperature changes, or circuit load. Fig.10 An example configuration of a bandgap adjustment unit (BG) is provided in The bandgap reference unit (BG) includes a first comparator 401 and a second comparator 403 , wherein the second comparator 403 is configured to enable the operation of the first comparator 401 .

[0113] The supply voltage (VDD) is provided as an input to the second comparator 403. The second comparator 403 is also configured to receive a base emitter voltage (VBE) reference as an input. The base emitter voltage (VBE) reference voltage generator may be in the form of a bipolar device for use as a reference for the second comparator 403. According to some of the example embodiments, the supply voltage (VDD) may be input to a divided reference before being provided to the second comparator 403 to ensure that the magnitude of the voltage evaluated by the second comparator 403 is within the operating range of the second comparator 403.

[0114] The second comparator 403 can be used to detect when the supply voltage (VDD) is greater than the VBE reference voltage. Once the supply voltage reaches a level greater than the VBE reference voltage, the second comparator 403 will send an enable signal (EN) to the first comparator 401, thereby enabling the operation of the first comparator 401. Once the supply voltage reaches a level greater than the VBE reference voltage, a true logic signal will also be sent to the AND logic element 405.

[0115] The first comparator 401 is configured to receive a supply voltage (VDD) and a generated bandgap voltage reference (VBG) as inputs. It should be understood that the divided supply voltage (VDD) may also be input to the first comparator 401 to ensure that the magnitude of the voltage evaluated by the second comparator 403 is within the operating range of the second comparator 403. Upon receiving an enable signal (EN) from the second comparator 403, the first comparator 401 will be able to compare the supply voltage (VDD) with the bandgap voltage (VBG) reference. Once the supply voltage (VDD) reaches a level above the bandgap voltage (VBG) reference, the first comparator 401 will send a logical true signal to the logic and element 405.

[0116] Under typical process and temperature conditions, with the bandgap voltage (VBG) reference and the supply voltage (VDD) as inputs, it is possible that the first comparator 401 is sufficient to indicate when the bandgap is close to the steady-state output voltage. For example, assuming a value of ~1V at minimum VDD operation, when the bandgap voltage (VBG) reference>1.0V, the enable signal (VBG_ok) will be flagged, thereby indicating that the supply voltage (VDD)>1.0V is guaranteed.

[0117] The problem with this solution is that when the supply voltage (VDD) is ramped up under non-ideal conditions (hot / cold temperatures, slow / fast silicon), it is possible that the bandgap voltage (VBG) reference can exceed this threshold and then drop back to 0 V as the supply voltage (VDD) ramps up. Under these conditions, the enable signal (VBG_ok) will mark high and then low for (potentially) multiple VDD voltages, and this can cause startup issues in subsequent circuitry.

[0118] To address such issues, a second comparator 403 is used between the supply voltage (VDD) and the base emitter voltage (VBE) reference. The intent of this circuit portion is to indicate when the supply voltage (VDD) is above a minimum voltage. This voltage threshold is selected to be the minimum value of the supply voltage (VDD) that guarantees that the bandgap voltage (VBG) reference will not fall back to 0V. This can be found from process-voltage-temperature (PVT) simulations. In other words, for a ramped supply voltage (VDD), this circuit portion will indicate when the bandgap will stabilize with power on. It should be understood that the base emitter voltage (VBE) reference can be configured to be equal to a determined minimum threshold voltage that guarantees that the bandgap voltage (VBG) will not fall back to 0V.

[0119] When this supply voltage (VDD) threshold voltage (e.g., base emitter voltage (VBE) reference) is reached, a second comparator 403 is used to enable the first comparator 401, which then detects whether the (stable) bandgap is actually powered on. According to some of the example embodiments, it is useful to use a second comparator 403 in addition to the first comparator 401, because, for example, for a fast VDD ramp, the first comparator 401 may generate a glitch, resulting in a false VBG_ok signal. In order to stop this behavior, a small delay (delay) can be added between the first comparator 401 being powered on and VBG_ok being active. The amount of delay required can be characterized in simulations on PVT for a fast VDD ramp. An example of such a delay can be on the order of a few nanoseconds.

[0120] Once the first comparator 401 and the second comparator 403 detect that the supply voltage is greater than the bandgap voltage (VBG) reference and the base emitter voltage (VBE) reference, respectively, the logic and element 405 will receive two logic true signals as inputs. Once the inputs to the logic and element 405 are both true signals, the element 405 is configured to send an enable signal (VBG_ok) to the voltage regulator 301, thereby enabling the regulator 301 to operate.

[0121] The voltage regulator is configured to generate a fixed output voltage of a preset magnitude that remains constant regardless of changes in input voltage or load conditions. The voltage regulator 301 will use the bandgap voltage (VBG) reference as a baseline or comparison to generate a regulated voltage (D VDD According to some of the example embodiments, the voltage regulating unit 301 may be a low dropout (LDO) regulator or any other voltage regulator capable of generating an output voltage regulated to a preset amplitude.

[0122] Regulated voltage (D VDD ) is provided to the power rail 304 used by the core circuitry of CMD 305 and further supplied to the POR comparator 303. Once the regulated voltage (D VDD ) is greater than the value of the bandgap voltage (VBG) reference, the POR comparator 303 will provide another enable signal (POR) to the core circuit system of CMD 305. The enable signal POR reminds the core circuit system of CMD 305 that the ramped supply voltage (VDD) has reached a safe level for operation. Thereafter, the core circuit system of CMD 305 will supply the regulated voltage (D VDD ) is used as a power source, for example, for its operation.

[0123] The description of the example embodiments provided herein has been presented for illustrative purposes. The description is not intended to be exhaustive or to limit the example embodiments to the precise form disclosed, and in view of the above teachings, modifications and variations are possible, or modifications and variations can be obtained by practicing various alternatives to the embodiments provided. The examples discussed herein are selected and described in order to explain the principles and essence of the various example embodiments and their practical applications, so that those skilled in the art can utilize the example embodiments in various ways and utilize the example embodiments with various modifications suitable for the specific purposes envisioned. The features of the embodiments described herein can be combined in all possible combinations of methods, devices, modules, systems, and computer program products. It should be understood that the example embodiments presented herein can be practiced in any combination with each other.

[0124] It should be noted that the word "comprising" does not necessarily exclude the presence of other elements or steps than those listed, and the word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. It should also be noted that any reference signs do not limit the scope of the claims, that example embodiments may be implemented at least in part by means of both hardware and software, and that several "components", "units" or "means" may be represented by the same item of hardware.

[0125] Various example embodiments described herein are described in the general context of method steps or processes, which in one aspect can be implemented by a computer program product embodied in a computer-readable medium, which includes computer-executable instructions, such as program code, executed by a computer in a networked environment. Computer-readable media may include removable and non-removable storage devices, including but not limited to read-only memory (ROM), random access memory (RAM), compact disk (CD), digital versatile disk (DVD), etc. In general, program modules may include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. Computer executable instructions, associated data structures, and program modules represent examples of program codes for performing the steps of the methods disclosed herein. A specific sequence of such executable instructions or associated data structures represents an example of corresponding actions for implementing the functions described in such steps or processes.

[0126] It should be understood that the processors 39, 52 described herein can be implemented using at least one processing unit (or at least one core) and one or more internal registers. It should also be understood that the processors 39, 52 described herein can be implemented using a circuit system configured to perform the operations described herein.

[0127] Various embodiments are described herein with reference to systems, methods, processes, devices, or computer-readable media. The disclosure of one is intended to be a disclosure of all. For example, it should be understood that the disclosure of the computer-readable medium described herein also constitutes a disclosure of the method implemented using the computer-readable medium and a system and device for implementing these methods, for example, via at least one processor or a circuit system configured to implement these methods. It should be understood that within the intended scope of the present disclosure, this form of disclosure is only for the convenience of discussion, and one or more aspects of one embodiment of this article can be combined with one or more aspects of other embodiments of this article.

[0128] In the drawings and description, exemplary embodiments have been disclosed. However, many variations and modifications may be made to these embodiments. Therefore, although specific terms are employed, these terms are used only in a general and descriptive sense and not for the purpose of limitation, and the scope of the embodiments is defined by the appended claims.

Claims

1. A monitoring device operable to report sensor measurements in a battery system, the monitoring device comprising: One or more circuit systems operable to obtain measurements of one or more pins of a battery system, the one or more circuit systems comprising: At least one circuit for monitoring current, the at least one circuit for monitoring current comprising: at least one other circuit for amplifying the change, the at least one other circuit for amplifying the change comprising at least one differential amplifier, a voltage reference electrically connected to a first input of the differential amplifier, the differential amplifier further comprising a second input and an output; at least one transconductance member, the at least one transconductance member comprising at least one output terminal electrically connected to the second input terminal of the differential amplifier and at least one input terminal electrically connected to the output terminal of the differential amplifier; wherein the second input terminal of the differential amplifier and the at least one output terminal of the at least one transconductance member are electrically connected to the one or more pins of the battery system; at least one current source electrically connected to at least one output terminal of at least one of the at least one transconductance member; and an output terminal electrically connected to at least one output terminal of at least one of the at least one transconductance member; Wherein the at least one circuit for monitoring current is operable to detect an interruption or absence of an electrical connection to a sensor connected to the one or more pins by monitoring the current required to cause a change in voltage on the one or more pins.

2. The monitoring device of claim 1, wherein the at least one transconductance member comprises at least one transistor.

3. The monitoring device of claim 2, wherein the at least one transistor comprises at least one pair of p-channel or n-type field effect transistors.

4. The monitoring device according to claim 3, wherein the at least one pair of p-channel or n-type field effect transistors comprises a first field effect transistor and a second field effect transistor, each field effect transistor comprising a source terminal, a drain terminal and a gate terminal, wherein the first field effect transistor and the second field effect transistor are arranged in parallel such that their respective gate terminals are electrically connected to each other and their respective source terminals are electrically connected to each other. 5 . The monitoring device according to claim 4 , wherein the output terminal of the differential amplifier is electrically connected to the gate terminals of the pair of field effect transistors. 6 . The monitoring device according to claim 5 , wherein the drain terminal of the first field effect transistor is electrically connected to the second input terminal of the differential amplifier.

7. The monitoring device of claim 6, wherein the at least one current source is electrically connected to the drain terminal of the second field effect transistor.

8. A monitoring device according to any preceding claim, wherein the at least one current source comprises a variable current source.

9. A monitoring device according to any preceding claim, wherein the at least one circuit for monitoring current comprises a first circuit for monitoring current and a second circuit for monitoring current, wherein the first circuit for measuring current comprises a p-channel field effect transistor and the second circuit for measuring current comprises an n-type field effect transistor.

10. A monitoring device according to any preceding claim, wherein the circuit for monitoring current further comprises at least one output amplifier arranged at the output of the circuit.

11. A monitoring device according to any preceding claim, wherein the at least one circuit for monitoring current is electrically connected to the one or more pins of the battery system via a multiplexer.

12. A monitoring device according to any preceding claim, wherein the current source provides a reference current.

13. A monitoring device according to any preceding claim, wherein the one or more circuit systems capable of obtaining measurement values ​​of one or more pins of a battery system include at least a first circuit capable of detecting an open circuit on a first pin and a second circuit capable of identifying a change in voltage on a second pin, wherein when a change in the voltage on the second pin is identified, the monitoring device is capable of detecting a short circuit.

14. A regulation system for providing a regulated voltage to a cell monitoring device CMD of a battery system during a power-on reset, wherein the battery system comprises at least one battery pack, each battery pack comprising a plurality of battery cells, wherein each battery cell is monitored via a corresponding CMD, the regulation system comprising: a bandgap reference unit (BG) configured to generate a bandgap reference voltage (VBG) based on a supply voltage (VDD) and further configured to generate a first enable signal (VBG_ok) once the bandgap reference voltage (VBG) is stable and at a level suitable for operational safety of the CMD core circuit (305); A voltage regulator unit (301) is configured to receive the bandgap reference voltage (VBG) and the first enable signal (VGB_ok) from the bandgap reference unit, and after receiving the first enable signal, the voltage regulator unit is further configured to generate the regulated voltage (D) for powering the CMD core circuit (305). VDD ), wherein the regulated voltage (D VDD );as well as A power-on reset comparator (303) configured to receive the bandgap reference voltage (VBG) from the bandgap reference unit (BG) and the regulated voltage (D VDD ), wherein the power-on reset comparator (303) is further configured to reset once the regulated voltage (D VDD ) is greater than the value of the bandgap reference voltage (VBG), a second enable signal (POR) is provided to the CMD core circuit 305, wherein the second enable signal (POR) enables the CMD core circuit to access the regulated voltage (D VDD ).

15. The regulation system according to claim 14, wherein the bandgap reference cell (BG) comprises: a first comparator (401) configured to receive the supply voltage VDD and the generated bandgap voltage reference (VBG) as inputs; a second comparator (403) configured to receive the supply voltage VDD and a base emitter voltage (VBE) reference as inputs; wherein the second comparator (403) is configured to enable operation of the first comparator (401) and provide a logical true to a logic AND element (405) once the second comparator detects that the supply voltage (VDD) is greater than the base emitter voltage (VBE) reference; wherein after being enabled by the second comparator (403), the first comparator (401) is configured to send a logical true to the logical AND element (405) once the first comparator detects that the supply voltage (VDD) is greater than the bandgap voltage (VBG) reference; and The logic AND element (405) is configured to provide the first enable signal (VBG_ok) to the voltage regulator unit (301) and provide the generated bandgap voltage (VBG) to the power-on reset comparator (303) once the inputs to the logic AND element are both true.

16. A method in a regulation system for providing a regulated voltage to a cell monitoring device CMD of a battery system during a power-on reset, wherein the battery system comprises at least one battery pack, each battery pack comprising a plurality of battery cells, wherein each battery cell is monitored via a corresponding CMD, the method comprising: generating a bandgap reference voltage (VGB) based on a supply voltage (VDD) via a bandgap reference unit (BG), and also generating a first enable signal (VBG_ok) once the bandgap reference voltage (VBG) is stable and at a level suitable for operational safety of the CMD core circuit (305); receiving the bandgap reference voltage (VBG) and the first enable signal (VGB_ok) from the bandgap reference unit via a voltage regulator unit (301); After receiving the first enable signal, a regulated voltage (D) is generated via the voltage regulator unit for powering the CMD core circuit (305). VDD ), wherein the regulated voltage (D VDD ); as well as The power-on reset comparator (303) receives the bandgap reference voltage (VBG) from the bandgap reference unit (BG) and the regulated voltage (D VDD ); Once the regulated voltage (D VDD ) is greater than the value of the bandgap reference voltage (VBG), a second enable signal (POR) is provided to the CMD core circuit (305) via the power-on reset comparator, wherein the second enable signal (POR) enables the CMD core circuit to access the regulated voltage (D VDD ).

17. The method according to claim 16, further comprising: Receiving the supply voltage VDD and the generated bandgap voltage reference (VBG) as inputs via a first comparator (401); receiving the supply voltage VDD and a base emitter voltage (VBE) reference as inputs via a second comparator (403); Once the second comparator detects that the supply voltage (VDD) is greater than the base emitter voltage (VBE) reference, the operation of the first comparator (401) is enabled via the second comparator (403) and a logic true is provided to the logic AND element (405); After being enabled, once the first comparator detects that the supply voltage (VDD) is greater than the bandgap voltage (VBG) reference, it sends a logic true to the logic and element (405) via the second comparator (403); as well as Once the inputs of the logic AND element are both true, the first enable signal (VBG_ok) is provided to the voltage regulator unit (301) via the logic AND element (405) and the generated bandgap voltage (VBG) is provided to the power-on reset comparator (303).

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