Array substrate, display panel and display device

Abstract

The invention discloses an array substrate, a display panel and a display device. The array substrate comprises: a substrate (1); the plurality of grid lines (2) are positioned on one side of the substrate (1) and extend along a first direction (X); a plurality of data lines (3) extending in a second direction (Y); the plurality of pixel electrodes (4) comprise a first pixel electrode (41) positioned on one side of the grid line (2) and a second pixel electrode (42) positioned on the other side of the grid line (2); the first pixel electrode (41) comprises a first sub-pixel electrode (411) and a second sub-pixel electrode (412) which are distributed along a first direction (X); the second pixel electrode (42) comprises a third sub-pixel electrode (421) and a fourth sub-pixel electrode (422) which are distributed along the first direction (X); one of the first sub-pixel electrode (411) and the second sub-pixel electrode (412) is electrically connected with one of the third sub-pixel electrode (421) and the fourth sub-pixel electrode (422).

Description

Array substrate, display panel, and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the international application filed with the State Intellectual Property Office of the People's Republic of China on August 29, 2023, with application number PCT / CN2023 / 115605 and application name "Array Substrate, Display Panel and Display Device", the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present disclosure relates to the field of semiconductor technology, and in particular to an array substrate, a display panel, and a display device. Background Art

[0004] The name UV2A comes from the multiplication of ultraviolet (UV) light and the VA method of the liquid crystal panel. This technology can precisely manipulate the alignment of liquid crystal molecules through ultraviolet light, greatly improving the light transmittance.

[0005] The key to UV2A lies in its use of a special polymer material as an alignment film, precisely controlling the tilt of liquid crystal molecules along the direction of ultraviolet light. This accuracy is measured in picometers (one trillionth of a meter). UV2A's advantage lies in its simple LCD panel structure, free of protrusions and slits. This "dream of LCD technicians" was explored as early as 30 years ago. Today, thanks to the availability of new materials, production equipment, and a refined processing process, this dream has become a reality. This simple LCD panel structure not only improves production efficiency but also offers numerous advantages in image quality.

[0006] Summary of the Invention

[0007] The present disclosure provides an array substrate, a display panel, and a display device. The array substrate includes:

[0008] substrate;

[0009] A plurality of gate lines are located on one side of the substrate and extend along a first direction;

[0010] a plurality of data lines extending along a second direction;

[0011] a plurality of pixel electrodes, the pixel electrodes comprising: a first pixel electrode located on one side of the gate line, and a second pixel electrode located on the other side of the gate line; the first pixel electrode comprising: a first sub-pixel electrode and a second sub-pixel electrode distributed along the first direction; the second pixel electrode comprising: a third sub-pixel electrode and a fourth sub-pixel electrode distributed along the first direction;

[0012] One of the first sub-pixel electrode and the second sub-pixel electrode is electrically connected to one of the third sub-pixel electrode and the fourth sub-pixel electrode.

[0013] In a possible implementation, the array substrate further includes: a plurality of transistors; the plurality of transistors electrically connected to the same pixel electrode are all electrically connected to the same data line and the same gate line;

[0014] The second sub-pixel electrode is located on a side of the first sub-pixel electrode away from the electrically connected data line, and the fourth sub-pixel electrode is located on a side of the third sub-pixel electrode away from the electrically connected data line; the first sub-pixel electrode is electrically connected to the fourth sub-pixel electrode.

[0015] In a possible implementation, the array substrate further includes: a first signal line extending along the second direction; the plurality of transistors include: a first transistor, a second transistor, and a third transistor;

[0016] The control electrode of the first transistor is electrically connected to the gate line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the first sub-pixel electrode and the fourth sub-pixel electrode;

[0017] The control electrode of the second transistor is electrically connected to the gate line, the first electrode of the second transistor is electrically connected to the data line, and the second electrode of the second transistor is electrically connected to the second sub-pixel electrode and the third sub-pixel electrode;

[0018] The control electrode of the third transistor is electrically connected to the gate line, the first electrode of the third transistor is multiplexed with the second electrode of the second transistor, and the second electrode of the third transistor is multiplexed with the first signal line.

[0019] In a possible embodiment, the pixel electrode further includes: a first sub-pixel electrode protrusion connected to the first sub-pixel electrode on the side facing the third sub-pixel electrode; and the second electrode of the first transistor is electrically connected to the first sub-pixel electrode through the first sub-pixel electrode protrusion.

[0020] In one possible implementation, the pixel electrode further includes: a connecting portion connecting the first sub-pixel electrode and the fourth sub-pixel electrode; the connecting portion includes: a first connecting portion extending along the second direction, and a second connecting portion extending along a third direction; the third direction intersects the first direction and the second direction;

[0021] One end of the first connecting portion is electrically connected to one end of the first sub-pixel electrode facing the third sub-pixel electrode, and the other end is electrically connected to the second connecting portion. The other end of the second connecting portion is electrically connected to one end of the fourth sub-pixel electrode facing the second sub-pixel electrode.

[0022] In a possible implementation manner, the pixel electrode further includes: a third sub-pixel electrode protrusion connected to a side of the third sub-pixel electrode facing the first sub-pixel electrode;

[0023] The second electrode of the second transistor is electrically connected to the third sub-pixel electrode through the third sub-pixel electrode protrusion.

[0024] In a possible embodiment, the pixel electrode further includes: a second sub-pixel electrode extension extending along the second direction, and a second sub-pixel electrode convex portion; one end of the second sub-pixel electrode extension is electrically connected to one end of the second sub-pixel electrode facing the fourth sub-pixel electrode, and the other end is electrically connected to the second sub-pixel electrode convex portion;

[0025] The second electrode of the second transistor is electrically connected to the second sub-pixel electrode through the second sub-pixel electrode protrusion.

[0026] In a possible implementation manner, an extending direction of the second sub-pixel electrode extending portion is parallel to an extending direction of the first connecting portion.

[0027] In a possible embodiment, the second sub-pixel electrode convex portion has a second sub-pixel electrode convex portion outer edge that is away from a side of the second sub-pixel electrode and extends along the first direction; the third sub-pixel electrode convex portion has a third sub-pixel electrode convex portion outer edge that is away from a side of the third sub-pixel electrode and extends along the first direction;

[0028] The extension line of the outer edge of the second sub-pixel electrode protrusion coincides with the extension line of the outer edge of the third sub-pixel electrode protrusion; or, the extension line of the outer edge of the second sub-pixel electrode protrusion at least partially overlaps with the third sub-pixel electrode protrusion; or, the extension line of the outer edge of the third sub-pixel electrode protrusion at least partially overlaps with the second sub-pixel electrode protrusion.

[0029] In a possible implementation manner, a line connecting the center of the convex portion of the third sub-pixel electrode and the center of the convex portion of the first sub-pixel electrode is parallel to the second direction.

[0030] In a possible implementation, the second electrode of the first transistor includes: a first transistor first portion extending along the first direction;

[0031] An orthographic projection of the first portion of the first transistor on the substrate and an orthographic projection of the first sub-pixel electrode protrusion on the substrate have an overlapping area.

[0032] In a possible implementation, the second electrode of the second transistor includes: a second transistor first portion extending along the first direction, and a second transistor second portion extending along the second direction and electrically connected to one end of the second transistor first portion;

[0033] The orthographic projection of the first part of the second transistor on the substrate has an overlapping area with the orthographic projection of the third sub-pixel electrode convex part on the substrate; the orthographic projection of the second part of the second transistor on the substrate has an overlapping area with the orthographic projection of the second sub-pixel electrode convex part on the substrate.

[0034] In a possible implementation manner, at least a portion of the second portion of the second transistor on the orthographic projection of the substrate overlaps with at least a portion of the second sub-pixel electrode extension on the orthographic projection of the substrate.

[0035] In a possible implementation, the first signal line has a recessed portion; and the second portion of the second transistor is located in at least a portion of the orthographic projection of the substrate, in an area surrounded by the orthographic projection of the recessed portion on the substrate.

[0036] In one possible implementation, the first signal line includes: a first signal portion, a second signal portion, and a third signal portion sequentially distributed along the second direction, a fourth signal portion extending along the first direction and connecting the second signal portion and the first signal portion, and a fifth signal portion extending along the first direction and connecting the second signal portion and the third signal portion.

[0037] An extension line of the first signal portion coincides with an extension line of the third signal portion; an extension line of the second signal portion does not coincide with an extension line of the first signal portion; the second signal portion, the fourth signal portion and the fifth signal portion constitute the recessed portion, and the fourth signal portion and / or the fifth signal portion at least partially overlap with the pixel electrode.

[0038] In a possible implementation, the array substrate further includes: a first common wiring located on one side of the gate line and extending along the first direction; the plurality of transistors include: a first transistor electrically connected to the data line, a second transistor, and a third transistor;

[0039] The control electrode of the first transistor is electrically connected to the gate line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the first sub-pixel electrode and the fourth sub-pixel electrode;

[0040] The control electrode of the second transistor is electrically connected to the gate line, the first electrode of the second transistor is electrically connected to the data line, and the second electrode of the second transistor is electrically connected to the second sub-pixel electrode and the third sub-pixel electrode;

[0041] The control electrode of the third transistor is electrically connected to the gate line, the first electrode of the third transistor is multiplexed with the second electrode of the second transistor, and the second electrode of the third transistor is electrically connected to the first common wiring.

[0042] In one possible implementation, the first sub-pixel electrode is electrically connected to the fourth sub-pixel electrode; the array substrate further includes: a plurality of transistors, a third common line located on one side of the gate line and extending along the first direction, and an auxiliary gate line located between the gate line and the third common line and extending along the first direction; the plurality of transistors include: a first transistor, a second transistor, and a third transistor;

[0043] The control electrode of the first transistor is electrically connected to the gate line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the first sub-pixel electrode and the fourth sub-pixel electrode;

[0044] The control electrode of the second transistor is electrically connected to the gate line, the first electrode of the second transistor is electrically connected to the data line, and the second electrode of the second transistor is electrically connected to the second sub-pixel electrode and the third sub-pixel electrode;

[0045] The control electrode of the third transistor is electrically connected to the auxiliary gate line, the first electrode of the third transistor reuses the second electrode of the first transistor, and the orthographic projection of the second electrode of the third transistor on the substrate has an overlapping area with the orthographic projection of the first common line on the substrate.

[0046] In one possible embodiment, the pixel electrode further includes: a connecting portion connecting the first sub-pixel electrode and the fourth sub-pixel electrode, and a first overlapping portion connected to the connecting portion; the connecting portion includes: a third connecting portion extending along the first direction, a fourth connecting portion, and a fifth connecting portion extending along the second direction;

[0047] One end of the third connecting portion is connected to the first sub-pixel electrode, one end of the fourth connecting portion is connected to the fourth sub-pixel electrode, one end of the fifth connecting portion is connected to the other end of the third connecting portion, and the other end of the fifth connecting portion is connected to the other end of the fourth connecting portion; the first overlapping portion is electrically connected to the third connecting portion and is away from a side of the first sub-pixel electrode to which it is connected;

[0048] The second electrode of the first transistor is electrically connected to the first sub-pixel electrode and the fourth sub-pixel electrode through the first connecting portion.

[0049] In one possible embodiment, the control electrode of the third transistor is electrically connected to the gate line; at least a portion of the orthographic projection of the third transistor and at least a portion of the orthographic projection of the first transistor on the substrate are located on different sides of the orthographic projection of the fifth connecting portion on the substrate.

[0050] In a possible implementation, the pixel electrode further includes: a first transition portion extending along the first direction, a second transition portion extending along the second direction, and a second overlapping portion;

[0051] One end of the first transition portion is electrically connected to one end of the second sub-pixel electrode facing the fourth sub-pixel electrode, the other end of the first transition portion is electrically connected to one end of the second transition portion; and the other end of the second transition portion is electrically connected to the second overlap portion;

[0052] The second electrode of the second transistor is electrically connected to the second sub-pixel electrode through the second connecting portion.

[0053] In a possible implementation manner, the second transition portion is parallel to an extending direction of the fifth connecting portion.

[0054] In one possible implementation, the control electrode of the third transistor is electrically connected to the auxiliary gate line; at least a portion of the orthographic projection of the third transistor and at least a portion of the orthographic projection of the first transistor on the substrate are located on the same side of the orthographic projection of the fifth connection portion on the substrate.

[0055] In a possible implementation, the fifth connection portion includes: a first sub-connection portion, a second sub-connection portion, and a third sub-connection portion;

[0056] The first sub-connection portion extends along a fourth direction, one end of the first sub-connection portion is electrically connected to the other end of the third connection portion, and the other end of the first sub-connection portion is electrically connected to the second sub-connection portion; the fourth direction intersects the first direction and the second direction;

[0057] The second sub-connection portion extends along the second direction, and the other end of the second sub-connection portion is electrically connected to one end of the third sub-connection portion;

[0058] The third sub-connection portion extends along the fourth direction, and the other end of the third sub-connection portion is electrically connected to the other end of the fourth connection portion.

[0059] In a possible implementation, the pixel electrode further includes: a first transition portion extending along the third direction, a second transition portion extending along the second direction, and a second overlapping portion;

[0060] One end of the first transition portion is electrically connected to one end of the second sub-pixel electrode facing the fourth sub-pixel electrode, the other end of the first transition portion is electrically connected to one end of the second transition portion; and the other end of the second transition portion is electrically connected to the second overlap portion;

[0061] The second electrode of the second transistor is electrically connected to the second sub-pixel electrode through the second connecting portion.

[0062] In a possible implementation manner, the pixel electrode further includes: a third transition portion extending along the first direction, and a third overlapping portion;

[0063] One end of the third transition portion is electrically connected to one end of the third sub-pixel electrode facing the first sub-pixel electrode, and the other end of the third transition portion is electrically connected to the third bridging portion;

[0064] The second electrode of the second transistor is electrically connected to the third sub-pixel electrode through the third connecting portion.

[0065] In a possible implementation manner, a first gap is formed between the third connecting portion and the first pixel electrode; a second gap is formed between the fourth connecting portion and the second pixel electrode;

[0066] A third gap is defined between the first transition portion and the first pixel electrode, and a fourth gap is defined between the third transition portion and the second pixel electrode.

[0067] In a possible implementation, the array substrate further includes: a fourth connecting portion; and the second electrode of the third transistor is electrically connected to the first common trace via the fourth connecting portion.

[0068] In one possible implementation, the fourth overlapping portion has a fourth overlapping portion outer edge along the first direction, the second overlapping portion has a second overlapping portion outer edge extending along the first direction; the first overlapping portion has a first overlapping portion outer edge extending along the second direction, and the third overlapping portion has a third overlapping portion outer edge extending along the second direction;

[0069] The extension line of the outer edge of the fourth overlapping portion coincides with the extension line of the outer edge of the second overlapping portion; the extension line of the outer edge of the first overlapping portion coincides with the extension line of the outer edge of the third overlapping portion.

[0070] In a possible implementation, the second electrode of the first transistor includes: a first transistor first portion extending along the first direction;

[0071] An orthographic projection of the first portion of the first transistor on the substrate and an orthographic projection of the first overlapping portion on the substrate have an overlapping area.

[0072] In a possible implementation, the second electrode of the second transistor includes: a second transistor first portion extending along the first direction, and a second transistor second portion extending along the second direction and electrically connected to one end of the second transistor first portion;

[0073] The orthographic projection of the first portion of the second transistor on the substrate overlaps with the orthographic projection of the third overlapping portion on the substrate; the orthographic projection of the second portion of the second transistor on the substrate overlaps with the orthographic projection of the second overlapping portion on the substrate.

[0074] In a possible implementation, the array substrate further includes: a plurality of transistors; the plurality of transistors electrically connected to the same pixel electrode are all electrically connected to the same data line and the same gate line;

[0075] The second sub-pixel electrode is located on a side of the first sub-pixel electrode away from the electrically connected data line, and the fourth sub-pixel electrode is located on a side of the third sub-pixel electrode away from the electrically connected data line; the first sub-pixel electrode is electrically connected to the third sub-pixel electrode, and the second sub-pixel electrode is electrically connected to the fourth sub-pixel electrode.

[0076] In a possible implementation, the array substrate further includes: a first signal line extending along the second direction; the plurality of transistors include: a first transistor, a second transistor, and a third transistor;

[0077] The control electrode of the first transistor is electrically connected to the gate line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the first sub-pixel electrode;

[0078] The control electrode of the second transistor is electrically connected to the gate line, the first electrode of the second transistor is electrically connected to the data line, and the second electrode of the second transistor is electrically connected to the fourth sub-pixel electrode;

[0079] The control electrode of the third transistor is electrically connected to the gate line, the first electrode of the third transistor is multiplexed with the second electrode of the second transistor, and the second electrode of the third transistor is multiplexed with the first signal line.

[0080] In a possible implementation, the pixel electrode further includes: a connecting portion; the connecting portion extends along the second direction and connects the first sub-pixel electrode and the third sub-pixel electrode.

[0081] In a possible implementation, the pixel electrode further includes: a connecting portion; the connecting portion includes: a first connecting portion, a second connecting portion, and a third connecting portion; the connecting portion connects the second sub-pixel electrode and the fourth sub-pixel electrode;

[0082] The first connecting portion extends along the third direction, one end of the first connecting portion is electrically connected to the second sub-pixel electrode, and the other end of the first connecting portion is electrically connected to one end of the second connecting portion;

[0083] The second connecting portion extends along the second direction, and the other end of the second connecting portion is electrically connected to one end of the third connecting portion;

[0084] The third connecting portion extends along a fourth direction, and the other end of the third connecting portion is electrically connected to the fourth sub-pixel electrode.

[0085] In a possible implementation, the first pixel electrode has a notch on a side facing the gate line; and at least a portion of the orthographic projection of the connecting portion on the substrate is located at the orthographic projection of the notch on the substrate.

[0086] In a possible implementation, the pixel electrode further includes: a first sub-pixel electrode protrusion connected to a side of the first sub-pixel electrode facing the third sub-pixel electrode; the second electrode of the first transistor is electrically connected to the first sub-pixel electrode via the first sub-pixel electrode protrusion;

[0087] The pixel electrode further includes: a fourth sub-pixel electrode protrusion connected to the fourth sub-pixel electrode facing the first sub-pixel electrode; and a second electrode of the second transistor is electrically connected to the fourth sub-pixel electrode through the third sub-pixel electrode protrusion.

[0088] In a possible implementation, the orthographic projections of the first sub-pixel electrode protrusion and the fourth sub-pixel electrode protrusion on the substrate are both located between the orthographic projection of the connecting portion on the substrate and the orthographic projection of the connecting portion on the substrate.

[0089] In a possible implementation, the first sub-pixel electrode convex portion has a first sub-pixel electrode convex portion outer edge extending along the second direction; and an extension line of the first sub-pixel electrode convex portion outer edge at least partially overlaps with the fourth sub-pixel electrode convex portion.

[0090] In a possible implementation, the array substrate further includes: a first common wiring located on one side of the gate line and extending along the first direction; the first common wiring is disconnected at a position where it intersects with the data line.

[0091] In a possible implementation, the array substrate further includes: a second common wiring group electrically connected to the first common wiring and extending toward a side away from the gate line, the second common wiring group including: two second common wirings;

[0092] The orthographic projection of the data line on the substrate and the gap between two second common lines of the same second common line group on the substrate have an overlapping area.

[0093] In a possible implementation, the array substrate further includes: a third common wiring located on the other side of the gate line and extending along the first direction, and a fourth common wiring group connected to the third common wiring and extending away from the gate line;

[0094] The third common routing line is disconnected at a position where it intersects with the data line; the fourth common routing line group includes: two fourth common routing lines; the orthographic projection of the data line on the substrate and the gap between the two fourth common routing lines of the same fourth common routing line group have an overlapping area on the orthographic projection of the substrate.

[0095] In a possible implementation, the array substrate further includes: a fifth common line extending along the first direction and electrically connected to the second common line, wherein the orthographic projection of the fifth common line on the substrate passes through a central area of ​​the orthographic projection of the second pixel electrode on the substrate.

[0096] In a possible embodiment, the array substrate further includes: a sixth common line extending along the first direction and electrically connected to the fourth common line, wherein the orthographic projection of the sixth common line passes through the central area of ​​the orthographic projection of the first pixel electrode on the substrate.

[0097] In a possible implementation, the first sub-pixel electrode and the second sub-pixel electrode each include: a first sub-electrode portion distributed along the second direction, and a second sub-electrode portion; the third sub-pixel electrode and the fourth sub-pixel electrode each include: a third sub-electrode portion distributed along the second direction, and a fourth sub-electrode portion;

[0098] The first sub-electrode portion, the second sub-electrode portion, the third sub-electrode portion, and the fourth sub-electrode portion all have multiple slits; and the extension direction of the slits of the first sub-electrode portion is the same as the extension direction of the slits of the fourth sub-electrode portion; the extension direction of the slits of the second sub-electrode portion is the same as the extension direction of the slits of the third sub-electrode portion.

[0099] In a possible implementation manner, the length of the slit perpendicular to the extending direction may be 2 μm to 4 μm.

[0100] In a possible implementation, the orthographic projection shapes of the first sub-pixel electrode, the second sub-pixel electrode, the third sub-pixel electrode, and the fourth sub-pixel electrode on the substrate are all rectangular.

[0101] In a possible implementation manner, the orthographic projection shapes of the first sub-electrode portion, the second sub-electrode portion, the third sub-electrode portion, and the fourth sub-electrode portion on the substrate are all trapezoidal;

[0102] In the first sub-pixel electrode and the fourth sub-pixel electrode, the trapezoidal first sub-electrode portion and the trapezoidal second sub-electrode portion are arranged opposite to each other with their top sides; in the second sub-pixel electrode and the third sub-pixel electrode, the trapezoidal first sub-electrode portion and the trapezoidal second sub-electrode portion are arranged opposite to each other with their bottom sides.

[0103] In a possible implementation manner, the orthographic projection shapes of the first sub-electrode portion, the second sub-electrode portion, the third sub-electrode portion, and the fourth sub-electrode portion on the substrate are all trapezoidal;

[0104] In the first sub-pixel electrode and the fourth sub-pixel electrode, the trapezoidal first sub-electrode portion and the trapezoidal second sub-electrode portion are arranged opposite to each other with their bottom sides; in the second sub-pixel electrode and the third sub-pixel electrode, the trapezoidal first sub-electrode portion and the trapezoidal second sub-electrode portion are arranged opposite to each other with their top sides.

[0105] In one possible embodiment, the first sub-pixel electrode includes: a first main portion extending and connected along the second direction, a second main portion, and a first side portion extending along the first direction; a plurality of first branches extending from the first main portion and the first side portion along a fourth direction; and a plurality of second branches extending from the second main portion and the first side portion along a fifth direction; the second sub-pixel electrode includes: a third main portion extending and connected along the second direction, a fourth main portion, a fifth main portion connected to one end of the third main portion and extending along the first direction, a sixth main portion connected to one end of the fourth main portion and extending along the first direction; a plurality of third branches extending from the third main portion and the fifth main portion along the fourth direction; and a plurality of fourth branches extending from the fourth main portion and the sixth main portion along the fifth direction; the plurality of first branches and the plurality of third branches are interdigitated, and the plurality of second branches and the plurality of fourth branches are interdigitated.

[0106] The third sub-pixel electrode includes: a seventh main portion extending and connected along the second direction, an eighth main portion, a ninth main portion connected to one end of the seventh main portion and extending along the first direction, a tenth main portion connected to one end of the eighth main portion and extending along the first direction, a plurality of fifth branches extending from the seventh main portion and the ninth main portion along the fourth direction, and a plurality of sixth branches extending from the eighth main portion and the tenth main portion along the fifth direction; the fourth sub-pixel electrode includes: an eleventh main portion extending and connected along the second direction, a twelfth main portion, and a second side portion extending along the first direction, a plurality of seventh branches extending from the eleventh main portion and the second side portion along the fourth direction, and a plurality of eighth branches extending from the twelfth main portion and the second side portion along the fifth direction; the plurality of fifth branches are interdigitated with the plurality of seventh branches, and the plurality of sixth branches are interdigitated with the plurality of eighth branches.

[0107] In a possible implementation, the array substrate further includes: a first conductive layer located on a side of the pixel electrode facing the substrate; the first conductive layer has a first hollow, a second hollow, a third hollow, and a fourth hollow;

[0108] The first hollow overlaps with at least a portion of the orthographic projection of the first sub-pixel electrode on the substrate in at least a portion of the orthographic projection of the substrate; the second hollow overlaps with at least a portion of the orthographic projection of the substrate in at least a portion of the orthographic projection of the substrate in at least a portion of the orthographic projection of the second sub-pixel electrode on the substrate; the third hollow overlaps with at least a portion of the orthographic projection of the substrate in at least a portion of the orthographic projection of the substrate in at least a portion of the orthographic projection of the third sub-pixel electrode on the substrate; the fourth hollow overlaps with at least a portion of the orthographic projection of the substrate in at least a portion of the orthographic projection of the substrate in at least a portion of the orthographic projection of the fourth sub-pixel electrode on the substrate.

[0109] An embodiment of the present disclosure further provides a display panel, which includes: the array substrate provided in the embodiment of the present disclosure, and also includes an opposite substrate arranged opposite to the array substrate, wherein the opposite substrate is provided with a common electrode layer.

[0110] In a possible implementation, the display panel further includes a liquid crystal layer located between the array substrate and the counter substrate;

[0111] The liquid crystal layer includes: a plurality of liquid crystal sections, at least one of the plurality of liquid crystal sections includes: a first sub-liquid crystal section, a second sub-liquid crystal section, a third sub-liquid crystal section, and a fourth sub-liquid crystal section; an orthographic projection of the liquid crystal section on the substrate overlaps with an orthographic projection of the pixel electrode on the substrate; an orthographic projection of the first sub-liquid crystal section on the substrate overlaps with an orthographic projection of the first sub-electrode section on the substrate; an orthographic projection of the second sub-liquid crystal section on the substrate overlaps with an orthographic projection of the second sub-electrode section on the substrate; an orthographic projection of the third sub-liquid crystal section on the substrate overlaps with an orthographic projection of the third sub-electrode section on the substrate; and an orthographic projection of the fourth sub-liquid crystal section on the substrate overlaps with an orthographic projection of the fourth sub-electrode section on the substrate;

[0112] An initial alignment direction of the first sub-liquid crystal section, an initial alignment direction of the second sub-liquid crystal section, an initial alignment direction of the third sub-liquid crystal section, and an initial alignment direction of the fourth sub-liquid crystal section are different from each other.

[0113] In a possible embodiment, the angle between the initial alignment direction of the first sub-liquid crystal portion and the first direction is in the range of 210° to 240°; the angle between the initial alignment direction of the second sub-liquid crystal portion and the first direction is in the range of 120° to 150°; the angle between the initial alignment direction of the third sub-liquid crystal portion and the first direction is in the range of 300° to 330°; and the angle between the initial alignment direction of the fourth sub-liquid crystal portion and the first direction is in the range of 30° to 60°.

[0114] In a possible implementation, the alignment direction of at least part of the liquid crystal at the junction of the first sub-liquid crystal portion and the second sub-liquid crystal portion is opposite to the alignment direction of at least part of the liquid crystal at the junction of the third sub-liquid crystal portion and the fourth sub-liquid crystal portion.

[0115] An embodiment of the present disclosure further provides a display device, which includes the display panel provided by the embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0116] FIG1A is a schematic top view of an array substrate according to an embodiment of the present disclosure;

[0117] FIG1B is an enlarged schematic diagram of the dotted line frame S1 in FIG1A ;

[0118] FIG1C is a schematic diagram of a single film layer of the gate line layer in FIG1A ;

[0119] FIG1D is a schematic diagram of a single film layer of the active layer in FIG1A ;

[0120] FIG1E is a schematic diagram of a single film layer of the data line in FIG1A ;

[0121] FIG1F is a schematic diagram of a single film layer of the first insulating layer in FIG1A ;

[0122] FIG1G is a schematic diagram of a single film layer of the pixel electrode in FIG1A ;

[0123] FIG1H is a schematic diagram of light effect simulation corresponding to FIG1A ;

[0124] FIG2A is a second schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0125] FIG2B is an enlarged schematic diagram of the dotted line frame S1 in FIG2A ;

[0126] FIG2C is a schematic diagram of a single film layer of the gate line layer in FIG2A ;

[0127] FIG2D is a schematic diagram of a single film layer of the active layer in FIG2A;

[0128] FIG2E is a schematic diagram of a single film layer of the data line in FIG2A ;

[0129] FIG2F is a schematic diagram of a single film layer of the first insulating layer in FIG2A ;

[0130] FIG2G is a schematic diagram of a single film layer of the pixel electrode in FIG2A ;

[0131] FIG2H is a schematic diagram of light effect simulation corresponding to FIG2A ;

[0132] FIG2I is a schematic cross-sectional view of FIG2B taken along the dotted line EF;

[0133] FIG3A is a third schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0134] FIG3B is an enlarged schematic diagram of the dotted line frame S1 in FIG3A ;

[0135] FIG3C is a schematic diagram of a single film layer of the gate line layer in FIG3A ;

[0136] FIG3D is a schematic diagram of a single film layer of the active layer in FIG3A;

[0137] FIG3E is a schematic diagram of a single film layer of the data line in FIG3A ;

[0138] FIG3F is a schematic diagram of a single film layer of the first insulating layer in FIG3A ;

[0139] FIG3G is a schematic diagram of a single film layer of the pixel electrode in FIG3A ;

[0140] FIG3H is a schematic diagram of light effect simulation corresponding to FIG3A ;

[0141] FIG4A is a fourth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0142] FIG4B is an enlarged schematic diagram of the dotted line frame S1 in FIG4A ;

[0143] FIG4C is a schematic diagram of a single film layer of the gate line layer in FIG4A ;

[0144] FIG4D is a schematic diagram of a single film layer of the active layer in FIG4A;

[0145] FIG4E is a schematic diagram of a single film layer of the data line in FIG4A ;

[0146] FIG4F is a schematic diagram of a single film layer of the first insulating layer in FIG4A ;

[0147] FIG4G is a schematic diagram of a single film layer of the pixel electrode in FIG4A ;

[0148] FIG4H is a schematic diagram of light effect simulation corresponding to FIG4A ;

[0149] FIG5A is a fifth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0150] FIG5B is an enlarged schematic diagram of the dotted line frame S1 in FIG5A ;

[0151] FIG5C is a schematic diagram of a single film layer of the gate line layer in FIG5A ;

[0152] FIG5D is a schematic diagram of a single film layer of the active layer in FIG5A;

[0153] FIG5E is a schematic diagram of a single film layer of the data line in FIG5A ;

[0154] FIG5F is a schematic diagram of a single film layer of the first insulating layer in FIG5A ;

[0155] FIG5G is a schematic diagram of a single film layer of the pixel electrode in FIG5A ;

[0156] FIG5H is a schematic diagram of light effect simulation corresponding to FIG5A ;

[0157] FIG6A is a sixth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0158] FIG6B is an enlarged schematic diagram of the dotted line frame S1 in FIG6A ;

[0159] FIG6C is a schematic diagram of a single film layer of the gate line layer in FIG6A;

[0160] FIG6D is a schematic diagram of a single film layer of the active layer in FIG6A;

[0161] FIG6E is a schematic diagram of a single film layer of the data line in FIG6A ;

[0162] FIG6F is a schematic diagram of a single film layer of the first insulating layer in FIG6A ;

[0163] FIG6G is a schematic diagram of a single film layer of the first conductive layer in FIG6A ;

[0164] FIG6H is a schematic diagram of a single film layer of the second insulating layer in FIG6A ;

[0165] FIG6I is a schematic diagram of a single film layer of the pixel electrode in FIG6A ;

[0166] FIG6J is a schematic diagram of the black matrix corresponding to FIG6A ;

[0167] FIG6K is a schematic diagram of light effect simulation corresponding to FIG6A ;

[0168] FIG7 is a schematic diagram of dark lines in a conventional 8-domain structure;

[0169] FIG8 is a schematic diagram of dark lines of an array substrate provided by an embodiment of the present disclosure;

[0170] FIG9 is a schematic diagram of a sub-pixel equivalent circuit according to an embodiment of the present disclosure;

[0171] FIG10 is a schematic cross-sectional view of a display panel provided by an embodiment of the present disclosure;

[0172] FIG11A is a seventh schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0173] FIG11B is an enlarged schematic diagram of the dotted line frame S1 in FIG11A ;

[0174] FIG11C is a schematic diagram of a single film layer of the gate line layer in FIG11A;

[0175] FIG11D is a schematic diagram of a single film layer of the active layer in FIG11A;

[0176] FIG11E is a schematic diagram of a single film layer of the data line in FIG11A ;

[0177] FIG11F is a schematic diagram of a single film layer of the first insulating layer in FIG11A ;

[0178] FIG11G is a schematic diagram of a single film layer of the pixel electrode in FIG11A ;

[0179] FIG11H is a schematic diagram of the black matrix corresponding to FIG11A ;

[0180] FIG11I is a schematic diagram of light effect simulation corresponding to FIG11A ;

[0181] FIG12 is an equivalent circuit diagram corresponding to FIG11A ;

[0182] FIG13A is an eighth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0183] FIG13B is a schematic diagram of a single film layer of the pixel electrode in FIG13A;

[0184] FIG13C is a schematic diagram of light effect simulation corresponding to FIG13A;

[0185] FIG14A is a ninth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0186] FIG14B is a schematic diagram of a single film layer of the pixel electrode in FIG14A;

[0187] FIG14C is a schematic diagram of light effect simulation corresponding to FIG14A;

[0188] FIG15A is a tenth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0189] FIG15B is a schematic diagram of a single film layer of the pixel electrode in FIG15A;

[0190] FIG15C is a schematic diagram of light effect simulation corresponding to FIG15A;

[0191] FIG16A is an eleventh schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0192] FIG16B is an enlarged schematic diagram of the dotted line frame S1 in FIG16A ;

[0193] FIG16C is a schematic diagram of a single film layer of the gate line layer in FIG16A;

[0194] FIG16D is a schematic diagram of a single film layer of the active layer in FIG16A;

[0195] FIG16E is a schematic diagram of a single film layer of the data line in FIG16A;

[0196] FIG16F is a schematic diagram of a single film layer of the first insulating layer in FIG16A;

[0197] FIG16G is a schematic diagram of a single film layer of the pixel electrode in FIG16A ;

[0198] FIG16H is a schematic diagram of the black matrix corresponding to FIG16A ;

[0199] FIG16I is a schematic diagram of light effect simulation corresponding to FIG16A ;

[0200] FIG17A is a twelfth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0201] FIG17B is a schematic diagram of a single film layer of the pixel electrode in FIG17A;

[0202] FIG17C is a schematic diagram of light effect simulation corresponding to FIG17A;

[0203] FIG18A is a thirteenth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0204] FIG18B is a schematic diagram of a single film layer of the pixel electrode in FIG18A ;

[0205] FIG18C is a schematic diagram of light effect simulation corresponding to FIG18A ;

[0206] FIG19A is a fourteenth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0207] FIG19B is a schematic diagram of a single film layer of the pixel electrode in FIG19A ;

[0208] FIG19C is a schematic diagram of light effect simulation corresponding to FIG19A ;

[0209] FIG20A is a fifteenth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0210] FIG20B is an enlarged schematic diagram of the dotted line frame S1 in FIG20A ;

[0211] FIG20C is a schematic diagram of a single film layer of the gate line layer in FIG20A;

[0212] FIG20D is a schematic diagram of a single film layer of the active layer in FIG20A;

[0213] FIG20E is a schematic diagram of a single film layer of the data line in FIG20A;

[0214] FIG20F is a schematic diagram of a single film layer of the first insulating layer in FIG20A;

[0215] FIG20G is a schematic diagram of a single film layer of the pixel electrode in FIG20A ;

[0216] FIG20H is a schematic diagram of a single film layer of the second insulating layer in FIG20A;

[0217] FIG20I is a schematic diagram of a single film layer of the first conductive layer in FIG20A ;

[0218] Schematic diagram of the black matrix corresponding to FIG20J ;

[0219] FIG20K is a schematic diagram of light effect simulation corresponding to FIG20A ;

[0220] FIG21A is a sixteenth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0221] FIG21B is a schematic diagram of a single film layer of the pixel electrode in FIG21A ;

[0222] FIG21C is a schematic diagram of light effect simulation corresponding to FIG21A ;

[0223] FIG22A is a seventeenth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0224] FIG22B is a schematic diagram of a single film layer of the pixel electrode in FIG22A ;

[0225] FIG22C is a schematic diagram of light effect simulation corresponding to FIG22A ;

[0226] FIG23A is an eighteenth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0227] FIG23B is a schematic diagram of a single film layer of the pixel electrode in FIG23A ;

[0228] FIG. 23C is a schematic diagram of light effect simulation corresponding to FIG. 23A . DETAILED DESCRIPTION

[0229] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure. The implementation methods can be implemented in multiple different forms. Ordinary technicians in the relevant technical field can easily understand the fact that the method and content can be transformed into one or more forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following implementation methods. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other in any way.

[0230] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0231] As used herein, "about" or "approximately the same" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "approximately the same" may mean that the difference relative to the stated value is within one or more standard deviations, or within ±30%, 20%, 10%, 5%. In this specification, "approximately the same" may refer to values ​​that are within 10% of each other.

[0232] In the accompanying drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments. As such, deviations from the shapes of the figures are to be expected as a result of, for example, manufacturing techniques and / or tolerances. Thus, the embodiments described herein should not be construed as limited to the specific shapes of the regions as shown herein, but rather include deviations in shape that result from, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. Furthermore, sharp corners illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the claims.

[0233] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which the constituent elements are described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0234] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the specific circumstances.

[0235] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with one or more functions.

[0236] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode (gate), a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0237] The gate of a transistor can also be referred to as the control electrode. The functions of the "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, the terms "source electrode" and "drain electrode" may be interchanged.

[0238] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus includes a state where the angle is greater than 85° and less than 95°.

[0239] In this specification, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0240] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0241] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0242] High-resolution products, such as 8K and 16K display products, are the main direction of subsequent products. However, the current 8K products using vertical alignment liquid crystal (VA) have problems with low transmittance and poor color deviation.

[0243] In view of this, referring to Figures 1A-1G, 2A-2G, 3A-3G, 4A-4G, 5A-5G, 6A-6G, 11A-11I, 13A-13C, 14A-14C, 15A-15C, 16A-16I, 17A-17C, 18A-18C, 19A-19C, 20A-20K, 21A-21C, 22A-22C, and 23A-23C, an embodiment of the present disclosure provides an array substrate, comprising:

[0244] Substrate 1;

[0245] A plurality of gate lines 2 are located on one side of the substrate 1 and extend along a first direction X;

[0246] The plurality of data lines 3 extend along a second direction Y; specifically, the second direction Y may intersect the first direction X; specifically, the second direction Y may be perpendicular to the first direction X; specifically, the second direction Y may be a direction of pixel electrode columns, and the first direction X may be a direction of pixel electrode rows;

[0247] A plurality of pixel electrodes 4, the pixel electrodes 4 including: a first pixel electrode 41 located on one side of the gate line 2, and a second pixel electrode 42 located on the other side of the gate line 2; the first pixel electrode 41 including: a first sub-pixel electrode 411 and a second sub-pixel electrode 412 distributed along the first direction X; the second pixel electrode 42 including: a third sub-pixel electrode 421 and a fourth sub-pixel electrode 422 distributed along the first direction X; specifically, for example, with reference to FIG1G , the pixel electrode 4 includes the first pixel electrode 41 located on the upper side of the gate line 2, and the second pixel electrode 42 located on the lower side of the gate line 2, wherein the first pixel electrode 41 includes the first sub-pixel electrode 411 located on the left side, and the second sub-pixel electrode 412 located on the right side; the second pixel electrode 42 includes the third sub-pixel electrode 421 located on the left side, and the fourth sub-pixel electrode 422 located on the right side;

[0248] One of the first subpixel electrode 411 and the second subpixel electrode 412 is electrically connected to one of the third subpixel electrode 421 and the fourth subpixel electrode 422. The brightness of the two electrically connected electrodes is different from the brightness of the other two electrodes. Specifically, for example, the first subpixel electrode 411 may be electrically connected to the third subpixel electrode 421, and the second subpixel electrode 412 may be electrically connected to the fourth subpixel electrode 422; or the first subpixel electrode 411 may be electrically connected to the fourth subpixel electrode 422, and the second subpixel electrode 412 may be electrically connected to the third subpixel electrode 422.

[0249] In the embodiment of the present disclosure, the pixel electrode 4 includes: a first pixel electrode 41 located on one side of the gate line 2, and a second pixel electrode 42 located on the other side of the gate line 2; the first pixel electrode 41 includes: a first sub-pixel electrode 411 and a second sub-pixel electrode 412 distributed along the first direction X; the second pixel electrode 42 includes: a third sub-pixel electrode 421 and a fourth sub-pixel electrode 422 distributed along the first direction X; and one of the first sub-pixel electrode 411 and the second sub-pixel electrode 412 is electrically connected to one of the third sub-pixel electrode 421 and the fourth sub-pixel electrode 422. That is, a pixel electrode 4 is divided into upper and lower parts, the upper half is further divided into left and right parts, and the lower half is also divided into left and right parts. The brightness of the two electrically connected parts is different from the brightness of the other two parts, and an 8-domain distribution can be formed in a sub-pixel. Compared with a conventional 8-domain structure, the array substrate provided by the embodiment of the present disclosure has fewer dark lines, better transmittance, and can compensate for the viewing angles, thereby improving the color deviation of the left and right viewing angles.

[0250] Specifically, as shown in Figures 7 and 8, Figure 7 shows the dark lines of the conventional 8-domain structure. It can be seen that there are more dark lines, which have a great impact on the transmittance. Figure 8 shows the dark lines of the array substrate provided by the embodiment of the present disclosure. It can be clearly seen that the number of dark lines is significantly reduced. In comparison, the 8-domain array substrate structure provided by the disclosed embodiment has obvious advantages in improving the transmittance. Moreover, the 8-domain structure shown in Figure 7 does not have a good liquid crystal angle that can compensate for the left and right viewing angles. The horizontal liquid crystals are all facing right, and there is no horizontal liquid crystal facing left. However, the array substrate provided by the embodiment of the present disclosure shown in Figure 8 can make the horizontal liquid crystals in the left and right directions compensate for each other's viewing angles, thereby improving the color deviation of the left and right viewing angles.

[0251] As shown in Figures 1A, 1G and 8, in a pixel electrode 4, the first pixel electrode 41 is a U-shaped slit, and the second pixel electrode 42 is an inverted U-shaped Slit; in conjunction with the extension direction of the slit F, the first pixel electrode 41 can be set with two liquid crystal alignment directions, which can be 225° and 135° respectively; the second pixel electrode 42 can be set with two liquid crystal alignment directions, which can be 315° and 45° respectively; and combined with the left and right divided light and dark areas, an alignment mode of 8 domains in a sub-pixel can be formed when using SUVA technology.

[0252] It should be noted that in the disclosed embodiment, the electrical connection between the first sub-pixel electrode 411 and the second sub-pixel electrode 412 and the third sub-pixel electrode 421 and the fourth sub-pixel electrode 422 may be achieved by electrically connecting the first sub-pixel electrode 411 and the second sub-pixel electrode 412 to the third sub-pixel electrode 421 and the fourth sub-pixel electrode 422 at the same layer as the pixel electrode 4, while the other two sub-pixel electrodes may not be connected at the same layer as the pixel electrode 4, but may be electrically connected through other structures, for example, both being connected to the same transistor drain. Specifically, for example, the first sub-pixel electrode 411 and the third sub-pixel electrode 421 may be electrically connected at the same layer as the pixel electrode 4, and both exhibit one brightness; while the second sub-pixel electrode 412 and the third sub-pixel electrode 421 may not be electrically connected at the same layer as the pixel electrode 4, but may be electrically connected to the same transistor drain (i.e., through the drain layer), and both exhibit a different brightness. The brightness of the two sub-pixel electrodes connected at the same layer as the pixel electrode 4 may be different from the brightness of the other two sub-pixel electrodes.

[0253] It can be understood that the brightness of the two connected together is different from the brightness of the other two, and refers to the brightness comparison within a sub-pixel when the display panel is powered on and lit.

[0254] In a possible embodiment, in combination with Figures 1A-1G, 2A-2G, 3A-3G, 4A-4G, 5A-5G, and 6A-6G, the array substrate further includes: a plurality of transistors T; a plurality of transistors electrically connected to the same pixel electrode 4, all electrically connected to the same data line 3 and the same gate line 2. For example, as shown in Figure 1B, there are three transistors electrically connected to the same pixel electrode 4, namely a first transistor T1, a second transistor T2, and a third transistor T3, and the three transistors are all electrically connected to the same data line 3 and the same gate line 2; the second sub-pixel electrode 412 is located on a side of the first sub-pixel electrode 411 away from the electrically connected data line 3, and the fourth sub-pixel electrode 422 is located on a side of the third sub-pixel electrode 421 away from the electrically connected data line 3; the first sub-pixel electrode 411 is electrically connected to the fourth sub-pixel electrode 422. Specifically, the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422 are electrically connected at the same layer as the pixel electrode 4, and the second sub-pixel electrode 412 and the third sub-pixel electrode 421 are both electrically connected to the second electrode TC of the second transistor T2. In the disclosed embodiment, the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422 are electrically connected at the pixel electrode 4, and the second sub-pixel electrode 412 and the third sub-pixel electrode 421 are electrically connected. That is, the four portions of the pixel electrode 4 are cross-connected in pairs, which facilitates the formation of an eight-domain distribution within the same pixel electrode 4.

[0255] It should be noted that the multiple transistors electrically connected to the same pixel electrode 4 may refer to being electrically connected to the same pixel electrode 4 directly or indirectly. For example, the first transistor T1 and the second transistor T2 may be directly electrically connected to the pixel electrode 4, and the third transistor T3, since it is electrically connected to the second transistor T2, may also be considered to be electrically connected to the pixel electrode 4. Specifically, the multiple transistors electrically connected to the same pixel electrode 4 may also be transistors that drive the same pixel electrode 4.

[0256] In a possible embodiment, as shown in FIG. 1A to FIG. 1G , the array substrate further includes: a first signal line 5 extending along a second direction Y; the plurality of transistors T include: a first transistor T1 , a second transistor T2 , and a third transistor T3 ;

[0257] The control electrode TA of the first transistor T1 is electrically connected to the gate line 2, the first electrode TB of the first transistor T1 is electrically connected to the data line 3, and the second electrode TC of the first transistor T1 is electrically connected to the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422. Specifically, the second electrode TC of the first transistor T1 can be electrically connected to the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422 through the first via hole K1.

[0258] The control electrode TA of the second transistor T2 is electrically connected to the gate line 2, the first electrode TB of the second transistor T2 is electrically connected to the data line 3, and the second electrode TC of the second transistor T2 is electrically connected to the second sub-pixel electrode 412 and the third sub-pixel electrode 421. Specifically, the second electrode TC of the second transistor T2 can be electrically connected to the third sub-pixel electrode 421 through a second via hole K2; the second electrode TC of the second transistor T2 can be electrically connected to the second sub-pixel electrode 412 through a third via hole K3.

[0259] The control electrode TA of the third transistor T3 is electrically connected to the gate line 2 , the first electrode TB of the third transistor T3 multiplexes the second electrode TC of the second transistor T2 , and the second electrode TC of the third transistor T3 multiplexes the first signal line 5 .

[0260] Figure 9 may be an equivalent circuit diagram corresponding to Figure 1B, wherein S is the data line on the left side of the pixel, that is, the signal line for transmitting the data signal of the current sub-pixel, that is, the data line electrically connected to the current sub-pixel, S is the data line on the right side of the pixel, and is also the data line of the horizontally adjacent pixel. The pixel circuit may include: a first transistor T1, a second transistor T2, a third transistor T3, a first capacitor Cpd_bright, a second capacitor Cgp_bright, a third capacitor Cst_bright, a fourth capacitor Clc_bright, a fifth capacitor Cpp_bright, a sixth capacitor Cpd_bright, a seventh capacitor Cpd_dark, an eighth capacitor Cgp_dark, a ninth capacitor Cst_dark, a tenth capacitor Clc_dark, an eleventh capacitor Cpd_bright, a twelfth capacitor CgD, and a thirteenth capacitor CcD; wherein a first capacitor Cpd_bright is formed between the first pixel electrode 41 and the data line 3, a second capacitor Cgp_bright is formed between the first pixel electrode 41 and the gate line 2, and a first capacitor Cpd_bright is formed between the first pixel electrode 41 and the third common wiring 23. A third capacitor Cst_dark can be formed in the overlapping area, a fourth capacitor Clc_dark can be formed between the first pixel electrode 41 and the common electrode on the opposite substrate side, a fifth capacitor Cpp_dark can be formed between the first pixel electrode 41 and the second pixel electrode 42, and a sixth capacitor Cpd_dark can be formed between the first pixel electrode 41 and the adjacent data line 3; a seventh capacitor Cpd_dark is formed between the second pixel electrode 42 and the data line 3, an eighth capacitor Cgp_dark is formed between the second pixel electrode 42 and the gate line 2, a ninth capacitor Cst_dark can be formed in the overlapping area of ​​the second pixel electrode 42 and the first common wiring 21, a tenth capacitor Clc_dark can be formed between the second pixel electrode 42 and the common electrode on the opposite substrate side, an eleventh capacitor Cpd_dark can be formed between the second pixel electrode 42 and the adjacent data line 3, a twelfth capacitor CgD can be formed in the overlapping area of ​​the gate line 2 and the first signal line 5, and a thirteenth capacitor CcD can be formed in the overlapping area of ​​the first signal line 5 and the first common wiring 21.

[0261] Specifically, in combination with Figure 1A and Figure 9, since the third transistor T3 is connected to the second transistor T2, the voltage loaded on the second sub-pixel electrode 412 and the third sub-pixel electrode 421 will be partially distributed to the twelfth capacitor CgD (and / or the thirteenth capacitor CcD, and / or the first signal line 5) through the third transistor T3, so that the voltage obtained by the second sub-pixel electrode 412 and the third sub-pixel electrode 421 is lower than the voltage obtained by the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422, and thus the luminous brightness of the second sub-pixel electrode 412 and the third sub-pixel electrode 421 is lower than the luminous brightness of the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422, thereby forming a display effect with different brightness and darkness in the sub-pixels.

[0262] In a possible implementation, the voltage applied to the first signal line 5 may be consistent with the voltage applied to the common electrode layer of the opposite substrate, that is, a common voltage is applied.

[0263] In one possible embodiment, as shown in conjunction with Figures 1A-1G , the pixel electrode 4 further includes: a first subpixel electrode protrusion 41A connected to the side of the first subpixel electrode 411 facing the third subpixel electrode 421; and the second electrode TB of the first transistor T1 is electrically connected to the first subpixel electrode 411 via the first subpixel electrode protrusion 41A. In the disclosed embodiment, the first subpixel electrode 411 is further provided with the side facing the third subpixel electrode 421 of the first subpixel electrode 41A. The wiring arrangement for the connection with the second electrode TB of the first transistor T1 is simple and regular, facilitating simple wiring between the first pixel electrode 41 and the second pixel electrode 42, and avoiding the risk of short circuit defects that can occur during etching and patterning when multiple patterns are arranged in a complex layout.

[0264] In a possible embodiment, in combination with Figures 1A to 1G, the pixel electrode 4 also includes: a connecting portion 44 connecting the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422; the connecting portion 44 includes: a first connecting portion 441 extending along the second direction Y, and a second connecting portion 442 extending along the third direction Z; one end of the first connecting portion 441 is electrically connected to one end of the first sub-pixel electrode 411 facing the third sub-pixel electrode 421, and the other end is electrically connected to the second connecting portion 442, and the other end of the second connecting portion 422 is electrically connected to one end of the fourth sub-pixel electrode 422 facing the second sub-pixel electrode 412.

[0265] In the embodiment of the present disclosure, the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422 are directly electrically connected to each other in the layer where the pixel electrode 4 is located through the connecting portion 44, and the connecting portion 44 includes: a first connecting portion 441 extending along the second direction Y, and a second connecting portion 442 extending along the third direction Z. The wiring method of the connecting portion 44 is simple and regular, which is conducive to simple wiring between the gap between the first pixel electrode 41 and the second pixel electrode 42, and avoids the risk of short circuit defects that may occur during etching patterning when the layout of multiple patterns is more complex.

[0266] In a possible embodiment, the third direction Z intersects with the first direction X and the second direction Y; the third direction Z can form an angle of 0 to 90° with the second direction Y, specifically, the third direction Z can form an angle of 30° to 60° with the second direction Y, specifically, the third direction Z can form an angle of 45° with the second direction Y.

[0267] In one possible embodiment, as shown in conjunction with Figures 1A-1G , the pixel electrode 4 further includes a third subpixel electrode protrusion 43A connected to the side of the third subpixel electrode 421 facing the first subpixel electrode 411. The second electrode TC of the second transistor T2 is electrically connected to the third subpixel electrode 421 via the third subpixel electrode protrusion 43A. In the disclosed embodiment, the third subpixel electrode 421 is further provided with the side facing the first subpixel electrode 411. The third subpixel electrode protrusion 43A is connected to the second electrode TC of the second transistor T2 in a simple and regular wiring manner, which facilitates simple wiring between the first pixel electrode 41 and the second pixel electrode 42, and avoids the risk of short circuit defects that may occur during etching and patterning when multiple patterns are arranged in a complex layout.

[0268] In a possible embodiment, in combination with Figures 1A to 1G, the pixel electrode 4 also includes: a second sub-pixel electrode extension portion 42B extending along the second direction Y, and a second sub-pixel electrode convex portion 42A; one end of the second sub-pixel electrode extension portion 42B is electrically connected to one end of the second sub-pixel electrode 412 on the side facing the fourth sub-pixel electrode 422, and the other end is electrically connected to the second sub-pixel electrode convex portion 42A; the second pole TC of the second transistor T2 is electrically connected to the second sub-pixel electrode 412 through the second sub-pixel electrode convex portion 42A. In the embodiment of the present disclosure, a second sub-pixel electrode extension portion 42B extending along the second direction Y and a second sub-pixel electrode protrusion 42A are further provided on the side of the second sub-pixel electrode 412 facing the fourth sub-pixel electrode 422. This facilitates the electrical connection of the second sub-pixel electrode 412 and the third sub-pixel electrode 421 to the second electrode TC of the second transistor T2, and the wiring method for connecting the second sub-pixel electrode 412 and the second electrode TC of the second transistor T2 is simple and regular, which facilitates the simple wiring between the gap between the first pixel electrode 41 and the second pixel electrode 42, and avoids the risk of short circuit defects that may occur during etching patterning when the layout of multiple patterns is more complex.

[0269] In one possible embodiment, as shown in Figures 1A to 1G, the extension direction of the second sub-pixel electrode extension portion 42B is parallel to the extension direction of the first connecting portion 441, which is conducive to simple wiring between the first pixel electrode 41 and the second pixel electrode 42, and avoids the risk of short circuit defects during etching patterning when the layout of multiple patterns is more complex.

[0270] In one possible embodiment, as shown in conjunction with FIG. 1A to FIG. 1G , the second sub-pixel electrode protrusion 42A has a second sub-pixel electrode protrusion outer edge f1 that is away from the second sub-pixel electrode 412 and extends along the first direction X; the third sub-pixel electrode protrusion 43A has a third sub-pixel electrode protrusion outer edge f2 that is away from the third sub-pixel electrode 421 and extends along the first direction X.

[0271] The extension line of the outer edge f1 of the second subpixel electrode's protrusion coincides with the extension line of the outer edge f2 of the third subpixel electrode's protrusion; alternatively, the extension line of the outer edge f1 of the second subpixel electrode's protrusion at least partially overlaps with the third subpixel electrode's protrusion 43A; alternatively, the extension line of the outer edge f2 of the third subpixel electrode's protrusion at least partially overlaps with the second subpixel electrode's protrusion 42A. This facilitates the electrical connection of both the second subpixel electrode 412 and the third subpixel electrode 421 to the second electrode TC of the second transistor T2, simplifies the wiring between the first pixel electrode 41 and the second pixel electrode 42, and avoids the risk of short circuits during etching and patterning when multiple patterns are complex.

[0272] In one possible embodiment, as shown in conjunction with FIG. 1A to FIG. 1G , a connecting line e1 between the center of the third sub-pixel electrode protrusion 43A and the center of the first sub-pixel electrode protrusion 41A is parallel to the second direction Y. This facilitates simplification of the pattern between the first pixel electrode 41 and the second pixel electrode 42 , and avoids the risk of short circuit defects that may occur during etching and patterning when multiple patterns are arranged in a complex manner.

[0273] In one possible embodiment, in combination with Figures 1A to 1G, the array substrate includes: a first axis f7 located between the first pixel electrode 41 and the second pixel electrode 42 and extending along the first direction X, and a third sub-pixel electrode protrusion 43A, which can be symmetrical with the first sub-pixel electrode protrusion 41A about the first axis f7.

[0274] In one possible embodiment, in combination with Figures 1A to 1G, the orthographic projection shape of the first sub-pixel electrode protrusion 41A on the substrate 1 can be a trapezoid, and the orthographic projection shape of the third sub-pixel electrode protrusion 43A on the substrate 1 can be a trapezoid; in one possible embodiment, the orthographic projection shape of the first sub-pixel electrode protrusion 41A on the substrate 1 can also be a rectangle, a semicircle or a semi-ellipse; the orthographic projection shape of the third sub-pixel electrode protrusion 43A on the substrate 1 can also be a rectangle, a semicircle or a semi-ellipse.

[0275] In one possible embodiment, as shown in conjunction with Figures 1A-1G , the second electrode TC of the first transistor T1 includes a first transistor first portion T1C1 extending along a first direction X; the orthographic projection of the first transistor first portion T1C1 on the substrate 1 overlaps with the orthographic projection of the first sub-pixel electrode protrusion 41A on the substrate 1. This facilitates electrical connection between the first transistor first portion T1C1 and the first sub-pixel electrode protrusion 41A via the first via K1.

[0276] In one possible embodiment, as shown in Figures 1A-1G, the second electrode TC of the first transistor T1 includes: a first transistor second portion T1C2 extending along the second direction Y and electrically connected to the first transistor first portion T1C1; specifically, the orthographic projection of the first transistor second portion T1C2 on the substrate 1 may have an overlapping area with the orthographic projection of the active pattern 6 on the substrate 1.

[0277] In one possible embodiment, with reference to Figures 1A to 1G, the second electrode TC of the second transistor T2 includes: a second transistor first portion T2C1 extending along the first direction X, and a second transistor second portion T2C2 extending along the second direction Y and electrically connected to one end of the second transistor first portion T2C1; the orthographic projection of the second transistor first portion T2C1 on the substrate 1 has an overlapping area with the orthographic projection of the third sub-pixel electrode convex portion 43A on the substrate 1, so that the second transistor first portion T2C1 and the third sub-pixel electrode convex portion 43A are electrically connected through the second via K2; the orthographic projection of the second transistor second portion T2C2 on the substrate 1 has an overlapping area with the orthographic projection of the second sub-pixel electrode convex portion 42A on the substrate 1, so that the second transistor second portion T2C2 and the second sub-pixel electrode convex portion 42A are electrically connected through the third via K3.

[0278] In one possible embodiment, as shown in Figures 1A to 1G, the second electrode TC of the second transistor T2 may further include: a second transistor third portion T2C3 electrically connected to the other end of the second transistor first portion T2C1 and extending along the second direction Y. Specifically, the orthographic projection of the second transistor third portion T2C3 on the substrate 1 may have an overlapping area with the orthographic projection of the active pattern 6 on the substrate 1.

[0279] In one possible embodiment, as shown in conjunction with Figures 1A-1G , at least a portion of the orthographic projection of the second portion T2C2 of the second transistor on the substrate 1 overlaps with at least a portion of the orthographic projection of the second sub-pixel electrode extension 42B on the substrate 1. Because the second portion T2C2 of the second transistor overlaps with the gate line 2, a coupling capacitor is formed therebetween. The second sub-pixel electrode extension 42B covers a portion of the second portion T2C2 of the second transistor, thereby shielding a portion of the coupling capacitor between the second portion T2C2 of the second transistor and the gate line 2. Furthermore, at least a portion of the orthographic projection of the second portion T2C2 of the second transistor on the substrate 1 overlaps with at least a portion of the orthographic projection of the second sub-pixel electrode extension 42B on the substrate 1. This facilitates wiring of the array substrate, reduces wiring width, and optimizes wiring layout.

[0280] In a possible implementation manner, the orthographic projection of the second portion T2C2 of the second transistor on the substrate 1 may not overlap with the orthographic projection of the second sub-pixel electrode extension portion 42B on the substrate 1 .

[0281] In one possible implementation, as shown in conjunction with Figures 1A-1G , the first signal line 5 has a recessed portion 50; at least a portion of the orthographic projection of the second portion T2C2 of the second transistor on the substrate 1 is located within the region enclosed by the orthographic projection of the recessed portion 50 on the substrate 1. In the disclosed embodiment, the first signal line 5 has the recessed portion 50. This allows the first signal line 5 and the second electrode TC of the second transistor T2 to be co-located on the same layer while avoiding the second portion T2C2 of the second transistor, thereby preventing a short circuit between the first signal line 5 and the second electrode TC of the second transistor T2.

[0282] In a possible embodiment, in combination with Figures 1A to 1G, the first signal line 5 includes: a first signal portion 51, a second signal portion 52, and a third signal portion 53 distributed in sequence along the second direction Y, and a fourth signal portion 54 extending along the first direction X and connecting the second signal portion 52 and the first signal portion 51, and a fifth signal portion 55 extending along the first direction X and connecting the second signal portion 52 and the third signal portion 53; an extension line of the first signal portion 51 coincides with an extension line of the third signal portion 53; an extension line of the second signal portion 52 does not coincide with an extension line of the first signal portion 51; the second signal portion 52, the fourth signal portion 54, and the fifth signal portion 55 constitute a recessed portion 50, and the fourth signal portion 54 and / or the fifth signal portion 55 at least partially overlap with the pixel electrode 4.

[0283] Specifically, the third signal portion 53 may serve as the second electrode TC of the third transistor T3 , so as to release part of the voltage of the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422 to the first signal line 5 through the third transistor T3 .

[0284] In one possible embodiment, as shown in Figures 1A-1G , the first signal lines 5 are formed on the same layer as the data lines 3. Thus, the first signal lines 5 are formed simultaneously with the data lines 3, thereby simplifying the array substrate manufacturing process and reducing the manufacturing cost of the array substrate while achieving different display effects of light and dark in the same sub-pixel.

[0285] In a possible embodiment, referring to Figures 2A-2G, 3A-3G, 4A-4G, and 5A-5G, the array substrate further includes: a first common trace 21 located on one side of the gate line 2 and extending along the first direction X; the plurality of transistors T include: a first transistor T1 electrically connected to the data line 3, a second transistor T2, and a third transistor T3;

[0286] The control electrode TA of the first transistor T1 is electrically connected to the gate line 2, the first electrode TB of the first transistor T1 is electrically connected to the data line 3, and the second electrode TC of the first transistor T1 is electrically connected to the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422. Specifically, the second electrode TC of the first transistor T1 can be electrically connected to the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422 through the first via hole K1.

[0287] The control electrode TA of the second transistor T2 is electrically connected to the gate line 2, the first electrode TB of the second transistor T2 is electrically connected to the data line 3, and the second electrode TC of the second transistor T2 is electrically connected to the second sub-pixel electrode 412 and the third sub-pixel electrode 421. Specifically, the second electrode TC of the second transistor T2 can be electrically connected to the third sub-pixel electrode 421 through a second via hole K2; the second electrode TC of the second transistor T2 can be electrically connected to the second sub-pixel electrode 412 through a third via hole K3.

[0288] The control electrode TA of the third transistor T3 is electrically connected to the gate line 2 , the first electrode TB of the third transistor T3 is multiplexed with the second electrode TC of the second transistor T2 , and the second electrode TC of the third transistor T3 is electrically connected to the first common wiring 21 .

[0289] In the embodiment of the present disclosure, since the third transistor T3 is connected to the second transistor T2, the voltage applied to the second sub-pixel electrode 412 and the third sub-pixel electrode 421 will be partially distributed to the first common wiring 21 through the third transistor T3, so that the voltage obtained by the second sub-pixel electrode 412 and the third sub-pixel electrode 421 is lower than the voltage obtained by the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422, and thus the luminous brightness of the second sub-pixel electrode 412 and the third sub-pixel electrode 421 is lower than the luminous brightness of the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422, thereby forming a display effect with different brightness and darkness in the sub-pixels.

[0290] In a possible embodiment, referring to Figures 11A-11I, 13A-13C, 14A-14C, and 15A-15C, the first sub-pixel electrode 411 is electrically connected to the fourth sub-pixel electrode 422; the array substrate further includes: a plurality of transistors, a third common line 23 located on one side of the gate line 2 and extending along the first direction X, and an auxiliary gate line 20 located between the gate line 2 and the third common line 23 and extending along the first direction X; the plurality of transistors T include: a first transistor T1, a second transistor T2, and a third transistor T3;

[0291] The control electrode TA of the first transistor T1 is electrically connected to the gate line 2 , the first electrode TB of the first transistor T1 is electrically connected to the data line 3 , and the second electrode TC of the first transistor T1 is electrically connected to the first sub-pixel electrode 411 ;

[0292] The control electrode TA of the second transistor T2 is electrically connected to the gate line 2, the first electrode TB of the second transistor T2 is electrically connected to the data line 3, and the second electrode TC of the second transistor T2 is electrically connected to the second sub-pixel electrode 412 and the third sub-pixel electrode 421; optionally, the first electrode TB of the second transistor T2 can be multiplexed with the first electrode TB of the first transistor T1 and connected to the data line 3;

[0293] The control electrode TA of the third transistor T3 is electrically connected to the auxiliary gate line 20. The first electrode TB of the third transistor T3 reuses the second electrode TC of the first transistor T1. The orthographic projection of the second electrode TC of the third transistor T3 on the substrate 1 has an overlapping area with the orthographic projection of the third common line 23 on the substrate 1.

[0294] Refer to Figure 12, where Figure 12 is an equivalent circuit diagram corresponding to Figure 11A, S is the data line on the left side of the pixel, that is, the signal line for transmitting the data signal of the current sub-pixel, that is, the data line electrically connected to the current sub-pixel, and the pixel circuit may include: a first transistor T1, a second transistor T2, a third transistor T3, a third capacitor Cst_bright, a fourth capacitor Clc_bright, a ninth capacitor Cst_dark, a tenth capacitor Clc_dark, and a fourteenth capacitor Cd; wherein, the overlapping area of ​​the first pixel electrode 41 and the third common wiring 23 can form the third capacitor Cst_bright, the first pixel electrode 41 and the common electrode on the opposite substrate side can form the fourth capacitor Clc_bright, the overlapping area of ​​the second pixel electrode 42 and the first common wiring 21 can form the ninth capacitor Cst_dark, the second pixel electrode 42 and the common electrode on the opposite substrate side can form the tenth capacitor Clc_dark, and the overlapping area of ​​the second electrode TC of the third transistor T3 and the third common wiring 23 can form the fourteenth capacitor Cd.

[0295] Specifically, the array substrate may further include a plurality of cascaded gate driving units, the nth gate line 2 may be electrically connected to the nth-level gate driving unit to transmit the gate signal output by the nth-level gate driving unit, the secondary gate line 22 and the auxiliary gate line 20 may be electrically connected to the n+mth-level gate driving unit, that is, the n+mth-level gate driving unit is electrically connected to the n+mth-row main gate line 2 and also electrically connected to the nth-row auxiliary gate line 20 to provide a gate signal to the n+mth-row gate line 2 and simultaneously provide a gate signal to the nth-row auxiliary gate line 20, so that when the first transistor T1 and the second transistor T2 of the n+mth row are turned on, The third transistor T3 of the nth row is also turned on at the same time, so that the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422 of the nth row are divided by the fourteenth capacitor Cd turned on by the third transistor T3, so that the voltage of the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422 is lower than the voltage of the second sub-pixel electrode 412 and the third sub-pixel electrode 421. Therefore, the luminance of the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422 is lower than the luminance of the second sub-pixel electrode 412 and the third sub-pixel electrode 421. More brightness steps can improve the color cast problem of the liquid crystal display panel.

[0296] Specifically, m≥1; specifically, m=6; for example, when n=1 and m=6, the 7th-level gate driving unit is electrically connected to the 7th-row main gate line 21 and also electrically connected to the 1st-row auxiliary gate line 22, so as to provide a gate signal to the 7th-row main gate line 21 and simultaneously provide a gate signal to the 1st-row auxiliary gate line 22, so as to turn on the first transistor T1 of the 7th row while also turning on the second transistor T2 of the 1st row, so as to reduce the luminous brightness of the second pixel electrode 4200 of the 1st row.

[0297] In one possible embodiment, referring to Figures 2A-2G, 3A-3G, 4A-4G, and 5A-5G, the pixel electrode 4 further includes: a connecting portion 44 connecting the first sub-pixel electrode 412 and the fourth sub-pixel electrode 422, and a first bridging portion PD1 connected to the connecting portion 44; the connecting portion 44 includes: a third connecting portion 443 extending along the first direction X, a fourth connecting portion 444, and a fifth connecting portion 445 extending along the second direction Y;

[0298] One end of the third connecting portion 443 is connected to the first sub-pixel electrode 411, one end of the fourth connecting portion 444 is connected to the fourth sub-pixel electrode 422, one end of the fifth connecting portion 445 is connected to the other end of the third connecting portion 443, and the other end of the fifth connecting portion 445 is connected to the other end of the fourth connecting portion 444. The first bridging portion PD1 is electrically connected to the first connecting portion 441 and is away from the first sub-pixel electrode 411 to which it is connected.

[0299] The second electrode TC of the first transistor T1 is electrically connected to the first sub-pixel electrode 411 and the fourth sub-pixel electrode 421 through the first connecting portion PD1 .

[0300] In the disclosed embodiment, the connecting portion 44 includes: a third connecting portion 443 extending along the first direction X, a fourth connecting portion 444, and a fifth connecting portion 445 extending along the second direction Y. The wiring of the connecting portion 44 is regular, which is conducive to simple wiring between the first pixel electrode 41 and the second pixel electrode 42, and avoids the risk of short circuit defects that may occur during etching patterning when the layout of multiple patterns is complex; moreover, the connecting portion 44 is also connected to the first overlapping portion PD1, so as to facilitate the electrical connection between the first overlapping portion PD1 and the second electrode TC of the first transistor T1 through the first via K1.

[0301] In a possible embodiment, referring to FIG2B , the control electrode TA of the third transistor T3 is electrically connected to the gate line 2; at least part of the orthographic projection of the third transistor T3 and the first transistor T1 on the substrate 1 are located on different sides of the orthographic projection of the fifth connection portion 445 on the substrate 1; optionally, the main structure of the orthographic projection of the third transistor T3 and the first transistor T1 on the substrate 1 may be located on different sides of the orthographic projection of the fifth connection portion 445 on the substrate 1; optionally, referring to FIG2B , the active pattern 6 of the third transistor T3 and the active pattern 6 of the first transistor T1 on the substrate 1 are located on different sides of the orthographic projection of the fifth connection portion 445 on the substrate 1.

[0302] In a possible embodiment, referring to Figures 2A-2G, 3A-3G, 4A-4G, and 5A-5G, the pixel electrode further includes: a first transition portion PZ1 extending along the first direction X, a second transition portion PZ2 extending along the second direction Y, and a second overlap portion PD2; one end of the first transition portion PZ1 is electrically connected to one end of the second sub-pixel electrode 412 facing the fourth sub-pixel electrode 422, and the other end of the first transition portion PZ1 is electrically connected to one end of the second transition portion PZ2; the other end of the second transition portion PZ2 is electrically connected to the second overlap portion PD2; and the second electrode TB of the second transistor T2 is electrically connected to the second sub-pixel electrode 412 through the second overlap portion PD2. In the embodiment of the present disclosure, a first transition portion PZ1, a second transition portion PZ2 extending along the second direction Y, and a second overlap portion PD2 are further provided on one side of the second sub-pixel electrode 412. In this way, the second sub-pixel electrode 412 is electrically connected to the second electrode TB of the second transistor T2, and the wiring method for electrically connecting the second sub-pixel electrode 412 to the second electrode TB of the second transistor T2 is simple and regular, which is conducive to the simple wiring between the gap between the first pixel electrode 41 and the second pixel electrode 42, and avoids the risk of short circuit defects that may occur during etching patterning when the layout of multiple patterns is more complex.

[0303] In one possible embodiment, the fifth connecting portion 445 can be linear, as shown in Figures 2A-2G, 3A-3G, 4A-4G, and 5A-5G, the fifth connecting portion 445 extends along the second direction Y; the second transfer portion PZ2 is parallel to the extension direction of the fifth connecting portion 445, which is conducive to simple wiring between the first pixel electrode 41 and the second pixel electrode 42, and avoids the risk of short circuit defects during etching patterning when the layout of multiple patterns is more complex.

[0304] In a possible embodiment, referring to FIG11B , the control electrode TA of the third transistor T3 is electrically connected to the auxiliary gate line 20; at least part of the orthographic projection of the third transistor T3 and the first transistor T1 on the substrate 1 is located on the same side of the orthographic projection of the fifth connection portion 445 on the substrate 1; optionally, the main structure of the orthographic projection of the third transistor T3 and the first transistor T1 on the substrate 1 may be located on the same side of the orthographic projection of the fifth connection portion 445 on the substrate 1; optionally, referring to FIG11B , the active pattern 6 of the third transistor T3 and the active pattern 6 of the first transistor T1 on the substrate 1 are located on the same side of the orthographic projection of the fifth connection portion 445 on the substrate 1.

[0305] In a possible embodiment, referring to Figures 11B and 11G, the fifth connection portion 445 may also be in the shape of a broken line, and the fifth connection portion 445 includes: a first sub-connection portion LL1, a second sub-connection portion LL2, and a third sub-connection portion LL3; the first sub-connection portion LL1 extends along the third direction Z, one end of which is electrically connected to the other end of the third connection portion 443, and the other end of which is electrically connected to the second sub-connection portion LL2; the third direction Z intersects with the first direction X and the second direction Y; the second sub-connection portion LL2 extends along the second direction Y, and the other end of the second sub-connection portion LL2 is electrically connected to one end of the third sub-connection portion LL3; the third sub-connection portion LL3 extends along the third direction Z, and the other end of the third sub-connection portion LL3 is electrically connected to the other end of the fourth connection portion 444.

[0306] In the embodiment of the present disclosure, the fifth connection portion 445 may also be in a zigzag shape, which can avoid the second electrode TC of the third transistor T3 and reduce the overlapping area between the fifth connection portion 445 and the second electrode TC of the third transistor T3, thereby reducing the coupling capacitance between the two.

[0307] In a possible embodiment, referring to FIG11B and FIG11G , the pixel electrode 4 further includes: a first transition portion PZ1 extending along the fourth direction G1, a second transition portion PZ2 extending along the second direction Y, and a second overlap portion PD2; one end of the first transition portion PZ1 is electrically connected to one end of the second sub-pixel electrode 412 facing the fourth sub-pixel electrode 422, and the other end of the first transition portion PZ1 is electrically connected to one end of the second transition portion PZ2; the other end of the second transition portion PZ2 is electrically connected to the second overlap portion PD2; and the second pole TC of the second transistor T2 is electrically connected to the second sub-pixel electrode 412 through the second overlap portion PD2.

[0308] In the embodiment of the present disclosure, the first transition portion PZ1 extends along the fourth direction G2 to avoid the second electrode TC of the third transistor T3 , thereby reducing the overlapping area between the first transition portion PZ1 and the second electrode TC of the third transistor T3 and thereby lowering the coupling capacitance therebetween.

[0309] In a possible implementation, the fourth direction G1 intersects the first direction X and the second direction Y. The fourth direction G1 may form an angle of 0° to 90° with the first direction X. Specifically, the angle formed by the fourth direction G1 and the first direction X is 30° to 60°. Specifically, the angle formed by the fourth direction G1 and the first direction X is 45°.

[0310] In a possible embodiment, referring to Figures 2A-2G, 3A-3G, 4A-4G, and 5A-5G, the extension line of the first transfer portion PZ1 coincides with the extension line of the third connection portion 443. This is conducive to simple wiring between the first pixel electrode 41 and the second pixel electrode 42, and avoids the risk of short circuit defects during etching patterning when the layout of multiple patterns is more complex.

[0311] In a possible embodiment, referring to Figures 2A-2G, 3A-3G, 4A-4G, and 5A-5G, the pixel electrode 4 further includes: a third transfer portion PZ3 extending along the first direction X, and a third overlap portion PD3; one end of the third transfer portion PZ3 is electrically connected to an end of the third sub-pixel electrode 421 facing the first sub-pixel electrode 411, and the other end of the third transfer portion PZ3 is electrically connected to the third overlap portion PD3; the second pole TC of the second transistor T2 is electrically connected to the third sub-pixel electrode 421 through the third overlap portion PD3. In the embodiment of the present disclosure, a third transfer portion PZ3 and a third overlap portion PD3 are further provided on one side of the third sub-pixel electrode 421, so as to electrically connect the third sub-pixel electrode 421 to the second electrode TB of the second transistor T2, and the wiring method for electrically connecting the third sub-pixel electrode 421 to the second electrode TB of the second transistor T2 is simple and regular, which is conducive to the simple wiring between the first pixel electrode 41 and the second pixel electrode 42, and avoids the risk of short circuit defects during etching patterning when the layout of multiple patterns is more complex.

[0312] In a possible embodiment, referring to Figures 2A-2G, 3A-3G, 4A-4G, and 5A-5G, the extension line of the third transfer portion PZ3 coincides with the extension line of the fourth connection portion 444. This is conducive to simple wiring between the first pixel electrode 41 and the second pixel electrode 42, and avoids the risk of short circuit defects during etching patterning when the layout of multiple patterns is more complex.

[0313] In a possible embodiment, referring to Figures 2A-2G, 3A-3G, 4A-4G, and 5A-5G, there is a first gap J1 between the third connecting portion 443 and the first pixel electrode 41; there is a second gap J2 between the fourth connecting portion 444 and the second pixel electrode 42; there is a third gap J3 between the first transition portion PZ1 and the first pixel electrode 41, and there is a fourth gap J4 between the third transition portion PZ3 and the second pixel electrode 42. Specifically, for example, as shown in Figure 2G, the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422 are two parts with brighter brightness, and the second sub-pixel electrode 412 and the third sub-pixel electrode 421 are two parts with darker brightness, and the first transfer portion PZ1 is a structure electrically connected to the second sub-pixel electrode 412 with darker brightness, and the loaded voltage is also lower, and it has a longer relative setting area with the first sub-pixel electrode 411 with a larger loaded voltage. By providing a third gap J3 between the first transfer portion PZ1 and the first sub-pixel electrode 411, it is possible to avoid problems such as breakdown when the two are close to each other and the voltage difference is large. Similarly, a fourth gap J4 is provided between the third transfer portion PZ3 and the fourth sub-pixel electrode 422, which is possible to avoid problems such as breakdown when the two are close to each other and the voltage difference is large. There is a first gap J1 between the third connecting portion 443 and the first pixel electrode 41; there is a second gap J2 between the fourth connecting portion 444 and the second pixel electrode 42, which can form a design that is relatively symmetrical with the third gap J3 and the fourth gap J4, which is conducive to the regular and neat layout of multiple patterns.

[0314] In a possible embodiment, referring to Figures 2A-2G, 3A-3G, 4A-4G, and 5A-5G, the array substrate further includes: a fourth connecting portion PD4; the second electrode TC of the third transistor T3 is electrically connected to the first common trace 21 through the fourth connecting portion PD4.

[0315] In a possible implementation, referring to FIG. 2A-2G , FIG. 3A-3G , FIG. 4A-4G , and FIG. 5A-5G , the second electrode TC of the third transistor T3 may be electrically connected to the first common trace 21 through a fourth via K4 .

[0316] In one possible embodiment, referring to FIG. 2I , which is a schematic cross-sectional view taken along the dotted line EF in FIG. 2B , the fourth via K4 may be a semi-via design. The fourth via K4 partially exposes the first common trace 21 and partially exposes the second electrode TC of the third transistor T3. The fourth bridging portion PD4 partially contacts the first common trace 21 and partially contacts the second electrode TC of the third transistor T3 at the fourth via K4, thereby electrically connecting the first common trace 21 to the second electrode TC of the third transistor T3 via the fourth bridging portion PD4. Specifically, the semi-via design of the fourth via K4 can form a stepped structure within the fourth via K4, thereby draining the alignment liquid and preventing moiré patterns from appearing on the image.

[0317] In a possible embodiment, referring to Figures 2A-2G, 3A-3G, 4A-4G, and 5A-5G, the fourth overlap portion PD4 has a fourth overlap portion outer edge f3 along the first direction X, and the second overlap portion PD2 has a second overlap portion outer edge f4 extending along the first direction X; the first overlap portion PD1 has a first overlap portion outer edge f5 extending along the second direction Y, and the third overlap portion PD3 has a third overlap portion outer edge f6 extending along the second direction Y; the extension line of the fourth overlap portion outer edge f3 coincides with the extension line of the second overlap portion outer edge f4; the extension line of the first overlap portion outer edge f5 coincides with the extension line of the third overlap portion outer edge f6.

[0318] In the embodiment of the present disclosure, the extension line of the outer edge f3 of the fourth overlap portion coincides with the extension line of the outer edge f4 of the second overlap portion; the extension line of the outer edge f5 of the first overlap portion coincides with the extension line of the outer edge f6 of the third overlap portion. The pattern distribution between the first pixel electrode 41 and the second pixel electrode 42 is simple and regular, avoiding the risk of short circuit defects during etching patterning when the layout of multiple patterns is complex.

[0319] In one possible embodiment, referring to Figures 2A-2G, 3A-3G, 4A-4G, and 5A-5G, the second electrode TC of the first transistor T1 includes a first transistor portion T1C1 extending along a first direction X; an orthographic projection of the first transistor portion T1C1 on the substrate 1 overlaps with an orthographic projection of the first bridging portion PD1 on the substrate 1. This facilitates electrical connection between the first transistor portion T1C1 and the first bridging portion PD1 via the first via K1.

[0320] In one possible embodiment, referring to Figures 2A-2G, 3A-3G, 4A-4G, and 5A-5G, the second electrode TC of the first transistor T1 includes: a first transistor second portion T1C2 extending along the second direction Y and electrically connected to the first transistor first portion T1C1; specifically, the orthographic projection of the first transistor second portion T1C2 on the substrate 1 may have an overlapping area with the orthographic projection of the active pattern 6 on the substrate 1.

[0321] In a possible embodiment, referring to Figures 2A to 2G, Figures 3A to 3G, Figures 4A to 4G, and Figures 5A to 5G, the second electrode TC of the second transistor T2 includes: a first portion T2C1 of the second transistor extending along the first direction X, and a second portion T2C2 of the second transistor extending along the second direction Y and electrically connected to one end of the first portion T2C1 of the second transistor; an orthographic projection of the first portion T2C1 of the second transistor on the substrate 1 and an orthographic projection of the third overlapping portion PD3 on the substrate 1 have an overlapping area, so that the first portion T2C1 of the second transistor is electrically connected to the third overlapping portion PD3 through the second via K2; an orthographic projection of the second portion T2C2 of the second transistor on the substrate and an orthographic projection of the second overlapping portion PD2 on the substrate 1 have an overlapping area, so that the second portion T2C2 of the second transistor is electrically connected to the second overlapping portion PD2 through the third via K3.

[0322] In a possible embodiment, referring to Figures 2A-2G, 3A-3G, 4A-4G, and 5A-5G, the second electrode TC of the second transistor T2 may further include: a second transistor third portion T2C3 electrically connected to the other end of the second transistor first portion T2C1 and extending along the second direction Y. Specifically, the orthographic projection of the second transistor third portion T2C3 on the substrate 1 may have an overlapping area with the orthographic projection of the active pattern 6 on the substrate 1.

[0323] In one possible implementation, referring to Figures 2A-2G, 3A-3G, 4A-4G, and 5A-5G, the second electrode TC of the third transistor T3 may include: a third transistor first portion T3C1 extending along the second direction Y, and a third transistor second portion T3C2 extending along the first direction X and connected to the third transistor first portion T3C1.

[0324] In a possible implementation, referring to FIG. 2A-2G , FIG. 3A-3G , FIG. 4A-4G , and FIG. 5A-5G , an extension direction of the first portion T3C1 of the third transistor is parallel to an extension direction of the second portion T2C2 of the second transistor.

[0325] In a possible embodiment, referring to Figures 20A-20K, 21A-21C, 22A-22C, and 23A-23C, the array substrate further includes: a plurality of transistors; a plurality of transistors T electrically connected to the same pixel electrode 4 are all electrically connected to the same data line 3 and the same gate line 2; the second sub-pixel electrode 412 is located on a side of the first sub-pixel electrode 411 away from the electrically connected data line 3, and the fourth sub-pixel electrode 422 is located on a side of the third sub-pixel electrode 421 away from the electrically connected data line 3; the first sub-pixel electrode 411 is electrically connected to the third sub-pixel electrode 421, and the second sub-pixel electrode 412 is electrically connected to the fourth sub-pixel electrode 422.

[0326] In the disclosed embodiment, the first sub-pixel electrode 411 is electrically connected to the third sub-pixel electrode 421 , and the second sub-pixel electrode 412 is electrically connected to the fourth sub-pixel electrode 422 , which can achieve local connection, make wiring simpler, and help improve the yield of the display panel.

[0327] Optionally, the multiple transistors T electrically connected to the same pixel electrode 4 can be transistors in a pixel circuit that drives the pixel electrode 4, that is, the multiple transistors in the pixel circuit that drives the same pixel electrode 4 are electrically connected to the same data line 3 and the same gate line 2.

[0328] In a possible embodiment, referring to FIG20B , the array substrate further includes: a first signal line 5 extending along the second direction Y; a plurality of transistors including: a first transistor T1, a second transistor T2, and a third transistor T3; a control electrode TA of the first transistor T1 is electrically connected to the gate line 2, a first electrode TB of the first transistor T1 is electrically connected to the data line 3, and a second electrode TC of the first transistor T1 is electrically connected to the first sub-pixel electrode 411; specifically, the second electrode TC of the first transistor T1 can be electrically connected to the first sub-pixel electrode 411 through a first via K1; the control electrode TA of the second transistor T2 is electrically connected to the gate line 2, a first electrode TB of the first transistor T1 is electrically connected to the data line 3, and a second electrode TC of the first transistor T1 is electrically connected to the first sub-pixel electrode 411. The electrode TA is electrically connected to the gate line 2, the first electrode TB of the second transistor T2 is electrically connected to the data line 3 (the first electrode TB of the second transistor T2 can be part of the multiplexed data line 3), and the second electrode TC of the second transistor T2 is electrically connected to the fourth sub-pixel electrode 422; specifically, the second electrode TC of the second transistor T2 can be electrically connected to the fourth sub-pixel electrode 422 through the second via K2; the control electrode TA of the third transistor T3 is electrically connected to the gate line 2, the first electrode TB of the third transistor T3 multiplexes the second electrode TC of the second transistor T2, and the second electrode TC of the third transistor T3 multiplexes the first signal line 5.

[0329] In a possible implementation, referring to FIG. 20B and FIG. 20G , the pixel electrode 4 further includes a connecting portion 44 ; the connecting portion 44 extends along the second direction Y and connects the first sub-pixel electrode 411 and the third sub-pixel electrode 421 .

[0330] In a possible embodiment, referring to FIG. 20B and FIG. 20G , the connecting portion 44 is made of the same layer and material as the first sub-pixel electrode 411 and the third sub-pixel electrode 421 . The connecting portion 44 can be formed at the same time as the first sub-pixel electrode 411 and the third sub-pixel electrode 421 are formed. This simplifies the manufacturing process of the array substrate.

[0331] In a possible embodiment, referring to Figures 20B and 20G, the pixel electrode 4 also includes: a connecting portion 45; the connecting portion 45 includes: a first connecting portion 451 and a second connecting portion 452; the connecting portion 45 connects the second sub-pixel electrode 412 and the fourth sub-pixel electrode 422; the first connecting portion 451 extends along the first direction X, with one end electrically connected to the second sub-pixel electrode 412 and the other end electrically connected to one end of the second connecting portion 452; the other end of the second connecting portion 452 is electrically connected to the fourth sub-pixel electrode 422.

[0332] In a possible embodiment, referring to FIG. 20B and FIG. 20G , the connecting portion 45 is made of the same layer and material as the second sub-pixel electrode 412 and the fourth sub-pixel electrode 422 . The connecting portion 45 can be formed while the second sub-pixel electrode 412 and the fourth sub-pixel electrode 422 are being formed. This simplifies the manufacturing process of the array substrate.

[0333] In one possible embodiment, the second connecting portion 452 may be a straight line extending along the second direction Y; in another possible embodiment, as shown in FIG. 20B , the second connecting portion 452 may be a broken line extending as a whole along the second direction Y, and may be bent at a local position.

[0334] In one possible implementation, as shown in FIG20G , the first pixel electrode 41 has a notch 46 on the side facing the gate line 2; at least a portion of the orthographic projection of the connecting portion 45 on substrate 1 is located at the orthographic projection of the notch 46 on substrate 1. In the disclosed embodiment, the first pixel electrode 41 has a notch 46 on the side facing the gate line 2 to avoid the first connecting portion 451.

[0335] In one possible implementation, as shown in FIG. 20G , the notch 46 may be located in the first sub-pixel electrode 411 in the first pixel electrode 41 ; in another possible implementation, the notch 46 may also be located in the second sub-pixel electrode 412 in the first pixel electrode 41 .

[0336] In one possible embodiment, referring to FIG. 20B and FIG. 20G , the pixel electrode 4 further includes: a first sub-pixel electrode protrusion 47 connected to the side of the first sub-pixel electrode 411 facing the third sub-pixel electrode 421; the second electrode TC of the first transistor T1 is electrically connected to the first sub-pixel electrode 411 via the first sub-pixel electrode protrusion 47;

[0337] The pixel electrode 4 further includes a fourth sub-pixel electrode protrusion 48 connected to the fourth sub-pixel electrode 422 facing the first sub-pixel electrode 411 . The second electrode TC of the second transistor T2 is electrically connected to the fourth sub-pixel electrode 422 via the fourth sub-pixel electrode protrusion 48 .

[0338] In a possible embodiment, referring to FIG. 20B and FIG. 20G , the orthographic projections of the first sub-pixel electrode protrusion 47 and the fourth sub-pixel electrode protrusion 48 on the substrate 1 are both located between the orthographic projection of the connecting portion 44 on the substrate 1 and the orthographic projection of the connecting portion 45 on the substrate 1. In this way, on the one hand, the first electrode TB of the third transistor T3 can be reused with the second electrode TC of the second transistor T2, thereby reducing the coupling capacitance Cgd between the gate line and the drain; on the other hand, the winding of the first signal line 5 can be reduced, thereby reducing the impedance of the first signal line 5, which is beneficial to improving the display effect. Moreover, more flat areas can be left vacant on the periphery to facilitate the setting of spacers.

[0339] In one possible embodiment, as shown in Figure 20G, the first sub-pixel electrode protrusion 47 has a first sub-pixel electrode protrusion outer edge 471 extending along the second direction Y; the fourth sub-pixel electrode protrusion 48 has a fourth sub-pixel electrode protrusion outer edge 481 extending along the second direction Y; the extension line of the first sub-pixel electrode protrusion outer edge 471 at least partially overlaps with the fourth sub-pixel electrode protrusion 48.

[0340] In one possible implementation, an extension line of the outer edge 471 of the first sub-pixel electrode protrusion coincides with the outer edge 481 of the fourth sub-pixel electrode protrusion. This allows the first sub-pixel electrode protrusion 47 and the fourth sub-pixel electrode protrusion 48 to be located in the same second direction Y, simplifying the wiring space of the array substrate.

[0341] In one possible embodiment, as shown in Figures 1A-1G , the array substrate further includes a first common trace 21 located on one side of the gate line 2 and extending along a first direction; the first common trace 21 is disconnected at a location where it intersects with the data line 3. This prevents the first common trace 21 from overlapping with the data line 3, which would increase the load on the data line 3 and affect signal transmission on the data line 3.

[0342] In one possible embodiment, referring to Figures 1A-1G, 2A-2G, 3A-3G, 4A-4G, and 5A-5G, the array substrate further includes: a second common routing group 22 electrically connected to the first common routing 21 and extending away from the gate line 2, the second common routing group 22 including: two second common routing lines 220; an orthographic projection of the data line 3 on the substrate 1 and a gap between the two second common routing lines 220 of the same second common routing group 22 having an overlapping area when projected on the substrate 1. The orthographic projections of the second common routing lines 220 on the substrate 1 are located on both sides of the orthographic projection of the data line 3 on the substrate 1, thereby improving the coupling capacitance between the data line 3 and the second pixel electrode 42.

[0343] In a possible embodiment, referring to Figures 1A-1G, 2A-2G, 3A-3G, 4A-4G, and 5A-5G, the array substrate further includes: a third common routing line 23 located on the other side of the gate line 2 and extending along the first direction X, and a fourth common routing line group 24 connected to the third common routing line 23 and extending toward a side away from the gate line 2; the third common routing line 23 is disconnected at the position where it intersects with the data line 3, so as to avoid the third common routing line 23 from overlapping with the data line 3, thereby increasing the load of the data line 3 and affecting the signal transmission of the data line 3; the fourth common routing line group 24 includes: two fourth common routing lines 240; the orthographic projection of the data line 3 on the substrate 1 and the gap between the two fourth common routing lines 240 of the same fourth common routing line group 24 have an overlapping area on the orthographic projection of the substrate 1. The orthographic projection of the fourth common line 240 on the substrate 1 is located on both sides of the orthographic projection of the data line 3 on the substrate 1 , which can improve the coupling capacitance between the data line 3 and the first pixel electrode 41 .

[0344] In one possible embodiment, the first common trace 21 and the third common trace 23 can be electrically connected by drilling holes in the display area in a bridge manner, or they can also be electrically connected in the non-display area. In one possible embodiment, the array substrate may further include a non-display area located outside the display area. The non-display area may be provided with a ring-shaped common trace surrounding the display area. The first common trace 21 and the third common trace 23 can both be electrically connected to the ring-shaped common trace to have the same common voltage signal.

[0345] In a possible embodiment, referring to Figures 1A to 1G, the array substrate further includes: a fifth common line 25 extending along the first direction X and electrically connected to the second common line 220, and the orthographic projection of the fifth common line 25 on the substrate passes through the central area of ​​the orthographic projection of the second pixel electrode 42 on the substrate 1.

[0346] In a possible embodiment, referring to Figures 1A to 1G, the array substrate further includes: a sixth common line 26 extending along the first direction X and electrically connected to the fourth common line 240, and the orthographic projection of the sixth common line 26 on the substrate 1 passes through the central area of ​​the orthographic projection of the first pixel electrode 41 on the substrate 1.

[0347] In a possible embodiment, referring to Figures 1A-1G, 2A-2G, 3A-3G, 4A-4G, and 5A-5G, the first sub-pixel electrode 411 and the second sub-pixel electrode 412 both include: a first sub-electrode portion P1 distributed along the second direction Y, and a second sub-electrode portion P2; the third sub-pixel electrode 421 and the fourth sub-pixel electrode 422 both include: a third sub-electrode portion P3 distributed along the second direction Y, and a fourth sub-electrode portion P4; the first sub-electrode portion P1, the second sub-electrode portion P2, the third sub-electrode portion P3, and the fourth sub-electrode portion P4 all have multiple slits F; and the extension direction of the slits F of the first sub-electrode portion P1 is the same as the extension direction of the slits F of the fourth sub-electrode portion P4; the extension direction of the slits F of the second sub-electrode portion P2 is the same as the extension direction of the slits F of the third sub-electrode portion P3.

[0348] In one possible embodiment, the length of the slit F in the direction perpendicular to the extension direction may be 2 μm to 4 μm. Specifically, the length of the slit F in the direction perpendicular to the extension direction may be 3 μm. In the embodiment of the present disclosure, in the array substrate provided based on the embodiment of the present disclosure, when the length of the slit F in the direction perpendicular to the extension direction is reduced to 3 μm, the dark lines almost disappear.

[0349] Specifically, referring to Figures 1A-1G, 2A-2G, 3A-3G, 4A-4G, and 5A-5G, the angle formed by the extension direction of the slit F of the first sub-electrode portion P1 and the first direction X can be 40° to 50°, for example, 45°; the angle formed by the extension direction of the slit F of the second sub-electrode portion P2 and the first direction X can be 130° to 140°, for example, 135°; the angle formed by the extension direction of the slit F of the third sub-electrode portion P3 and the first direction X can be 130° to 140°, for example, 135°; the angle formed by the extension direction of the slit F of the fourth sub-electrode portion P4 and the first direction X can be 40° to 50°, for example, 45°.

[0350] Specifically, the angle formed by the liquid crystal alignment direction in the area where the first sub-electrode portion P1 is located and the first direction X can be 220° to 230°, for example, 225°; the angle formed by the liquid crystal alignment direction in the area where the second sub-electrode portion P2 is located and the first direction X can be 130° to 140°, for example, 135°; the angle formed by the liquid crystal alignment direction in the area where the third sub-electrode portion P3 is located and the first direction X can be 310° to 320°, for example, 315°; and the angle formed by the liquid crystal alignment direction in the area where the fourth sub-electrode portion P4 is located and the first direction X can be 40° to 50°, for example, 45°. By achieving four alignment directions in the area where a pixel electrode 4 is located, and combining them with the divided bright and dark areas, an alignment mode of eight domains in a sub-pixel can be formed when using the Super UV Photo Alignment (SUVA) technology.

[0351] In a possible implementation, referring to FIG. 1A-FIG , and FIG. 4A-FIG , the orthographic projection shapes of the first sub-pixel electrode 411 , the second sub-pixel electrode 412 , the third sub-pixel electrode 421 , and the fourth sub-pixel electrode 422 on the substrate 1 are all rectangular.

[0352] In one possible embodiment, referring to Figures 2A to 2G , the orthographic projection shapes of the first sub-electrode portion P1, the second sub-electrode portion P2, the third sub-electrode portion P3, and the fourth sub-electrode portion P4 on the substrate 1 are all trapezoidal; in the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422, the trapezoidal first sub-electrode portion P1 and the trapezoidal second sub-electrode portion P2 are arranged with their top sides facing each other (i.e., with their short sides facing each other); in the second sub-pixel electrode 412 and the third sub-pixel electrode 421, the trapezoidal first sub-electrode portion P1 and the trapezoidal second sub-electrode portion P2 are arranged with their bottom sides facing each other (i.e., with their long sides facing each other). In the embodiment of the present disclosure, the first pixel electrode 41 and the second pixel electrode 42 can be divided in a manner parallel to the extension direction of the slit F, which can have a better transmittance effect.

[0353] In one possible embodiment, referring to Figures 3A to 3G , the orthographic projection shapes of the first sub-electrode portion P1, the second sub-electrode portion P2, the third sub-electrode portion P3, and the fourth sub-electrode portion P4 on the substrate 1 are all trapezoidal; in the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422, the trapezoidal first sub-electrode portion P1 and the trapezoidal second sub-electrode portion P2 are arranged with their bottom sides facing each other (that is, with their long sides facing each other); in the second sub-pixel electrode 412 and the third sub-pixel electrode 421, the trapezoidal first sub-electrode portion P1 and the trapezoidal second sub-electrode portion P2 are arranged with their top sides facing each other (that is, with their short sides facing each other). In the embodiment of the present disclosure, the first pixel electrode 41 and the second pixel electrode 42 can be divided in a manner perpendicular to the extension direction of the slit F, which can have a better transmittance effect.

[0354] In one possible embodiment, referring to FIG. 5A to FIG. 5G , the first sub-pixel electrode 411 includes: a first main portion PA1 extending and connected along the second direction Y, a second main portion PA2, and a first side portion PC1 extending along the first direction X, a plurality of first branches PB1 extending from the first main portion PA1 and the first side portion PC1 along the fourth direction G1, and a plurality of second branches PB2 extending from the second main portion PA2 and the first side portion PC1 along the fifth direction G2; the second sub-pixel electrode 412 includes: a third main portion PA3 extending and connected along the second direction Y, a fourth main portion PA4, and a first side portion PC1 extending along the first direction X. The main portion PA4; a fifth main portion PA5 connected to one end of the third main portion PA3 and extending along the first direction X; a sixth main portion PA6 connected to one end of the fourth main portion PA4 and extending along the first direction X; a plurality of third branches PB3 extending from the third main portion PA3 and the fifth main portion PA5 along the fourth direction G1; and a plurality of fourth branches PB4 extending from the fourth main portion PA4 and the sixth main portion PA6 along the fifth direction G2; the plurality of first branches PB1 and the plurality of third branches PB3 are arranged in an interdigitated manner, and the plurality of second branches PB2 and the plurality of fourth branches PB4 are arranged in an interdigitated manner.

[0355] The third sub-pixel electrode 421 includes: a seventh main portion PA7 extending and connected along the second direction Y, an eighth main portion PA8, a ninth main portion PA9 connected to one end of the seventh main portion PA7 and extending along the first direction X, a tenth main portion PA10 connected to one end of the eighth main portion PA8 and extending along the first direction X, a plurality of fifth branches PB5 extending from the seventh main portion PA7 and the ninth main portion PA9 along the fourth direction G1, and a plurality of sixth branches PB6 extending from the eighth main portion PA8 and the tenth main portion PA10 along the fifth direction G2; the fourth sub-pixel electrode 422 includes: an eleventh main portion PA11 extending and connected along the second direction Y, a twelfth main portion PA12, and a second side portion PC2 extending along the first direction X, Multiple seventh branches PB7 extending from the second side PC2 along the fourth direction G1, and multiple eighth branches PB8 extending from the twelfth main portion PA12 and the second side PC2 along the fifth direction G2; multiple fifth branches PB5 and multiple seventh branches PB7 are distributed in a forked manner, and multiple sixth branches PB6 and multiple eighth branches PB8 are distributed in a forked manner.

[0356] It should be noted that, for the array substrate structure corresponding to Figures 2A, 3A, and 5A provided in the embodiment of the present disclosure, a first signal line 5 can be set, and part of the voltage can be released to the first signal line 5 through the third transistor T3 to achieve a display effect with different light and dark. Similarly, for the array substrate shown in Figure 1A provided in the embodiment of the present disclosure, the first signal line 5 can also be not set, and part of the voltage can be released to the first common wiring 21 through the third transistor T3 to achieve a display effect with different light and dark. The embodiment of the present disclosure does not impose any restrictions on this.

[0357] In a possible embodiment, referring to Figures 6A to 6J, the array substrate further includes: a first conductive layer 7 located on the side of the pixel electrode 4 facing the substrate 1; the first conductive layer 7 has a first hollow L1, a second hollow L2, a third hollow L3, and a fourth hollow L4; at least a portion of the orthographic projection of the first hollow L1 on the substrate 1 overlaps with at least a portion of the orthographic projection of the first sub-electrode portion P1 on the substrate 1; at least a portion of the orthographic projection of the second hollow L2 on the substrate 1 overlaps with at least a portion of the orthographic projection of the second sub-electrode portion P2 on the substrate 1; at least a portion of the orthographic projection of the third hollow L3 on the substrate 1 overlaps with at least a portion of the orthographic projection of the third sub-electrode portion P3 on the substrate 1; at least a portion of the orthographic projection of the fourth hollow L4 on the substrate 1 overlaps with at least a portion of the orthographic projection of the fourth sub-electrode portion P4 on the substrate 1.

[0358] In the embodiment of the present disclosure, for a display panel in a VA display mode in which an array substrate is provided with a pixel electrode layer and a counter substrate is provided with a common electrode layer, a first conductive layer 7 is further provided on the side of the pixel electrode 4 facing the substrate 1; the first conductive layer 7 has a first hollow L1, a second hollow L2, a third hollow L3, and a fourth hollow L4, which can make the liquid crystal twist more uniform, reduce the dark lines corresponding to the pixel electrode, reduce the width of the black matrix, and improve the transmittance of the display panel; in addition, in addition to the vertical electric field formed by the pixel electrode and the common electrode in the array substrate, the pixel electrode and the first conductive layer 7 will form a lateral electric field, which can increase the deflection direction of the liquid crystal and improve the color deviation problem of the display panel.

[0359] Specifically, the first conductive layer 7 can be located between the substrate 1 and the layer where the pixel electrode 4 is located. Specifically, the first conductive layer 7 can be loaded with the same signal as the common electrode layer of the opposite substrate. The first conductive layer 7 can be a transparent electrode layer, and the material of the first conductive layer 7 can be indium tin oxide.

[0360] In a possible embodiment, referring to FIG6G , the first conductive layer 7 may further include a first conductive connection portion 71, wherein the orthographic projection of the first conductive connection portion 71 on the substrate 1 covers the orthographic projection of the data line 3 on the substrate 1, and covers the orthographic projection of the gate line 2 on the substrate 1. In the embodiment of the present disclosure, the orthographic projection of the first conductive connection portion 71 on the substrate 1 covers the orthographic projection of the data line 3 on the substrate 1, and the coupling capacitance between the pixel electrode and the data line 3, as well as the coupling capacitance between the pixel electrode and the gate line 2, can be shielded by the first conductive connection portion 71, thereby avoiding the need for the second common wiring 220 (and / or the fourth common wiring 240), or reducing the number or line width of the second common wiring 220 (and / or the fourth common wiring 240), thereby increasing the transmittance of the display panel.

[0361] In a possible embodiment, referring to FIG6G , the first conductive layer 7 may further include a fifth hollow L5, a sixth hollow L6, a seventh hollow L7, and an eighth hollow L8; wherein, at least a portion of the orthographic projection of the fifth hollow L5 on the substrate 1 may overlap with at least a portion of the orthographic projection of the first via K1 on the substrate 1; at least a portion of the orthographic projection of the sixth hollow L6 on the substrate 1 may overlap with at least a portion of the orthographic projection of the second via K2 on the substrate 1; at least a portion of the orthographic projection of the seventh hollow L7 on the substrate 1 may overlap with at least a portion of the orthographic projection of the third via K3 on the substrate 1; the fifth hollow L5, the sixth hollow L6, and the seventh hollow L7 are arranged to facilitate conduction between the pixel electrode 4 above the first conductive layer 7 and the transistor below the first conductive layer 7.

[0362] In the embodiment of the present disclosure, the first conductive layer 7 may further include an eighth hollow L8, which can avoid overlapping capacitance between the gate line 2 and the first conductive layer 7, affecting the pixel charging rate; however, if the first conductive layer 7 is completely hollowed out in the area where the gate line 2 is located, light leakage will occur. In the embodiment of the present disclosure, the eighth hollow L8 is only set in the partial area where the first conductive layer 7 and the gate line 2 overlap, which can reduce light leakage and reduce the overlapping capacitance between the gate line 2 and the first conductive layer 7, thereby ensuring the charging rate.

[0363] In a possible embodiment, the length h2 of the eighth hollow L8 in the first direction X may be one-fifth to four-fifths of the length h1 of the second hollow L2 in the first direction; in a possible embodiment, the length h2 of the eighth hollow L8 in the first direction X may be one-quarter to three-quarters of the length h1 of the second hollow L2 in the first direction; in a possible embodiment, the length h2 of the eighth hollow L8 in the first direction X may be one-half of the length h1 of the second hollow L2 in the first direction.

[0364] In one possible embodiment, the length h4 of the eighth hollow L8 in the second direction Y may be one-fifth to four-fifths of the distance h3 between the second hollow L2 and the third hollow L3; in one possible embodiment, the length h4 of the eighth hollow L8 in the second direction Y may be one-quarter to three-quarters of the distance h3 between the second hollow L2 and the third hollow L3; in one possible embodiment, the length h4 of the eighth hollow L8 in the second direction Y may be one-half of the distance h3 between the second hollow L2 and the third hollow L3.

[0365] In a possible implementation, an outer edge extension line of the eighth hollow L8 extending along the second direction Y and away from the side of the sixth hollow L6 coincides with an outer edge extension line of the second hollow L2 extending along the second direction Y.

[0366] In a possible embodiment, in combination with Figures 6A to 6J and Figure 10, the data line 3 can be located on the side of the gate line 2 away from the substrate 1, the first conductive layer 7 can be located on the side of the data line 3 away from the gate line 2, the pixel electrode 4 can be located on the side of the first conductive layer 7 away from the data line 3, and a gate insulating layer can be provided between the layer where the gate line 2 is located and the layer where the data line 3 is located. An active layer can be provided between the gate insulating layer and the data line 3 (the active layer can include an active pattern 6, and the active layer material can be amorphous silicon, low-temperature polycrystalline silicon, metal oxide, etc., which is not limited here). A first insulating layer 91 can be provided between the data line 3 and the first conductive layer 7, and a second insulating layer 92 can be provided between the first conductive layer 7 and the pixel electrode 4.

[0367] 1H , 2H , 3H , 4H , 5H , and 6K , the disclosed embodiment performs optical simulations on different array substrate structures. By comparing the horizontal dark lines in the center of the sub-pixels, it can be clearly seen that for the array substrate structures corresponding to FIG. 1H , 2H , 3H , 4H , and 5H without the first conductive layer 7 , the transmittance corresponding to the structure of FIG. 2A is the highest.

[0368] Based on the same inventive concept, an embodiment of the present disclosure further provides a display panel, which includes: an array substrate as provided in the embodiment of the present disclosure, and also includes an opposite substrate arranged opposite to the array substrate, wherein the opposite substrate is provided with a common electrode layer.

[0369] In a possible embodiment, referring to FIG10 and FIG8 , the display panel further includes a liquid crystal layer 10 located between the array substrate and the counter substrate; the liquid crystal layer 10 includes: a plurality of liquid crystal portions PJ, at least one liquid crystal portion PJ of the plurality of liquid crystal portions PJ includes: a first sub-liquid crystal portion PJ1, a second sub-liquid crystal portion PJ2, a third sub-liquid crystal portion PJ3, and a fourth sub-liquid crystal portion PJ4; an orthographic projection of the liquid crystal portion PJ on the substrate 1 overlaps with an orthographic projection of the pixel electrode 4 on the substrate 1; an orthographic projection of the first sub-liquid crystal portion PJ1 on the substrate 1 overlaps with an orthographic projection of the first sub-electrode portion P1 on the substrate 1; an orthographic projection of the second sub-liquid crystal portion PJ2 on the substrate 1 overlaps with an orthographic projection of the second sub-electrode portion P2 on the substrate 1; an orthographic projection of the third sub-liquid crystal portion PJ3 on the substrate 1 overlaps with an orthographic projection of the third sub-electrode portion P3 on the substrate 1; and an orthographic projection of the fourth sub-liquid crystal portion PJ4 on the substrate 1 overlaps with an orthographic projection of the fourth sub-electrode portion P4 on the substrate 1;

[0370] The initial alignment directions of the first sub-liquid crystal portion PJ1 , the second sub-liquid crystal portion PJ2 , the third sub-liquid crystal portion PJ3 , and the fourth sub-liquid crystal portion PJ4 are different from each other.

[0371] It is understandable that the initial alignment direction of the liquid crystal may be the alignment direction of the liquid crystal when no voltage is applied.

[0372] In a possible embodiment, as shown in Figure 8, the angle range between the initial alignment direction of the first sub-liquid crystal portion PJ1 and the first direction X is 210°~240°; the angle range between the initial alignment direction of the second sub-liquid crystal portion PJ2 and the first direction X is 120°~150°; the angle range between the initial alignment direction of the third sub-liquid crystal portion PJ3 and the first direction X is 300°~330°; the angle range between the initial alignment direction of the fourth sub-liquid crystal portion PJ4 and the first direction X is 30°~60°.

[0373] In a possible embodiment, as shown in Figure 8, the alignment direction of at least part of the liquid crystal at the junction of the first sub-liquid crystal portion PJ1 and the second sub-liquid crystal portion PJ2 is opposite to the alignment direction of at least part of the liquid crystal at the junction of the third sub-liquid crystal portion PJ3 and the fourth sub-liquid crystal portion PJ4.

[0374] In one possible embodiment, as shown in FIG8 , the liquid crystal at the junction of the first and second liquid crystal sub-sections PJ1 and PJ2 is aligned parallel to the first direction X and faces leftward. The liquid crystal at the junction of the third and fourth liquid crystal sub-sections PJ3 and PJ4 is aligned parallel to the first direction X and faces rightward. Compared to the conventional SUVA structure shown in FIG7 , which lacks a good liquid crystal angle to compensate for left and right viewing angles, all lateral liquid crystals face rightward, with no lateral liquid crystals facing leftward. In the disclosed embodiment, as shown in FIG8 , the lateral liquid crystals face both leftward and rightward, allowing the left and right lateral liquid crystals to compensate for each other's viewing angles, thereby improving left-right color shift.

[0375] In one possible implementation, as shown in conjunction with Figures 6A to 6J and Figure 10 , the display panel may further be provided with a black matrix 8, and the orthographic projection of the black matrix 8 on the substrate 1 may cover the orthographic projection of the gate line 2 on the substrate 1, and cover the orthographic projection of the data line 3 on the substrate 1. Specifically, the counter substrate may include a counter substrate 90, and the black matrix 8 may be located between the counter substrate 90 and the common electrode layer (not shown in Figure 10 ).

[0376] In one possible embodiment, as shown in Figure 10, the first conductive layer 7 is located on the side of the pixel electrode 4 away from the opposite substrate. In this public embodiment, the first conductive layer 7 is located on the side of the pixel electrode 4 away from the opposite substrate, which can isolate (or shield) the first overlapping capacitance between the pixel electrode 4 and the gate line 2 and the second overlapping capacitance between the pixel electrode 4 and the data line 3, greatly reducing the risk of crosstalk. At the same time, due to the presence of the first conductive layer 7, the distance between the pixel electrodes 4 can be reduced, so that the pixel electrode 4 and the gate line 2 overlap (overlap), the pixel electrode 4 and the data line 3 overlap (overlap), reducing the risk of liquid crystal light leakage, thereby reducing the width of the black matrix, increasing the pixel aperture ratio, and improving the pixel transmittance.

[0377] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, which includes a display panel provided by the embodiment of the present disclosure.

[0378] In specific implementations, in the embodiments of the present disclosure, the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigation system, or the like. Other essential components of the display device are well understood by those skilled in the art and are not detailed here, nor should they be construed as limitations of the present disclosure.

[0379] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0380] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. An array substrate, wherein: include: substrate; A plurality of gate lines, located on one side of the substrate and extending along a first direction; A plurality of data lines extending along a second direction; A plurality of pixel electrodes, the pixel electrodes comprising: a first pixel electrode located on one side of the gate line, and a second pixel electrode located on the other side of the gate line; the first pixel electrode comprising: a first sub-pixel electrode and a second sub-pixel electrode distributed along the first direction; the second pixel electrode comprising: a third sub-pixel electrode and a fourth sub-pixel electrode distributed along the first direction; One of the first sub-pixel electrode and the second sub-pixel electrode is electrically connected to one of the third sub-pixel electrode and the fourth sub-pixel electrode.

2. The array substrate according to claim 1, wherein: The array substrate further comprises: a plurality of transistors; the plurality of transistors electrically connected to the same pixel electrode are all electrically connected to the same data line and the same gate line; The second sub-pixel electrode is located on a side of the first sub-pixel electrode away from the electrically connected data line, and the fourth sub-pixel electrode is located on a side of the third sub-pixel electrode away from the electrically connected data line; the first sub-pixel electrode is electrically connected to the fourth sub-pixel electrode.

3. The array substrate according to claim 2, wherein: The array substrate further comprises: a first signal line extending along the second direction; the plurality of transistors comprises: a first transistor, a second transistor, and a third transistor; The control electrode of the first transistor is electrically connected to the gate line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the first sub-pixel electrode and the fourth sub-pixel electrode; The control electrode of the second transistor is electrically connected to the gate line, the first electrode of the second transistor is electrically connected to the data line, and the second electrode of the second transistor is electrically connected to the second sub-pixel electrode and the third sub-pixel electrode; The control electrode of the third transistor is electrically connected to the gate line, the first electrode of the third transistor multiplexes with the second electrode of the second transistor, and the second electrode of the third transistor multiplexes with the first signal line.

4. The array substrate according to claim 3, wherein: The pixel electrode further includes: a first sub-pixel electrode protrusion connected to the first sub-pixel electrode on a side facing the third sub-pixel electrode; and a second electrode of the first transistor is electrically connected to the first sub-pixel electrode through the first sub-pixel electrode protrusion.

5. The array substrate according to claim 4, wherein: The pixel electrode further includes: a connecting portion connecting the first sub-pixel electrode and the fourth sub-pixel electrode; the connecting portion includes: a first connecting portion extending along the second direction, and a second connecting portion extending along a third direction; the third direction intersects the first direction and the second direction; One end of the first connection portion is electrically connected to one end of the first subpixel electrode facing the third subpixel electrode, and the other end is electrically connected to the second connection portion. The other end of the second connection portion is electrically connected to one end of the fourth subpixel electrode facing the second subpixel electrode.

6. The array substrate according to any one of claims 3 to 5, wherein: The pixel electrode further includes: a third sub-pixel electrode protrusion connected to a side of the third sub-pixel electrode facing the first sub-pixel electrode; The second electrode of the second transistor is electrically connected to the third sub-pixel electrode through the third sub-pixel electrode protrusion.

7. The array substrate according to claim 6, wherein: The pixel electrode further includes: a second sub-pixel electrode extension extending along the second direction, and a second sub-pixel electrode convex portion; one end of the second sub-pixel electrode extension is electrically connected to one end of the second sub-pixel electrode facing the fourth sub-pixel electrode, and the other end is electrically connected to the second sub-pixel electrode convex portion; The second electrode of the second transistor is electrically connected to the second sub-pixel electrode through the second sub-pixel electrode protrusion.

8. The array substrate according to claim 7, wherein: An extending direction of the second sub-pixel electrode extending portion is parallel to an extending direction of the first connecting portion.

9. The array substrate according to claim 7 or 8, wherein: The second sub-pixel electrode convex portion has a second sub-pixel electrode convex portion outer edge away from one side of the second sub-pixel electrode and extending along the first direction; the third sub-pixel electrode convex portion has a third sub-pixel electrode convex portion outer edge away from one side of the third sub-pixel electrode and extending along the first direction; The extension line of the outer edge of the second sub-pixel electrode protrusion coincides with the extension line of the outer edge of the third sub-pixel electrode protrusion; or, the extension line of the outer edge of the second sub-pixel electrode protrusion at least partially overlaps with the third sub-pixel electrode protrusion; or, the extension line of the outer edge of the third sub-pixel electrode protrusion at least partially overlaps with the second sub-pixel electrode protrusion.

10. The array substrate according to claim 7 or 8, wherein: A connecting line between the center of the third sub-pixel electrode protrusion and the center of the first sub-pixel electrode protrusion is parallel to the second direction.

11. The array substrate according to any one of claims 4 to 10, wherein: The second electrode of the first transistor includes: a first transistor first portion extending along the first direction; The orthographic projection of the first portion of the first transistor on the substrate has an overlapping area with the orthographic projection of the first sub-pixel electrode convex portion on the substrate.

12. The array substrate according to any one of claims 8 to 11, wherein: The second electrode of the second transistor includes: a second transistor first portion extending along the first direction, and a second transistor second portion extending along the second direction and electrically connected to one end of the second transistor first portion; The orthographic projection of the first portion of the second transistor on the substrate has an overlapping area with the orthographic projection of the third sub-pixel electrode convex portion on the substrate; the orthographic projection of the second portion of the second transistor on the substrate has an overlapping area with the orthographic projection of the second sub-pixel electrode convex portion on the substrate.

13. The array substrate according to claim 12, wherein: At least a portion of the second portion of the second transistor on the orthographic projection of the substrate overlaps with at least a portion of the second sub-pixel electrode extension portion on the orthographic projection of the substrate.

14. The array substrate according to claim 13, wherein: The first signal line has a recessed portion; and the second portion of the second transistor is located at least partially in a region surrounded by the recessed portion in the orthographic projection of the substrate.

15. The array substrate according to claim 14, wherein: The first signal line includes: a first signal portion, a second signal portion, and a third signal portion sequentially distributed along the second direction, a fourth signal portion extending along the first direction and connecting the second signal portion with the first signal portion, and a fifth signal portion extending along the first direction and connecting the second signal portion with the third signal portion; An extension line of the first signal portion coincides with an extension line of the third signal portion; an extension line of the second signal portion coincides with an extension line of the first signal portion; the second signal portion, the fourth signal portion and the fifth signal portion constitute the recessed portion, and the fourth signal portion and / or the fifth signal portion at least partially overlap with the pixel electrode.

16. The array substrate according to claim 2, wherein: The array substrate further comprises: a first common wiring located at one side of the gate line and extending along the first direction; the plurality of transistors comprises: a first transistor electrically connected to the data line, a second transistor, and a third transistor; The control electrode of the first transistor is electrically connected to the gate line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the first sub-pixel electrode and the fourth sub-pixel electrode; The control electrode of the second transistor is electrically connected to the gate line, the first electrode of the second transistor is electrically connected to the data line, and the second electrode of the second transistor is electrically connected to the second sub-pixel electrode and the third sub-pixel electrode; The control electrode of the third transistor is electrically connected to the gate line, the first electrode of the third transistor is multiplexed with the second electrode of the second transistor, and the second electrode of the third transistor is electrically connected to the first common wiring.

17. The array substrate according to claim 1, wherein: The first sub-pixel electrode is electrically connected to the fourth sub-pixel electrode; the array substrate further comprises: a plurality of transistors, a third common wiring located at one side of the gate line and extending along the first direction, and an auxiliary gate line located between the gate line and the third common wiring and extending along the first direction; the plurality of transistors comprises: a first transistor, a second transistor, and a third transistor; The control electrode of the first transistor is electrically connected to the gate line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the first sub-pixel electrode. catch; The control electrode of the second transistor is electrically connected to the gate line, the first electrode of the second transistor is electrically connected to the data line, and the second electrode of the second transistor is electrically connected to the second sub-pixel electrode and the third sub-pixel electrode; The control electrode of the third transistor is electrically connected to the auxiliary gate line, the first electrode of the third transistor reuses the second electrode of the first transistor, and the orthographic projection of the second electrode of the third transistor on the substrate has an overlapping area with the orthographic projection of the first common line on the substrate.

18. The array substrate according to claim 3, 16 or 17, wherein: The pixel electrode further includes: a connecting portion connecting the first sub-pixel electrode and the fourth sub-pixel electrode, and a first overlapping portion connected to the connecting portion; the connecting portion includes: a third connecting portion, a fourth connecting portion, and a fifth connecting portion extending along the first direction; One end of the third connection portion is connected to the first sub-pixel electrode, one end of the fourth connection portion is connected to the fourth sub-pixel electrode, one end of the fifth connection portion is connected to the other end of the third connection portion, and the other end of the fifth connection portion is connected to the other end of the fourth connection portion; the first lap portion is electrically connected to the third connection portion and is away from a side of the connected first sub-pixel electrode; The second electrode of the first transistor is electrically connected to the first sub-pixel electrode and the fourth sub-pixel electrode through the first overlapping portion.

19. The array substrate according to claim 18, wherein: The control electrode of the third transistor is electrically connected to the gate line; at least a portion of the orthographic projection of the third transistor on the substrate and at least a portion of the orthographic projection of the first transistor on the substrate are located on different sides of the orthographic projection of the fifth connecting portion on the substrate.

20. The array substrate according to claim 18 or 19, wherein: The pixel electrode further includes: a first transition portion extending along the first direction, a second transition portion extending along the second direction, and a second overlap portion; One end of the first adapter is electrically connected to one end of the second sub-pixel electrode facing the fourth sub-pixel electrode, and the other end of the first adapter is electrically connected to one end of the second adapter. The other end of the second transition portion is electrically connected to the second overlap portion; The second electrode of the second transistor is electrically connected to the second sub-pixel electrode through the second connecting portion.

21. The array substrate according to claim 20, wherein: The fifth connecting portion extends along the second direction; the second transition portion is parallel to an extending direction of the fifth connecting portion.

22. The array substrate according to claim 18, wherein: The control electrode of the third transistor is electrically connected to the auxiliary gate line; at least part of the orthographic projection of the third transistor on the substrate and at least part of the orthographic projection of the first transistor on the substrate are located on the same side of the orthographic projection of the fifth connecting portion on the substrate.

23. The array substrate according to claim 22, wherein: The fifth connection portion includes: a first sub-connection portion, a second sub-connection portion, and a third sub-connection portion; The first sub-connection portion extends along a third direction, one end of which is electrically connected to the other end of the third connection portion, and the other end of which is electrically connected to the second sub-connection portion; the third direction intersects the first direction and the second direction; The second sub-connection portion extends along the second direction, and the other end of the second sub-connection portion is electrically connected to one end of the third sub-connection portion; The third sub-connection portion extends along the third direction, and the other end of the third sub-connection portion is electrically connected to the other end of the fourth connection portion.

24. The array substrate according to claim 22 or 23, wherein: The pixel electrode further includes: a first transition portion extending along the fourth direction, a second transition portion extending along the second direction, and a second overlap portion; One end of the first adapter portion is electrically connected to one end of the second sub-pixel electrode facing the fourth sub-pixel electrode, the other end of the first adapter portion is electrically connected to one end of the second adapter portion; the other end of the second adapter portion is electrically connected to the second lap portion; The second electrode of the second transistor is electrically connected to the second sub-pixel electrode through the second connecting portion.

25. The array substrate according to any one of claims 18 to 24, wherein: The pixel electrode further includes: a third transition portion extending along the first direction, and a third overlap portion; One end of the third adapter portion is electrically connected to one end of the third sub-pixel electrode facing the first sub-pixel electrode, and the other end of the third adapter portion is electrically connected to the third bridging portion; The second electrode of the second transistor is electrically connected to the third sub-pixel electrode through the third bridging portion.

26. The array substrate according to claim 25, wherein: A first gap is formed between the third connecting portion and the first pixel electrode; a second gap is formed between the fourth connecting portion and the second pixel electrode; A third gap is formed between the first transition portion and the first pixel electrode, and a fourth gap is formed between the third transition portion and the second pixel electrode.

27. The array substrate according to any one of claims 18 to 21, wherein: The array substrate further includes: a fourth overlapping portion; and the second electrode of the third transistor is electrically connected to the first common wiring through the fourth overlapping portion.

28. The array substrate according to claim 27, wherein: The fourth overlapping portion has a fourth overlapping portion outer edge along the first direction, the second overlapping portion has a second overlapping portion outer edge extending along the first direction; the first overlapping portion has a first overlapping portion outer edge extending along the second direction, and the third overlapping portion has a third overlapping portion outer edge extending along the second direction; The extension line of the outer edge of the fourth overlapping portion coincides with the extension line of the outer edge of the second overlapping portion; the extension line of the outer edge of the first overlapping portion coincides with the extension line of the outer edge of the third overlapping portion.

29. The array substrate according to any one of claims 25 to 28, wherein: The second electrode of the first transistor includes: a first transistor first portion extending along the first direction; An orthographic projection of the first portion of the first transistor on the substrate has an overlapping area with an orthographic projection of the first overlapping portion on the substrate.

30. The array substrate according to any one of claims 25 to 29, wherein: The second electrode of the second transistor includes: a second transistor first portion extending along the first direction, and a second transistor second portion extending along the second direction and electrically connected to one end of the second transistor first portion; The orthographic projection of the first portion of the second transistor on the substrate and the third overlapping portion on the substrate The orthographic projection of the substrate has an overlapping area; the orthographic projection of the second portion of the second transistor on the substrate has an overlapping area with the orthographic projection of the second overlapping portion on the substrate.

31. The array substrate according to claim 1, wherein: The array substrate further comprises: a plurality of transistors; the plurality of transistors electrically connected to the same pixel electrode are all electrically connected to the same data line and the same gate line; The second sub-pixel electrode is located on a side of the first sub-pixel electrode away from the electrically connected data line, and the fourth sub-pixel electrode is located on a side of the third sub-pixel electrode away from the electrically connected data line; the first sub-pixel electrode is electrically connected to the third sub-pixel electrode, and the second sub-pixel electrode is electrically connected to the fourth sub-pixel electrode.

32. The array substrate according to claim 30, wherein: The array substrate further comprises: a first signal line extending along the second direction; the plurality of transistors comprises: a first transistor, a second transistor, and a third transistor; The control electrode of the first transistor is electrically connected to the gate line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the first sub-pixel electrode; The control electrode of the second transistor is electrically connected to the gate line, the first electrode of the second transistor is electrically connected to the data line, and the second electrode of the second transistor is electrically connected to the fourth sub-pixel electrode; The control electrode of the third transistor is electrically connected to the gate line, the first electrode of the third transistor multiplexes with the second electrode of the second transistor, and the second electrode of the third transistor multiplexes with the first signal line.

33. The array substrate according to claim 31 or 32, wherein: The pixel electrode further includes: a connecting portion; the connecting portion extends along the second direction and connects the first sub-pixel electrode and the third sub-pixel electrode.

34. The array substrate according to any one of claims 31 to 33, wherein: The pixel electrode further comprises: a connecting portion; the connecting portion comprises: a first connecting portion and a second connecting portion; the connecting portion connects the second sub-pixel electrode and the fourth sub-pixel electrode; The first connecting portion extends along the first direction, one end of which is electrically connected to the second sub-pixel electrode, and the other end of which is electrically connected to one end of the second connecting portion; The other end of the second connecting portion is electrically connected to the fourth sub-pixel electrode.

35. The array substrate according to any one of claims 31 to 34, wherein: The first pixel electrode has a notch on a side facing the gate line; at least a portion of the connecting portion on the orthographic projection of the substrate is located at the orthographic projection of the notch on the substrate.

36. The array substrate according to any one of claims 31 to 35, wherein: The pixel electrode further includes: a first sub-pixel electrode protrusion connected to the first sub-pixel electrode facing the third sub-pixel electrode; the second electrode of the first transistor is electrically connected to the first sub-pixel electrode through the first sub-pixel electrode protrusion; The pixel electrode further includes: a fourth sub-pixel electrode protrusion connected to the fourth sub-pixel electrode facing the first sub-pixel electrode; and a second electrode of the second transistor is electrically connected to the fourth sub-pixel electrode through the fourth sub-pixel electrode protrusion.

37. The array substrate according to claim 36, wherein: The orthographic projections of the first sub-pixel electrode convex portion and the fourth sub-pixel electrode convex portion on the substrate are both located between the orthographic projection of the connecting portion on the substrate and the orthographic projection of the connecting portion on the substrate.

38. The array substrate according to claim 36 or 37, wherein: The first sub-pixel electrode convex portion has a first sub-pixel electrode convex portion outer edge extending along the second direction; an extension line of the first sub-pixel electrode convex portion outer edge at least partially overlaps with the fourth sub-pixel electrode convex portion.

39. The array substrate according to any one of claims 2 to 15 and 31 to 38, wherein: The array substrate further includes: a first common wiring located at one side of the gate line and extending along the first direction; the first common wiring is disconnected at a position where it intersects with the data line.

40. The array substrate according to any one of claims 16 to 39, wherein: The array substrate further comprises: a second common wiring group electrically connected to the first common wiring and extending to a side away from the gate line, the second common wiring group comprising: two second common wirings; The orthographic projection of the data line on the substrate and the gap between two second common lines of the same second common line group on the substrate have an overlapping area.

41. The array substrate according to claim 40, wherein: The array substrate further includes: a third common wiring located at the other side of the gate line and extending along the first direction, and a fourth common wiring group connected to the third common wiring and extending away from the gate line; The third common routing line is disconnected at a position where it crosses the data line; the fourth common routing line group includes: two fourth common routing lines; the orthographic projection of the data line on the substrate and the gap between the two fourth common routing lines of the same fourth common routing line group have an overlapping area on the orthographic projection of the substrate.

42. The array substrate according to claim 40 or 41, wherein: The array substrate further includes: a fifth common line extending along the first direction and electrically connected to the second common line, wherein the orthographic projection of the fifth common line on the substrate passes through a central area of ​​the orthographic projection of the second pixel electrode on the substrate.

43. The array substrate according to any one of claims 40 to 42, wherein: The array substrate further includes: a sixth common line extending along the first direction and electrically connected to the fourth common line, wherein the orthographic projection of the sixth common line on the substrate passes through a central area of ​​the orthographic projection of the first pixel electrode on the substrate.

44. The array substrate according to any one of claims 1 to 43, wherein: The first sub-pixel electrode and the second sub-pixel electrode each include: a first sub-electrode portion and a second sub-electrode portion distributed along the second direction; the third sub-pixel electrode and the fourth sub-pixel electrode each include: a third sub-electrode portion and a fourth sub-electrode portion distributed along the second direction; The first sub-electrode portion, the second sub-electrode portion, the third sub-electrode portion, and the fourth sub-electrode portion all have a plurality of slits; and an extension direction of the slits of the first sub-electrode portion is the same as an extension direction of the slits of the fourth sub-electrode portion; and an extension direction of the slits of the second sub-electrode portion is the same as an extension direction of the slits of the third sub-electrode portion.

45. The array substrate according to claim 44, wherein: The length of the slit in a direction perpendicular to the extending direction may be 2 μm to 4 μm.

46. ​​The array substrate according to claim 44 or 45, wherein: The orthographic projection shapes of the first sub-pixel electrode, the second sub-pixel electrode, the third sub-pixel electrode, and the fourth sub-pixel electrode on the substrate are all rectangular.

47. The array substrate according to claim 44 or 45, wherein: The orthographic projection shapes of the first sub-electrode portion, the second sub-electrode portion, the third sub-electrode portion, and the fourth sub-electrode portion on the substrate are all trapezoidal; In the first sub-pixel electrode and the fourth sub-pixel electrode, the first trapezoidal sub-electrode portion and the second trapezoidal sub-electrode portion are arranged opposite to each other with their top sides; in the second sub-pixel electrode and the third sub-pixel electrode, the first trapezoidal sub-electrode portion and the second trapezoidal sub-electrode portion are arranged opposite to each other with their bottom sides.

48. The array substrate according to claim 44 or 45, wherein: The orthographic projection shapes of the first sub-electrode portion, the second sub-electrode portion, the third sub-electrode portion, and the fourth sub-electrode portion on the substrate are all trapezoidal; In the first sub-pixel electrode and the fourth sub-pixel electrode, the first trapezoidal sub-electrode portion and the second trapezoidal sub-electrode portion are arranged opposite to each other with their bottom sides; in the second sub-pixel electrode and the third sub-pixel electrode, the first trapezoidal sub-electrode portion and the second trapezoidal sub-electrode portion are arranged opposite to each other with their top sides.

49. The array substrate according to claim 44 or 45, wherein: The first sub-pixel electrode comprises: a first main portion extending and connected along the second direction, a second main portion, and a first side portion extending along the first direction, a plurality of first branches extending along a fourth direction from the first main portion and the first side portion, and a plurality of second branches extending along a fifth direction from the second main portion and the first side portion; the second sub-pixel electrode comprises: a third main portion extending and connected along the second direction, a fourth main portion, a fifth main portion connected to one end of the third main portion and extending along the first direction, a sixth main portion connected to one end of the fourth main portion and extending along the first direction, a plurality of third branches extending along the fourth direction from the third main portion and the fifth main portion, and a plurality of fourth branches extending along the fifth direction from the fourth main portion and the sixth main portion; the plurality of first branches are interdigitated with the plurality of third branches, and the plurality of second branches are interdigitated with the plurality of fourth branches; The third sub-pixel electrode includes: a seventh main portion extending and connected along the second direction, a Eight main parts, a ninth main part connected to one end of the seventh main part and extending along the first direction, a tenth main part connected to one end of the eighth main part and extending along the first direction, a plurality of fifth branches extending from the seventh main part and the ninth main part along the fourth direction, and a plurality of sixth branches extending from the eighth main part and the tenth main part along the fifth direction; the fourth sub-pixel electrode includes: an eleventh main part extending and connected along the second direction, a twelfth main part, and a second side part extending along the first direction, a plurality of seventh branches extending from the eleventh main part and the second side part along the fourth direction, and a plurality of eighth branches extending from the twelfth main part and the second side part along the fifth direction; the plurality of fifth branches are interdigitated with the plurality of seventh branches, and the plurality of sixth branches are interdigitated with the plurality of eighth branches.

50. The array substrate according to any one of claims 1 to 49, wherein: The array substrate further comprises: a first conductive layer located on the side of the pixel electrode facing the substrate; the first conductive layer has a first hollow, a second hollow, a third hollow, and a fourth hollow; The first hollowing out overlaps at least part of the orthographic projection of the substrate with at least part of the orthographic projection of the first sub-pixel electrode on the substrate; the second hollowing out overlaps at least part of the orthographic projection of the substrate with at least part of the orthographic projection of the second sub-pixel electrode on the substrate; the third hollowing out overlaps at least part of the orthographic projection of the substrate with at least part of the orthographic projection of the third sub-pixel electrode on the substrate; the fourth hollowing out overlaps at least part of the orthographic projection of the substrate with at least part of the orthographic projection of the fourth sub-pixel electrode on the substrate.

51. A display panel, wherein: include: The array substrate according to any one of claims 1 to 50 further comprises an opposing substrate arranged opposite to the array substrate, wherein the opposing substrate is provided with a common electrode layer.

52. The display panel according to claim 51, wherein: The display panel further includes a liquid crystal layer located between the array substrate and the opposite substrate; The liquid crystal layer comprises: a plurality of liquid crystal sections, at least one of the plurality of liquid crystal sections comprises: a first sub-liquid crystal section, a second sub-liquid crystal section, a third sub-liquid crystal section, and a fourth sub-liquid crystal section; the orthographic projection of the liquid crystal section on the substrate overlaps with the orthographic projection of the pixel electrode on the substrate; the orthographic projection of the first sub-liquid crystal section on the substrate overlaps with the orthographic projection of the first sub-electrode section on the substrate The orthographic projections of the second sub-liquid crystal portion on the substrate overlap with the orthographic projection of the second sub-electrode portion on the substrate; the orthographic projection of the third sub-liquid crystal portion on the substrate overlaps with the orthographic projection of the third sub-electrode portion on the substrate; the orthographic projection of the fourth sub-liquid crystal portion on the substrate overlaps with the orthographic projection of the fourth sub-electrode portion on the substrate; An initial alignment direction of the first sub-liquid crystal section, an initial alignment direction of the second sub-liquid crystal section, an initial alignment direction of the third sub-liquid crystal section, and an initial alignment direction of the fourth sub-liquid crystal section are different from each other.

53. The display panel according to claim 52, wherein: The angle range between the initial alignment direction of the first sub-liquid crystal section and the first direction is 210°~240°; the angle range between the initial alignment direction of the second sub-liquid crystal section and the first direction is 120°~150°; the angle range between the initial alignment direction of the third sub-liquid crystal section and the first direction is 300°~330°; the angle range between the initial alignment direction of the fourth sub-liquid crystal section and the first direction is 30°~60°.

54. The display panel according to claim 52 or 53, wherein: The alignment direction of at least part of the liquid crystals at the junction of the first sub-liquid crystal portion and the second sub-liquid crystal portion is opposite to the alignment direction of at least part of the liquid crystals at the junction of the third sub-liquid crystal portion and the fourth sub-liquid crystal portion.

55. A display device, wherein: Comprising a display panel as described in any one of claims 51-54.

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