Data protection techniques in stacked memory architectures

Abstract

Methods, systems, and apparatus are described for data protection techniques in stacked memory architectures. A memory system having a stacked memory architecture may include error correction information associated with a data set that includes a plurality of data segments stored across a plurality of memory arrays and in some instances across a plurality of dies of the memory system. As part of a write operation for a first data segment of a dataset, the memory system may retrieve remaining data segments of the dataset and calculate error correction information using the first data segment and the remaining data segments. As part of a read operation for a second data segment of the data set, the memory system may retrieve each data segment of the data set and perform an error correction operation on the data set using the error correction information.

Description

[0001] Cross Reference

[0002] This patent application claims priority to U.S. patent application No. 18 / 762,284, filed by Keeth et al. on July 2, 2024, entitled “DATA PROTECTION TECHNIQUES IN STACKED MEMORY ARCHITECTURES,” and U.S. Provisional Application No. 63 / 535,128, filed by Keeth et al. on August 29, 2023, entitled “DATA PROTECTION TECHNIQUES INSTACKED MEMORY ARCHITECTURES,” each of which is assigned to its assignee and the entire contents of each of which are expressly incorporated herein by reference. Technical Field

[0003] The following relates to one or more systems for memory, including data protection techniques in a stacked memory architecture. Background Art

[0004] Memory devices are used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell is programmable to one of two supported states, typically represented by a logical 1 or a logical 0. In some examples, a single memory cell may support more than two states, either of which may be stored by the memory cell. To store information, a memory device may write (e.g., program, set, assign) a state to a memory cell. To access stored information, a memory device may read (e.g., sense, detect, retrieve, determine) a state from a memory cell.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selection memory, chalcogenide memory technology, NOR and NAND memory devices, and others. Memory cells can be described in terms of volatile configurations or non-volatile configurations. Memory cells in non-volatile configurations can maintain a stored logic state for a long time, even in the absence of external power. Memory cells in volatile configurations lose their stored state when disconnected from external power. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 An example of a system supporting data protection techniques in a stacked memory architecture according to examples disclosed herein is presented.

[0007] Figure 2 An example of a system supporting data protection techniques in a stacked memory architecture according to examples disclosed herein is presented.

[0008] Figure 3 and 4 An example of an interface architecture supporting data protection techniques in a stacked memory architecture according to examples disclosed herein is presented.

[0009] Figure 5A and 5B An example of a data set supporting data protection techniques in a stacked memory architecture according to examples disclosed herein is presented.

[0010] Figure 6 A block diagram showing logic blocks supporting data protection techniques in a stacked memory architecture according to examples disclosed herein.

[0011] Figures 7 to 9 A flow chart illustrating a method of supporting data protection techniques in a stacked memory architecture according to examples disclosed herein is shown. DETAILED DESCRIPTION

[0012] Some memory systems may include a semiconductor die stack, which includes one or more memory dies (e.g., array dies) stacked with a logic die, which is operable to access a set of memory arrays distributed across one or more memory dies. This stacked architecture may be implemented as part of a tightly coupled dynamic random access memory (TCDRAM) system, and may support solutions for memory-centric logic, such as a graphics processing unit (GPU) and other implementations. In some examples, the TCDRAM system may be tightly coupled (e.g., physically coupled, electrically coupled, directly coupled) to a processor (e.g., a GPU or other host) as part of a physical memory map accessible to the processor. This coupling may include one or more processors implemented in the same semiconductor die as at least a portion of the TCDRAM system (e.g., as part of a logic die) or one or more processors implemented in a die that is directly coupled (e.g., fused) to another die that includes at least a portion of the TCDRAM system or otherwise coupled to another die that includes at least a portion of the TCDRAM system (e.g., via a silicon interposer or other interposer component). Unlike cache-based memory, the TCDRAM system cannot be supported by an external memory hierarchy with the same physical address. For example, a TCDRAM system may be associated with and located within a dedicated base address, wherein each portion of the TCDRAM system may not overlap within the address.

[0013] A stacked memory architecture (e.g., a TCDRAM system) can store data sets, such as codewords or data stripes, across multiple memory arrays associated with one or more semiconductor dies. In some instances, the data set can be organized into multiple segments (e.g., each associated with a corresponding memory array, each associated with a corresponding memory die), and each segment can be protected using a set of corresponding error correction information, parity bits, or both. However, in some instances, a specific die of the system or a channel between a die and a logic block of the system may be damaged or otherwise associated with an error within a segment of the data set. Because the size of the error within the segment may exceed the error detection or correction capability of the error correction information, this damaged die or channel may cause an uncorrectable error within the data set. In some cases, addresses affected by a damaged die or channel may be marked as defective (e.g., mapped out), which may improve some aspects of the system's ability to avoid errors (e.g., in the long run, after marking or avoiding damaged dies or channels). However, this may reduce the system's memory capacity or may make the data susceptible to errors (e.g., in the short term, before marking a damaged die or channel).

[0014] According to examples disclosed herein, a memory system having a stacked memory architecture may support data protection techniques (e.g., error control techniques) associated with data sets, each of which includes multiple data segments stored across multiple memory arrays and, in some instances, across multiple dies of the memory system. For example, as part of a write operation for a first data segment of a data set, the memory system may retrieve the remaining data segments of the data set and calculate error correction information using the first data segment and the remaining data segment. In some other instances, the memory system may not retrieve the remaining data segments of the data set and may instead retrieve and modify the error correction information using the first data segment. As part of a read operation for a second data segment of the data set, the memory system may retrieve each data segment of the data set and use the error correction information to perform an error correction operation on the data set. By supporting data protection techniques associated with data sets that are each stored across multiple memory arrays and, in some instances, across multiple dies (e.g., tightly coupled dies, directly coupled dies), the memory system may support improving the integrity of stored data, improving data correction capabilities, and improving reliability and repair techniques, thereby further improving system performance, such as improving the throughput of the stacked memory architecture and reducing its latency.

[0015] Features of the present disclosure are illustrated and described in the context of systems and dies. Features of the present disclosure are further illustrated and described in the context of interface architectures, data channels, and flow charts.

[0016] Figure 1 An example of a system 100 supporting data protection techniques in a stacked memory architecture according to examples disclosed herein is shown. The system 100 may include a portion of an electronic device, such as a computing device, a mobile computing device, a wireless communication device, a graphics processing device, a vehicle, or other system. The system 100 includes a host system 105, a memory system 110, and one or more channels 115 (e.g., for providing a communicative coupling) coupling the host system 105 and the memory system 110. The system 100 may include one or more memory systems 110, but aspects of the one or more memory systems 110 may be described in the context of a single memory system 110.

[0017] The host system 105 may be an example of a processing system (e.g., circuitry, one or more processors, an application processing system, a processing circuitry, one or more processing components) that uses memory to perform processes (e.g., applications, functions, calculations), such as a computing device, a mobile computing device, a wireless communication device, a graphics processing device, a wearable device, an Internet connection device, a vehicle controller, a single chip system (SoC), or other fixed or portable electronic devices, among other examples. The host system 105 may include one or more of an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or other components (e.g., peripheral components, input / output controllers not shown). The components of the host system 105 may be coupled to each other using a bus 135.

[0018] The external memory controller 120 may be configured to enable information (e.g., data, commands, control information, configuration information) communication between components of the system 100 (e.g., between components of the host system 105 (e.g., the processor 125) and the memory system 110). For example, the external memory controller 120 may generate commands to write data to or read data from the memory system 110 or otherwise communicate with the memory system 110 (e.g., in response to or otherwise in support of an application of the host system 105). The external memory controller 120 may process (e.g., convert, translate) communications exchanged between the host system 105 and the memory system 110. In some examples, the external memory controller 120 or other components of the system 100 or associated functionality described herein may be implemented by or be part of the processor 125. For example, the external memory controller 120 may be hardware, firmware, or software (e.g., instructions), or some combination thereof, implemented by the processor 125 or other components of the system 100 or the host system 105. Although the external memory controller 120 is illustrated as being external to the memory system 110, in some examples, the external memory controller 120 or its functionality described herein may be implemented by one or more components of the memory system 110 (e.g., the memory system controller 155, the local memory controller 165), or vice versa. In various examples, the host system 105 or the external memory controller 120 may be referred to as a host.

[0019] Processor 125 is operable to provide functionality (e.g., control functionality, processing functionality) for system 100 or host system 105. Processor 125 may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof (e.g., as one or more processing components that are individually or collectively configured to support an application of host system 105). In some examples, processor 125 may be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or a SoC, among other examples.

[0020] In some examples, the system 100 or the host system 105 may include an input component, an output component, or a combination thereof. The input component may include a sensor, a microphone, a keyboard, another processor (e.g., on a printed circuit board), an interface (e.g., a user interface, an interface between other devices), or a peripheral device that interfaces with the system 100 via one or more peripheral components, as well as other examples. The output component may include a display, an audio speaker, a printing device, another processor on a printed circuit board, or a peripheral device that interfaces with the system 100 via one or more peripheral components, as well as other examples.

[0021] The memory system 110 may be a component of the system 100 operable to provide physical memory locations (e.g., addresses) that may be used or referenced by the system 100 (e.g., by the host system 105). The memory system 110 may include a memory system controller 155 and one or more memory dies 160 (e.g., memory chips) for supporting data storage capacity. The memory system 110 may be configured to cooperate with one or more different types of host systems 105, and may respond to and execute commands provided by the host system 105 (e.g., via the external memory controller 120). For example, the memory system 110 (e.g., the memory system controller 155) may receive a write command indicating that the memory system 110 will store data received from the host system 105, or receive a read command indicating that the memory system 110 will provide data stored in the memory die 160 to the host system 105, or receive a refresh command indicating that the memory system 110 will refresh data stored in the memory die 160, as well as other types of commands and operations.

[0022] The memory system controller 155 may include components (e.g., circuitry, logic, instructions) operable to control the operation of the memory system 110. The memory system controller 155 may include hardware, firmware, or instructions that enable the memory system 110 to perform various operations, and may be operable to receive, transmit, or execute commands, data, or control information related to the operation of the memory system 110. The memory system controller 155 may be operable to communicate with one or more of the external memory controller 120, one or more memory dies 160, or the processor 125. In some examples, the memory system controller 155 may cooperate with the local memory controller 165 of the memory die 160 to control the operation of the memory system 110.

[0023] Each memory die 160 may include one or more local memory controllers 165 and one or more memory arrays 170. A memory array 170 may be a collection of memory cells, each of which may be operable to store one or more bits of data. A memory array 170 may include a two-dimensional (2D) array of memory cells or a three-dimensional (3D) array of memory cells. In some examples, a two-dimensional (2D) memory die 160 may include a single memory array 170. In some examples, a three-dimensional (3D) memory die 160 may include two or more memory arrays 170, which may be stacked on top of each other or positioned side-by-side with each other (e.g., relative to a substrate).

[0024] The local memory controller 165 may include components (e.g., circuitry, logic, instructions) operable to control the operation of the memory die 160. In some examples, the local memory controller 165 may be operable to communicate (e.g., receive or transmit data or commands or both) with the memory system controller 155. In some examples, the memory system 110 may not include a memory system controller 155, and the local memory controller 165 or the external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 may be operable to communicate with the memory system controller 155, with other local memory controllers 165, or directly with the external memory controller 120 or the processor 125, or any combination thereof. Examples of components that may be included in the memory system controller 155 or the local memory controller 165 or both may include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transmitting signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, a sensing component for sensing the state of memory cells of the memory array 170, a writing component for writing states to memory cells of the memory array 170, or various other components operable to support the described operations of the memory system 110.

[0025] The host system 105 (e.g., external memory controller 120) and the memory system 110 (e.g., memory system controller 155) may communicate information (e.g., data, commands, control information, configuration information) using one or more channels 115. Each channel 115 may be an example of a transmission medium that carries information, and each channel 115 may include one or more signal paths (e.g., transmission media, electrical conductors, conductive paths) between terminals associated with components of the system 100. For example, a channel 115 may be associated with a first terminal (e.g., including one or more pins, including one or more pads) at the host system 105 and a second terminal at the memory system 110. A terminal may be an example of a conductive input or output point of a device of the system 100, and a terminal may be operable to serve as part of a channel 115. In some implementations, at least the channel 115 between the host system 105 and the memory system 110 may include or be referred to as a host interface (e.g., a physical host interface). In some implementations, the host interface may include or be associated with interface circuitry (e.g., signal drivers, signal latches) at the host system 105 (e.g., at the external memory controller 120) or at the memory system 110 (e.g., at the memory system controller 155), or both.

[0026] In some examples, channels 115 (e.g., associated signal paths and terminals) may be dedicated to conveying one or more types of information. For example, channels 115 may include one or more command and address channels, one or more clock signal channels, one or more data channels, and other channels or combinations thereof. In some examples, signaling may be conveyed via channels 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of a signal may be recorded for each clock cycle (e.g., on either a rising or falling edge of a clock signal). In DDR signaling, two modulation symbols of a signal may be recorded for each clock cycle (e.g., on both a rising edge and a falling edge of a clock signal).

[0027] In some examples, at least a portion of the system 100 may implement a stacked die architecture in which multiple semiconductor dies are physically and communicatively coupled. In some such implementations, circuitry for accessing one or more memory arrays 170 (e.g., circuitry of the memory system 110) may be distributed among multiple semiconductor dies in a stack (e.g., a stack of multiple directly coupled semiconductor dies). For example, a first die may include a set of multiple first interface blocks (e.g., memory interface blocks, examples of first interface circuitry) and one or more second dies may include corresponding second interface blocks each coupled to the first interface block of the first die, each configured to access one or more memory arrays of the second die. In some examples, the system may include a controller (e.g., a memory controller, an interface controller, a host interface controller, at least a portion of the external memory controller 120) of a first interface block group for supporting access operations (e.g., for accessing one or more memory arrays 170) via each set of one or more first interface blocks. In some examples, such a controller may be located in the same first die as the first interface block.

[0028] In some examples, a plurality of semiconductor dies of a memory system 110 (e.g., a TCDRAM system) may include one or more array dies (e.g., a memory die 160) stacked with a logic die (e.g., which includes a host system 105, coupled with another die including the host system 105), the logic die including an interface block operable to access a set of memory arrays 170 distributed across one or more second dies. The memory system 110 having a stacked memory architecture may support data protection techniques associated with data sets, each of which includes a plurality of data segments stored across a plurality of memory arrays 170 and, in some examples, across a plurality of memory dies 160 of the memory system 110. For example, as part of a write operation for a first data segment of a data set (e.g., in response to a command from the host system 105), the memory system 110 may retrieve the remaining data segments of the data set and calculate error correction information using the first data segment and the remaining data segments. In some other examples, the memory system 110 may not retrieve the remaining data segments of the data set and may instead retrieve and modify error correction information using the first data segment. As part of the read operation for the second data segment of the data set, the memory system 110 can retrieve each data segment of the data set and use the error correction information to perform an error correction operation on the data set. By supporting data protection techniques associated with data sets that are each stored across multiple memory arrays 170 and, in some instances, across multiple memory dies 160, the memory system 110 can support improved integrity of stored data, improved data correction capabilities, and improved reliability and repair techniques, thereby further improving system performance, such as improving throughput and reducing latency of a stacked memory architecture.

[0029] In addition to being applied in the systems described herein, the management command techniques for stacked memory architectures may also be implemented to support artificial intelligence or machine learning applications and other types of computationally intensive applications. As the use of artificial intelligence increases to support machine learning, analysis, decision making, or other related applications, electronic devices may be expected to support artificial intelligence applications and processes. For example, artificial intelligence applications may be associated with accessing relatively large amounts of data for analytical purposes and may benefit from a memory system that can effectively and efficiently store relatively large amounts of data or access stored data relatively quickly. Implementation of the techniques described herein may support artificial intelligence and machine learning techniques by improving the integrity of data stored to multiple memory dies 160 (including by improving the error detection and correction capabilities of error correction information associated with codewords stored across multiple memory dies 160). Such techniques may improve the reliability of data stored in a memory array (e.g., a tightly coupled stack of array dies), thereby supporting high-performance host applications by increasing the throughput of a stacked memory architecture and reducing its latency.

[0030] Figure 2 An example of a system 200 (e.g., a semiconductor system, a system coupling semiconductor dies, a TCDRAM system) supporting data protection techniques in a stacked memory architecture according to examples disclosed herein is shown. System 200 illustrates an example of a die 205 (e.g., die 205-a, a semiconductor die, a logic die, a processor die, a host die) coupled with one or more dies 240 (e.g., dies 240-a-1 and 240-a-2, a semiconductor die, a memory die, an array die). Die 205 or die 240 can be formed using a corresponding semiconductor substrate (e.g., a crystalline semiconductor material substrate such as silicon, germanium, silicon-germanium, gallium arsenide, or gallium nitride) or a silicon-on-insulator (SOI) substrate (e.g., silicon on glass (SOG), silicon on sapphire (SOS)) or an epitaxial semiconductor material formed on another substrate, among other examples. Although the illustrated example of system 200 includes two dies 240, system 200 according to the described techniques may include any number of one or more dies 240 coupled to die 205, as well as other dies in stacked or other coupled arrangements. Furthermore, although the non-limiting examples of system 200 are generally described herein in terms of application to memory systems, memory subsystems, memory devices, or combinations thereof, examples of system 200 are not limited thereto. For example, aspects of the present disclosure may be equally applicable to any computing system, computing subsystem, processing system, processing subsystem, component, device, structure, or other type of system or subsystem used for applications such as data collection, data processing, data storage, networking, communications, power, artificial intelligence, single-chip systems, control, telemetry, sensing and monitoring, digital entertainment, or any combination thereof.

[0031] System 200 illustrates an example of interface circuitry between a host and memory (e.g., via a host interface, via a physical host interface) implemented in (e.g., distributed among) multiple semiconductor dies (e.g., a stack of directly coupled dies). For example, die 205-a may include a set of one or more interface blocks 220 (e.g., interface blocks 220-a-1 and 220-a-2, memory interface blocks), and each die 240 may include a set of one or more interface blocks 245 (e.g., access interface blocks) and one or more memory arrays 250 (e.g., die 240-a-1 includes interface block 245-a-1 coupled to a set of one or more memory arrays 250-a-1, die 240-a-2 includes interface block 245-a-2 coupled to a set of one or more memory arrays 250-a-2). Memory array 250 may be an example of memory array 170 and may include memory cells of various architectures, such as RAM, DRAM, SDRAM, SRAM, FeRAM, MRAM, RRAM, PCM, chalcogenide, NOR, or NAND memory cells, or any combination thereof.

[0032] Although the example of system 200 is illustrated as including one interface block 245 in each die 240, a die 240 in accordance with the described techniques may include any number of one or more interface blocks 245, each coupled to a set of corresponding one or more memory arrays 250 and each coupled to an interface block 220 of die 205. Thus, the interface circuitry of system 200 may include one or more interface blocks 220 of die 205, wherein each interface block 220 is coupled (e.g., in communication) with one or more interface blocks 245 of die 240 (e.g., external to die 205). In some examples, the coupled combination of interface blocks 220 and interface blocks 245 (e.g., coupled via a bus associated with one or more channels, such as one or more data channels, one or more control channels, one or more clock channels, one or more pseudo channels, or a combination thereof) may include or be referred to as a data path associated with a set of corresponding one or more memory arrays 250.

[0033] In some implementations, the die 205 may include a host processor 210. The host processor 210 may be an example of the host system 105 or a portion thereof (e.g., an aspect of the processor 125, the external memory controller 120, or both). The host processor 210 may be configured to perform operations that implement the storage of the memory array 250 (e.g., for supporting applications or other functions of the host system 105, which may request access to the memory array 250). For example, the host processor 210 may receive data read from the memory array 250 or may transmit data written to the memory array 250, or both (e.g., according to the application or other operation of the host processor 210). Additionally or alternatively, the host processor 210 may be external to the die 205, such as in another semiconductor die or other component that is coupled (e.g., communicatively coupled, directly coupled, bonded, coupled via another intervening component) to the die 205 via one or more contacts 212 (e.g., externally accessible terminals of the die 205).

[0034] The host processor 210 may be configured to perform signaling communication (eg, transmission, reception) with the interface block 220 via the host interface 216 (eg, physical host interface), which may implement reference Figure 1 In some examples, the host interface 216 can provide a communication coupling between the physical or functional boundaries of the host system 105 and the memory system 110. For example, the host processor 210 can be configured to communicate access signaling (e.g., control signaling, access command signaling, data signaling, configuration signaling) via the host interface 216 to support access operations (e.g., read operations, write operations) and other operations to the memory array 250. Although the example of the system 200 includes a single host interface 216, a system according to the described techniques can include any number of one or more host interfaces 216 for accessing the memory array 250 of the system.

[0035] In some examples, a respective host interface 216 may be coupled between a set of one or more interface blocks 220 (e.g., interface blocks 220-a-1 and 220-a-2) and a respective controller 215. The controller 215 may be an example of control circuitry (e.g., memory controller circuitry, host interface control circuitry) associated with the host system 105, and may be associated with a respective instance implementing one or more aspects of the external memory controller 120 or the memory system controller 155, or a combination thereof. For example, the controller 215 may be operable to respond to instructions (e.g., requests, commands) from the host processor 210 to access one or more memory arrays 250 to support functions or applications of the host processor 210, transmit associated commands (e.g., for one or more interface blocks 220) to access one or more memory arrays 250, or communicate data (e.g., write data, read data) with the host processor 210, as well as other functions.

[0036] In some examples, the one or more controllers 215 may be implemented in the die 205 (e.g., the same die that includes the one or more interface blocks 220), whether the host processor 210 is included in the die 205 or external to the die 205. In some other examples, the controller 215 or associated circuitry or functionality may be implemented external to the die 205 (e.g., in another die (not shown) coupled to the respective interface block 220 via respective terminals of each of the respective host interfaces 216), which may be in the same or a different die than the die that includes the host processor 210. The interface block 220 may be operated via a single controller 215 or by one or more of a set of multiple controllers 215 (e.g., according to a controller multiplexing scheme). In some other examples, aspects of the one or more controllers 215 may be included in the host processor 210 (e.g., as a memory interface of the host processor 210, as a memory interface of the host system 105).

[0037] Although in some examples the controller 215 may be directly coupled with one or more interface blocks 220 (not shown), in some other examples, the controller 215 (e.g., host interface 216) may be coupled with a set of multiple interface blocks 220 via a logic block 225 (e.g., logic circuitry for a channel set, logic circuitry for host interface 216, multiplexing circuitry). For example, the logic block 225 may be coupled with interface block 220-a-1 via bus 223-a-1 and with interface block 220-a-2 via bus 223-a-1. The controller 215 and one or more corresponding interface blocks 220 may communicate (e.g., cooperate) using the host interface 216 via the logic block 225 to perform one or more operations associated with accessing a set of corresponding one or more memory arrays 250 (e.g., scheduling operations, access operations, operations initiated by the host processor 210).

[0038] In some examples, the logic block 225, the controller 215, or the host interface 216, or a combination thereof, may be associated with a “channel set” corresponding to a plurality of memory arrays 250 (e.g., for parallel or otherwise coordinated access of the plurality of memory arrays 250). For example, such a channel set may be associated with a plurality of memory arrays 250 accessed via a single interface block 245, or a plurality of memory arrays 250 each accessed via a respective one of the interface blocks 245, or a plurality of memory arrays 250 each accessed via a respective one of the interface blocks 220, any of which may be associated with signaling via a single logic block 225, via a single host interface 216, or via a single controller 215. These and other configurations for implementing one or more channel sets in a system may support various techniques for parallel and high bandwidth data transfer, memory management operations, repair and replacement techniques, or power and thermal distribution and other techniques that exploit the described coupling of components and interfaces between multiple semiconductor dies (e.g., in accordance with a tightly coupled configuration of the system 200). In some examples, such techniques may be implemented in a manner that is transparent to host interface 216 or other aspects of host system 105 (eg, at or using logic block 225 ).

[0039] In some examples, the host interface 216 may include a set of respective one or more signal paths for each logic block 225 or interface block 220, such that the host processor 210 may communicate with each logic block 225 or interface block 220 via its corresponding set of signal paths (e.g., according to selection of a corresponding set of logic blocks 225 or interface blocks 220 for performing access operations via the selection of the host processor 210). Additionally or alternatively, the host interface 216 may include one or more signal paths shared between multiple logic blocks 225 (not shown) or interface blocks 220, and the logic blocks 225, interface blocks 220, or host processor 210, or any of these, may interpret, ignore, respond to, or suppress response signaling via the shared signal paths of the host interface 216 based on a logic indication (e.g., an addressing indication associated with the logic block 225 or interface block 220, an interface enable signal, or an interface select signal, which may be provided by the host processor 210, the corresponding logic block 225, or the corresponding interface block 220 depending on the signaling direction).

[0040] In some examples, the host processor 210 may determine an access address (e.g., a logical address of the memory array 250, a physical address of the memory array 250, an address of the logic block 225, an address of the interface block 220, an address of the host interface 216, in response to an application of the host processor 210 or an application supported by the host processor 210) and determine to which controller 215 to transmit access signaling for the access address (e.g., the controller 215, logic block 225, or interface block 220 corresponding to the address). In some examples, the address may be associated with a row of memory cells of the memory array 250, a column of memory cells of the memory array 250, or both. The host processor 210 may transmit access signaling (e.g., one or more access signals, one or more access commands) to determine the controller 215, and the determination controller 215 may in turn transmit the access signaling to the corresponding logic block 225 or interface block 220. The corresponding interface block 220 may then transmit access signaling to the coupling interface block 245 to access the determined address (eg, of the corresponding memory array 250 ).

[0041] The die 205 may also include a logic block 230 (e.g., a shared logic block, a central logic block, a common logic circuit system, an evaluation circuit system, a memory system configuration circuit system, a memory system management system) that may be configured to communicate (e.g., transmit, receive) signaling with the logic block 225, the interface block 220, or both of the die 205. In some cases, the logic block 230 may be configured to communicate information (e.g., commands, instructions, instructions, data) with one or more logic blocks 225 or interface blocks 220 to facilitate operation of the system 200. For example, the logic block 230 may be configured to transmit configuration signaling (e.g., initialization signaling, evaluation signaling, mapping signaling) that may be received by the logic block 225 or interface block 220 to support configuration of the logic block 225 or interface block 220 or other aspects of operating the die 240 (e.g., via a corresponding interface block 245). The logic block 230 may be coupled to each logic block 225 and each interface block 220 via a corresponding bus. In some examples, such buses may each include a set of respective one or more signal paths such that logic block 230 may communicate with each logic block 225 or each interface block 220 via a respective set of signal paths. Additionally or alternatively, such buses may include one or more signal paths (not shown) shared between multiple logic blocks 225 or interface blocks 220.

[0042] In some implementations, logic block 230 may be configured to communicate (e.g., transmit, receive) signals with host processor 210 (e.g., via a bus, via contacts 212 of host processor 210 external to die 205) such that logic block 230 may support an interface between host processor 210 and logic block 225 or interface block 220. For example, host processor 210 may be configured to transmit initialization signaling (e.g., boot commands) or other configuration or operational signaling, which may be received by logic block 230 to support initialization, configuration, evaluation, or other operations of logic block 225 or interface block 220. Additionally or alternatively, in some implementations, logic block 230 may be configured to communicate (e.g., transmit, receive) signals with components external to system 200 (e.g., via contacts 234, which may be externally accessible terminals of die 205) such that logic block 230 may support an interface that bypasses host processor 210. Additionally or alternatively, the logic block 230 may communicate with the host processor 210 and may communicate with one or more memory arrays 250 of the one or more dies 240 (e.g., for performing self-test operations on accesses to the memory arrays 250). In some examples, such implementations may support evaluation, configuration, or other operations of the system 200 via one or more contacts 234 accessible at a physical interface of the system during manufacturing, assembly, validation, or other operations associated with the system 200 (e.g., prior to coupling with the host processor 210, when the host processor 210 is not implemented, for operations independent of the host processor). Additionally or alternatively, the logic block 230 may implement one or more aspects of the controller 215. For example, the logic block 230 may include or operate as one or more controllers 215 and may perform operations attributed to the controller 215.

[0043] Each interface block 220 may be coupled to at least one respective bus 221 of die 205 and a respective bus 246 of die 240, the buses being configured to communicate signaling with the corresponding interface block 245 (e.g., via one or more associated signal paths). For example, interface block 220-a-1 may be coupled to interface block 245-a-1 via bus 221-a-1 and bus 246-a-1, and interface block 220-a-2 may be coupled to interface block 245-a-2 via bus 221-a-2 and bus 246-a-2. In some examples, die 240 may include a bus, such as bus 255, that bypasses the operational circuitry of die 240 (e.g., bypasses the interface block 245 of a given die 240). For example, interface block 220-a-2 may be coupled to interface block 245-a-2 of die 240-a-2 via bus 255-a-1 of die 240-a-1, which may bypass interface block 245 of die 240-a-1. Such techniques may be extended for interconnection between more than two dies 240 (e.g., for interconnection via respective buses 255 of multiple dies 240).

[0044] The respective signal paths of buses 221, 246, and 255 may be coupled to one another from one die to another via various arrangements of contacts at the surfaces of the interfacing dies (e.g., exposed contacts of the respective dies, metal surfaces). For example, bus 221-a-1 may be coupled to bus 246-a-1 via contacts 222-a-1 of die 205-a (e.g., at the surface of die 205) and contacts 247-a-1 of die 240-a-1, bus 221-a-2 may be coupled to bus 255-a-1 via contacts 222-a-2 of die 205 and contacts 256-a-1 of die 240-a-1, bus 255-a-1 may be coupled to bus 246-a-2 via contacts 257-a-1 of die 240-a-1 and contacts 247-a-2 of die 240-a-2, and so on. Although each respective bus is illustrated with a single line coupled via a singular contact, it should be understood that each signal path of a given bus may be associated with a respective contact to support separate communication coupling of each signal path via the given bus. In some examples, bus 255 may pass through a portion of die 240 (e.g., in an in-plane direction, along a direction different from the thickness direction, in a waterfall arrangement, in a staircase arrangement), which may support the arrangement of contacts 222 along the surface of die 205 and other contacts coupled to interface blocks 245 of different dies 240 along the stacking direction (e.g., via respective contacts 256 and 257 that do not overlap when viewed along the thickness direction).

[0045] The interconnection of the interface contacts may be supported by a variety of techniques. For example, in a hybrid bonding implementation, the interface contacts may be coupled by fusing the conductive material (e.g., electrically conductive material) of the interface contacts (e.g., without solder or other intervening material between the contacts). For example, in an assembled condition, the coupling of die 205-a with die 240-a-1 may include fusing the conductive material of contact 222-a-2 with the conductive material of contact 256-a-1, and the coupling of die 240-a-1 with die 240-a-2 may include fusing the conductive material of contact 257-a-1 with the conductive material of contact 247-a-2, and so on. In some examples, such coupling may include inoperable fusion of contacts (e.g., non-communicative coupling, physical coupling), such as fusion of contact 260-a-1 and contact 256-a-2, both of which are not coupled to the operable circuitry of die 240-a-1 or 240-a-2. In some examples, such techniques may be implemented to improve coupling strength or uniformity (e.g., implementing contact 260 that may not be operably coupled to interface block 245 or interface block 220), or such coupling may be a byproduct of duplication of components that may be operable or inoperable in various configurations. (For example, for a die 240 having contacts 256 and 257 arranged together, contacts 256-a-1 and 257-a-1 provide a communication path between interface block 245-a-2 and interface block 220-a-2, but contacts 256-a-2 and 257-a-2 do not provide a communication path between interface block 245 and interface block 220).

[0046] In some examples, the fusion of conductive material between the dies (e.g., between contacts) may be accompanied by fusion of other materials at one or more surfaces of the interfacing dies. For example, in an assembled condition, the coupling of die 205 with die 240-a-1 may include fusion of dielectric material 207 (e.g., non-conductive material) of die 205-a with dielectric material 242 of die 240-a-1, and the coupling of die 240-a-1 with die 240-a-2 may include fusion of dielectric material 242 of die 240-a-1 with dielectric material 242 of die 240-a-2. In some examples, such dielectric materials may include oxides, nitrides, carbides, oxide-nitrides, oxide-carbides, or other conversions or dopings of substrate materials (e.g., semiconductor substrate materials) of die 205 or die 240, as well as other materials that may support such fusion. However, the coupling between die 205 and die 240 may be implemented according to other techniques, which may implement solder, adhesives, thermal interface materials, and other intervening materials.

[0047] In some examples, the dies 240 may be coupled in a stack (e.g., to form a "cube" or other arrangement of dies 240), and one or more of such stacks may subsequently be coupled with the die 205 (e.g., in a stack-to-chip bonding arrangement). In some examples, respective groups of one or more dies 240 may be coupled with each die 205 of a plurality of dies 205 formed in a wafer (e.g., in a chip-to-wafer bonding arrangement, in a stack-to-wafer bonding arrangement, before dicing the wafer of dies 205), and the dies 205 of the wafer to which their respective groups of dies 240 are coupled may be separated from each other (e.g., by at least dicing the wafer of dies 205). In some other examples, respective groups of one or more dies 240 may be coupled with respective dies 205 after the dies 205 are separated from the wafer of dies 205 (e.g., in a chip-to-chip bonding arrangement). In some other examples, a set of one or more respective wafers, each including a plurality of dies 240, may be coupled into a stack (e.g., in a wafer-to-wafer bonding arrangement). In various examples, after such techniques, the stack of dies 240 may be separated from the coupled wafer, or the wafer stack with dies 240 may be coupled with another wafer including a plurality of dies 205 (e.g., in a second wafer-to-wafer bonding arrangement), after which the system 200 may be separated from the coupled wafer. In some other examples, the wafer-to-wafer coupling technique may be implemented by stacking one or more wafers of dies 240 (e.g., sequentially) on top of a wafer of dies 205 prior to separation into the system 200, as well as other examples for forming the system 200.

[0048] The buses 221, 246, and 255 may be implemented to provide configuration signaling (e.g., coordination signaling, logic signaling, modulation signaling, digital signaling) between the interface block 220 and the corresponding interface block 245, which may involve various modulation or coding techniques through the transmission interface block (e.g., via the driver component of the transmission interface block). In some examples, this signaling may be supported (e.g., accompanied) by clock signaling communicated (e.g., coordinated with the signal transmission) via the corresponding bus. For example, the bus may be configured to pass one or more clock signals transmitted by the interface block 220 for reception by the interface block 245 (e.g., for triggering a latch or other receiving component of the interface block 245 to receive a signal, for supporting the timing control operation of the interface block 245). Additionally or alternatively, the bus may be configured to pass one or more clock signals transmitted by the interface block 245 for reception by the interface block 220 (e.g., for triggering a latch or other receiving component of the interface block 220 to receive a signal, for supporting the timing control operation of the interface block 220). Such clock signals may be associated with communication (e.g., unidirectional communication, bidirectional communication, deterministic communication) of various signaling (e.g., control signaling, command signaling, data signaling, or any combination thereof). For example, a bus may include one or more signal paths for a data bus (e.g., one or more data lanes, a DQ bus, a data interface via an interface block) to communicate according to one or more corresponding clock signals (e.g., a data clock signal) or one or more signal paths for a control bus (e.g., a command / address (C / A) bus, a command interface via an interface block) to communicate according to one or more clock signals (e.g., a control clock signal), or any combination thereof.

[0049] Interface block 220, interface block 245, logic block 225, and logic block 230 may each include circuitry (signaling circuitry, multiplexing circuitry, processing circuitry, controller circuitry, logic circuitry, physical components, hardware) in various configurations (e.g., hardware configurations, logic configurations, software or instruction configurations) that support functionality assigned to the respective block for accessing or otherwise operating a set of corresponding memory arrays 250. For example, interface block 220 may include circuitry configured to perform a first subset of operations supporting access of memory arrays 250, and interface block 245 may include circuitry configured to perform a second subset of operations supporting access of memory arrays 250. In some examples, interface block 220, interface block 245, and logic block 225 may support functional partitioning or distribution of functionality associated with memory system controller 155, local memory controller 165, or both across multiple dies (e.g., die 205 and at least one die 240). In some implementations, logic block 230 may be configured to coordinate or configure aspects of the operation of interface block 220, interface block 245, logic block 225, or a combination thereof and may support one or more aspects of implementing memory system controller 155. Such operations or subsets of operations may include operations performed in response to commands from host processor 210 or controller 215 or operations performed without commands from host processor 210 or controller 215 (e.g., operations determined or initiated by logic block 225, operations determined or initiated by interface block 220, operations determined or initiated by interface block 245, operations determined or initiated by logic block 230), or various combinations thereof.

[0050] In some implementations, system 200 may include one or more instances of nonvolatile storage devices, such as nonvolatile storage device 235 of die 205, nonvolatile storage device 270 of one or more dies 240, or a combination thereof. In some examples, logic block 230, logic block 225, interface block 220, interface block 245, or a combination thereof may be configured to communicate signaling with the one or more instances of nonvolatile storage devices. For example, logic block 230, logic block 225, interface block 220, or interface block 245 may be suitably coupled to the one or more instances of nonvolatile storage devices via one or more buses (not shown) or corresponding contacts (not shown) that may each include one or more signal paths operable to convey signaling (e.g., command signaling, data signaling). In some examples, logic block 230, one or more logic blocks 225, one or more interface blocks 220, one or more interface blocks 245, or a combination thereof may configure one or more operations based on information (e.g., instructions, configurations, parameters) stored in one or more instances of non-volatile storage. Additionally or alternatively, in some examples, logic block 230, one or more logic blocks 225, one or more interface blocks 220, one or more interface blocks 245, or a combination thereof may write information (e.g., configuration information, evaluation information) stored in one or more instances of non-volatile storage. In some examples, such non-volatile storage may include fuses, antifuses, or other types of one-time programmable storage elements, or any combination thereof.

[0051] In some implementations, the system 200 may include one or more sensors (e.g., one or more sensors 237 of the die 205, one or more sensors 275 of the die 240, or a combination thereof). In some implementations, the logic block 230, the logic block 225, the interface block 220, the interface block 245, or a combination thereof may be configured to receive one or more indications based on measurements of the one or more sensors of the system 200. For example, the logic block 230, the logic block 225, the interface block 220, or the interface block 245 may be coupled to the one or more sensors via one or more buses (not shown) or corresponding contacts (not shown). Such sensors may include temperature sensors, current sensors, voltage sensors, counters, and other types of sensors. In some examples, the logic block 230, the one or more logic blocks 225, the one or more interface blocks 220, the one or more interface blocks 245, or a combination thereof may configure one or more operations based on the output of the one or more sensors. For example, the logic block 230 may configure one or more operations of the logic block 225 or the interface block 220 based on signaling (e.g., indication, data) received from one or more sensors. Additionally or alternatively, the logic block 225 or the interface block 220 may generate access signaling for transmission to the corresponding interface block 245 based on one or more sensors.

[0052] In some examples, the circuitry of logic block 225, interface block 220, interface block 245, or logic block 230, or any combination thereof, may include components (e.g., transistors) formed at least in part from doped portions of a substrate of a respective die. In some examples, the substrate of die 205 may have characteristics (e.g., materials, material properties, physical shapes, or dimensions) that are different from characteristics of a substrate of die 240. Additionally or alternatively, in some examples, transistors formed from the substrate of die 205 may have characteristics (e.g., manufacturing characteristics, performance characteristics, physical shapes, or dimensions) that are different (e.g., according to a different transistor architecture, according to a different transistor design) from transistors formed from the substrate of die 240.

[0053] In some examples, the interface block 220 may support a layout of one or more components within the interface block 220. For example, the layout may include paired components sharing access ports (e.g., command ports, data ports). In addition, in some examples, the layout may support an interface for the controller 215 (e.g., host interface 216) that is different from an interface for the interface block 245 (e.g., via bus 221). For example, the host interface 216 may be synchronous and have separate channels for read and write operations, while the interface between the interface block 220 and one or more interface blocks 245 may be asynchronous and support both read and write operations performed with the same channel. In some examples, the signaling of the host interface 216 may be implemented with a determination timing (e.g., a determination between the controller 215 and the logic block 225 or one or more interface blocks 220), which may be associated with a configuration timing between a first signal and a response second signal. In some examples, signaling between interface block 220 and one or more interface blocks 245 may be implemented with timing different from that of host interface 216 (eg, according to a different clock frequency, according to a timing offset, such as a phase offset), which may be deterministic or indeterminate.

[0054] The die 240 may include one or more cells 265 (e.g., modules) separated from a semiconductor wafer having a pattern (e.g., a two-dimensional pattern) of cells 265. Although each die 240 of the system 200 is illustrated as having a single cell 265 (e.g., cell 265-a-1 of die 240-a-1, cell 265-a-2 of die 240-a-2), a die 240 according to the described techniques may include any number of cells 265 that may be arranged in various patterns (e.g., groups of one or more cells 265 along a row direction, groups of one or more cells 265 along a column direction, and other patterns). Each cell 265 may include at least the circuitry of a corresponding interface block 245 and a memory array 250, a bus 251, a bus 246, and one or more contacts 247 corresponding to the corresponding interface block 245. In some examples, each unit 265 may also include one or more buses 255, contacts 256, contacts 257, or contacts 260 as appropriate (e.g., associated with respective interface blocks 245 of units 265 of different dies 240), which may support various degrees of stackability or modularity between or via units 265 of other dies 240. Although the examples of non-volatile storage 270 and sensors 275 are illustrated as being external to the unit 265, in some other examples, the non-volatile storage 270, sensors 275, or both may additionally or alternatively be included in the unit 265.

[0055] In some examples, the interface block 220 may include circuitry configured to receive first access command signaling (e.g., from the host processor 210, from the controller 215, from the logic block 225, via the host interface 216, from the host processor 210 or the controller 215 external to the die 205 via one or more contacts 212, based on a request from a host application) and transmit second access command signaling based on (e.g., in response to) the received first access command signaling to a respective (e.g., coupled) interface block 245. The interface block 245 may thus include circuitry configured to receive second access command signaling from the respective interface block 220 and, in some examples, access a respective set of one or more memory arrays 250 based on (e.g., in response to) the received second access command signaling. In various examples, the first access command signaling may include an access command associated with an operation type (e.g., a read operation, a write operation, a refresh operation, a memory management operation), which may be associated with an indication of an address (e.g., a logical address, a physical address) of one or more memory arrays 250. In some examples, the first access command signaling may include an indication of a logical address associated with the memory array 250, and the circuitry of the interface block 220 may be configured to generate a second access command signaling to indicate a physical address associated with the memory array 250 (e.g., a row address, a column address, using a logical-to-physical (L2P) table or other mapping or calculation functionality of the interface block 220).

[0056] In some examples, to support write operations of the system 200, the circuitry of the interface block 220 may be configured to receive (e.g., from the host processor 210, from the controller 215, from the logic block 225) a first data signaling associated with a first access command signaling and transmit a second data signaling (e.g., associated with a second access command signaling) based on the received first access command signaling and the first data signaling. The interface block 245 may therefore be configured to receive the second data signaling and write data to the one or more memory arrays 250 based on the received second access command signaling and the second data signaling (e.g., according to an indicated address associated with the first access command signaling). In some instances, interface block 220 may include error control functionality (e.g., error detection circuitry, error correction circuitry, error correction code (ECC) logic, an ECC engine) that supports interface block 220 in generating second data signaling based on performing error control operations using received first data signaling (e.g., detecting or correcting errors in the first data signaling, determining one or more parity bits conveyed in the second data signaling and written with the data).

[0057] In some examples, to support read operations of system 200, the circuitry of interface block 245 may be configured to read data from memory array 250 based on received second access command signaling and to transmit first data signaling based on the read data. Interface block 220 may thus be configured to receive first data signaling and to transmit second data signaling based on the received first data signaling (e.g., to host processor 210, to controller 215, to logic block 225). In some examples, interface block 220 may include error control functionality that enables interface block 220 to generate second data signaling based on performing error control operations using received first data signaling (e.g., detecting or correcting errors in the first data signaling, which may include calculations involving one or more parity bits received with the first data signaling).

[0058] In some examples, access command signaling and other signaling transmitted to the interface block 245 may be generated (e.g., based on access command signaling received from the host processor 210, based on start signaling received from the host processor 210, without receiving or otherwise independently of signaling from the host processor 210) according to various determination or generation techniques configured at the interface block 220 or logic block 225 (e.g., based on a configuration modified at the interface block 220 or logic block 225 for accessing the memory array 250). In some examples, such techniques may involve signaling or other coordination with the logic block 230, the logic block 225, the host processor 210, one or more controllers 215, one or more instances of non-volatile storage devices, one or more sensors, or any combination thereof. Such techniques may support the interface block 220 or logic block 225 in configuring aspects of access operations and other operations performed by the corresponding interface block 245 on the memory array 250. For example, interface block 220 or logic block 225 may include evaluation circuitry, access configuration circuitry, signaling circuitry, scheduling circuitry, repair circuitry, refresh circuitry, error control circuitry, adverse access (e.g., row hammer) mitigation circuitry, and other circuitry that is operable to configure operations associated with one or more dies (e.g., operations associated with accessing memory array 250 of die 240).

[0059] According to examples disclosed herein, the system 200 (e.g., one or more logic blocks 225) can support data protection techniques associated with data sets that each include multiple data segments stored across multiple memory arrays 250 and, in some examples, across multiple dies 240. For example, as part of a write operation for a first data segment of the data set (e.g., to a first memory array 250, via an interface block 245, via an interface block 220), the system 200 (e.g., logic block 225) can retrieve the remaining data segments of the data set (e.g., from one or more second memory arrays 250, via one or more other interface blocks 245, via one or more other interface blocks 220) and calculate error correction information using the first data segment and the remaining data segments. Alternatively, the system 200 (e.g., logic block 225) may not retrieve the remaining data segments of the data set and may instead retrieve and modify error correction information using the first data segment. As part of the read operation for the second data segment of the data set, the system 200 (e.g., logic block 225) can retrieve each data segment of the data set (e.g., from the corresponding memory array 250, via the corresponding interface block 245, via the corresponding interface block 220) and use the error correction information to perform an error correction operation on the data set. By supporting data protection techniques associated with data sets that are each stored across multiple memory arrays 250 and, in some instances, across multiple dies 240, the system 200 (e.g., logic block 225) can support improved integrity of stored data, improved data correction capabilities, and improved reliability and repair techniques, thereby further improving the performance of the system 200 that implements the stacked memory architecture to increase throughput and reduce latency thereof.

[0060] Figure 3 An example of an interface architecture 300 supporting data protection techniques in a stacked memory architecture according to examples disclosed herein is shown. Interface architecture 300 illustrates an example of an interface block 245-b (e.g., of die 240) coupled with an interface block 220-b (e.g., of die 205). Interface block 245-b may be communicatively coupled with interface block 220-b via one or more of bus 301, bus 302, bus 303, and bus 304, each of which may be an example of one or more signal paths of bus 221 and bus 246 as well as bus 255, as appropriate.

[0061] The interface block 245-b includes a control interface 310 (e.g., a command interface) that can be configured to communicate with the interface block 220-b for signaling. For example, the control interface 310 can include a circuit system (e.g., a receiver, one or more latches) configured to receive control signaling (e.g., modulation control signaling, access command signaling, configuration signaling, address signaling, such as row address signaling or column address signaling) via the bus 301-a. The control interface 310 can also include a circuit system configured to receive clock signaling (e.g., clock signaling associated with the control interface 310, clock signaling with one or more phases (e.g., true and complementary phases), dk_t / c signaling from the interface block 220-b) via the bus 302-a. The control interface 310 can use the bus 302-a to receive control signaling of the bus 301-a (e.g., for triggering one or more latches). The control interface 310 may transmit (eg, forward) control signaling and clock signaling (eg, for timing of other operations of the interface block 245 - b ) to the interface controller 320 .

[0062] The interface block 245-b also includes two data interfaces 330 (e.g., data interfaces 330-a-1 and 330-a-2), which may also be configured to communicate signaling with the interface block 220-b. Each data interface 330 may include a corresponding bus and circuitry, the operation of which may be associated with (e.g., controlled by, coordinated with, operated based on) control signaling via the control interface 310. Although the example of the interface block 245-b includes two data interfaces 330 associated with the control interface 310 (e.g., arranged in a "channel pair", arranged in a "pseudo-channel pair"), the techniques described for the interface block 245 may include any number of one or more data interfaces 330 and associated buses and circuitry for a given control interface 310 of the interface block 245.

[0063] Each data interface 330 may be associated with a corresponding data path circuit system, which may include corresponding first-in-first-out (FIFO) and serialization / deserialization (SERDES) circuit systems (e.g., FIFO / SERDES 340), corresponding write / sense circuit systems 350, corresponding synchronization and sequencing circuit systems (e.g., synchronization / sequencing logic 360), and corresponding timing circuit systems 370, as well as interconnect signal paths (e.g., one or more buses). However, in some other examples, the data path circuit systems may be arranged in a different manner or may include different circuit system components, which may include circuit systems dedicated to the corresponding data paths or shared between data paths or various combinations thereof. Each data interface 330 may also be associated with a set of corresponding one or more memory arrays 250. In some examples, each memory array 250 may be understood to include corresponding addressing circuit systems, such as memory bank logic or decoders (e.g., row decoders, column decoders) or memory cell sense amplifier circuit systems and other array circuit systems. However, in some other examples, at least a portion of this circuit system may be included in the interface block 245.

[0064] Each data interface 330 may include circuitry (e.g., one or more latches, one or more drivers) configured to communicate (e.g., receive, transmit) data signaling (e.g., modulated data signaling, DQ signaling) via the corresponding bus 303. Each data interface 330 may also include circuitry for communicating clock signaling via the corresponding bus 304, which may support the data interface 330 to receive a clock signal (e.g., a first clock signaling associated with the data interface 330, a clock signaling having one or more phases (e.g., true and complementary phases), DQS_t / c signaling from the interface block 220-b, clock signaling associated with a data reception or write operation) or the data interface 330 to transmit a clock signal (e.g., a second clock signaling associated with the data interface 330, RDQS_t / c signaling to the interface block 220-b, clock signaling associated with a data transmission or read operation), or both. In some examples, data interface 330, bus 303, or a combination of bus 303 and bus 304 may be associated with a "pseudo-channel," and multiple pseudo-channels may be associated with the same control interface 310 or the same control bus (e.g., bus 301, a combination of bus 301 and bus 302). In some implementations, pseudo-channels of multiple interface blocks 245 may be grouped together (e.g., functionally, logically, electrically, such as by hard-wired signal paths or multiplexing circuitry) to support a channel set (e.g., associated with a corresponding host interface 216). Each data interface 330 may transmit clock signaling (e.g., received clock signaling, DQS_t / c signaling) to synchronization / sequencing logic 360 via a respective bus (e.g., for timing of other operations of interface block 245-b).

[0065] The interface controller 320 may support various functionalities (e.g., control functionality or configuration functionality) of the interface block 245-b for accessing or otherwise managing the operation of the coupled memory array 250. For example, the interface controller 320 may support access command coordination or configuration, latency or timing compensation, access command buffering (e.g., according to a FIFO or other organizational scheme), mode registers or logic for configuration settings or test functionality (e.g., evaluation functionality, BIST functionality), and other functions or combinations thereof. For each data path of the interface block 245 (e.g., associated with a corresponding data interface 330), the interface controller 320 may be configured to transmit signaling (e.g., address signaling, such as a row address or row activation signaling) to the corresponding memory array 250 via a bus. For each data path of the interface block 245, the interface controller 320 may communicate signaling (eg, timing signaling (which may be based on clock signaling received from the control interface 310), configuration signaling) with the corresponding timing circuitry 370 and synchronization / sequencing logic 360 via a corresponding bus.

[0066] For each data path, a respective timing circuitry 370 may support timing of various operations (e.g., activation, coupling operations, signal latching, signal driving) relative to timing signaling received from the interface controller 320. For example, the timing circuitry 370 may include a timing chain (e.g., a global column timing chain) configured to generate one or more clock signals or other enable signals for controlling the operation of the respective data path, and such signaling may include transitions (e.g., rising edge transitions, falling edge transitions, on / off transitions) that are offset from, occur at a different rate from, or otherwise differ from transitions of the signaling from the interface controller 320 to support a given operation or combination of operations. For example, the timing circuitry 370 may be configured to transmit signaling (e.g., address signaling, such as column address or column activation signaling) to the respective memory array 250, transmit signaling (e.g., latch or driver timing signaling) to the respective write / sense circuitry 350, and transmit signaling (e.g., timing signaling) to the respective synchronization / sequencing logic.

[0067] For each data path, a respective FIFO / SERDES 340 may be configured to convert between data signaling of a first bus width (e.g., a relatively wider bus width, a data read / write (DRW) bus, a bus for communicating with a write / sense circuitry 350 having a relatively greater number of signal paths) and a second bus width (e.g., a relatively narrower bus width, a bus for communicating with a data interface 330 having a relatively lesser number of signal paths). In some examples, such conversion may be accompanied by changing the signaling rate between signaling from the data interface 330 and the write / sense circuitry 350 (e.g., for maintaining a given throughput). In various examples, the FIFO / SERDES 340 may receive data signaling from the data interface 330 and transmit data signaling to the write / sense circuitry 350 (e.g., for supporting write operations), or may receive data signaling from the sense circuitry 350 and transmit data signaling to the data interface 330 (e.g., for supporting read operations). In some examples (eg, for supporting read operations), the FIFO / SERDES 340 may be configured to transmit clock signaling (eg, RDQS_t / c signaling) to the data interface 330, which may be forwarded to the interface block 220-b.

[0068] The timing or other synchronization of the operations performed by the FIFO / SERDES 340 may be supported by one or more clock signals and other signaling received from the corresponding synchronization / sequencing logic 360. For example, the synchronization / sequencing logic 360 may generate or otherwise coordinate clock signaling to support different signaling rates for different buses (e.g., based on received clock signaling). Additionally or alternatively, the FIFO / SERDES 340 may operate in one direction (e.g., for data transmission to the data interface 330, for data reception from the data interface 330) or other modes based on configuration signaling received from the synchronization / sequencing logic 360.

[0069] For each data path, a respective write / sense circuitry 350 may be configured to support access (e.g., data signaling, write signaling, read signaling) of a respective group of one or more memory arrays 250. For example, the write / sense circuitry 350 may be coupled to the memory arrays 250 via a bus (e.g., a global input / output (GIO) bus), which may include respective signal paths associated with each memory array 250 or may include signal paths shared by all memory arrays 250 of the group, in which case the memory array circuitry may include multiplexing circuitry operable to couple the bus with selected ones of the memory arrays 250. In some examples, the bus between the write / sense circuitry 350 and the group of one or more memory arrays 250 may include the same number of signal paths as the bus between the write / sense circuitry 350 and the FIFO / SERDES 340 (e.g., for signaling GIO[287:0]) or the same number of signal paths as the number of columns in each memory array 250. In some other examples, the memory array 250 may include a number of columns that is an integer multiple of the number of signal paths of the bus, in which case the memory array circuitry (e.g., each memory array 250) may include decoding circuitry operable to couple a subset of the memory cell columns or associated circuitry to the bus.

[0070] To support write operations, write / sense circuitry 350 may be configured to drive signaling operable to write one or more logic states to memory cells of memory array 250 (e.g., based on received data, based on received timing signaling, based on data signaling received via bus 303, and based on control signaling received via bus 301-a). In some examples, such signaling may be transmitted to or otherwise associated with supporting circuitry of memory array 250 (e.g., as an output of a signal corresponding to the logic state to be written), such as sense amplifier circuitry, voltage sources, current sources, or other driver circuitry operable to apply a bias across a storage element of a memory cell (e.g., across a capacitor, across a ferroelectric capacitor) or to apply a charge, current, or other signaling to a storage element of a memory cell (e.g., applying current to a chalcogenide or other configurable memory material, applying charge to a gate of a NAND memory cell), as well as other examples.

[0071] To support read operations, the write / sense circuitry 350 may be configured to receive signaling, which the write / sense circuitry 350 may further amplify for communication through the interface block 245-b. For example, the write / sense circuitry 350 may be configured to receive signaling corresponding to a logic state read from the memory array 250, but at a relatively low driver strength (e.g., relatively 'analog' signaling, which may be associated with a relatively low drive strength of a sense amplifier of the memory array 250). The write / sense circuitry 350 may therefore include further sense amplification (e.g., data sense amplifiers (DSAs) between signal paths between the write / sense circuitry and one or more groups of the memory array and corresponding signal paths between the write / sense circuitry and the FIFO / SERDES), each of which may have a relatively high drive strength (e.g., for driving relatively 'digital' signaling).

[0072] Features of interface architecture 300 may be repeated in various numbers and arrangements to support semiconductor systems having multiple dies, such as various instances of system 200. In an example embodiment, each die 240 may be configured with 64 instances of interface block 245-b, which may support a data signaling width of 9,216 signal paths for each die 240 (e.g., where each bus 303 of a channel pair is associated with 72 signal paths). For system 200 having a stack of 8 dies 240 coupled to die 205, die 205 may thus be configured with 512 instances of interface block 220-b, thereby supporting a total data signaling width of 73,738 signal paths for system 200. However, in other embodiments, die 205 and die 240 may be configured with different numbers of interface blocks 220 and 245, respectively, and system 200 may be configured with different numbers of dies 240 per die 205.

[0073] Figure 4An example of an interface architecture 400 supporting data protection techniques in a stacked memory architecture according to examples disclosed herein is shown. The interface architecture 400 may illustrate aspects of an interface between a host interface 216 (e.g., a controller 215, a host processor 210) and a corresponding set of multiple memory arrays 250, such as an interface between the host interface 216 and a set of multiple interface blocks 245 (e.g., via logic blocks 225-a, via one or more interface blocks 220), an interface between the host interface 216 and a set of multiple dies 240 (e.g., stacked along the z-direction), or both, as well as other architectures. For example, the set of multiple memory arrays 250 supported by the interface architecture 400 may be located in a single die 240 or multiple dies 240 (e.g., a respective die 240 for each memory array 250, a respective die 240 for a subset of multiple memory arrays 250). In various examples, one or more instances of interface architecture 400 can be implemented in die 205 (eg, multiple instances of interface architecture 400 tiled along the x-direction, along the y-direction, or along both).

[0074] The interface architecture 400 may include a section 405 corresponding to a set of contacts 410 and a set of contacts 415 (e.g., ports, interfaces) associated with through silicon vias (TSVs) accessing a memory array 250 of a set of one or more dies 240. In some examples, contacts in the set of contacts 410, the set of contacts 415, or both may be instances of or otherwise associated with contacts 222. For example, the section 405 may include a set of contacts 410-a corresponding to TSVs accessing a first subset of the memory array 250 (e.g., a set of interface blocks 245 corresponding to the one or more dies 240), and may include a set of contacts 410-b corresponding to TSVs accessing a second subset of the memory array 250 (e.g., a set of interface blocks 245 corresponding to the one or more dies 240, which may be the same as or different from the set of interface blocks 245 associated with the set of contacts 410-a). Each group of contacts 410 may be arranged as one or more rows of contacts. For example, contact group 410-a may include 8 rows of contacts (e.g., for supporting a stack of 8 dies 240), and each row of contacts may correspond to a group of corresponding one or more memory arrays 250 (e.g., interface blocks 245 of corresponding dies 240). In some examples, each row of contacts in a group of contacts 410 may be associated with a bus 303 (e.g., of a pseudo channel), a bus 304, or a combination thereof.

[0075] The segment 405 may also include a set of contacts 415, which may include one or more rows of control contacts (e.g., one or more rows of control ports) associated with commands or other control signaling for accessing the memory array group 250 associated with the interface architecture 400. For example, the contact set 415 may also include 8 rows of contacts (e.g., for supporting stacking of 8 dies 240), and each row of contacts may correspond to a respective interface block 245 (e.g., a respective control interface 310). In some examples, each row of contacts in the contact set 415 may be associated with the bus 301, the bus 302, or a combination thereof.

[0076] In some examples, the contact groups 410-a and 410-b may be arranged on both sides of the contact group 415, which may allow each row of command contacts in the contact group 415 to correspond to two pseudo channels (e.g., two buses 303, two buses 304, or both), one for each subset of the memory array 250. However, the number of contacts per group of contacts 410 or per group of contacts 415, or rows or other portions thereof, may be variable and may be adjusted based on the number of memory arrays 250 or dies 240 supported by the interface architecture 400, as well as other aspects.

[0077] Interface architecture 400 may include section 420, which may include drivers (e.g., transmitter circuitry, receiver circuitry, interfaces, ports) operable to communicate read data, write data, and commands to and from die set 240 via contacts of section 405. For example, contact set 410-a and contact set 410-b may be coupled to a set of drivers 425-a and a set of drivers 425-b, respectively. Similarly, contact set 415 may be coupled to a set of drivers 430, and driver set 430 may include one or more row command drivers (e.g., command ports).

[0078] In some examples, the interface architecture 400 may include a set of data path blocks 435 corresponding to the memory array group 250 (e.g., corresponding to a set of interface blocks 245, corresponding to the die group 240). Each data path block 435 may receive data directed from or to a corresponding memory array 250 in the memory array group 250 (e.g., from a group of one or more dies 240). The data path blocks 435 may be arranged such that a first subset of the data path blocks 435 corresponding to a first subset of the memory arrays 250 are located in a first region of the section 450 of the interface architecture 400, and a second subset of the data path blocks 435 corresponding to a second subset of the memory arrays 250 are located in a second region of the section 450, as illustrated. This may support routing between the data path blocks 435 and corresponding rows of drivers in the driver group 425-a and driver group 425-b. In some examples, a subset of one or more of the datapath blocks 435 (eg, a pair of datapath blocks 435 in a pseudo channel pair arrangement) may each be included in or otherwise associated with a respective interface block 220 .

[0079] In some cases, the datapath blocks 435 may each be configured to perform error control operations on a corresponding subset of one or more memory arrays 250 (e.g., on a corresponding die 240, on a corresponding interface block 245). For example, each datapath block 435 may be configured to generate an error correction code (ECC) and perform error control operations on a corresponding die 240 using the ECC. The ECC generated by the datapath block 435 may be stored with the data (e.g., in the same memory array 250, in a different memory array 250, in the same die 240, in a different die 240). The datapath block 435 may perform an ECC process on a read operation to check the data read from the memory array 250 using the associated ECC and detect or correct (or both) one or more errors before outputting the data from the datapath block 435 (e.g., to the logic block 225-a, to the host interface 216, to the controller 215, to the host processor 210).

[0080] In some examples, the interface architecture 400 may include a set of controllers 440 associated with receiving commands from the host system 105 (e.g., from the host processor 210, from the controller 215, via the host interface 216, via the logic block 225-a) and performing control operations. For example, the controller 440 may support cross-bank scheduling, such as scheduling row and column commands, monitoring timing associated with multiple dies 240 (e.g., DRAM timing, column address strobe (CAS) timing), mapping logical addresses to physical addresses associated with a die group 240 (e.g., a group of one or more memory arrays 250), performing column repair and row repair procedures, or any combination thereof. In some examples, the interface architecture 400 may include a controller 440 for each of a set of interface blocks 245, which may be on the same die 240 or on multiple dies 240 (e.g., respective dies 240). The controllers 440 may be positioned within the section 450 between a first subset of the data path blocks 435 corresponding to a first subset of the memory array 250 and a second subset of the data path blocks 435 corresponding to a second subset of the memory array 250. In some examples, each of the controllers 440 may be included in or otherwise associated with a respective interface block 220 (e.g., an interface block 220 that is the same as a pair of data path blocks 435 in a pseudo channel pair arrangement).

[0081] In some examples, the interface architecture 400 may include a set of repair blocks 445, which may each be common to and shared by a set of multiple controllers 440. For example, a single repair block 445 may be associated with performing repair operations corresponding to a controller pair 440 (e.g., column repair and row repair operations, for a pair of interface blocks 245, for a pair of dies 240). In some cases, the repair block set 445 may be configured to perform address swapping based on repair data received from a non-volatile storage device 235 or a non-volatile storage device 270. In some examples, the repair block 445 may store the received repair data in a memory array of the repair block 445 (e.g., a volatile memory array, such as an SRAM array). By sharing the repair blocks 445 between the controller pairs 440, the interface architecture 400 may have a smaller size, such as by reducing the number of repair blocks 445 and memory arrays 250 associated with the repair blocks 445.

[0082] The data path block 435 and the controller 440 may be coupled to the logic block 225-a according to various arrangements. For example, each coupling of the logic block 225-a and a pair of the data path block 435 and the corresponding controller 440 (e.g., arranged according to a pseudo channel pair) may be an instance of the bus 223. The interface architecture 400 (e.g., the logic block 225-a) may also include a set of data path interfaces 480 and a set of controller interfaces 485 that support interfacing with the host interface 216 (e.g., the controller 215, the host processor 210, the host system 105) (e.g., receiving data and commands and sending data and commands to the host interface 216). For example, the data path interface 480 may support receiving data or sending data via the host interface 416, and the command interface 485 may support receiving commands from the host interface 416. In some examples, data path interface 480 and controller interface 485 may each be an instance of one or more conductive channels (e.g., conductors, terminals, pins, pads, nodes) associated with host interface 216 and may support coupling interface architecture 400 with controller 215 (e.g., of die 205, external to die 205).

[0083] In some examples, each data path interface 480 may be coupled with a respective data path block 435, and each controller interface 485 may be coupled with a respective controller 440. In some cases, the data path block 435 and the controller 440 may receive data and commands from or send data and commands to the data path interface 480 and the controller interface 485 via a set of multiplexers 465 (e.g., of the logic block 225-a). For example, the multiplexer set 465 may be operable to route incoming or outgoing data from the data path interface 480 to the corresponding data path block 435 and may be operable to route incoming commands from the controller interface 485 to the corresponding controller 440.

[0084] The interface architecture 400 (e.g., logic block 225-a) may include a processor 470 (e.g., processing circuitry, logic circuitry, one or more processing elements) that supports various functionalities for controlling or coordinating aspects of the system 200 (e.g., aspects of the operations of the plurality of interface blocks 220 or using the plurality of interface blocks 220). For example, the processor 470 may be an instance of circuitry that supports functions or otherwise implements circuitry, such as logic, multiplexing, configuration, evaluation, repair, error control, or any combination thereof (e.g., configured by hardware, configured by instructions). In some examples, the processor 470 may be coupled with each of the controllers 440 and may be operable to execute a program to test aspects of operating the die 240 (e.g., by a corresponding controller 440) by issuing commands associated with a test program (e.g., executed during manufacturing testing). In some examples, the processor 470 may additionally or alternatively initiate or assist in executing a row repair program and a column repair program (e.g., via a repair block 445), such as by storing or providing logic associated with the row repair program and the column repair program. In some examples, processor 470 may receive repair data from nonvolatile storage device 235 or nonvolatile storage device 270 and may initiate a row repair procedure or a column repair procedure based on the repair data (eg, via corresponding repair block 445 ).

[0085] In some cases, each data path interface 480 or corresponding data path block 435 may form one or more respective conductive paths (e.g., of channels, pseudo-channels) and may each be operable to independently communicate data according to a data size (e.g., 32 bytes, via any number of one or more signal paths). For example, the interface architecture 400 may transmit a data set associated with a read operation through a single data path block 435 and data path interface 480 using a series of data segments of the data size. Additionally or alternatively, the interface architecture 400 may transmit multiple data segments of the data set (e.g., in parallel) by transmitting each data segment using a respective data path block 435 and a respective data path interface 480. To support concurrent transfer of data segments, the data set may be stored across a set of memory arrays 250 (e.g., across a set of dies 240) such that each data segment is stored in a respective memory array 250 (e.g., the data set may be striped across multiple memory arrays 250, which may include striping across multiple dies 240).

[0086] Figure 5AAn example of a data set 500 supporting data protection techniques in a stacked memory architecture according to examples disclosed herein is shown. The data set 500 may illustrate an example of data communicated between a host system 105 and a memory system 110 (e.g., a TCDRAM system) in a multi-channel ECC configuration. For example, the data set 500 may include a plurality of data segments 505-a communicated through a set of conductive paths (e.g., channels, pseudo-channels). In various examples, the data set 500 may refer to a common set of payloads 510 of at least some (e.g., each) of the data segments 505-a or, as appropriate, a common set of payloads 510 and error correction information 515 of at least some (e.g., each) of the data segments 505-a. In the illustrative example, the payload 510 of the data segment 505-a may be 32 bytes, but any size of payload 510 or data segment 505-a may be implemented in the described techniques.

[0087] In some cases, the memory system 110 (e.g., logic block 225) may communicate each of the data segments 505-a concurrently through respective conductive paths (e.g., bus 251, bus 246, bus 221, bus 223). For example, the memory system 110 may store the data set 500 across a set of memory arrays 250 arranged on one or more dies 240. In some cases, the memory system 110 may store each data segment 505-a of the data set 500 at a separate memory array 250, a separate die 240, or both (e.g., the data set 500 may be striped across pseudo channels of the memory system 110). In some implementations, the memory system 110 may include a set of interface blocks 220 arranged on the die 205, which may support communication of the data segments 505-a between respective memory arrays 250 and separate components, such as the host system 105 (e.g., controller 215, host processor 210).

[0088] In some examples, each interface block 220 may be coupled to a respective die 240 and a respective set of one or more memory arrays 250 (e.g., coupled to an interface block 245 of a die 240). A logic block 225 associated with a die 205 may support accessing a data segment 505-a of a data set 500 across a set of dies 240 as part of an access command (e.g., a read command or a write command for the data set). Each interface block 220 may be configured (e.g., by a logic block 225) to retrieve (e.g., in the case of a read command) or transfer (e.g., in the case of a write command) a respective data segment 505-a of a data set 500 from a corresponding memory array 250 of a respective die 240 (e.g., via a respective interface block 245).

[0089] In some examples, the die 205 (e.g., logic block 225) may include a set of data path blocks 435, each of which is operable to communicate data with a corresponding interface block 245, a corresponding die 240, or both. Thus, the memory system 110 may support independent access to the data segment 505-a via each interface block 245 or die 240 (e.g., via the data path block 435, using the logic block 225). For example, as part of an access operation for the data segment 505-a, the interface block 220 may communicate the data segment 505-a with the corresponding interface block 245 using a channel (e.g., bus 303) between the interface block 220 and the interface block 245. Additionally or alternatively, the memory system 110 (e.g., logic block 225) may communicate multiple data segments 505-a of the data set 500 (e.g., in parallel, concurrently) by communicating each data segment 505-a using a corresponding interface block 220 and a corresponding interface block 245 (e.g., to a corresponding die 240).

[0090] To support data integrity of a data set 500 stored across multiple memory arrays 250, one or more data segments 505-a (e.g., data segments 505-a-9 and 505-a-10, which may alternatively be referred to as error control segments) of the data set 500 may include or otherwise be associated with error correction information 520 (e.g., parity information, parity bits, set-level error correction information, stripe-level error correction information) corresponding to the data set 500. The error correction information 520 may support correction of, for example, a failure of an entire data segment 505-a of the data set 500 or at least its payload 510 (e.g., a failure of the memory array 250, a failure of the die 240 or one or more associated buses, a single 32-byte read failure). The memory system 110 (e.g., logic block 225, processor 470) may generate or update error correction information 520 for the data set 500 as part of a write operation for any one or more of the data segments 505-a of the data set 500, and may use the error correction information 520 to detect or correct (or both) one or more errors within the data set 500 as part of a read operation for one or more of the data segments 505-a. In some examples, such techniques may implement 10 dies 240 to provide a full address space for this solution, with 10 associated pseudo channels associated with the same secure memory bank.

[0091] In some cases, the memory system 110 (e.g., logic block 225, processor 470) may store the error correction information 520 separately from other portions of the data set 500 at one or more dies 240. For example, the memory system 110 may include a first number of dies 240 (e.g., 8 dies 240) allocated to store data of the data set 500 (e.g., data segments 505-a-1 through 505-a-8) and may include a second number of dies 240 (e.g., 2 dies 240) allocated to store the error correction information 520 of the data set 500. In such examples, the memory system 110 may store each data segment 505-a at a respective die 240, and the error correction information 520 may remain in the same allocated die 240 or may rotate between the dies 240. Additionally or alternatively, the memory system 110 may distribute the data of the data set 500 and the error correction information 520 of the data set 500 across each of the dies 240 (e.g., across 10 dies). In such an example, the error correction information 520 may include a set of portions, each portion stored at a respective die 240. In various other examples, the memory system 110 may distribute the data set 500 across more than 10 dies 240 or fewer than 10 dies 240.

[0092] In some examples, the memory system 110 may receive (e.g., at the logic block 225) a write command to store the data segment 505-a to the die 240. In some cases, the write command may indicate that the data segment 505-a is part of the data set 500. Additionally or alternatively, the memory system 110 (e.g., the logic block 225, the processor 470) may associate the data segment 505-a with the data set 500 based on metadata associated with the data segment 505-a (e.g., the address of the data segment 505-a). In some examples, each data segment 505-a may be stored to the same address or portion thereof (e.g., the same bank address, row address, column address, or a combination thereof) within the respective memory array 250, which may support efficient access of the data set 500.

[0093] As part of the write operation, the memory system 110 (e.g., logic block 225, processor 470) may retrieve each data segment 505-a of the associated data set 500 from the corresponding memory array 250 of the die 240 (e.g., via the corresponding interface block 245, via the corresponding interface block 220, via the corresponding data path block 435) and may add the data segment 505-a to the data set 500 (e.g., by overwriting or modifying the data segment 505-a stored to the memory array 250 indicated by the write command). The memory system 110 (e.g., logic block 225, processor 470) may generate error correction information 520 using each data segment 505-a of the data set 500. For example, the logic block 225 may perform an error control operation on the data set 500 to calculate the error correction information 520. The memory system 110 (e.g., logic block 225) may store the data set 500 (including the generated error correction information 520) to the memory array group 250 (e.g., to the die group 240). For example, the memory system 110 may transfer each data segment 505 - a of the data set 500 to a respective memory array 250 of one or more dies 240 (eg, via a respective interface block 245 , via a respective interface block 220 ).

[0094] Additionally or alternatively, the memory system 110 may receive (e.g., at the logic block 225) a read command to retrieve the data segment 505-a of the data set 500 as part of a read operation to retrieve the data segment 505-a from the set of memory arrays 250. In some cases, the read command may indicate that the data segment 505-a is part of the data set 500. Additionally or alternatively, the memory system 110 (e.g., the logic block 225) may determine that the data segment 505-a is associated with the data set 500 based on metadata associated with the data segment 505-a (e.g., the address of the data segment 505-a).

[0095] As part of the read operation, the memory system 110 (e.g., logic block 225) may retrieve each data segment 505-a of the associated data set 500 and error correction information 520 corresponding to the data set 500 from the corresponding memory array 250 of the one or more dies 240 (e.g., via the corresponding interface block 245, via the corresponding interface block 220). The memory system 110 (e.g., logic block 225, processor 470) may use the error correction information 520 to perform error control operations (e.g., set-level error detection operations, set-level error correction operations) on the data set 500 to correct or detect (or both) one or more errors within the data set 500. The memory system 110 (e.g., logic block 225) may output the data segment 505-a (e.g., through the host interface 216, to the controller 215, to the host processor 210, to the host system 105).

[0096] In some examples, the memory system 110 may employ a hierarchy of error control techniques to support the integrity of the data set 500. For example, as part of a write operation for a data segment 505-a, the memory system 110 (e.g., the logic block 225, the processor 470, the interface block 220) may generate error correction information 515 (e.g., segment-level error control information) for a payload 510 of the data segment 505-a and may cause the error correction information 515 to be stored with the payload 510 of the data segment 505-a. As part of a read operation for the data segment 505-a, the memory system 110 (e.g., the logic block 225, the processor 470, the interface block 220) may retrieve the error correction information 515 associated with the payload 510 of the data segment 505-a. The memory system 110 (e.g., the logic block 225, the processor 470, the interface block 220) may use the error correction information 515 to perform an error control operation (e.g., a segment-level error detection operation, a segment-level error correction operation) on the payload 520-a, and may output at least the payload 510 of the data segment 505 (e.g., to the logic block 225 or a portion thereof for output to the host interface 216). In some cases, the error correction information 515 may be associated with an ECC scheme, such as a single error correction double error detection (SECDED) scheme or a double error correction triple error detection (DECTED) scheme that may operate on each data segment 505-a. In some such instances, the error control operation associated with the data segment 505-a may be followed by the error correction information 520 to perform an error control operation associated with the data set 500 (e.g., a set-level error detection operation, a set-level error correction operation). In some other examples, the error correction information 515 may be omitted from the data segment 505 - a (eg, segment-level error control operations are omitted) such that the data segment 505 - a may include only the payload 510 .

[0097] In some examples, using error correction information 520 to detect and correct errors within a data set 500 may support improved data integrity, but may be associated with relatively large power and performance penalties. For example, because the error correction information 520 is generated using all of the data segments 505-a of the data set 500, a read operation or a write operation for a single data segment 505-a of the data set 500 may include the memory system 110 (e.g., logic block 225, processor 470) retrieving each data segment 505-a of the data set 500 to perform an error correction operation using the error correction information 520. Thus, this approach may be associated with a relatively large minimum access size (e.g., a minimum access of a 256-byte payload 510 striped across 8 memory arrays 250). In addition, because each memory array 250 (e.g., each die 240, each interface block 245) can support a page size that is relatively larger than the size of the data segment 505-a (e.g., a 5-kilobyte page size relative to a 32-byte data segment), retrieving each data segment 505-a of the data set 500 can result in a relatively large access operation to the memory array 250.

[0098] Figure 5B An example of a data set 501 supporting data protection techniques in a stacked memory architecture according to examples disclosed herein is shown. The data set 501 may illustrate an example of data communicated between a host system 105 and a memory system 110 (e.g., a TCDRAM system) in a multi-channel redundant array of independent disks (RAID) configuration. For example, the data set 501 may include a plurality of data segments 505-b communicated through a set of conductive paths (e.g., channels, pseudo channels). In various examples, the data set 501 may refer to a common set of payloads 510 of at least some (e.g., each) of the data segments 505-a or, as appropriate, a common set of payloads 510 and error correction information 525 of at least some (e.g., each) of the data segments 505-a. In the illustrative example, the payload 510 of the data segment 505-a may be 32 bytes, but any size of payload 510 or data segment 505-a may be implemented in the described techniques.

[0099] As with the example of data set 500, in some cases, the memory system 110 may communicate each of the data segments 505-b concurrently through respective conductive paths. For example, the memory system 110 may store the data set 501 across a set of memory arrays 250 arranged on one or more dies 240. In some cases, the memory system 110 may store each data segment 505-a of the data set 500 at a separate memory array 250, a separate die 240, or both (e.g., the data set 501 may be striped across pseudo channels of the memory system 110). In some implementations, the memory system 110 may include a set of interface blocks 220 arranged on the die 205 that may support communication of the data segments 505-a between respective memory arrays 250 and separate components, such as the host system 105.

[0100] In some examples, the logic block 225 associated with the die 205 may support accessing data segments 505-b of a data set 501 across a group of dies 240 as part of an access command (e.g., a read command or a write command for the data set). Each interface block 220 may be configured to retrieve (e.g., in the case of a read command) or transfer (e.g., in the case of a write command) a corresponding data segment 505-b of the data set 501 from a corresponding memory array 250 of a corresponding die 240. In some examples, the memory system 110 may support accessing the data segments 505-b independently via each interface block 245 or die 240 (e.g., via the data path block 435, using the logic block 225). For example, as part of an access operation for a data segment 505-b, an interface block 220 may communicate the data segment 505-b with a corresponding interface block 245 using a channel between the interface block 220 and the interface block 245. Additionally or alternatively, the memory system 110 may communicate multiple data segments 505-b of a data set 501 by communicating each data segment 505-b using a respective interface block 220 and a respective interface block 245 (e.g., to a respective die 240).

[0101] To support data integrity of a data set 501 stored across multiple memory arrays 250 (e.g., across multiple dies 240), one or more data segments 505-b (e.g., data segment 505-b-9, which may alternatively be referred to as an error control segment) of the data set 501 may include or otherwise be associated with error correction information 530 (e.g., parity information, parity bits, set-level error correction information, stripe-level error correction information) corresponding to the data set 501. The error correction information 530 may support correction of, for example, a failure of an entire data segment 505-b of the data set 501 or at least its payload 510 (e.g., a failure of a memory array 250, a failure of a die 240 or a failure of one or more associated buses, a single 32-byte read failure). For example, the data protection scheme implemented for the data set 501 may be an example of a RAID scheme or may be similar to a RAID scheme, and the error correction information 530 may be calculated using all of the data segments 505-b of the data set 501. In this example, the error correction information 530 may be the result of a logical operation (e.g., an exclusive OR (XOR) operation) performed across each data segment 505-b. Thus, if any data segment 505-b of the data set 501 is corrupted, the data segment 505-b may be recovered by performing a logical operation across each of the other data segments 505-b and the error correction information 530. In some examples, such techniques may implement nine dies 240 to provide a full address space for this solution, with nine associated pseudo channels associated with the same secure storage repository.

[0102] In some cases, the memory system 110 may store the error correction information 530 separately from other portions of the data set 501 at one or more dies 240. For example, the memory system 110 may include a first number of dies 240 (e.g., 8 dies 240) allocated to store data of the data set 501 (e.g., data segments 505-b-1 through 505-b-8) and may include a second number of dies 240 (e.g., 1 die 240) allocated to store the error correction information 520 of the data set 500. In such examples, the memory system 110 may store each data segment 505-b at a respective die 240, and the error correction information 530 may remain in the same allocated die 240 or may rotate between the dies 240.

[0103] In some examples, the memory system 110 may receive (e.g., at a logic block) a write command to store a data segment 505-b (e.g., a "new" data segment 505-b) to the die 240. In some cases, the write command may indicate that the new data segment 505-b is part of the data set 501. Additionally or alternatively, the memory system 110 may associate the new data segment 505-b with the data set 501 based on metadata associated with the new data segment 505-b (e.g., an address of the new data segment 505-b). In some examples, each data segment 505-b of the data set 501 may be stored to the same address or portion thereof (e.g., the same bank address, row address, column address, or a combination thereof) within a respective memory array, which may support efficient access of the data set 501.

[0104] As part of the write operation, the memory system 110 (e.g., logic block 225, processor 470) may retrieve error correction information 530 and, in some cases, may retrieve a data segment 505-b stored at an address included in the write command (e.g., "old" data segment 505-b). The memory system 110 may modify the error correction information 530 using the new data segment 505-b and the old data segment 505-b of the write command (e.g., in a read-modify-write (RMW) scheme). For example, the memory system 110 may perform a logical operation to calculate the updated error correction information 530 (e.g., by "XORing out" the old data segment 505-b and "XORing in" the new data segment 505-b). Alternatively, the memory system 110 may retrieve each data segment 505-b associated with the data set 501 and may calculate the updated error correction information 530 using each data segment 505-b. The memory system 110 may modify the data set 501 to include the new data segment 505-b. For example, the memory system 110 may store the new data segment 505-b and the updated error correction information 530 to the memory array group 250 (e.g., of the die group 240). For example, the memory system 110 may transmit the new data segment 505-b to the first die 240 (e.g., via the first interface block 245, via the first interface block 220, via the first data path block 435) and may transmit the error correction information 530 to the second die 240 (e.g., via the second interface block 245, via the second interface block 220, via the second data path block 435).

[0105] In some cases (e.g., to implement an error control technique hierarchy), the memory system 110 (e.g., interface block 220, logic block 225, processor 470) may generate error correction information 525 (e.g., one or more parity bits, one or more CRC bits) for the payload 510 (e.g., of the new data segment 505-b). For example, the error correction information 525 may be associated with an error control scheme (e.g., for segment-level error detection, for segment-level error correction) configured to detect and, in some cases, correct one or more errors within the payload 510. For example, one or more bits of the error correction information 525 may be implemented in a cyclic redundancy check (CRC) scheme. In such cases, the memory system 110 (e.g., interface block 220, logic block 225, processor 470) may cause the error correction information 525 to be stored with the payload 510 as part of storing the new data segment 505-b.

[0106] Additionally or alternatively, the memory system may receive (e.g., at logic block 225) a read command to retrieve data segment 505-b of data set 501 as part of a read operation to retrieve data segment 505-b of data set 501 from a set of memory arrays 250. In some cases, the read command may indicate that data segment 505-b is part of data set 501. Additionally or alternatively, the memory system 110 may determine that data segment 505-b is associated with data set 501 based on metadata associated with data segment 505-b (e.g., an address of second data segment 505-b).

[0107] As part of the read operation, the memory system 110 may retrieve the data segment 505-b (e.g., via the interface block 245, via the interface block 220, via the data path block 435) and may perform error control operations on the data segment 505-b using the error correction information 525 included in the data segment 505-b. If the memory system 110 (e.g., the interface block 220, the logic block 225, the processor 470) does not detect an error in the data segment 505-b (e.g., in the payload 510) or if the memory system 110 (e.g., the interface block 220, the logic block 225, the processor 470) corrects the error within the data segment 505-b (e.g., in the payload 510), then the memory system 110 may output at least the payload 510 of the data segment 505-b (e.g., via the logic block 225, via the host interface 216) without retrieving each of the other data segments 505-b of the data set 501. That is, the memory system may refrain from retrieving the entire data set 501 (eg, refrain from retrieving other data segments 525 - b ).

[0108] Alternatively, if the memory system 110 detects an error within a data segment 505-b, the memory system 110 may retrieve each data segment 505-b of the associated data set 501 and error correction information 530 corresponding to the data set 501 from the corresponding memory array 250 (e.g., via the corresponding interface block 245, via the corresponding interface block 220). The memory system 110 (e.g., logic block 225, processor 470) may correct the error, for example, by performing an XOR operation on the other data segments 505-b of the data set 501 and the error correction information 530 to recover or reconstruct the data segment 505-b in which the error was detected. The memory system 110 (e.g., logic block 225) may output the data segment 505-b (e.g., through the host interface 216, to the controller 215, to the host processor 210, to the host system 105).

[0109] In some cases, the memory system 110 (e.g., the logic block 225) may migrate the error correction information 530 between different memory arrays 250 (e.g., between different dies 240). For example, because the error correction information 530 may be accessed relatively more frequently than each data segment 505-b of the data set 501 (e.g., because the error correction information 530 is accessed for each write operation associated with the data set 501), the memory system 110 may mitigate hot spots by transferring the error correction information 530 from a first memory array 250 (e.g., of the first die 240) to a second memory array 250 (e.g., of the second die 240).

[0110] Using error correction information 530 to correct errors within data set 501 may support improved data integrity and may be associated with relatively lower power and performance penalties (e.g., compared to using error correction information 520). For example, because error correction information 530 may be modified using “new” data segments 505-b and “old” data segments 505-b, a write operation to a single data segment 505-b of data set 501 may not involve the memory system 110 retrieving every data segment 505-b of data set 501 to update error correction information 530.

[0111] Figure 6 A block diagram 600 is shown of a logic block 620 that supports data protection techniques in a stacked memory architecture according to examples disclosed herein. The logic block 620 may be referenced Figures 1 to 5B620, or its various components may be examples of means for performing various aspects of data protection techniques in a stacked memory architecture, as described herein. For example, logic block 620 may include command receiving component 625, data retrieval component 630, error correction information retrieval component 635, error control component 640, parity information retrieval component 645, data storage component 650, data output component 655, parity information storage component 660, or any combination thereof. Components of each of these components or subcomponents thereof (e.g., one or more processors, one or more memories) may communicate directly or indirectly with each other (e.g., via one or more buses).

[0112] In some examples, the command receiving component 625 may be configured as or otherwise support means for receiving, at a logic block of a first semiconductor die of the semiconductor system (e.g., from the controller 215, from the host processor 210), a command to read a data segment stored at the semiconductor system, the semiconductor system including a plurality of memory arrays (e.g., memory array 250) of a set of one or more second semiconductor dies (e.g., die 240) coupled to the first semiconductor die (e.g., die 205). The data retrieving component 630 may be configured as or otherwise support means for retrieving, at the logic block, a plurality of data segments of a data set including the data segment based on receiving the command (e.g., via the one or more interface blocks 245, via the one or more interface blocks 220), each of the plurality of data segments being retrieved from a respective first memory array of the plurality of memory arrays. The error correction information retrieval component 635 may be configured as or otherwise support means for retrieving error correction information associated with a data set based on receiving a command at a logic block (e.g., via one or more interface blocks 245, via one or more interface blocks 220), the error correction information being retrieved from one or more corresponding second memory arrays of the plurality of memory arrays. The error control component 640 may be configured as or otherwise support means for performing an error control operation on the data set based on the error correction information at a logic block.

[0113] In some examples, the error correction information retrieval component 635 may be configured as or otherwise support means for retrieving second error control information associated with the data segment from a corresponding first memory array of the plurality of memory arrays (e.g., via one or more interface blocks 245, via one or more interface blocks 220). In some examples, the error control component 640 may be configured as or otherwise support means for performing a second error control operation on the data segment based on the second error control information associated with the data segment based on retrieving the data segment (e.g., at logic block 225, at interface block 220).

[0114] In some examples, the error correction information includes a plurality of portions, and each portion of the plurality of portions is stored at a respective second semiconductor die in the group of one or more second semiconductor dies.

[0115] In some examples, each of the plurality of data segments is stored at a respective second semiconductor die in the group of one or more second semiconductor die.

[0116] In some examples, data output component 655 may be configured or otherwise support means for outputting a data segment from a logic block based on performing an error control operation.

[0117] In some examples, the first semiconductor die includes a plurality of interface blocks (eg, interface block 220) coupled with a logic block, each operable to access one or more respective memory arrays (eg, respective memory array 250, via one or more interface blocks 245) of a plurality of memory arrays.

[0118] In some examples, retrieving the plurality of data segments includes retrieving each of the plurality of data segments from a corresponding first memory array of the plurality of memory arrays via a corresponding first interface block of the plurality of interface blocks; and retrieving error correction information includes retrieving error correction information from one or more corresponding second memory arrays of the plurality of memory arrays via one or more corresponding second interface blocks of the plurality of interface blocks.

[0119] Additionally or alternatively, in some examples, the command receiving component 625 may be configured to or otherwise support means for receiving, at a logic block of a first semiconductor die of the semiconductor system, a command to read a data segment stored at the semiconductor system, the semiconductor system comprising a plurality of memory arrays of a set of one or more second semiconductor dies coupled to the first semiconductor die. In some examples, the error control component 640 may be configured to or otherwise support means for detecting an error in the data segment based on receiving a command to read the data segment. In some examples, the data retrieval component 630 may be configured to or otherwise support means for retrieving, at the logic block, a plurality of data segments of a data set comprising the data segment based on detecting an error in the data segment, each of the plurality of data segments being retrieved from a respective first memory array of the plurality of memory arrays. The parity information retrieval component 645 may be configured to or otherwise support means for retrieving, at the logic block, parity information associated with the data set based on detecting an error in the data segment, the parity information being retrieved from one or more respective second memory arrays of the plurality of memory arrays. In some examples, error control component 640 can be configured or otherwise support means for correcting errors in data segments based on parity information and multiple data segments of a data set at a logical block.

[0120] In some examples, the first semiconductor die includes a plurality of interface blocks coupled with the logic block, each operable to access one or more respective memory arrays of the plurality of memory arrays.

[0121] In some examples, data retrieval component 630 may be configured or otherwise support means for: retrieving the plurality of data segments includes retrieving each of the plurality of data segments from a corresponding first memory array in the plurality of memory arrays via a corresponding first interface block in the plurality of interface blocks. In some examples, parity information retrieval component 645 may be configured or otherwise support means for: retrieving parity information includes retrieving parity information from one or more corresponding second memory arrays in the plurality of memory arrays via one or more corresponding second interface blocks in the plurality of interface blocks.

[0122] In some examples, error control component 640 may be configured as or otherwise support means for performing, by an interface block among the plurality of interface blocks, an error control operation on a data segment based on error control information associated with the data segment, and detecting an error in the data segment may be based on performing the error control operation.

[0123] In some examples, the command receiving component 625 may be configured or otherwise support means for receiving, at the logic block, a second command to read a second data segment stored at the semiconductor system. In some examples, the data retrieving component 630 may be configured or otherwise support means for retrieving, at the logic block, the second data segment based on receiving the second command. In some examples, the data retrieving component 630 may be configured or otherwise support means for refraining from retrieving, at the logic block, a second data set including the second data segment and parity information associated with the second data set based on no errors detected in the second data segment. In some examples, the data storage component 655 may be configured or otherwise support means for outputting the second data segment from the logic block.

[0124] In some examples, error control component 640 can be configured as or otherwise support means for performing an exclusive-OR operation using parity information and a data set, and correcting errors can be based on performing the exclusive-OR operation.

[0125] In some examples, data output component 655 may be configured or otherwise support means for outputting data segments from a logic block based on correcting errors.

[0126] Additionally or alternatively, in some examples, the command receiving component 625 may be configured to or otherwise support means for receiving, at a logic block of a first semiconductor die of the semiconductor system, a command to write a data segment at the semiconductor system, the semiconductor system comprising a plurality of memory arrays of a set of one or more second semiconductor dies coupled to the first semiconductor die. In some examples, the error control component 640 may be configured to or otherwise support means for modifying, by the logic block, parity information stored at a first memory array of the plurality of memory arrays, the parity information being associated with a plurality of data segments of a data set comprising the data segment, each of the plurality of data segments being stored at a respective second memory array of the plurality of memory arrays. The data storage component 650 may be configured to or otherwise support means for modifying, by the logic block, the data set to include the data segment based on writing the data segment to a second memory array of the plurality of memory arrays.

[0127] In some examples, to support modifying the parity information, the parity information retrieval component 645 may be configured or otherwise support means for retrieving the parity information from the first memory array at the logical block. In some examples, to support modifying the parity information, the error control component 640 may be configured or otherwise support means for generating second parity information for the data set based on the parity information and the data segment at the logical block. In some examples, to support modifying the parity information, the parity information storage component 660 may be configured or otherwise support means for writing the second parity information to the first memory array.

[0128] In some examples, data retrieval component 630 may be configured or otherwise support means for retrieving a second data segment of the data set at the logical block, and generating the second parity information may be based on comparing the data segment to the second data segment.

[0129] In some examples, error control component 640 may be configured or otherwise support means for generating one or more parity bits for a data segment at a logic block based on receiving a command, and modifying the data set may be based on writing the one or more parity bits to the first memory array.

[0130] In some examples, parity information storage component 660 may be configured as or otherwise support means for transferring parity information from a first memory array to a third memory array of the plurality of memory arrays.

[0131] In some examples, each of the plurality of data segments is stored at a respective second semiconductor die in the group of one or more second semiconductor die.

[0132] In some examples, the first semiconductor die includes a plurality of interface blocks coupled with the logic block, each operable to access one or more respective memory arrays of the plurality of memory arrays.

[0133] In some examples, each of the plurality of interface blocks is coupled with a respective second semiconductor die via a respective channel between each interface block and a respective second semiconductor die of the group of one or more second semiconductor dies.

[0134] In some examples, error control component 640 can be configured as or otherwise support means for performing an exclusive-OR operation using the parity information and the data set, and modifying the parity information can be based on performing the exclusive-OR operation.

[0135] In some examples, the described functionality of logic block 620 or its various components may be supported by or may refer to at least a portion of at least one processor, where such at least one processor may include one or more processing elements (e.g., a controller, a microprocessor, a microcontroller, a digital signal processor, a state machine, discrete gate logic, discrete transistor logic, discrete hardware components, or any combination of one or more of such elements). In some examples, the described functionality of logic block 620 or its various components may be implemented at least in part by instructions (e.g., stored in a memory, a non-transitory computer-readable medium) that are executable by such at least one processor.

[0136] Figure 7 A flowchart illustrating a method 700 for supporting data protection techniques in a stacked memory architecture according to an example disclosed herein is shown. The operations of the method 700 may be implemented by the logic blocks or components thereof described herein. For example, the operations of the method 700 may be implemented by reference to Figures 1 to 6 The described logic block 620 or logic block 225, interface block 220 or a combination thereof is executed. In some examples, the logic block may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the logic block may use dedicated hardware to perform aspects of the described functions.

[0137] At 705, the method may include receiving, at a logic block of a first semiconductor die of the semiconductor system, a command to read a data segment stored at the semiconductor system, the semiconductor system including a plurality of memory arrays of a set of one or more second semiconductor dies coupled to the first semiconductor die. For example, the first semiconductor die may include a logic block (e.g., logic block 225) that may receive the command from controller 215. In some examples, aspects of operation 705 may be described with reference to Figure 6 The command receiving component 625 described above performs the above operations.

[0138] At 710, the method may include retrieving, at a logic block, a plurality of data segments of a data set including a data segment based on receiving a command, each of the plurality of data segments being retrieved from a respective first memory array of the plurality of memory arrays. For example, the logic block may be coupled to one or more interface blocks (e.g., interface block 220) that may retrieve the respective data segments from the respective memory array 250. In some examples, aspects of operation 710 may be referred to as Figure 6 The data retrieval component 630 described above performs the above.

[0139] At 715, the method may include retrieving, at the logic block, error correction information associated with the data set based on receiving the command, the error correction information being retrieved from one or more corresponding second memory arrays of the plurality of memory arrays. For example, the interface block 220 may retrieve the error correction information from the memory array 250. In some examples, aspects of operation 715 may be referred to as Figure 6 The error correction information retrieval component 635 described above performs the above.

[0140] At 720, the method may include performing, at a logic block, an error control operation on the data set based on the error correction information. For example, logic block 225 may include one or more error correction circuits (e.g., of processor 470) for performing the error control operation. In some examples, aspects of operation 720 may be described with reference to Figure 6 The error control component 640 performs the described operations.

[0141] In some examples, the apparatus described herein may perform one or several methods, such as method 700. The apparatus may include features, circuitry, logic, means, or instructions (such as a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0142] Aspect 1: A method, apparatus, or non-transitory computer-readable medium, comprising operations, features, circuit systems, logic, means, or instructions, or any combination thereof, for: receiving, at a logic block of a first semiconductor die of a semiconductor system, a command to read a data segment stored at the semiconductor system, the semiconductor system comprising a plurality of memory arrays of a set of one or more second semiconductor die coupled to the first semiconductor die; retrieving, at the logic block, a plurality of data segments of a data set including the data segment based on receiving the command, each of the plurality of data segments being retrieved from a respective first memory array of the plurality of memory arrays; retrieving, at the logic block, error correction information associated with the data set based on receiving the command, the error correction information being retrieved from one or more respective second memory arrays of the plurality of memory arrays; and performing, at the logic block, an error control operation on the data set based on the error correction information.

[0143] Aspect 2: The method, apparatus, or non-transitory computer-readable medium according to Aspect 1, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: retrieving second error control information associated with the data segment from the corresponding first memory array of the plurality of memory arrays; and performing a second error control operation on the data segment based on the second error control information associated with the data segment based on retrieving the data segment.

[0144] Aspect 3: A method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 2, wherein the error control information includes multiple parts, each of the multiple parts is stored at a corresponding second semiconductor die in the group of one or more second semiconductor dies.

[0145] Aspect 4: The method, apparatus, or non-transitory computer-readable medium of any of Aspects 1-3, wherein each of the plurality of data segments is stored at a respective second semiconductor die in the set of one or more second semiconductor dies.

[0146] Aspect 5: The method, apparatus, or non-transitory computer-readable medium of any one of Aspects 1 to 4, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for outputting the data segment from the logic block based on performing the error control operation.

[0147] Aspect 6: The method, apparatus, or non-transitory computer-readable medium of any one of aspects 1 to 5, wherein the first semiconductor die includes a plurality of interface blocks coupled to the logic block, each of which is operable to access one or more respective memory arrays of the plurality of memory arrays.

[0148] Aspect 7: A method, apparatus, or non-transitory computer-readable medium according to Aspect 6, wherein retrieving the multiple data segments includes retrieving each of the multiple data segments from the corresponding first memory array in the multiple memory arrays via a corresponding first interface block in the multiple interface blocks; and retrieving the error correction information includes retrieving the error correction information from the one or more corresponding second memory arrays in the multiple memory arrays via one or more corresponding second interface blocks in the multiple interface blocks.

[0149] Figure 8 A flowchart illustrating a method 800 for supporting data protection techniques in a stacked memory architecture according to an example disclosed herein is shown. The operations of the method 800 may be implemented by the logic blocks or components thereof described herein. For example, the operations of the method 800 may be implemented by reference to Figures 1 to 6The described logic block 620 or logic block 225, interface block 220 or a combination thereof is executed. In some examples, the logic block may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the logic block may use dedicated hardware to perform aspects of the described functions.

[0150] At 805, the method may include receiving, at a logic block of a first semiconductor die of the semiconductor system, a command to read a data segment stored at the semiconductor system, the semiconductor system including a plurality of memory arrays of a set of one or more second semiconductor dies coupled to the first semiconductor die. For example, the first semiconductor die may include a logic block (e.g., logic block 225) that may receive the command from controller 215. In some examples, aspects of operation 805 may be described with reference to Figure 6 The command receiving component 625 described above performs the above operations.

[0151] At 810, the method may include detecting an error in the data segment based on receiving a command to read the data segment. For example, logic block 225 may include one or more error correction circuits (e.g., of processor 470) for detecting errors. In some examples, aspects of operation 810 may be described with reference to Figure 6 The error control component 640 performs the described operations.

[0152] At 815, the method may include retrieving, at a logic block, a plurality of data segments of a data set including the data segment based on detecting an error in the data segment, each of the plurality of data segments being retrieved from a respective first memory array of the plurality of memory arrays. For example, logic block 225 may be coupled to one or more interface blocks (e.g., interface block 220) that may retrieve the respective data segments from respective memory arrays 250. In some examples, aspects of operation 815 may be referred to as Figure 6 The data retrieval component 630 described above performs the above.

[0153] At 820, the method may include retrieving, at the logic block, parity information associated with the data set based on detecting an error in the data segment, the parity information being retrieved from one or more corresponding second memory arrays of the plurality of memory arrays. For example, the interface block 220 may retrieve the parity information from the memory array 250. In some examples, aspects of operation 820 may be performed by reference to Figure 6 The parity information retrieval component 645 described above performs the above.

[0154] At 825, the method may include correcting errors in the data segments based on the parity information and the plurality of data segments of the data set at the logic block. For example, the logic block 225 may include one or more error correction circuits (e.g., of the processor 470) for correcting errors. In some examples, aspects of operation 825 may be described with reference to Figure 6 The error control component 640 performs the described operations.

[0155] In some examples, the apparatus described herein may perform one or several methods, such as method 800. The apparatus may include features, circuitry, logic, means, or instructions (such as a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0156] Aspect 8: A method, apparatus, or non-transitory computer-readable medium, comprising operations, features, circuit systems, logic, means, or instructions, or any combination thereof, for: receiving, at a logic block of a first semiconductor die of a semiconductor system, a command to read a data segment stored at the semiconductor system, the semiconductor system comprising a plurality of memory arrays of a set of one or more second semiconductor die coupled to the first semiconductor die; detecting an error in the data segment based on receiving the command to read the data segment; retrieving, at the logic block, a plurality of data segments of a data set including the data segment based on detecting the error in the data segment, each of the plurality of data segments being retrieved from a respective first memory array of the plurality of memory arrays; retrieving, at the logic block, parity information associated with the data set based on detecting the error in the data segment, the parity information being retrieved from one or more respective second memory arrays of the plurality of memory arrays; and correcting, at the logic block, the error in the data segment based on the parity information and the plurality of data segments of the data set.

[0157] Aspect 9: The method, apparatus, or non-transitory computer-readable medium of aspect 8, wherein the first semiconductor die includes a plurality of interface blocks coupled to the logic block, each operable to access one or more respective memory arrays of the plurality of memory arrays.

[0158] Aspect 10: The method, apparatus, or non-transitory computer-readable medium of Aspect 9, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: retrieving the plurality of data segments comprises retrieving each of the plurality of data segments from the corresponding first memory array in the plurality of memory arrays via a corresponding first interface block in the plurality of interface blocks; and retrieving the parity information comprises retrieving the parity information from the one or more corresponding second memory arrays in the plurality of memory arrays via one or more corresponding second interface blocks in the plurality of interface blocks.

[0159] Aspect 11: A method, apparatus or non-transitory computer-readable medium according to any one of Aspects 9 to 10, further comprising operations, features, circuit systems, logic, components or instructions or any combination thereof for: an interface block among the multiple interface blocks performs an error control operation on the data segment based on error control information associated with the data segment, wherein detecting the error in the data segment is based on performing the error control operation.

[0160] Aspect 12: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 8 to 11, further comprising the following operations, features, circuit systems, logic, components, or instructions, or any combination thereof: receiving, at the logic block, a second command to read a second data segment stored at a semiconductor system; retrieving, at the logic block, the second data segment based on receiving the second command; suppressing, at the logic block, retrieval of a second data set including the second data segment and parity information associated with the second data set based on no error detected in the second data segment; and outputting the second data segment from the logic block.

[0161] Aspect 13: The method, apparatus, or non-transitory computer-readable medium of any one of Aspects 8 to 12, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for performing an XOR operation using the parity information and the data set, wherein correcting the error is based on performing the XOR operation.

[0162] Aspect 14: The method, apparatus, or non-transitory computer-readable medium of any one of Aspects 8 to 13, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: outputting the data segment from the logic block based on correcting the error.

[0163] Fig. 9 A flowchart illustrating a method 900 for supporting data protection techniques in a stacked memory architecture according to an example disclosed herein is shown. The operations of the method 900 may be implemented by the logic blocks or components thereof described herein. For example, the operations of the method 900 may be implemented by reference to Figures 1 to 6 The described logic block 620 or logic block 225, interface block 220 or a combination thereof is executed. In some examples, the logic block may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the logic block may use dedicated hardware to perform aspects of the described functions.

[0164] At 905, the method may include receiving, at a logic block of a first semiconductor die of the semiconductor system, a command to write a data segment at the semiconductor system, the semiconductor system including a plurality of memory arrays of a set of one or more second semiconductor dies coupled to the first semiconductor die. For example, the first semiconductor die may include a logic block (e.g., logic block 225) that may receive the command from the controller 215. In some examples, aspects of operation 905 may be described with reference to Figure 6 The command receiving component 625 described above performs the above operations.

[0165] At 910, the method may include modifying, by a logic block, parity information stored at a first memory array in a plurality of memory arrays, the parity information being associated with a plurality of data segments of a data set including the data segments, each of the plurality of data segments being stored at a respective second memory array in the plurality of memory arrays. For example, logic block 225 may include circuitry (e.g., of processor 470) operable to modify the parity information. In some examples, aspects of operation 910 may be performed by reference to Figure 6 The error control component 640 performs the described operations.

[0166] At 915, the method may include modifying, by the logic block, the data set to include the data segment based on writing the data segment to a second memory array in the plurality of memory arrays. For example, logic block 225 may include circuitry (e.g., of processor 470) operable to modify the data segment. In some examples, aspects of operation 915 may be described with reference to Figure 6 The data storage component 650 is described as performing.

[0167] In some examples, the apparatus described herein may perform one or several methods, such as method 900. The apparatus may include features, circuitry, logic, means, or instructions (such as a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0168] Aspect 15: A method, apparatus, or non-transitory computer-readable medium, comprising operations, features, circuit systems, logic, means, or instructions, or any combination thereof, for: receiving, at a logic block of a first semiconductor die of a semiconductor system, a command to write a data segment at the semiconductor system, the semiconductor system comprising a plurality of memory arrays of a group of one or more second semiconductor die coupled to the first semiconductor die; modifying, by the logic block, parity information stored at a first memory array of the plurality of memory arrays, the parity information being associated with a plurality of data segments of a data set including the data segment, each of the plurality of data segments being stored at a corresponding second memory array of the plurality of memory arrays; and modifying, by the logic block, the data set to include the data segment based on writing the data segment to a second memory array of the plurality of memory arrays.

[0169] Aspect 16: A method, apparatus, or non-transitory computer-readable medium according to Aspect 15, wherein modifying the parity information includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: retrieving the parity information from the first memory array at the logic block; generating second parity information for the data set based on the parity information and the data segment at the logic block; and writing the second parity information to the first memory array.

[0170] Aspect 17: The method, apparatus, or non-transitory computer-readable medium of Aspect 16, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: retrieving a second data segment of the data set at the logic block, wherein generating the second parity information is based on comparing the data segment with the second data segment.

[0171] Aspect 18: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 15 to 17, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: generating one or more parity bits for the data segment at the logic block based on receiving the command, wherein modifying the data set is based on writing the one or more parity bits to a first memory array.

[0172] Aspect 19: The method, apparatus, or non-transitory computer-readable medium of any one of Aspects 15 to 18, further comprising operations, features, circuit systems, logic, means, or instructions, or any combination thereof, for transferring the parity information from the first memory array to a third memory array of the plurality of memory arrays.

[0173] Aspect 20: The method, apparatus, or non-transitory computer-readable medium of any of Aspects 15-19, wherein each of the plurality of data segments is stored at a respective second semiconductor die in the set of one or more second semiconductor dies.

[0174] Aspect 21: The method, apparatus, or non-transitory computer-readable medium of any of Aspects 15 to 20, wherein the first semiconductor die includes a plurality of interface blocks coupled to the logic block, each operable to access one or more respective memory arrays of the plurality of memory arrays.

[0175] Aspect 22: The method, apparatus, or non-transitory computer-readable medium of Aspect 21, wherein each of the plurality of interface blocks is coupled to a respective second semiconductor die in the set of one or more second semiconductor dies via a respective channel between each interface block and the respective second semiconductor die.

[0176] Aspect 23: The method, apparatus, or non-transitory computer-readable medium of any one of Aspects 15 to 22, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for performing an XOR operation using the parity information and the data set, wherein modifying the parity information is based on performing the XOR operation.

[0177] It should be noted that the aspects described herein describe possible implementations, and that operations and steps may be rearranged or otherwise modified and other implementations are possible. Furthermore, portions from two or more of the methods may be combined.

[0178] A system is described. The following provides an overview of aspects of the system described herein:

[0179] Aspect 24: A system comprising: a group of one or more second semiconductor dies of a semiconductor system, the group of one or more second semiconductor dies comprising a plurality of memory arrays; and a first semiconductor die of the semiconductor system, coupled to the group of one or more second semiconductor dies, the first semiconductor die comprising a logic block, the logic block being configured to: receive a command to read a data segment stored at the semiconductor system; retrieve a plurality of data segments of a data set comprising the data segment based on receiving the command, each of the plurality of data segments being retrieved from a corresponding first memory array of the plurality of memory arrays; retrieve error correction information associated with the data set based on receiving the command, the error correction information being retrieved from one or more corresponding second memory arrays of the plurality of memory arrays; and perform an error control operation on the data set based on the error correction information.

[0180] Aspect 25: The system of aspect 24, wherein the first semiconductor die further comprises a plurality of interface blocks coupled with the logic block, each operable to access one or more respective memory arrays of the plurality of memory arrays.

[0181] Aspect 26: A system according to Aspect 25, wherein: in order to retrieve the multiple data segments, the logic block is further configured to retrieve the multiple data segments via a corresponding first interface block among the multiple interface blocks; and in order to retrieve the error correction information, the logic block is further configured to retrieve the error correction information via one or more corresponding second interface blocks among the multiple interface blocks.

[0182] A system is described. The following provides an overview of aspects of the system described herein:

[0183] Aspect 27: A system comprising: a group of one or more second semiconductor dies of a semiconductor system, the group of one or more second semiconductor dies comprising a plurality of memory arrays; and a first semiconductor die of the semiconductor system, coupled to the group of one or more second semiconductor dies, the first semiconductor die comprising a logic block, the logic block being configured to: receive a command to read a data segment from the semiconductor system; detect an error in the data segment based on receiving the command to read the data segment; retrieve a plurality of data segments of a data set comprising the data segment based on detecting the error in the data segment, each of the plurality of data segments being retrieved from a corresponding first memory array of the plurality of memory arrays; retrieve parity information associated with the data set based on detecting the error in the data segment, the parity information being retrieved from one or more corresponding second memory arrays of the plurality of memory arrays; and correct the error in the data segment based on the parity information and the plurality of data segments of the data set.

[0184] Aspect 28: The system of aspect 27, wherein the first semiconductor die further comprises a plurality of interface blocks coupled with the logic block, each operable to access one or more respective memory arrays of the plurality of memory arrays.

[0185] Aspect 29: A system according to Aspect 28, wherein: in order to retrieve the multiple data segments, the logic block is further configured to retrieve the multiple data segments via a corresponding first interface block among the multiple interface blocks; and in order to retrieve the parity information, the logic block is further configured to retrieve the parity information via one or more corresponding second interface blocks among the multiple interface blocks.

[0186] Aspect 30: A system according to any one of Aspects 28 to 29, wherein an interface block among the multiple interface blocks is configured to: perform an error control operation on the data segment based on error control information associated with the data segment, wherein detecting the error in the data segment is based on performing the error control operation.

[0187] The information and signals described herein may be represented using any of a variety of different techniques and technologies. For example, data, instructions, commands, information, signals, bits, or signaling symbols that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, a signal may represent a signal bus, where the bus may have various bit widths.

[0188] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication (e.g., conductive contact, connection, coupling) with each other if there is any electrical path (e.g., conductive path) between the components that can support the flow of signals (e.g., charge, current, voltage) between the components at any time. The conductive path between components that are in electronic communication (e.g., conductive contact, connection, coupling) with each other may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components or may be an indirect conductive path that includes an intermediate component (e.g., a switch, transistor, or other component). In some examples, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components (e.g., switches or transistors).

[0189] The switch components (e.g., transistors) discussed herein may be field effect transistors (FETs) and may include a source (e.g., a source terminal), a drain (e.g., a drain terminal), a channel between the source and the drain, and a gate (e.g., a gate terminal). The conductivity of the channel may be controlled (e.g., modulated) by applying a voltage to the gate, which may, in some examples, cause the channel to become conductive. The switch component may be an example of an n-type FET or a p-type FET.

[0190] The description set forth herein describes example configurations in conjunction with the accompanying drawings and does not represent all examples that may be implemented or within the scope of the claims. The "Detailed Description" includes specific details for providing an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0191] In the accompanying drawings, similar components or features may have the same reference label. Similar components may be distinguished by following the reference label with one or more dashes and an additional label that distinguishes the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components with the same first reference label, regardless of the additional reference labels.

[0192] The functions described herein may be implemented in hardware, software executed by a processing system (e.g., one or more processors, one or more controllers, control circuitry, processing circuitry, logic circuitry), firmware, or any combination thereof. If implemented in software executed by a processing system, the functions may be stored on or transmitted over a computer-readable medium as one or more instructions (e.g., code). Due to the nature of software, the functions described herein may be implemented using software executed by a processing system, hardware, firmware, hardwiring, or a combination of any of these. Features implementing the functions may be physically located at various locations, including distributed such that portions of the functions are implemented at different physical locations.

[0193] The illustrative blocks and modules described herein may be implemented or executed with one or more processors (e.g., DSPs, ASICs, FPGAs, discrete gate logic, discrete transistor logic, discrete hardware components, other programmable logic devices, or any combination thereof) designed to perform the functions described herein. A processor may be an example of a microprocessor, a controller, a microcontroller, a state machine, or other type of processor. A processor may also be implemented as at least one of one or more computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0194] As used herein (including in the claims), "or" used in a list of items (e.g., a list of items preceded by a phrase such as "at least one of" or "one or more of") indicates an inclusive list, so that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be interpreted as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0195] As used herein (including in the claims), the article "a" before a noun is open-ended and should be understood to refer to "at least one" of those nouns or "one or more" of those nouns. Therefore, the terms "one", "at least one", "one or more", and "at least one of one or more" are interchangeable. For example, if a claim recites "a component" that performs one or more functions, each of the individual functions may be performed by a single component or any combination of multiple components. Therefore, the term "a component" having a characteristic or performing a function may refer to "at least one of one or more components" having a specific characteristic or performing a specific function. The subsequent use of the term "the / said" to refer to the component introduced with the article "a" may refer to any or all of the one or more components. For example, a component introduced with the article "a" may be understood to mean "one or more components", and the subsequent reference to "the component" in the claim may be understood to be equivalent to referring to "at least one of one or more components". Similarly, a component introduced as "one or more components" subsequently referenced using the term "the / said" may refer to any or all of the one or more components. For example, a subsequent reference to "one or more components" in a claim may be understood to be equivalent to referring to "at least one of the one or more components."

[0196] Computer-readable media include both non-transitory computer storage media and communication media, including any media that facilitates the transfer of a computer program from one location to another. Non-transitory storage media may be any available media or a combination of multiple media that can be accessed by a computer. For example, but not limited to, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disk storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media or combination of media that can be used to carry or store desired program code components in the form of instructions or data structures and can be accessed by a computer or processor.

[0197] The description and drawings are provided to enable one of ordinary skill in the art to make or use the present disclosure. One of ordinary skill in the art will appreciate the various modifications of the present disclosure, and the techniques disclosed herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but should be given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method comprising: receiving, at a logic block of a first semiconductor die of a semiconductor system, a command to read a data segment stored at the semiconductor system, the semiconductor system comprising a plurality of memory arrays of a group of one or more second semiconductor dies coupled to the first semiconductor die; detecting an error in the data segment based on receiving the command to read the data segment; retrieving, at the logic block, a plurality of data segments of a data set including the data segment based on detecting the error in the data segment, each of the plurality of data segments being retrieved from a respective first memory array of the plurality of memory arrays; retrieving, at the logic block, parity information associated with the data set based on detecting the error in the data segment, the parity information being retrieved from one or more respective second memory arrays of the plurality of memory arrays; and The errors in the data segments are corrected at the logical block based on the parity information and the plurality of data segments of the data set.

2. The method of claim 1, wherein the first semiconductor die comprises a plurality of interface blocks coupled to the logic block, the plurality of interface blocks each being operable to access one or more respective memory arrays of the plurality of memory arrays.

3. The method according to claim 2, wherein: retrieving the plurality of data segments comprises retrieving each of the plurality of data segments from the respective first memory array of the plurality of memory arrays via a respective first interface block of the plurality of interface blocks; and Retrieving the parity information includes retrieving the parity information from the one or more corresponding second memory arrays of the plurality of memory arrays via one or more corresponding second interface blocks of the plurality of interface blocks.

4. The method according to claim 2, further comprising: An error control operation is performed, by an interface block of the plurality of interface blocks, on the data segment based on error control information associated with the data segment, wherein detecting the error in the data segment is based on performing the error control operation.

5. The method according to claim 1, further comprising: receiving, at the logic block, a second command to read a second data segment stored at the semiconductor system; retrieving, at the logic block, the second data segment based on receiving the second command; refraining, at the logic block, from retrieving a second data set including the second data segment and parity information associated with the second data set based on a lack of errors detected in the second data segment; and The second data segment is output from the logic block.

6. The method according to claim 1, further comprising: An exclusive-OR operation is performed using the parity information and the data set, wherein correcting the error is based on performing the exclusive-OR operation.

7. The method according to claim 1, further comprising: The data segment is output from the logic block based on correcting the error.

8. A method comprising: receiving, at a logic block of a first semiconductor die of a semiconductor system, a command to write a data segment at the semiconductor system, the semiconductor system comprising a plurality of memory arrays of a set of one or more second semiconductor dies coupled to the first semiconductor die; modifying, by the logic block, parity information stored at a first memory array of the plurality of memory arrays, the parity information being associated with a plurality of data segments of a data set including the data segment, each of the plurality of data segments being stored at a respective second memory array of the plurality of memory arrays; and The data set is modified, by the logic block, to include the data segment based on writing the data segment to a second memory array of the plurality of memory arrays.

9. The method of claim 8, wherein modifying the parity information comprises: retrieving the parity information from the first memory array at the logic block; generating, at the logic block, second parity information of the data set based on the parity information and the data segment; and The second parity information is written to the first memory array.

10. The method according to claim 9, further comprising: A second data segment of the data set is retrieved at the logical block, wherein generating the second parity information is based on comparing the data segment to the second data segment.

11. The method according to claim 8, further comprising: One or more parity bits for the data segment are generated at the logic block based on receiving the command, wherein modifying the data set is based on writing the one or more parity bits to a first memory array.

12. The method according to claim 8, further comprising: The parity information is transferred from the first memory array to a third memory array of the plurality of memory arrays.

13. The method of claim 8, wherein each of the plurality of data segments is stored at a respective second semiconductor die in the set of one or more second semiconductor die.

14. The method of claim 8, wherein the first semiconductor die comprises a plurality of interface blocks coupled to the logic block, the plurality of interface blocks each operable to access one or more respective memory arrays of the plurality of memory arrays.

15. The method of claim 14, wherein each of the plurality of interface blocks is coupled with a respective second semiconductor die in the set of one or more second semiconductor dies via a respective channel between each interface block and the respective second semiconductor die.

16. The method according to claim 8, further comprising: An exclusive-OR operation is performed using the parity information and the data set, wherein modifying the parity information is based on performing the exclusive-OR operation.

17. A method comprising: receiving, at a logic block of a first semiconductor die of a semiconductor system, a command to read a data segment stored at the semiconductor system, the semiconductor system comprising a plurality of memory arrays of a group of one or more second semiconductor dies coupled to the first semiconductor die; retrieving, at the logic block, a plurality of data segments of a data set including the data segment based on receiving the command, each of the plurality of data segments being retrieved from a respective first memory array of the plurality of memory arrays; retrieving, at the logic block, error correction information associated with the data set based on receiving the command, the error correction information being retrieved from one or more respective second memory arrays of the plurality of memory arrays; and An error control operation is performed at the logic block on the data set based on the error correction information.

18. The method according to claim 17, further comprising: retrieving second error control information associated with the data segment from the corresponding first memory array of the plurality of memory arrays; and A second error control operation is performed on the data segment based on retrieving the data segment based on second error control information associated with the data segment.

19. The method of claim 17, wherein the error correction information comprises a plurality of portions, each portion of the plurality of portions being stored at a respective second semiconductor die in the set of one or more second semiconductor die.

20. The method of claim 17, wherein each of the plurality of data segments is stored at a respective second semiconductor die in the set of one or more second semiconductor die.

21. The method of claim 17, further comprising: The data segment is output from the logic block based on performing the error control operation.

22. The method of claim 17, wherein the first semiconductor die comprises a plurality of interface blocks coupled to the logic block, the plurality of interface blocks each operable to access one or more respective memory arrays of the plurality of memory arrays.

23. The method of claim 22, wherein: retrieving the plurality of data segments comprises retrieving each of the plurality of data segments from the respective first memory array of the plurality of memory arrays via a respective first interface block of the plurality of interface blocks; and Retrieving the error correction information includes retrieving the error correction information from the one or more corresponding second memory arrays of the plurality of memory arrays via one or more corresponding second interface blocks of the plurality of interface blocks.

24. A system comprising: a set of one or more second semiconductor dies of the semiconductor system, the set of one or more second semiconductor dies comprising a plurality of memory arrays; and a first semiconductor die of the semiconductor system coupled to the set of one or more second semiconductor dies, the first semiconductor die comprising a logic block configured to: receiving a command to read a data segment from the semiconductor system; detecting an error in the data segment based on receiving the command to read the data segment; retrieving a plurality of data segments of a data set including the data segment based on detecting the error in the data segment, each of the plurality of data segments being retrieved from a respective first memory array of the plurality of memory arrays; retrieving parity information associated with the data set based on detecting the error in the data segment, the parity information retrieved from one or more respective second memory arrays of the plurality of memory arrays; and The errors in the data segments are corrected based on the parity information and the plurality of data segments of the data set.

25. The system of claim 24, wherein the first semiconductor die further comprises a plurality of interface blocks coupled to the logic block, the plurality of interface blocks each operable to access one or more respective memory arrays of the plurality of memory arrays.

26. The system of claim 25, wherein: To retrieve the plurality of data segments, the logic block is further configured to retrieve the plurality of data segments via a corresponding first interface block of the plurality of interface blocks; and To retrieve the parity information, the logic block is further configured to retrieve the parity information via one or more respective second interface blocks of the plurality of interface blocks.

27. The system of claim 25, wherein an interface block of the plurality of interface blocks is configured to: An error control operation is performed on the data segment based on error control information associated with the data segment, wherein detecting the error in the data segment is based on performing the error control operation.

28. A system comprising: a set of one or more second semiconductor dies of the semiconductor system, the set of one or more second semiconductor dies comprising a plurality of memory arrays; and a first semiconductor die of the semiconductor system coupled to the set of one or more second semiconductor dies, the first semiconductor die comprising a logic block configured to: receiving a command to read a data segment stored at the semiconductor system; retrieving a plurality of data segments of a data set including the data segment based on receiving the command, each of the plurality of data segments being retrieved from a respective first memory array of the plurality of memory arrays; retrieving error correction information associated with the data set based on receiving the command, the error correction information being retrieved from one or more respective second memory arrays of the plurality of memory arrays; and An error control operation is performed on the data set based on the error correction information.

29. The system of claim 28, wherein the first semiconductor die further comprises a plurality of interface blocks coupled to the logic block, the plurality of interface blocks each operable to access one or more respective memory arrays of the plurality of memory arrays.

30. The system of claim 29, wherein: To retrieve the plurality of data segments, the logic block is further configured to retrieve the plurality of data segments via a corresponding first interface block of the plurality of interface blocks; and To retrieve the error correction information, the logic block is further configured to retrieve the error correction information via one or more respective second interface blocks of the plurality of interface blocks.

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