Semiconductor device and method of manufacturing the same

Abstract

The present invention relates to a method for manufacturing a semiconductor device, comprising: a step for forming a second silicon carbide layer, which has a first conductivity-type impurity density different from that of a first silicon carbide layer and has a first film thickness D2, in a first region on the upper surface of the first silicon carbide layer of a first conductivity type; a step for forming a third silicon carbide layer of the second conductivity type having a film thickness D4 in a second region of the upper surface; a step for forming a fourth silicon carbide layer on the first silicon carbide layer, the fourth silicon carbide layer having a lower concentration of first conductivity-type impurities than the second silicon carbide layer and having a film thickness D1; a step for measuring a second film thickness (D3) of the second silicon carbide layer and a film thickness (D1) of the fourth silicon carbide layer in a direction from the first silicon carbide layer toward the fourth silicon carbide layer after the fourth silicon carbide layer has been formed; and forming a trench penetrating the fourth silicon carbide layer and reaching a predetermined depth of the third silicon carbide layer on the basis of the film thickness D1 of the fourth silicon carbide layer, the first film thickness D2 of the second silicon carbide layer, the second film thickness D3, and the film thickness D4 of the third silicon carbide layer.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same. Background Art

[0002] As a material for the next generation of semiconductor devices, SiC (silicon carbide) is expected. Compared with Si (silicon), silicon carbide has a band gap of about 3 times, a breakdown electric field strength of about 10 times, and a thermal conductivity of about 3 times. Therefore, by using SiC, semiconductor devices with low loss and high temperature operation can be realized.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2019-004010

[0006] Patent Document 2: Japanese Patent Application Publication No. 2017-050516 Summary of the invention

[0007] Problem that the invention aims to solve

[0008] An object of the present invention is to provide a semiconductor device with improved yield and a method for manufacturing the same.

[0009] Means used to solve problems

[0010] The method for manufacturing a semiconductor device of an embodiment comprises the following steps: a step of forming a second silicon carbide layer in a first region on an upper surface of a first silicon carbide layer of a first conductivity type, the second silicon carbide layer having a first conductivity type impurity density different from that of the first silicon carbide layer and having a first film thickness D2; a step of forming a third silicon carbide layer of a second conductivity type having a film thickness D4 in a second region on the upper surface; a step of forming a fourth silicon carbide layer on the first silicon carbide layer, the fourth silicon carbide layer having a first conductivity type impurity concentration lower than that of the second silicon carbide layer and having a film thickness D1; ​​a step of measuring a second film thickness D3 of the second silicon carbide layer in a direction from the first silicon carbide layer to the fourth silicon carbide layer after the fourth silicon carbide layer is formed, and a film thickness D1 of the fourth silicon carbide layer; and a step of forming a groove penetrating the fourth silicon carbide layer and reaching a specified depth of the third silicon carbide layer based on the film thickness D1 of the fourth silicon carbide layer, the first film thickness D2 of the second silicon carbide layer, the second film thickness D3 of the second silicon carbide layer, and the film thickness D4 of the third silicon carbide layer.

[0011] Effects of the Invention

[0012] According to the present invention, it is possible to provide a semiconductor device with improved yield and a method for manufacturing the same. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1It is a schematic cross-sectional view of the semiconductor device according to the first embodiment.

[0014] Figure 2 This is a schematic diagram showing an example of a location where the first area is arranged.

[0015] Figure 3 Schematic cross-sectional views showing the manufacturing process of the semiconductor device according to the first embodiment.

[0016] Figure 4 It is a schematic cross-sectional view of a semiconductor device according to a second embodiment.

[0017] Figure 5 Schematic cross-sectional views showing the manufacturing process of the semiconductor device according to the second embodiment.

[0018] Figure 6 It is a schematic cross-sectional view of a semiconductor device according to a third embodiment.

[0019] Figure 7 It is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the third embodiment.

[0020] Figure 8 It is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment. DETAILED DESCRIPTION

[0021] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following description, the same reference numerals are given to the same components and the like, and the description of the components and the like that have been described once will be appropriately omitted.

[0022] In the following instructions, when using n + 、n、n - and p + ,p,p - In the case of symbols, these symbols indicate the relative high and low impurity concentrations in each conductivity type. + Compared with n, the impurity concentration of n-type is relatively high. - Indicates that the impurity concentration of n-type is relatively lower than that of n-type. + Compared with p type, the impurity concentration of p type is relatively high. - Indicates that the p-type impurity concentration is relatively lower than that of the p-type. + Type, n - The type is abbreviated as n type, and p + Type, p - The type is abbreviated as p-type.

[0023] The impurity concentration can be measured by CV measurement (capacitance measurement). In addition, the impurity concentration can be measured, for example, by SIMS (Secondary Ion Mass Spectrometry). In addition, the relative level of the impurity concentration can also be determined, for example, based on the level of the carrier concentration obtained by SCM (Scanning Capacitance Microscopy). In addition, the depth and other distances of the impurity region can be obtained, for example, by SIMS. In addition, the width, depth and other distances of the impurity region can be obtained, for example, based on the SCM image.

[0024] Hereinafter, the first conductivity type is referred to as n-type, and the second conductivity type is referred to as p-type.

[0025] In this specification, in order to indicate the positional relationship of components, the upper direction of the drawings is described as "up", and the lower direction of the drawings is described as "down". In this specification, the concepts of "up" and "down" are not necessarily terms indicating the relationship with the direction of gravity.

[0026] (First Embodiment)

[0027] The method for manufacturing a semiconductor substrate of the present embodiment comprises the following steps: a step of forming a second silicon carbide layer in a first region on an upper surface of a first silicon carbide layer of a first conductivity type, the second silicon carbide layer having a first conductivity type impurity density different from that of the first silicon carbide layer and having a first film thickness D2; a step of forming a third silicon carbide layer of a second conductivity type having a film thickness D4 in a second region on the upper surface; a step of forming a fourth silicon carbide layer on the first silicon carbide layer, the fourth silicon carbide layer having a first conductivity type impurity concentration lower than that of the second silicon carbide layer and having a film thickness D1; ​​a step of measuring a second film thickness D3 of the second silicon carbide layer in a direction from the first silicon carbide layer to the fourth silicon carbide layer after the fourth silicon carbide layer is formed, and a film thickness D1 of the fourth silicon carbide layer; and a step of forming a groove penetrating the fourth silicon carbide layer and reaching a specified depth of the third silicon carbide layer based on the film thickness D1 of the fourth silicon carbide layer, the first film thickness D2 of the second silicon carbide layer, the second film thickness D3 of the second silicon carbide layer, and the film thickness D4 of the third silicon carbide layer.

[0028] Figure 1 2 is a schematic cross-sectional view of the semiconductor device 100 according to the present embodiment.

[0029] The semiconductor device 100 includes a first electrode 60 , a silicon carbide substrate 2 , a first silicon carbide layer 4 , a second silicon carbide layer 20 , a third silicon carbide layer 22 , a fourth silicon carbide layer 24 , a fifth silicon carbide layer 26 , a sixth silicon carbide layer 28 , a trench 70 , a first insulating film 72 , a second insulating film 74 , a second electrode 62 , and a third electrode 64 .

[0030] The semiconductor device 100 of the present embodiment is a trench-type MISFET (Metal Insulator Semiconductor Field Effect Transistor). In addition, MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is a type of MISFET.

[0031] Here, an X direction, a Y direction perpendicularly intersecting the X direction, and a Z direction perpendicularly intersecting the X direction and the Y direction are defined. The first electrode 60, the silicon carbide substrate 2, the first silicon carbide layer 4, the fourth silicon carbide layer 24, and the third electrode 64 are arranged in parallel in the XY plane. The Z direction is parallel to the direction in which the first electrode 60, the silicon carbide substrate 2, the first silicon carbide layer 4, the fourth silicon carbide layer 24, and the third electrode 64 are stacked. The Z direction is parallel to the direction from the first electrode 60 to the third electrode 64.

[0032] n + The silicon carbide substrate 2 of type includes, for example, 1×10 18 atoms / cm 3 Above and 1×10 19 atoms / cm 3 Here, the n-type impurity is, for example, N (nitrogen). However, the n-type impurity may be, for example, P (phosphorus). In addition, the n-type impurity may be, for example, both N (nitrogen) and P (phosphorus). The silicon carbide substrate 2 is, for example, a hexagonal SiC substrate (n + Substrate). The silicon carbide substrate 2 is a substrate that functions as a drain of a MISFET, for example.

[0033] n - The first silicon carbide layer 4 of the type is provided on the silicon carbide substrate 2. The first silicon carbide layer 4 includes, for example, 1×10 15 atoms / cm 3 Above and 5×10 16 atoms / cm 3 The first silicon carbide layer 4 has a thickness of, for example, 4 μm or more and 50 μm or less. The first silicon carbide layer 4 is, for example, a silicon carbide layer formed by epitaxial growth using a CVD (Chemical Vapor Deposition) method on the silicon carbide substrate 2. The first silicon carbide layer 4 is, for example, a layer that functions as a drift layer of a MISFET.

[0034] The first silicon carbide layer 4 has a first surface 6 and a second surface 8. The second surface 8 is provided on the opposite side of the first surface 6. The second surface 8 is in contact with the silicon carbide substrate 2, for example. The first surface 6 is an example of an upper surface.

[0035] The n-type second silicon carbide layer 20 is provided in the first region 10 of the first surface 6. The n-type impurity concentration of the second silicon carbide layer 20 is different from the n-type impurity concentration of the first silicon carbide layer 4. When the second silicon carbide layer 20 is used as a current diffusion layer of a MOSFET, the n-type impurity concentration of the second silicon carbide layer 20 is preferably higher than the n-type impurity concentration of the first silicon carbide layer 4. Hereinafter, the n-type impurity concentration of the second silicon carbide layer 20 is higher than the n-type impurity concentration of the first silicon carbide layer 4 for explanation. The second silicon carbide layer 20 includes, for example, 5×10 16 atoms / cm 3 Above and 5×10 17 atoms / cm 3 The second silicon carbide layer 20 has a thickness of, for example, 0.2 μm or more and 1.0 μm or less. The second silicon carbide layer 20 is a base doping layer for CV measurement of impurity concentration described later. The second silicon carbide layer 20 is formed, for example, by ion implanting n-type impurities into the first region 10 using a patterned hard mask not shown. Here, as a hard mask, for example, a silicon oxide film or a silicon nitride film is preferably used.

[0036] Figure 2 AB is a schematic diagram showing an example of a location where the first area 10 is arranged. Figure 2 A is a schematic plan view of a wafer 200 for manufacturing the semiconductor device 100 of the present embodiment. The semiconductor device 100 is provided on a semiconductor chip 150. The semiconductor chip 150 is obtained by dicing the wafer 200.

[0037] The TEG (Test Element Group) region (TEG chip) 10b is an example of a region where the first region 10 is configured. The TEG region 10b4 is provided at the end of the wafer surface of the wafer 200. The TEG region 10b1, the TEG region 10b2, and the TEG region 10b3 are provided at a portion of the wafer surface of the wafer 200 that is closer to the center than the TEG region 10b4. The TEG region is a region where a test chip is provided on the wafer 200 for the purpose of evaluating semiconductor processes and semiconductor devices. In addition, the size of the TEG region 10b may be appropriately changed according to the width of the CV measurement probe R described later.

[0038] The dicing region (scribe lane) 10c is another example of a region where the first region 10 is configured. The dicing region 10c is provided between each semiconductor chip 150. The dicing region 10c is a region cut by a dicing blade or the like during dicing. In addition, the size of the dicing region (scribe lane) 10c may be appropriately changed according to the width of the CV measurement probe R described later.

[0039] Figure 2 B is a diagram showing another example of an area where the first area 10 is arranged. Figure 2 B shows a semiconductor chip 180 as an example. Figure 2 B is a schematic top view of the semiconductor chip 180. An outer peripheral region 92 is provided around the device region (active region) 90. The outer peripheral region 92 is another example of a region where the first region 10 is disposed. In addition, the size of the outer peripheral region 92 may be appropriately changed according to the width of the CV measurement probe R described later.

[0040] In addition, the place where the first area 10 is arranged is not limited to the above-mentioned place.

[0041] The p-type third silicon carbide layer 22 is provided in the second region 12 of the first surface 6. The third silicon carbide layer 22 is a layer provided at the bottom of the trench 70 for the purpose of relaxing the electric field at the bottom of the trench 70 described later. The third silicon carbide layer 22 includes, for example, 5×10 16 atoms / cm 3 Above and 5×10 17 atoms / cm 3 The thickness of the third silicon carbide layer 22 is, for example, 0.2 μm or more and 1.0 μm or less. The p-type impurity is, for example, Al (aluminum). The third silicon carbide layer 22 is formed by, for example, ion implantation into the second region 12 using a patterned hard mask (not shown). Figure 1 In the figure, the length of the first region 10 in the X direction is shown to be substantially the same as the length of the second region 12 in the X direction. However, the length of the first region 10 in the X direction may be appropriately changed according to the width of the CV measurement probe R described later.

[0042] n - The fourth silicon carbide layer 24 of the type is provided on the first silicon carbide layer 4, the second silicon carbide layer 20, and the third silicon carbide layer 22. The fourth silicon carbide layer 24 is a layer formed on the first silicon carbide layer 4, the second silicon carbide layer 20, and the third silicon carbide layer 22 after the second silicon carbide layer 20 and the third silicon carbide layer 22 are formed. The fourth silicon carbide layer 24 is, for example, a layer that functions as a drift layer of a MISFET. The fourth silicon carbide layer 24, for example, includes 1×10 15 atoms / cm 3 Above and 5×1016 atoms / cm 3 The n-type impurity concentration of the fourth silicon carbide layer 24 is lower than the n-type impurity concentration of the second silicon carbide layer 20. The film thickness of the fourth silicon carbide layer 24 is, for example, not less than 0.5 μm and not more than 2 μm.

[0043] The p-type fifth silicon carbide layer 26 is provided on the fourth silicon carbide layer 24. The fifth silicon carbide layer 26 functions as a base of the MISFET. Figure 1 The fifth silicon carbide layer 26 a and the fifth silicon carbide layer 26 b are illustrated in FIG.

[0044] The n-type sixth silicon carbide layer 28 is provided on the fifth silicon carbide layer 26. The sixth silicon carbide layer 28 functions as a contact layer of the MISFET. Figure 1 2 , a sixth silicon carbide layer 28 a and a sixth silicon carbide layer 28 b are illustrated.

[0045] The trench 70 reaches the third silicon carbide layer 22 from the fourth silicon carbide layer 24 . The bottom of the trench 70 is disposed in the third silicon carbide layer 22 .

[0046] The first insulating film 72 is provided on the inner wall of the trench 70 in the trench 70. The first insulating film 72 is a gate insulating film of the MOSFET. The first insulating film 72 includes an insulating material such as silicon oxide, for example.

[0047] The second electrode 62 is provided in the trench 70 so as to face the fifth silicon carbide layer 26 via the first insulating film 72. The second electrode 62 is a gate electrode of the MISFET and is made of a conductive material such as conductive polysilicon containing impurities.

[0048] The second insulating film 74 is provided on the second electrode 62. The second insulating film 74 includes an insulating material such as silicon oxide.

[0049] The first electrode 60 is disposed under the silicon carbide substrate 2. The first electrode 60 is in contact with the silicon carbide substrate 2. The first electrode 60 includes, for example, a metal or a metal semiconductor compound. The first electrode 60 includes, for example, NiSi (nickel silicide), Ti (titanium), Ni (nickel), Ag (silver) or Au (gold). The first electrode 60 is a drain electrode of the MISFET.

[0050] The third electrode 64 is provided on the fourth silicon carbide layer 24, the fifth silicon carbide layer 26, the sixth silicon carbide layer 28 and the second insulating film 74. The third electrode 64 is, for example, in contact with the fourth silicon carbide layer 24, the fifth silicon carbide layer 26, the sixth silicon carbide layer 28 and the second insulating film 74. The third electrode 64 has, for example, a stacked structure of Ti (titanium) and Al (aluminum). In addition, the third electrode 64 may also include a metal silicide such as NiSi in a portion in contact with the fourth silicon carbide layer 24, the fifth silicon carbide layer 26 and the sixth silicon carbide layer 28.

[0051] Figure 3 AF are schematic cross-sectional views showing the manufacturing steps of the semiconductor device 100 according to the present embodiment.

[0052] First, in Figure 3 A is formed on the silicon carbide substrate 2 (not shown) by epitaxial growth using CVD. - Type first silicon carbide layer 4.

[0053] Next, in the first region 10 of the first surface 6 of the first silicon carbide layer 4, an n-type second silicon carbide layer 20 is formed by ion implantation using, for example, a patterned hard mask not shown. Here, the film thickness of the second silicon carbide layer 20 in the depth direction (-z direction) is D2 (the first film thickness D2 of the second silicon carbide layer 20). The first film thickness D2 of the second silicon carbide layer 20 can be obtained, for example, by performing a CV measurement on the second silicon carbide layer 20 after performing an activation annealing treatment of impurities described later. In addition, in the case of SiC, impurity elements are difficult to diffuse compared to Si. Therefore, in the case of SiC, under general activation annealing conditions of impurity elements, diffusion of impurity elements hardly occurs. Therefore, in the case of forming the second silicon carbide layer 20 by ion implantation, there is almost no difference between the design value of the film thickness and the measured value. Therefore, this design value can also be used as the first film thickness D2.

[0054] In addition, in the second region 12 of the first surface 6 of the first silicon carbide layer 4, a p-type third silicon carbide layer 22 is formed by ion implantation using a patterned hard mask not shown. The film thickness of the third silicon carbide layer 22 in the depth direction (-z direction) is D4. Here, the third silicon carbide layer 22 is formed by ion implantation. As described above, in the case of SiC, impurity elements are difficult to diffuse compared to Si. Therefore, in the case of SiC, under general activation annealing conditions of impurity elements, diffusion of impurity elements hardly occurs. Therefore, in the case of forming the third silicon carbide layer 22 by ion implantation, there is almost no difference between the design value of the film thickness and the measured value. Therefore, the design value of the film thickness of the third silicon carbide layer 22 can be adopted as the film thickness D4. ( Figure 3 A).

[0055] Next, an epitaxial growth method using a CVD method is used to form n silicon carbide layers 4, 20, and 22 on the first silicon carbide layer 4, the second silicon carbide layer 20, and the third silicon carbide layer 22. - The fourth silicon carbide layer 24 is of type.

[0056] The formation of the fourth silicon carbide layer 24 is described. The silicon carbide substrate 2, the first silicon carbide layer 4, the second silicon carbide layer 20 and the third silicon carbide layer 22 are placed in an epitaxial growth furnace not shown. Next, in an H2 (hydrogen) gas atmosphere, for example, it is heated to a temperature of 1500°C or more and 1700°C or less, thereby etching and cleaning the first surface 6 with H2. By this etching, the film thickness of the second silicon carbide layer 20 is reduced from D2 to D3 (the second film thickness D3 of the second silicon carbide layer 20). The difference between D2 and D3 is, for example, greater than 0.01 μm and about 0.2 μm. However, the difference between D2 and D3 is not limited to this.

[0057] In addition, the film thickness of the third silicon carbide layer 22 is also reduced from D4 by the above-mentioned etching.

[0058] Next, Si (silicon) gas and C (carbon) gas as SiC raw material gas and n-type impurity gas are put into the epitaxial growth furnace together with H2 (hydrogen) gas. Here, Si (silicon) gas is, for example, SiH4 (monosilane) gas. In addition, C (carbon) gas is, for example, C3H8 (propane) gas. In addition, n-type impurity gas is, for example, N2 (nitrogen) gas. Then, for example, by maintaining at a temperature of 1500°C or more and 1700°C or less, the fourth silicon carbide layer 24 is formed. Here, the film thickness of the fourth silicon carbide layer 24 in the depth direction (z direction) is D1.

[0059] Here, the cleaning of the first surface 6 by H 2 etching and the formation of the fourth silicon carbide layer 24 are usually performed continuously in the same epitaxial growth furnace.

[0060] Next, the CV measurement probe R is moved to the fourth silicon carbide layer 24 on the second silicon carbide layer 20. Then, the CV measurement is performed ( Figure 3 C). Here, the CV measurement probe R used for CV measurement can be a contact type or a non-contact type. As a non-contact CV measurement probe, for example, a CnCV230 device manufactured by SemilabSDI can be preferably used. Figure 3 AC, Figure 3 In EF, the length of the first region 10 in the X direction is shown to be substantially the same as the length of the second region 12 in the X direction. However, the length of the first region 10 in the X direction may be changed appropriately according to the width of the CV measurement probe R.

[0061] Figure 3D is the concentration distribution (profile) in the depth direction (-z direction) of the impurity concentration obtained by CV measurement. Using this concentration distribution, the film thickness D1 of the fourth silicon carbide layer 24 and the second film thickness D3 of the second silicon carbide layer 20 can be obtained. Here, for example, the n-type impurity concentration of the second silicon carbide layer 20 is higher than the n-type impurity concentration of the first silicon carbide layer 4 and the n-type impurity concentration of the fourth silicon carbide layer 24. Therefore, the portion of the depth where the n-type impurity concentration is higher can be set as the second film thickness D3 of the second silicon carbide layer 20.

[0062] The amount by which the second silicon carbide layer 20 is etched is ((the first film thickness D2 of the second silicon carbide layer 20) - (the second film thickness D3 of the second silicon carbide layer 20)). Therefore, the amount by which the first surface 6 and the third silicon carbide layer 22 are etched can be set to ((the first film thickness D2 of the second silicon carbide layer 20) - (the second film thickness D3 of the second silicon carbide layer 20)).

[0063] Next, a fifth silicon carbide layer 26 is formed on the fourth silicon carbide layer 24 by ion implantation using a hard mask (not shown) or the like. Also, a sixth silicon carbide layer 28 ( Figure 3 E).

[0064] Here, for example, a p-type contact layer (not shown) may be formed. Also, an activation annealing treatment of impurities may be performed.

[0065] Next, a groove 70 of a specified depth penetrating the fourth silicon carbide layer 24 and reaching the third silicon carbide layer 22 is formed based on the film thickness D1 of the fourth silicon carbide layer 24, the first film thickness D2 of the second silicon carbide layer 20, the second film thickness D3 of the second silicon carbide layer 20, and the film thickness D4 of the third silicon carbide layer, for example by RIE (Reactive Ion Etching).

[0066] Here, when the film thickness of the third silicon carbide layer 22 is set to D4, the specified depth of the groove 70 is preferably determined based on (the film thickness D1 of the fourth silicon carbide layer) + ((the film thickness D4 of the third silicon carbide layer) - ((the first film thickness D2 of the second silicon carbide layer) - (the second film thickness D3 of the second silicon carbide layer))) / 2.

[0067] Next, the first insulating film 72 , the second electrode 62 , the second insulating film 74 , the first electrode 60 , and the third electrode 64 are formed as appropriate to obtain the semiconductor device 100 of the present embodiment.

[0068] Next, the effects of this embodiment will be described.

[0069] In the trench type MISFET, in order to relax the electric field at the bottom of the trench 70 , it is considered to provide the p-type third silicon carbide layer 22 at the location where the bottom of the trench 70 is located.

[0070] However, after forming the third silicon carbide layer 22, the first silicon carbide layer 4, the second silicon carbide layer 20, and the third silicon carbide layer 22 are etched by the H2 gas introduced into the epitaxial growth furnace before forming the fourth silicon carbide layer 24. The etching amount of the H2 gas and the film thickness of the fourth silicon carbide layer 24 vary depending on the state of the epitaxial growth furnace, the warping of the substrate, and the like.

[0071] Therefore, when the trench 70 is formed, the bottom of the trench 70 may not be provided in the third silicon carbide layer 22. This causes a problem in that the yield of the semiconductor device is reduced.

[0072] Therefore, the manufacturing method of the semiconductor device of the present embodiment comprises the following steps: a step of forming a second silicon carbide layer in a first region on an upper surface of a first silicon carbide layer of a first conductivity type, the second silicon carbide layer having a first conductivity type impurity density different from that of the first silicon carbide layer and having a first film thickness D2; a step of forming a third silicon carbide layer of a second conductivity type having a film thickness D4 in a second region on the upper surface; a step of forming a fourth silicon carbide layer on the first silicon carbide layer, the fourth silicon carbide layer having a first conductivity type impurity concentration lower than that of the second silicon carbide layer and having a film thickness D1; ​​a step of measuring a second film thickness D3 of the second silicon carbide layer in a direction from the first silicon carbide layer to the fourth silicon carbide layer after the fourth silicon carbide layer is formed, and a film thickness D1 of the fourth silicon carbide layer; and a step of forming a groove penetrating the fourth silicon carbide layer and reaching a specified depth of the third silicon carbide layer based on the film thickness D1 of the fourth silicon carbide layer, the first film thickness D2 of the second silicon carbide layer, the second film thickness D3 of the second silicon carbide layer, and the film thickness D4 of the third silicon carbide layer.

[0073] The above-mentioned etching amount of the H2 gas can be obtained in the manufacturing process of the semiconductor device by using the first film thickness D2 and the second film thickness D3 of the second silicon carbide layer. Therefore, the obtained etching amount of the H2 gas can be reflected in the depth of the formed groove 70. Therefore, a manufacturing method of a semiconductor device with improved yield can be provided.

[0074] When the depth of the groove 70 is determined based on (the film thickness D1 of the fourth silicon carbide layer) + ((the film thickness D4 of the third silicon carbide layer) - ((the first film thickness D2 of the second silicon carbide layer) - (the second film thickness D3 of the second silicon carbide layer))) / 2), the depth of the groove 70 is controlled in such a way that the bottom of the groove 70 becomes the center of the third silicon carbide layer in the Z direction. Therefore, a method for manufacturing a semiconductor device with a further improved yield can be provided.

[0075] The first region 10 may be provided in the TEG region, the scribe line street, and the peripheral region because the influence on the device characteristics can be suppressed.

[0076] According to the present embodiment, a semiconductor device with improved yield and a method for manufacturing the same can be provided.

[0077] (Second Embodiment)

[0078] The present embodiment is different from the first embodiment in that the first area is provided around the second area on the first surface. Here, description of the contents overlapping with the first embodiment is omitted.

[0079] Figure 4 1 is a schematic cross-sectional view of a semiconductor device 110 according to the present embodiment. Figure 5 AF are schematic cross-sectional views showing the manufacturing process of the semiconductor device according to the present embodiment.

[0080] The first region 10 is provided around the second region 12 so as to surround the second region 12. Therefore, the second silicon carbide layer 20 is provided around the third silicon carbide layer 22.

[0081] In other words, in the semiconductor device 110 of the present embodiment, it can be said that the first region 10 is also provided in the device region 90 ( Figure 2 B) Therefore, in the semiconductor device 110 of the present embodiment, it can be said that the second silicon carbide layer 20 is also provided in the device region 90 .

[0082] The second silicon carbide layer 20 functions as a current diffusion layer, and thus the resistance component and on-resistance of the semiconductor device can be further reduced.

[0083] In addition, the second silicon carbide layer 20 of the present embodiment is formed on the first silicon carbide layer 4 by an epitaxial growth method using a CVD method, for example, similarly to the first silicon carbide layer 4. This can reduce the ion implantation step by one step.

[0084] According to the present embodiment, a semiconductor device with improved yield and a method for manufacturing the same can be provided.

[0085] (Third Embodiment)

[0086] The present embodiment is different from the first and second embodiments in that the concentration distribution of the first conductivity type impurity in the second silicon carbide layer in the direction from the first silicon carbide layer to the fourth silicon carbide layer has a plurality of peaks.

[0087] The semiconductor device of this embodiment comprises: a first electrode; a first conductive type silicon carbide substrate, which is arranged on the first electrode; a first conductive type silicon carbide layer, which is arranged on the silicon carbide substrate; and a second silicon carbide layer, which is arranged in a first region of an upper surface of the first silicon carbide layer, wherein the first conductive type impurity density is higher than that of the first silicon carbide layer, and the concentration distribution of the first conductive type impurity in a direction from the first electrode to the first silicon carbide layer has a plurality of peaks; a second conductive type third silicon carbide layer, which is arranged in a second region of the upper surface; and a fourth silicon carbide layer, which is arranged on the first silicon carbide layer. a fifth silicon carbide layer of the second conductivity type, which is disposed on the fourth silicon carbide layer; a sixth silicon carbide layer of the first conductivity type, which is disposed on the fifth silicon carbide layer; a groove, which penetrates the fourth silicon carbide layer and reaches the third silicon carbide layer; a first insulating film, which is disposed in the groove; a second electrode, which is disposed in the groove in a manner opposite to the fifth silicon carbide layer with the first insulating film interposed therebetween; a second insulating film, which is disposed on the second electrode; and a third electrode, which is disposed on the sixth silicon carbide layer and the second insulating film.

[0088] Here, description of contents overlapping with those of the first embodiment and the second embodiment will be omitted.

[0089] Figure 6 is a schematic cross-sectional view of a semiconductor device 120 according to this embodiment. Figure 6 In the embodiment, the second silicon carbide layer 20 is provided around the third silicon carbide layer 22, for example, similarly to the semiconductor device 110 of the second embodiment. Furthermore, the second silicon carbide layer 20 includes: an eighth silicon carbide layer 20a having a higher n-type impurity concentration than the first silicon carbide layer 4, a ninth silicon carbide layer 20b provided on the eighth silicon carbide layer 20a and having a lower n-type impurity concentration than the eighth silicon carbide layer 20a, and a tenth silicon carbide layer 20c provided on the ninth silicon carbide layer 20b and having a higher n-type impurity concentration than the ninth silicon carbide layer 20b and the fourth silicon carbide layer 24. For example, the film thicknesses of the eighth silicon carbide layer 20a, the ninth silicon carbide layer 20b, and the tenth silicon carbide layer 20c are respectively about 0.1 μm. The n-type impurity concentrations of the eighth silicon carbide layer 20a and the tenth silicon carbide layer 20c are, for example, 1×10 17 atoms / cm 3 In addition, the n-type impurity concentration of the ninth silicon carbide layer 20b is, for example, 5×10 16 atoms / cm 3 about.

[0090] Figure 7 AF are schematic cross-sectional views showing the manufacturing process of the semiconductor device of this embodiment. Figure 7In D, the concentration distribution (profile) in the depth direction (−z direction) of the impurity concentration obtained by CV measurement has a plurality of peaks corresponding to the n-type impurity concentrations of the eighth silicon carbide layer 20 a and the tenth silicon carbide layer 20 c .

[0091] In this embodiment, it is possible to Figure 7 D is used to estimate the film thickness of the second silicon carbide layer 20. Specifically, the film thicknesses of the eighth silicon carbide layer 20a, the ninth silicon carbide layer 20b, and the tenth silicon carbide layer 20c are each about 0.1 μm. Figure 7 D, the amount of etching by H2 gas can be visually known. Figure 7 It can be seen from D that the tenth silicon carbide layer 20 c is etched by about half, so the etching amount can be estimated to be about 0.05 μm. In this way, the process of obtaining the film thickness of the second silicon carbide layer 20 before forming the fourth silicon carbide layer 24 can be simplified.

[0092] According to the present embodiment, a semiconductor device with improved yield and a method for manufacturing the same can be provided.

[0093] (Fourth Embodiment)

[0094] The semiconductor device of this embodiment is different from the semiconductor devices of the first to third embodiments in that a seventh silicon carbide layer 30 having a higher first conductivity type impurity concentration than the first silicon carbide layer 4 and the fourth silicon carbide layer 24 is further provided between the first silicon carbide layer 4 and the fourth silicon carbide layer 24 .

[0095] The manufacturing method of the semiconductor device of the present embodiment differs from the manufacturing method of the semiconductor device of the first to third embodiments in that, after forming the third silicon carbide layer and before forming the fourth silicon carbide layer, there is also a step of forming a seventh silicon carbide layer on the third silicon carbide layer having a first conductive type impurity concentration higher than that of the first silicon carbide layer and the fourth silicon carbide layer.

[0096] Here, description of contents overlapping with those of the first to third embodiments will be omitted.

[0097] Figure 8 1 is a schematic cross-sectional view of a semiconductor device 130 according to the present embodiment.

[0098] The seventh silicon carbide layer 30 functions as a current diffusion layer, and therefore, the resistance component and the on-resistance of the semiconductor device can be further reduced.

[0099] According to the present embodiment, a semiconductor device with improved yield and a method for manufacturing the same can be provided.

[0100] Several embodiments and examples of the present invention have been described, but these embodiments and examples are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments or their variations are included in the scope or subject matter of the invention, and are included in the invention described in the claims and their equivalents.

[0101] Furthermore, the above-mentioned embodiments can be summarized as the following technical solutions.

[0102] (Technical Solution 1)

[0103] A method for manufacturing a semiconductor device comprises the following steps:

[0104] forming a second silicon carbide layer in a first region on an upper surface of the first silicon carbide layer of the first conductivity type, wherein the second silicon carbide layer has a first conductivity type impurity density different from that of the first silicon carbide layer and has a first film thickness D2;

[0105] forming a third silicon carbide layer of the second conductivity type having a film thickness D4 in a second region of the upper surface;

[0106] forming a fourth silicon carbide layer on the first silicon carbide layer, wherein the fourth silicon carbide layer has a lower first conductivity type impurity concentration than the second silicon carbide layer and has a film thickness D1;

[0107] a step of measuring a second film thickness D3 of the second silicon carbide layer in a direction from the first silicon carbide layer to the fourth silicon carbide layer and a film thickness D1 of the fourth silicon carbide layer after forming the fourth silicon carbide layer; and

[0108] A step of forming a trench having a predetermined depth penetrating the fourth silicon carbide layer and reaching the third silicon carbide layer based on the film thickness D1 of the fourth silicon carbide layer, the first film thickness D2 and the second film thickness D3 of the second silicon carbide layer, and the film thickness D4 of the third silicon carbide layer.

[0109] (Technical Solution 2)

[0110] A method for manufacturing a semiconductor device according to Technical Solution 1, wherein a groove of the specified depth is formed based on (film thickness D1 of the fourth silicon carbide layer) + ((film thickness D4 of the third silicon carbide layer) - ((first film thickness D2 of the second silicon carbide layer) - (second film thickness D3 of the second silicon carbide layer))) / 2.

[0111] (Technical Solution 3)

[0112] The method for manufacturing a semiconductor device according to technical solution 1 or technical solution 2, wherein before the step of forming a groove penetrating the fourth silicon carbide layer and reaching the predetermined depth of the third silicon carbide layer based on the film thickness D1 of the fourth silicon carbide layer, the first film thickness D2 and the second film thickness D3 of the second silicon carbide layer, and the film thickness D4 of the third silicon carbide layer, the method further comprises the following step:

[0113] forming a fifth silicon carbide layer of the second conductivity type on the fourth silicon carbide layer on the third silicon carbide layer; and

[0114] forming a sixth silicon carbide layer of the first conductivity type on the fifth silicon carbide layer,

[0115] After the step of forming the groove penetrating the fourth silicon carbide layer and reaching the predetermined depth of the third silicon carbide layer based on the film thickness D1 of the fourth silicon carbide layer, the first film thickness D2 and the second film thickness D3 of the second silicon carbide layer, and the film thickness D4 of the third silicon carbide layer, the following step is further included:

[0116] forming a first insulating film in the trench;

[0117] forming a second electrode in the trench so as to face the fifth silicon carbide layer via the first insulating film;

[0118] forming a second insulating film on the second electrode;

[0119] forming a first electrode under the first silicon carbide layer; and

[0120] The step of forming a third electrode on the sixth silicon carbide layer.

[0121] (Technical Solution 4)

[0122] The method for manufacturing a semiconductor device according to any one of Technical Solutions 1 to 3, wherein, on the upper surface, the first region is arranged around the second region.

[0123] (Technical Solution 5)

[0124] The method for manufacturing a semiconductor device according to any one of Technical Solution 1 to Technical Solution 4, wherein the first region is provided in a TEG region of the semiconductor device.

[0125] (Technical Solution 6)

[0126] The method for manufacturing a semiconductor device according to any one of Technical Solutions 1 to 4, wherein the first region is provided on a scribe line of the semiconductor device.

[0127] (Technical Solution 7)

[0128] The method for manufacturing a semiconductor device according to Technical Solution 1, wherein the first region is provided in a peripheral region of the semiconductor device.

[0129] (Technical Solution 8)

[0130] The method for manufacturing a semiconductor device according to any one of Technical Solutions 1 to 7, wherein a concentration distribution of the first conductive type impurity of the second silicon carbide layer in a direction from the first silicon carbide layer to the fourth silicon carbide layer has a plurality of peaks.

[0131] (Technical Solution 9)

[0132] A method for manufacturing a semiconductor device according to any one of Technical Solutions 1 to Technical Solutions 7, wherein, after forming the third silicon carbide layer and before forming the fourth silicon carbide layer, the following step is further included: forming a seventh silicon carbide layer on the third silicon carbide layer having a first conductive type impurity concentration higher than that of the first silicon carbide layer and the fourth silicon carbide layer.

[0133] (Technical Solution 10)

[0134] A semiconductor device comprising:

[0135] a first electrode;

[0136] A silicon carbide substrate of a first conductivity type, disposed on the first electrode;

[0137] A first silicon carbide layer of a first conductivity type, which is disposed on the silicon carbide substrate;

[0138] a second silicon carbide layer, which is disposed in a first region of an upper surface of the first silicon carbide layer and has a higher first conductivity type impurity density than the first silicon carbide layer;

[0139] A third silicon carbide layer of the second conductivity type, which is disposed in the second region of the upper surface;

[0140] a fourth silicon carbide layer, which is disposed on the first silicon carbide layer and has a lower first conductivity type impurity concentration than the second silicon carbide layer;

[0141] a fifth silicon carbide layer of the second conductivity type, disposed on the fourth silicon carbide layer;

[0142] a sixth silicon carbide layer of the first conductivity type, disposed on the fifth silicon carbide layer;

[0143] a groove penetrating the fourth silicon carbide layer and reaching the third silicon carbide layer;

[0144] a first insulating film disposed in the trench;

[0145] a second electrode disposed in the trench so as to face the fifth silicon carbide layer via the first insulating film;

[0146] a second insulating film provided on the second electrode; and

[0147] A third electrode is provided on the sixth silicon carbide layer and the second insulating film.

[0148] Description of Reference Numerals

[0149] 2: Silicon carbide substrate

[0150] 4: First silicon carbide layer

[0151] 6: Side 1

[0152] 8: Side 2

[0153] 10: First Area

[0154] 10b: TEG area

[0155] 10c: Cutting area

[0156] 12: Second Area

[0157] 20: Second silicon carbide layer

[0158] 20a: Eighth silicon carbide layer

[0159] 20b: Ninth silicon carbide layer

[0160] 20c: tenth silicon carbide layer

[0161] 22: The third silicon carbide layer

[0162] 24: Fourth silicon carbide layer

[0163] 26: Fifth silicon carbide layer

[0164] 28: Sixth silicon carbide layer

[0165] 30: Seventh silicon carbide layer

[0166] 60: First electrode

[0167] 62: Second electrode

[0168] 64: The third electrode

[0169] 70: Groove

[0170] 72: First insulating film

[0171] 74: Second insulating film

[0172] 90: Device area

[0173] 92: Peripheral area

[0174] 100: Semiconductor devices

[0175] 110: Semiconductor devices

[0176] 120: Semiconductor devices

[0177] 130: Semiconductor devices

[0178] 150: Semiconductor chips

[0179] 180: Semiconductor chips

[0180] 200: Chip

[0181] D1: film thickness

[0182] D2: First film thickness

[0183] D3: Second film thickness

[0184] D4: film thickness

[0185] R: CV assay probe

Claims

1. A method for manufacturing a semiconductor device, comprising the following steps: forming a second silicon carbide layer in a first region on an upper surface of the first silicon carbide layer of the first conductivity type, wherein the second silicon carbide layer has a first conductivity type impurity density different from that of the first silicon carbide layer and has a first film thickness D2; forming a third silicon carbide layer of the second conductivity type having a film thickness D4 in a second region of the upper surface; forming a fourth silicon carbide layer on the first silicon carbide layer, wherein the fourth silicon carbide layer has a lower first conductivity type impurity concentration than the second silicon carbide layer and has a film thickness D1; a step of measuring a second film thickness D3 of the second silicon carbide layer in a direction from the first silicon carbide layer to the fourth silicon carbide layer and a film thickness D1 of the fourth silicon carbide layer after the fourth silicon carbide layer is formed; as well as A step of forming a trench having a predetermined depth penetrating the fourth silicon carbide layer and reaching the third silicon carbide layer based on the film thickness D1 of the fourth silicon carbide layer, the first film thickness D2 and the second film thickness D3 of the second silicon carbide layer, and the film thickness D4 of the third silicon carbide layer.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The trench of the specified depth is formed based on (film thickness D1 of the fourth silicon carbide layer)+((film thickness D4 of the third silicon carbide layer)-((first film thickness D2 of the second silicon carbide layer)-(second film thickness D3 of the second silicon carbide layer))) / 2.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: Before the step of forming a groove penetrating the fourth silicon carbide layer and reaching the predetermined depth of the third silicon carbide layer based on the film thickness D1 of the fourth silicon carbide layer, the first film thickness D2 and the second film thickness D3 of the second silicon carbide layer, and the film thickness D4 of the third silicon carbide layer, the following step is further included: forming a fifth silicon carbide layer of the second conductivity type on the fourth silicon carbide layer on the third silicon carbide layer; and forming a sixth silicon carbide layer of the first conductivity type on the fifth silicon carbide layer, After the step of forming the groove penetrating the fourth silicon carbide layer and reaching the predetermined depth of the third silicon carbide layer based on the film thickness D1 of the fourth silicon carbide layer, the first film thickness D2 and the second film thickness D3 of the second silicon carbide layer, and the film thickness D4 of the third silicon carbide layer, the following step is further included: forming a first insulating film in the trench; forming a second electrode in the trench so as to face the fifth silicon carbide layer via the first insulating film; forming a second insulating film on the second electrode; forming a first electrode under the first silicon carbide layer; and The step of forming a third electrode on the sixth silicon carbide layer.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: On the upper surface, the first region is arranged around the second region.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: The first region is provided in a TEG region of the semiconductor device.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: The first region is disposed on a scribe line of the semiconductor device.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: The first region is provided in an outer peripheral region of the semiconductor device.

8. The method for manufacturing a semiconductor device according to any one of claims 1 to 7, wherein: A concentration distribution of the first conductivity type impurity in the second silicon carbide layer in a direction from the first silicon carbide layer to the fourth silicon carbide layer has a plurality of peaks.

9. The method for manufacturing a semiconductor device according to any one of claims 1 to 7, wherein: After forming the third silicon carbide layer and before forming the fourth silicon carbide layer, the method further includes forming, on the third silicon carbide layer, a seventh silicon carbide layer having a higher first conductivity type impurity concentration than the first silicon carbide layer and the fourth silicon carbide layer.

Images