Light detection device and electronic apparatus

Abstract

Provided is a light detection device that can reduce the occurrence of difficulty in configuring a transfer gate and a charge holding section due to a reduction in pixel size. Specifically, the light detection device of the present invention comprises: a semiconductor substrate; a trench section that divides the semiconductor substrate into a plurality of element regions; a photoelectric conversion part which is formed in each of the element regions and generates and accumulates charges according to a light receiving amount; a charge holding part which is formed in each of the element regions and holds charges generated in the photoelectric conversion part; and a transfer transistor that transfers the charge accumulated in the photoelectric conversion section to the charge holding section. Further, the charge holding portion is formed so as to reach a predetermined depth within the element region from a first surface of the element region, the first surface being a surface facing a light incident surface of the element region. Furthermore, the transfer transistor has a gate electrode that continuously covers at least a portion of a first surface of the element region and at least a portion of a second surface, the first surface avoiding a first region in which the charge holding portion is formed, and the gate electrode is disposed in the element region. The second surface is a surface on the trench portion side of the element region.

Description

Technical Field

[0001] The present technology (technology according to the present disclosure) relates to a light detection device and an electronic device. Background Art

[0002] Conventionally, for example, a light detection device including a first substrate having a photoelectric conversion portion, a transfer transistor, and a charge holding portion (FD: floating diffusion portion) and a second substrate stacked on the first substrate and having a pixel transistor other than the transfer transistor has been proposed (for example, see Patent Document 1). By configuring the photoelectric conversion portion, the transfer transistor, and the FD on a substrate different from the substrate on which the pixel transistor other than the transfer transistor is configured in the light detection device described in Patent Document 1, these areas are ensured even if the pixel size is miniaturized, and the pixel characteristics can be maintained.

[0003] [Citation list]

[0004] [Patent Document]

[0005] [Patent Document 1]

[0006] International Patent Application Publication No. WO 2020 / 121725 Summary of the invention

[0007] [Technical issues]

[0008] However, in the photodetection device described in Patent Document 1, as the pixel size is further reduced in size, there is a possibility that the arrangement of the FD and the gate electrode (transfer gate) of the transfer transistor may become difficult.

[0009] An object of the present disclosure is to provide a light detection device and an electronic device which can reduce the difficulty in arranging a transfer gate and a charge holding portion caused by a reduction in pixel size.

[0010] [Solution to the problem]

[0011] As the gist of the present disclosure, the light detecting device of the present disclosure includes (a) a semiconductor substrate, (b) a groove portion, which divides the semiconductor substrate into a plurality of element regions, (c) a photoelectric conversion portion, which is formed in each of the element regions and generates and accumulates charges according to the amount of light received, (d) a charge holding portion, which is formed in each of the element regions and holds the charges generated in the photoelectric conversion portion, and (e) a transfer transistor, which transfers the charges accumulated in the photoelectric conversion portion to the charge holding portion, wherein (f) the charge holding portion is formed to reach a predetermined depth in the element region from a first surface of the element region, the first surface being a surface opposite to a light incident surface of the element region, and (g) the transfer transistor has a gate electrode, the gate electrode continuously covering at least a portion of the first surface of the element region avoiding the first region and at least a portion of a second surface, the first region being a region where the charge holding portion is formed, and the second surface being a surface on the groove portion side of the element region.

[0012] As the gist of the present disclosure, an electronic device of the present disclosure includes a light detecting device, the light detecting device including (a) a semiconductor substrate, (b) a groove portion, which divides the semiconductor substrate into a plurality of element regions, (c) a photoelectric conversion portion, which is formed in each of the element regions and generates and accumulates charge according to the amount of light received, (d) a charge holding portion, which is formed in each of the element regions and holds the charge generated in the photoelectric conversion portion, and (e) a transfer transistor, which transfers the charge accumulated in the photoelectric conversion portion to the charge holding portion, (f) the charge holding portion is formed to reach a predetermined depth in the element region from a first surface of the element region, the first surface being a surface opposite to a light incident surface of the element region, and (g) the transfer transistor has a gate electrode, the gate electrode continuously covering at least a portion of the first surface of the element region avoiding the first region and at least a portion of a second surface, the first region being a region where the charge holding portion is formed, and the second surface being a surface on the groove portion side of the element region. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a diagram showing the overall configuration of a solid-state imaging device according to the first embodiment.

[0014] Figure 2 A diagram showing a circuit configuration of a pixel.

[0015] Figure 3 It is shown along Figure 1 A diagram showing a cross-sectional structure of a solid-state imaging device taken along line AA in FIG.

[0016] Figure 4 It is shown along Figure 3A diagram showing a cross-sectional structure of a solid-state imaging device taken along line BB in FIG.

[0017] Figure 5 is a diagram showing a connection state between an FD and a pixel transistor.

[0018] Figure 6 It is shown along Figure 3 A diagram showing the planar structure of the gate electrode taken along line CC in FIG.

[0019] Figure 7 It is a perspective view showing the configuration of a device region and a gate electrode.

[0020] Figure 8 is a diagram showing the operation of the solid-state imaging device.

[0021] Fig. 9 It is shown along Figure 3 A diagram showing a plane structure of the well electrode cut along line DD in FIG.

[0022] Fig. 10A It is a diagram showing a method of manufacturing a gate electrode.

[0023] Fig. 10B It is a diagram showing a method of manufacturing a gate electrode.

[0024] Fig. 10C It is a diagram showing a method of manufacturing a gate electrode.

[0025] Fig. 10D It is a diagram showing a method of manufacturing a gate electrode.

[0026] Fig. 10E It is a diagram showing a method of manufacturing a gate electrode.

[0027] Fig.10F It is a diagram showing a method of manufacturing a gate electrode.

[0028] Fig.11 1 is a diagram showing a planar structure of a gate electrode according to a modification example.

[0029] Fig.12 It is shown along Fig.11 A diagram showing a cross section of the gate electrode taken along line EE in FIG.

[0030] Fig.13 1 is a diagram showing a planar structure of a gate electrode according to a modification example.

[0031] Fig.14 1 is a diagram showing a planar structure of a gate electrode according to a modification example.

[0032] Fig.15 1 is a diagram showing a planar structure of a gate electrode according to a modification example.

[0033] Fig.16 1 is a diagram showing a planar structure of a gate electrode according to a modification example.

[0034] Fig.17 1 is a diagram showing a planar structure of a gate electrode according to a modification example.

[0035] Fig.18 A diagram showing a planar structure of a gate electrode according to a modification example.

[0036] Fig.19 1 is a diagram showing a planar structure of a gate electrode according to a modification example.

[0037] Fig. 20 1 is a diagram showing a planar structure of a gate electrode according to a modification example.

[0038] Fig.21 1 is a diagram showing a planar structure of a gate electrode according to a modification example.

[0039] Fig. 22 1 is a diagram showing a planar structure of a gate electrode according to a modification example.

[0040] Fig.23 : is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a modification.

[0041] Fig.24 : is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a modification.

[0042] Fig.25 1 is a diagram showing a planar structure of a gate electrode according to a modification example.

[0043] Fig.26 1 is a diagram showing a planar structure of a gate electrode according to a modification example.

[0044] Fig. 27 1 is a diagram showing a planar structure of a gate electrode according to a modification example.

[0045] Fig.28 1 is a diagram showing a planar structure of a gate electrode according to a modification example.

[0046] Fig.29 1 is a diagram showing a planar structure of a gate electrode according to a modification example.

[0047] Fig.30 : is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a modification.

[0048] Fig.31 : is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a modification.

[0049] Fig.32: is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a modification.

[0050] Fig.33 : is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a modification.

[0051] Fig.34 is a diagram showing the overall configuration of an electronic device according to a second embodiment. DETAILED DESCRIPTION

[0052] In the following, reference will be made to Figures 1 to 34 Examples of light detection devices and electronic devices according to embodiments of the present disclosure are described. Embodiments of the present disclosure will be described in the following order. Note that the present disclosure is not limited to the following examples. In addition, the effects described herein are illustrative and not restrictive, and other effects may exist.

[0053] 1. First embodiment: solid-state imaging device

[0054] 1-1 Overall Structure of Solid-State Imaging Device

[0055] 1-2 Pixel circuit structure

[0056] 1-3 Composition of the main parts

[0057] 1-4 Method for manufacturing gate electrode

[0058] 1-5 Variations

[0059] 2. Second Embodiment: Application Example of Electronic Equipment

[0060] <1. First Implementation Method>

[0061] [1-1 Overall Configuration of Solid-State Imaging Device]

[0062] A solid-state imaging device 1 (“light detecting device” in a broad sense) according to a first embodiment of the present disclosure will be described. Figure 1 is a diagram showing the overall configuration of a solid-state imaging device 1 according to the first embodiment.

[0063] Figure 1 The solid-state imaging device 1 in the embodiment is a back-illuminated complementary metal oxide semiconductor (CMOS) image sensor. Fig.34 As shown, the solid-state imaging device 1 (1002) captures image light (incident light) from a subject via a lens group 1001, converts the amount of incident light that forms an image on an imaging surface into an electrical signal in units of pixels, and outputs it as a pixel signal.

[0064] like Figure 1As shown, the solid-state imaging device 1 includes a pixel region 2 , a vertical drive circuit 3 , a column signal processing circuit 4 , a horizontal drive circuit 5 , an output circuit 6 , and a control circuit 7 .

[0065] The pixel region 2 has a plurality of pixels 8 arranged in a two-dimensional array. The pixels 8 have Figure 2 As the plurality of pixel transistors, for example, a transfer transistor 13, a reset transistor 14, an amplifier transistor 15, and a selection transistor 16 (see Figure 2 ).

[0066] For example, the vertical drive circuit 3 is configured using a shift register. The vertical drive circuit 3 sequentially outputs selection pulses to the pixel drive lines 9. (Refer to Figure 2 ), each pixel 8 in the pixel area 2 is sequentially selected in units of rows, and the pixel signal of the selected pixel 8 is output to the column signal processing circuit 4 through the vertical signal line 10. The pixel signal is a signal obtained from the charge generated in the photoelectric conversion unit 12.

[0067] For example, the column signal processing circuit 4 is configured for each column of the pixels 8, and performs signal processing for each pixel column on the pixel signals output from the pixels 8 of one row. As the signal processing, for example, correlated double sampling (CDS) and analog-to-digital (AD) conversion for removing fixed pattern noise inherent to the pixels can be used.

[0068] For example, the horizontal driving circuit 5 is configured using a shift register and sequentially outputs horizontal scanning pulses to the column signal processing circuits 4 , sequentially selects each column signal processing circuit 4 , and causes the selected column signal processing circuit 4 to output the pixel signal after signal processing to the horizontal signal line 11 .

[0069] The output circuit 6 performs signal processing on pixel signals sequentially output from the respective column signal processing circuits 4 through the horizontal signal line 11 and outputs the pixel signals. As the signal processing, for example, various types of digital signal processing such as buffering, black level adjustment, and column variation correction can be used.

[0070] The control circuit 7 generates a clock signal and a control signal used as an operation reference of the vertical drive circuit 3, the column signal processing circuit 4, the horizontal drive circuit 5, etc. based on the vertical synchronization signal, the horizontal synchronization signal, and the main clock signal (not shown). In addition, the control circuit 7 outputs the generated clock signal and control signal to the vertical drive circuit 3, the column signal processing circuit 4, the horizontal drive circuit 5, etc.

[0071] [1-2 pixel circuit configuration]

[0072] Next, the circuit configuration of the pixel 8 will be described. Figure 2 It is a diagram showing the circuit configuration of the pixel 8.

[0073] like Figure 2 As shown, the pixel 8 has a photoelectric conversion unit 12, four pixel transistors (a transfer transistor 13, a reset transistor 14, an amplifier transistor 15, and a selection transistor 16) and a floating diffusion unit (hereinafter also referred to as "FD 17"). As the transfer transistor 13, the reset transistor 14, the amplifier transistor 15, and the selection transistor 16, for example, an n-channel MOS transistor can be used. In addition, FD 17 is a charge holding unit that holds the charge (for example, electrons) generated in the photoelectric conversion unit 12. For example, an n-type semiconductor region formed by high-concentration ion implantation of n-type impurities can be used. In addition, as the pixel drive line 9, for example, each pixel 8 in the same row is provided with a transfer line 18, a reset line 19, and a selection line 20 shared by each pixel 8 in the same row. One end of the transmission line 18, one end of the reset line 19, and one end of the selection line 20 are all connected to the vertical drive circuit 3.

[0074] The photoelectric converter 12 has an anode electrode electrically connected to a supply source of a predetermined potential (eg, ground), and has a cathode electrode connected to a gate electrode of the amplifier transistor 15 via the transfer transistor 13. The photoelectric converter 12 generates charge according to the amount of light received.

[0075] The transfer transistor 13 is connected between the cathode electrode of the photoelectric conversion unit 12 and the FD 17. A high level (eg, Vdd) is regarded as a transfer pulse that is activated (hereinafter also referred to as "active high"). The transfer pulse is applied to the gate electrode of the transfer transistor 13 via the transfer line 18. , the transfer transistor 13 is turned on, and the charge accumulated in the photoelectric conversion portion 12 is transferred to the FD 17 .

[0076] The drain electrode of the reset transistor 14 is connected to the pixel power supply Vdd, and the source electrode is connected to the FD 17. Before the charge is transferred from the photoelectric conversion section 12 to the FD 17 through the transfer transistor 13, a high active reset pulse is applied to the gate electrode of the reset transistor 14 via the reset line 19. When a reset pulse is applied to the gate electrode , the reset transistor 14 is turned on, drains the charge accumulated in the FD 17 to the pixel power supply Vdd, and resets the FD 17.

[0077] The gate electrode of the amplifier transistor 15 is connected to the FD 17, and the drain electrode is connected to the pixel power supply Vdd. Furthermore, after resetting, the amplifier transistor 15 outputs a signal corresponding to the potential of the FD 17 after charge transfer by the transfer transistor 13 as a pixel signal.

[0078] The drain electrode of the selection transistor 16 is connected to the source electrode of the amplification transistor 15, and the source electrode is connected to the vertical signal line 10. The selection pulse active high The select pulse is applied to the gate electrode of the select transistor 16 via the select line 20. , the selection transistor 16 is turned on, and the pixel signal output from the amplification transistor 15 is output to the vertical signal line 10.

[0079] [1-3 Main components]

[0080] Next, a specific structure of the solid-state imaging device 1 will be described. Figure 3 It is shown along Figure 1 A diagram showing a cross-sectional configuration of the solid-state imaging device 1 taken along line AA in FIG.

[0081] like Figure 3 As shown, the solid-state imaging device 1 has a configuration in which a first substrate 100, a second substrate 200, and a third substrate 300 are stacked in order from the light incident surface side of the solid-state imaging device.

[0082] The first substrate 100 has a photoelectric conversion unit 12, a transfer transistor 13, and an FD 17. In addition, the second substrate 200 has a pixel transistor 21 that reads out the charge held in the FD 17. For example, examples of the pixel transistor 21 that reads out the charge include a reset transistor 14, an amplification transistor 15, and a selection transistor 16 (refer to Figure 2 ). In addition, the third substrate 300 has a logic circuit 22 that processes a pixel signal obtained from the charge read out from the second substrate 200. For example, an example of the logic circuit 22 includes a vertical drive circuit 3, a column signal processing circuit 4, a horizontal drive circuit 5, an output circuit 6, and a control circuit 7 (refer to Figure 1 ). In addition, the color filter 23 and the microlens 24 are sequentially stacked on the light incident surface (hereinafter also referred to as “back surface S1 ”) side of the first substrate 100 . Figure 3 The case where one color filter 23 and one microlens 24 are arranged for four photoelectric conversion sections 12 arranged in a 2×2 array is shown.

[0083] In addition, the first substrate 100 includes a semiconductor substrate 25 and a wiring layer 28. In addition, the second substrate 200 includes a semiconductor layer 200S and a wiring layer 200T. In addition, the third substrate 300 includes a semiconductor layer 300S and a wiring layer 300T. The semiconductor substrate 25, the wiring layer 28, the semiconductor layer 200S, the wiring layer 200T, the wiring layer 300T, and the semiconductor layer 300S are arranged in order. For example, the first substrate 100 and the second substrate 200 (that is, the FD 17 and the pixel transistor 21) are electrically connected to each other via electrodes (contacts 31) extending in the thickness direction of the first substrate 100. In addition, for example, the second substrate 200 and the third substrate 300 are electrically connected to each other via electrode pads 201 exposed in front of the wiring layer 200T and electrode pads 301 exposed in front of the wiring layer 300T. As a material of the electrode pad 201, for example, copper (Cu) or aluminum (Al) can be used.

[0084] Next, the specific structure of the first substrate 100 will be described.

[0085] like Figure 3 As shown, the first substrate 100 has a structure in which a semiconductor substrate 25, an insulating film 26 and a planarization film 27 are stacked in order from the second substrate 200 side. In addition, a wiring layer 28 is arranged on the surface of the semiconductor substrate 25 on the second substrate 200 side (hereinafter also referred to as "front surface S2").

[0086] For example, the semiconductor substrate 25 is formed using a silicon (Si) substrate. On the semiconductor substrate 25, the photoelectric conversion unit 12 is formed in each region of each pixel 8. That is, on the semiconductor substrate 25, a plurality of photoelectric conversion units 12 are arranged in a two-dimensional array. The photoelectric conversion unit 12 has a well region 12a of a first conductivity type (e.g., p-type) and a second conductivity type region 12b of a second conductivity type (conductivity type opposite to the first conductivity type; for example, n-type) forming a pn junction with the well region 12a. The well region 12a is continuously formed on the entire side wall surface S4 (the "second surface" in a broad sense) of the groove portion 29, the entire light incident surface (hereinafter also referred to as the "back surface S3") of the element region 30, and the entire front surface S2 of the element region 30. Therefore, the well region 12a is exposed on the entire back surface S3 side of the element region 30, the entire side wall surface S4 side of the element region 30, and the entire front surface S2 side of the element region 30 (the "first surface" in a broad sense; the surface opposite to the light incident surface). In addition, the thickness of the portion of the well region 12a located on the front S2 side of the element region 30 is greater than the thickness of the portion of the well region 12a located on the back S3 side. In addition, the second conductive type region 12b is formed in the region on the center side within the element region 30 so that it contacts the well region 12a. The photoelectric conversion unit 12 forms a photodiode through the pn junction between the well region 12a and the second conductive type region 12b, and generates charges (e.g., electrons) according to the amount of light received. In addition, the photoelectric conversion unit 12 accumulates the charges generated by the photoelectric conversion in the electrostatic capacitance generated at the pn junction.

[0087] In addition, in the semiconductor substrate 25, the groove portion 29 is formed in all regions between the adjacent photoelectric conversion portions 12. That is, the groove portion 29 is formed in a lattice shape surrounding each photoelectric conversion portion 12. The groove portion 29 penetrates the semiconductor substrate 25 from the back surface S3 side to the front surface S2 side. Here, as shown in FIG. Figure 3 and Figure 4 As shown, it can be said that the groove portion 29 divides the semiconductor substrate 25 into a plurality of regions (hereinafter also referred to as “element regions 30 ”). Furthermore, it can be said that the photoelectric conversion portion 12 is formed in each element region 30 . Figure 4 It is shown along Figure 3 1 is a diagram showing a cross-sectional structure of the solid-state imaging device 1 taken along line BB in FIG. Each element region 30 has a cubic shape having four surfaces (side wall surfaces S4 ) on the groove portion 29 side.

[0088] In addition, if Figure 3As shown, FD 17 is formed in a region on the front S2 side (the side opposite to the light incident surface) of the element region 30 within the element region 30. When viewed in the thickness direction of the semiconductor substrate 25, FD 17 is formed in the central portion of the element region 30. In addition, FD 17 is formed to reach a predetermined depth within the element region 30 from the front S2 of the element region 30. Therefore, FD 17 is exposed on the front S2 of the semiconductor substrate 25. In addition, the length to the depth position (predetermined depth position) where the front end portion of FD 17 is located is shorter than the thickness of the portion of the well region 12a located on the front S2 side of the element region 30. Therefore, FD 17 is surrounded by the well region 12a and is separated from the second conductive type region 12b. FD 17 is formed using an n-type semiconductor region, and holds the charge transferred from the photoelectric conversion portion 12 to FD 17 through the gate electrode 33. As shown Figure 5 As shown, the FD 17 extends in the thickness direction of the first substrate 100, is electrically connected to the wiring in the wiring layer 200T of the second substrate 200 via the contact member 31 ("electrode" in a broad sense) extending from the first substrate 100 to the second substrate 200, and is electrically connected to the pixel transistor 21 (for example, the amplifying transistor 15 (see Figure 2 ) of the gate electrode). Figure 3 The FDs 17 are electrically connected to the corresponding contacts 31 disposed facing the front surface S2 of the device region 30. The contacts 31 are electrically connected to the regions on the front surface S2 of the device region 30 where the FDs 17 are formed (regions where the FDs 17 are exposed; hereinafter also referred to as "first regions 47").

[0089] In addition, if Figure 3 , Figure 6 and Figure 7 As shown, at the end portion on the front surface S2 side of the element region 30 , the gate electrode 33 is formed so as to surround the end portion via the gate insulating film 32 . Figure 6 It is shown along Figure 3 FIG. 1 is a diagram of a plane structure of a gate electrode cut by line CC in FIG. Figure 7 : is a perspective view showing the configuration of the element region 30 and the gate electrode 33. The gate electrode 33 has a flat surface electrode 34 covering the front face S2 of the element region 30 and a flat side electrode 35 covering each of the four side wall faces S4 (faces on the groove portion 29 side) of the element region 30. By forming the surface electrode 34, the area of ​​the gate electrode 33 on the second substrate 200 side can be increased, the contact 39 for the gate electrode 33 can be prevented from being misaligned with the gate electrode 33, and a double contact can also be formed as the contact 39. The surface electrode 34 is configured to avoid the region (first region 47) where the FD 17 is exposed on the front face S2 of the element region 30, and has an opening (hereinafter also referred to as "first opening 36") that exposes the first region 47. Note that although Figure 6 and Figure 7 An example in which a rectangular opening is used as an example of the first opening 36 is shown, but this is not the only example. Openings having various shapes, such as polygonal or circular shapes, may be used. The electrical connection between the contact 31 and the FD 17 is established through the first opening 36. Here, it can be said that the gate electrode 33 continuously covers at least a portion of the front face S2 of the element region 30 (the "first face" in a broad sense) that avoids the region (first region 47) where the FD 17 is formed and at least a portion of the surface on the groove portion 29 side of the element region 30 (the "second face" in a broad sense; the side wall surface S4). Figure 3 The gate electrode 33 is shown to continuously cover all the areas of the front surface S2 of the element region 30 where the FD 17 is not formed and the four side wall surfaces S4 of the element region 30 at the end on the front surface S2 side of the element region 30. In addition, the inner peripheral surface of the first opening 36 of the surface electrode 34 is covered by the side wall 37. Note that Figure 6 and Figure 7 Omitted Figure 3 An illustration of the side wall 37 is shown in FIG.

[0090] The side surface electrode 35 extends from the front surface S2 of the semiconductor substrate 25 to a position deeper than the end portion on the back surface S3 side of the FD 17. The gate electrode 33 is electrically connected to the wiring in the wiring layer 200T of the second substrate 200 via the contact 39 extending in the thickness direction of the first substrate 100. Figure 3 3 shows a case where each gate electrode 33 is electrically connected to a corresponding contact 39 arranged facing the front side S2 of the element region 30. When the charge is transferred from the photoelectric conversion unit 12 to the FD 17, the transfer transistor 13 applies a predetermined voltage (for example, Vdd) to the gate electrode 33 via the contact 39. When the predetermined voltage is applied to the gate electrode 33, as shown in FIG. Figure 8 As shown, the transfer transistor 13 makes the potential in the entire element region 30 (except the region of the FD 17) deeper at the depth position where the gate electrode 33 is arranged. That is, a region 38 in which the potential is modulated is formed between the photoelectric conversion section 12 and the FD 17. By forming the region 38 in which the potential is modulated, a transfer path for vertically transferring the charge accumulated in the photoelectric conversion section 12 from the photoelectric conversion section 12 to the FD 17 can be formed. As a result, the charge transfer path can be minimized, and the charge transfer efficiency can be improved.

[0091] Note that, in the case where a predetermined voltage is not applied to the gate electrode 33 , the transfer transistor 13 does not form the region 38 in which the potential is modulated, and therefore, does not form a charge transfer path.

[0092] In addition, the insulating film 26 is buried in the inner space of the groove portion 29 whose side wall surface S4 is partially covered by the side electrode 35. The gate electrodes 33 (side electrodes 35) of the adjacent element regions 30 are electrically insulated from each other by burying the insulating film 26. As the material of the insulating film 26, for example, silicon oxide (SiO2) or silicon nitride (SiN) can be used.

[0093] In addition, the well region 12a of the photoelectric conversion unit 12 is electrically connected to a supply source of a predetermined potential (for example, ground) via a well electrode 40. The well electrode 40 is formed to face the back surface S3 of the semiconductor substrate 25, and Fig. 9 As shown, the well electrode 40 is arranged along the groove portion 29 so as to close the opening on the back surface S3 side of the groove portion 29 . Fig. 9 It is shown along Figure 3 FIG. 4 is a diagram showing a planar structure of the well electrode 40 intercepted by the line DD in FIG. The well electrode 40 is electrically connected to the portion of the well region 12a exposed on the back side S3 of the element region 30. Therefore, the well electrode 40 is formed in a lattice shape covering the opening on the back side S3 of the groove portion 29, and also serves as an inter-pixel light shielding portion that prevents light from entering the opening. As a material for the well electrode 40, for example, a metal such as aluminum (Al) or tungsten (W) can be used.

[0094] The insulating film 26 is arranged on the back surface S3 side of the semiconductor substrate 25, and continuously covers the entire back surface S3 and the inside of the groove portion 29. The planarization film 27 is arranged on the light incident surface (hereinafter also referred to as "back surface S5") side of the insulating film 26, and continuously covers the back surface S5, so that the back surface S1 of the first substrate 100 becomes flat. As a material of the planarization film 27, for example, the same material as the insulating film 26, such as silicon oxide (SiO2) or silicon nitride (SiN), can be used.

[0095] The wiring layer 28 is arranged on the front surface S2 side of the semiconductor substrate 25. The wiring layer 28 has an interlayer dielectric film and wirings (not shown) stacked in multiple layers via the interlayer dielectric film.

[0096] As explained above, in the solid-state imaging device 1 according to the first embodiment, the FD 17 is formed to reach a predetermined depth inside the element region 30 from the front face S2 of the element region 30. In addition, the solid-state imaging device 1 has a configuration in which the transfer transistor 13 has the gate electrode 33 that continuously covers at least a portion of the front face S2 of the element region 30 that avoids the region (the first region 47; the first face) where the FD 17 is formed and at least a portion of the surface (the side wall surface S4; the second face) on the groove portion 29 side of the element region 30. As a result, the FD 17 is located inside the element region 30, but the gate electrode 33 is located outside the element region 30 (in the groove portion 29). Therefore, for example, compared with the case where a structure in which both the FD 17 and the gate electrode 33 are located inside the element region 30 is adopted, an additional space having a size corresponding to the gate electrode 33 can be created inside the element region 30. Therefore, for example, even when miniaturization of the pixel size progresses and the size of the element region 30 is reduced, degradation in the degree of freedom of configuration of the gate electrode 33 (transfer gate) of the transfer transistor 13 and the FD 17 can be reduced. Therefore, difficulty in configuration of the transfer gate and the FD 17 caused by reduction in pixel size can be reduced.

[0097] Furthermore, the solid-state imaging device 1 according to the first embodiment has a configuration in which the gate electrode 33 continuously covers all regions of the front face S2 of the element region 30 where the FD 17 is not formed and all four side wall faces S4 of the element region 30. Therefore, the gate electrode 33 can effectively perform modulation, and Figure 8 As shown, at the depth position where the gate electrode 33 (side electrode 35) is arranged, the potential in the entire element region 30 can be deepened. Therefore, the charge accumulated in the photoelectric conversion unit 12 can be vertically transferred from the photoelectric conversion unit 12 to the FD 17 through the region where the potential has been deepened, the charge transfer path can be minimized, and the charge transfer efficiency can be improved. In addition, since the structure of the gate electrode 33 is simple, the gate electrode 33 can be formed with a small number of steps, and the gate electrode 33 can be easily formed.

[0098] [1-4 Method for manufacturing gate electrode]

[0099] Next, a method for manufacturing the gate electrode 33 will be described.

[0100] First, if Fig. 10AAs shown in FIG. 1 , after the groove portion 29 and the element region 30 are formed in the semiconductor substrate 25, the front surface S2 side of the semiconductor substrate 25 is covered with polysilicon 55 (including the etching mask 56), and the polysilicon 55 is buried in the groove portion 29. Note that a silicon oxide film (not shown) may be formed between the element region 30 and the polysilicon 55. The etching mask 56 is a mask having a single-layer structure or a multi-layer structure that covers the front surface S2 of each element region 30. Next, as shown in FIG. Fig. 10B As shown in FIG. 1 , the front side S8 of the polysilicon 55 is etched back, and the etching mask 56 and the end of the element region 30 are exposed. Fig. 10C As shown, the gate insulating film 32 is formed to continuously cover the front surface S2 of the element region 30 and the front surface S8 of the polysilicon 55. Note that before the gate insulating film 32 is formed, the above-mentioned silicon oxide film (not shown) is removed from the exposed end portion of the element region 30 in advance.

[0101] Next, if Fig. 10D As shown in FIG. 1 , the unevenness on the front surface S9 of the gate insulating film 32 is covered with doped polysilicon 57 (the material of the gate electrode 33). Fig. 10E As shown, the doped polysilicon 57 is processed to form the gate electrode 33. Next, as shown in FIG. Fig.10F As shown, the wiring layer 28 is formed on the front surface S2 side of the semiconductor substrate 25, and the gate electrode 33 is covered with an insulating film.

[0102] The gate electrode 33 can be formed through such steps.

[0103] Note that as a manufacturing process of the solid-state imaging device 1, Fig.10F After the steps shown in FIG. 1 , the polysilicon 55 in the groove portion 29 is removed, and the insulating film 26 is formed in the groove portion 29. Thus, a layer in which the insulating film 26 is buried in the inner space of the groove portion 29 is formed. Figure 3 The structure shown.

[0104] [1-5 Modification Example]

[0105] (1) Note that although in the example shown in the first embodiment, the first opening 36 of the gate electrode 33 is a small opening, other configurations may be adopted. Fig.11 and Fig.12 As shown, the first opening 36 can be made larger. By making the first opening 36 larger, the area of ​​the FD 17 can be made larger. In addition, the size of the side wall 37 can be increased, the offset between the gate electrode 33 and the FD 17 can be increased, and the electric field generated between the gate electrode 33 and the FD 17 can be reduced. Fig.11 is shown along with Figure 3 FIG. 3 is a diagram showing a planar structure of the gate electrode 33 taken at a position corresponding to the line CC in FIG. Fig.12 It is shown along Fig.11 A diagram showing a cross-sectional structure of the gate electrode 33 taken along line EE in FIG.

[0106] (2) In addition, although the gate electrode 33 (side electrode 35) covers all four side wall surfaces S4 of the element region 30 in the example shown in the first embodiment, other structures may be adopted. Fig.13 , Fig.14 , Fig.15 and Fig.16 As shown, in other possible configurations, the gate electrode 33 (side electrode 35) covers only one, two or three of the four side wall surfaces S4 of the element region 30. Therefore, in the groove portion 29 on the side of the surface (side wall surface S4) not covered by the side electrode 35, an additional space having a size corresponding to the side electrode 35 can be generated in the groove portion 29. Therefore, the formation of the side electrode 35 (the side electrode 35 of other element regions 30) in the groove portion 29 and the embedding of the insulating film 26 can be easily performed. In addition, the area on the front face S2 of the element region 30 but not covered by the surface electrode 34 can be made larger, and the area of ​​the FD 17 can be made larger. In addition, for example, as described later, in the case of using a well contact 46 (refer to Figure 23 to Figure 26 In the case of a structure in which the well contact 46 is connected from the front surface S2 side of the element region 30 to the well region 12a, the layout freedom of the well contact 46 can be improved.

[0107] Fig.13 and Fig.14 The case where the gate electrode 33 (side electrode 35 ) covers three of the four side wall surfaces S4 of the device region 30 is shown. Fig.15 The case where the gate electrode 33 (side electrode 35 ) covers two of the four side wall surfaces S4 is shown. Fig.16 The gate electrode 33 (side electrode 35) covers one of the four side wall surfaces S4. Fig.14 The composition shown in Fig.13 , and is a modification of the configuration shown in , in which an opening is formed in the center of the surface electrode 34 and the center of the front surface S2 of the element region 30 is not covered by the surface electrode 34 .

[0108] (3) Furthermore, although in the example shown in the first embodiment, the FD 17 of each element region 30 (each pixel 8) is individually connected to the corresponding pixel transistor 21, other configurations may be adopted. Fig.17 , Fig.18 , Fig.19 , Fig. 20 , Fig.21 and Fig. 22As shown, in other possible configurations, the FDs 17 of two or more pixels 8 (element region 30 ) have an FD sharing configuration in which the FDs 17 are electrically connected to each other, and the FDs 17 having the FD sharing configuration are electrically connected to one pixel transistor 21 . Fig.17 , Fig.18 and Fig.19 The case where the pixel sharing unit 41 including four pixels 8 of 2×2 is regarded as a sharing unit of the FD 17 is shown, and the case where the FD 17 (first region 47) of each pixel 8 is formed near the center portion of the pixel sharing unit 41 is shown. That is, when viewed in the thickness direction of the semiconductor substrate 25, the FD 17 (first region 47) is formed at the corner of the pixel 8 (that is, the corner of the element region 30). In addition, in these configurations, the FD 17 is exposed at the side wall surface S4 of the corner of the element region 30. Note that, Fig.17 The illustrated configuration is a configuration in which the contact 31 of the FD 17 is arranged near the central portion of the pixel sharing unit 41 and the four contacts 31 are electrically connected to each other via wirings in the wiring layer 200T of the second substrate 200 .

[0109] also, Fig.18 The structure shown in the figure includes a pad portion 42 (a "first shared connection portion" in a broad sense) and a through electrode 43 (a "first electrode" in a broad sense) instead of Fig.17 The pad portion 42 is formed in the wiring layer 28 of the first substrate 100 (at a position facing the front face S2 of the element region 30), and is arranged in the center of the pixel sharing unit 41 when viewed in the thickness direction of the semiconductor substrate 25 (when viewed in a plan view). When viewed in a plan view, the pad portion 42 is arranged to overlap two or more FDs 17 ( Fig.18 As a material of the pad portion 42, for example, doped polysilicon doped with impurities can be used. The pad portion 42 is electrically connected to the two or more FD 17 ( Fig.18 In addition, the through electrode 43 extends in the thickness direction of the semiconductor substrate 25, one end of which is electrically connected to the pad portion 42, and the other end of which is electrically connected to the wiring in the wiring layer 200T of the second substrate 200, and is electrically connected to the pixel transistor 21 (for example, the amplifying transistor 15 (see Figure 2 ) gate electrode). Therefore, the through electrode 43 electrically connects the pad portion 42 of the first substrate 100 and the pixel transistor 21 (see Figure 3 ). Therefore, according to Fig.18The illustrated configuration can reduce the number of electrodes and can reduce parasitic capacitance, for example, compared with a method of connecting the FD 17 individually to the pixel transistor 21 through the contact 31 .

[0110] also, Fig.19 The structure shown in the figure includes a side contact 44 (broadly speaking, a "first shared connection portion") and a through electrode 45 (broadly speaking, a "first electrode") instead of Fig.17 The side contact 44 is formed in the groove portion 29 of the first substrate 100 and is arranged at the center of the pixel sharing unit 41 when viewed in the thickness direction of the semiconductor substrate 25 (when viewed in a plan view). The side contact 44 is arranged at two or more FDs 17 ( Fig.19 Between the four FD 17) Fig.19 The side contact 44 is formed in the groove portion 29 between the four FDs in the element region 30 so that the side contact 44 contacts each of the two or more FDs 17. As a material of the side contact 44, for example, doped polysilicon doped with impurities can be used. The side contact 44 is electrically connected to the two or more FDs 17 ( Fig.19 In addition, the through electrode 45 extends in the thickness direction of the semiconductor substrate 25, one end of which is electrically connected to the side contact 44, and the other end of which is electrically connected to the wiring in the wiring layer 200T of the second substrate 200, and is electrically connected to the pixel transistor 21 (for example, the amplifying transistor 15 (refer to Figure 2 ) gate electrode). Therefore, the through electrode 45 electrically connects the side contact 44 of the first substrate 100 and the pixel transistor 21 (refer to Figure 3 ). Therefore, according to Fig.19 The illustrated configuration can reduce the number of electrodes, for example, and can reduce parasitic capacitance, compared with a method in which the FD 17 is connected to the pixel transistor 21 through a separate contact 31 (electrode).

[0111] also, Fig. 20 , Fig.21 and Fig. 22 1 and 2. The case where a pixel sharing unit 41 including two pixels 8 is regarded as a sharing unit of the FD 17 and the FD 17 of each pixel 8 (element region 30) is formed near the center portion of the pixel sharing unit 41 is shown. Fig.17 The same composition as shown, Fig. 20 The configuration shown is a configuration in which the contact 31 of the FD 17 is arranged near the center portion of the pixel sharing unit 41 and the two contacts 31 are electrically connected to each other in the wiring layer 200T of the second substrate 200 (not shown). Fig.18The same composition as shown, Fig.21 and Fig. 22 The illustrated structure includes a pad portion 42 and a through electrode 43 . Fig.21 The case where the pad portion 42 is larger in size is shown. Fig. 22 The case where the size of the pad portion 42 is small is shown.

[0112] (4) In addition, although in the example shown in the first embodiment, the well region 12a is electrically connected to a supply source of a predetermined potential (for example, ground) via the well electrode 40 arranged along the groove portion 29, other configurations may be adopted. Fig.23 , Fig.24 and Fig.25 As shown, in another possible configuration, the well region 12a is electrically connected to a supply source of a predetermined potential (ground) via a contact (hereinafter also referred to as a "well contact 46") formed for each element region 30 and extending in the thickness direction of the first substrate 100. Note that Fig.23 The configuration shown in FIG. 4 is a configuration in which the well contact 46 is formed to face the back surface S3 of the element region 30 and is electrically connected to a portion of the well region 12 a exposed on the back surface S3 side. Fig.26 Shown include Fig.12 The case of the large-sized FD 17 is shown in FIG.

[0113] also, Fig.24 and Fig.25 The configuration shown is a configuration in which a well contact 46 is formed to face the front face S2 of the element region 30 and is electrically connected to a portion of the well region 12a of each element region 30 that is exposed on the front face S2 side. That is, each well region 12a is electrically connected to a separate contact (well contact 46). Fig.24 and Fig.25 In the illustrated configuration, the surface electrode 34 of the gate electrode 33 is formed on the front surface S2 of each element region 30 so as to avoid not only the region (first region 47) where the FD 17 is formed but also a portion of the region (hereinafter also referred to as "second region 48") where the well region 12a is formed. The well contact 46 is electrically connected to the second region 48. Fig.24 It is shown along Fig.25 FIG. 2 is a diagram of a cross section of the semiconductor substrate 25 taken along line FF in FIG. Note that, unlike the portion near the FD 17, the portion near the well contact 46 does not need to be modulated, as shown in FIG. Fig.26 As shown, the area A1 of the second region 48 can be made larger than the area A2 of the first region 47 (A1>A2). By making A1 larger than A2, high-precision contact forming technology is not required when forming the well contact 46, thereby reducing manufacturing costs.

[0114] In addition, for example, Fig. 27 and Fig.28 As shown, in another possible configuration, the well regions 12 a (element regions 30 ) of two or more pixels 8 are electrically connected to each other. Fig. 27 The configuration shown is a configuration including a second region 48, a pad portion 49 (a "second shared connection portion" in a broad sense), and a through electrode 50 (a "second electrode" in a broad sense) at each of the four corners of a pixel sharing unit 41 including four pixels 8 of 2×2. Note that Fig. 27 It also includes Fig.18 The pad portion 49 is formed in the wiring layer 28 of the first substrate 100 (at a position facing the front face S2 of the element region 30), and when viewed in the thickness direction of the semiconductor substrate 25 (when viewed in a plan view), the pad portion 49 is arranged in the center of the four pixel sharing units 41 of 2×2. When viewed in a plan view, the pad portion 49 is arranged to overlap two or more well regions 12a ( Fig. 27 As a material of the pad portion 49, for example, doped polysilicon doped with impurities can be used. The pad portion 49 is electrically connected to the two or more well regions 12a ( Fig. 27 The through electrode 43 extends in the thickness direction of the semiconductor substrate 25, one end of which is electrically connected to the pad portion 49, and the other end of which is electrically connected to the wiring in the wiring layer 200T of the second substrate 200, and is electrically connected to the supply source of the predetermined potential (ground) possessed by the second substrate 200 via the wiring. Therefore, the through electrode 43 electrically connects the pad portion 49 of the first substrate 100 and the supply source of the predetermined potential possessed by the second substrate 200. Therefore, according to Fig. 27 The illustrated configuration can reduce the number of electrodes and can reduce parasitic capacitance, for example, compared with a method in which the well region 12 a is connected to a supply source of a predetermined potential through a separate contact.

[0115] also, Fig.28 The configuration shown is a configuration including a side contact 51 (a "second shared connection portion" in a broad sense) and a through electrode 52 (a "second electrode" in a broad sense) at each of the four corners of the pixel sharing unit 41 including four pixels 8 of 2×2. Note that Fig.28 It also includes Fig.19The side contact 51 is formed in the groove portion 29 of the first substrate 100, and when viewed in the thickness direction of the semiconductor substrate 25 (when viewed in a plan view), the side contact 51 is arranged in the center portion of the four pixel sharing units 41 of 2×2. The side contact 51 is arranged in two or more well regions 12a ( Fig.28 Between the four well regions 12a) ( Fig.28 The side contact 51 is formed in the groove portion 29 between the four well regions 12a in the element region 30 so that the side contact 51 contacts each of the two or more well regions 12a. As a material of the side contact 51, for example, doped polysilicon doped with impurities can be used. The side contact 51 is electrically connected to the two or more well regions 12a ( Fig.28 In addition, the through electrode 52 extends in the thickness direction of the semiconductor substrate 25, one end of which is electrically connected to the side contact 51, and the other end of which is electrically connected to the wiring in the wiring layer 200T of the second substrate 200, and is electrically connected to the supply source of the predetermined potential (ground) possessed by the second substrate 200 via the wiring. Therefore, the through electrode 52 electrically connects the side contact 51 of the first substrate 100 and the supply source of the predetermined potential (ground) possessed by the second substrate 200. Therefore, according to Fig.28 The illustrated configuration can reduce the number of electrodes and can reduce parasitic capacitance, for example, compared with a method in which the well region 12 a is connected to a supply source of a predetermined potential through a separate contact (electrode).

[0116] (5) In addition, although the gate electrode 33 includes the surface electrode 34 and the side electrode 35 in the example shown in the first embodiment, other configurations may be adopted. Fig.29 As shown, in another possible configuration, in addition to the surface electrode 34 and the side electrode 35, the gate electrode 33 further has a vertical electrode portion 53 that reaches a predetermined depth in the element region 30 from the front face S2 of the element region 30. The vertical electrode portion 53 is arranged at a portion of the surface electrode 34 close to the FD 17 (close to the first region 47). Fig.29 The case where two cylindrical vertical electrode portions 53 are formed in each gate electrode 33 is shown. Note that the shape and number of the vertical electrode portions 53 are not limited thereto. The vertical electrode portion 53 can enhance modulation near the FD 17 .

[0117] (6) In addition, although the groove width of the groove portion 29 is constant in the example shown in the first embodiment, other configurations may be adopted. Fig.30 and Fig.31As shown, in other possible configurations, the groove width W1 of the portion of the side wall surface S4 of the groove portion 29 covered by the gate electrode 33 (side electrode 35) is greater than the groove width W2 of the portion of the side wall surface S4 of the groove portion 29 not covered by the gate electrode 33 (side electrode 35) (W1>W2). Therefore, in the portion covered by the side electrode 35 in the groove portion 29, an additional space corresponding to the increase in the groove width (W1-W2) can be generated. Therefore, the formation of the side electrode 35 in the groove portion 29 and the embedding of the insulating film 26 can be easily performed. Fig.30 The case where the width W3 between the side electrodes 35 is smaller than the groove width W2 is shown. Fig.31 The case where the groove width W2 and the width W3 are the same is shown.

[0118] (7) Furthermore, although the example shown in the first embodiment is that the FD 17 in the first substrate 100 and the pixel transistor 21 in the second substrate 200 are electrically connected to each other through the contact 31, other configurations may be adopted. Fig.32 As shown, in another possible configuration, the FD 17 in the first substrate 100 and the pixel transistor 21 in the second substrate 200 are electrically connected to each other via the wiring 28a in the wiring layer 28 of the first substrate 100 and the electrode (hereinafter also referred to as “through electrode 54”) reaching the second substrate 200 from the wiring layer 28. Note that Fig.32 It also includes Fig.28 . The wiring 28a in the wiring layer 28 of the first substrate 100 is electrically connected to the corresponding contact 31 extending from the front face S2 of the FD 17. In addition, the through electrode 54 extends in the thickness direction of the semiconductor substrate 25, and one end is electrically connected to the wiring 28a in the wiring layer 28, and the other end is electrically connected to the wiring 200Ta in the wiring layer 200T of the second substrate 200. In addition, the other end is electrically connected to the wiring 200Ta in the wiring layer 200T of the second substrate 200 and is electrically connected to the pixel transistor 21 (for example, the amplifier transistor 15 (refer to Figure 2 ) gate electrode). Therefore, the wiring 28a in the wiring layer 28, the through electrode 54, and the wiring 200Ta in the wiring layer 200T electrically connect the FD 17 and the pixel transistor 21 to each other. As the material of the wiring 28a and 200Ta, for example, doped polysilicon, tungsten (W), or copper (Cu) can be used.

[0119] In addition, for example, Fig.33As shown, in another possible configuration, the FD 17 and the pixel transistor 21 are electrically connected to each other via a plurality of first electrode pads 28b arranged on a surface of the first substrate 100 on the second substrate 200 side (hereinafter also referred to as the “front side S6”) and a plurality of second electrode pads 200Tb arranged on a surface of the second substrate 200 on the first substrate 100 side (hereinafter also referred to as the “back side S7”) and bonded to the corresponding first electrode pads 28b. Figure 3 The connection between the second substrate 200 and the third substrate 300 is the same as shown. Fig.33 The configuration shown is a configuration in which a Cu-Cu connection is used as a connection between the first substrate 100 and the second substrate 200. One end of the first electrode pad 28b is electrically connected to the corresponding contact 31 extending from the front face S2 of the FD 17, and the other end is exposed on the front face S6 of the wiring layer 200T. In addition, one end of the second electrode pad 200Tb is exposed on the back face S7 of the wiring layer 200T and is electrically connected to the corresponding first electrode pad 28b, and the other end is electrically connected to the corresponding wiring 200Ta in the wiring layer 200T of the second substrate 200, and is electrically connected to the pixel transistor 21 (for example, the amplifying transistor 15 (refer to Figure 2 ) gate electrode). Therefore, the first electrode pad 28b in the first substrate 100 and the second electrode pad 200Tb in the second substrate 200 electrically connect the FD 17 and the pixel transistor 21 to each other. As the material of the first electrode pad 28b and the material of the second electrode pad 200Tb, for example, copper (Cu) or aluminum (Al) can be used.

[0120] (8) In addition, the present technology can be applied not only to the solid-state imaging device 1 as the above-mentioned image sensor, but also to a light detection device generally including a distance measuring sensor (also called a ToF (time of flight) sensor) for measuring distance. The distance measuring sensor is a sensor that emits irradiation light toward an object, detects reflected light generated by reflection of the irradiation light on the surface of the object, and calculates the distance to the object based on the flight time from the emission of the irradiation light to the reception of the reflected light. As the light receiving pixel structure of the distance measuring sensor, the structure of the above-mentioned pixel 8 can be adopted.

[0121] <2. Second Implementation Method>

[0122] The technology according to the present disclosure (the present technology) can be applied to various electronic devices.

[0123] Fig.34 This is a diagram showing a schematic configuration example of an imaging device (video camera, digital camera, etc.) as an electronic device to which the present technology is applied.

[0124] like Fig.34As shown, the imaging device 1000 includes a lens group 1001, a solid-state imaging device 1002 (the solid-state imaging device 1 according to the first embodiment), a digital signal processor (DSP) circuit 1003, a frame memory 1004, a monitor 1005, and a memory 1006. The DSP circuit 1003, the frame memory 1004, the monitor 1005, and the memory 1006 are connected to each other via a bus 1007.

[0125] The lens group 1001 guides incident light (image light) from a subject to the solid-state imaging device 1002 , and forms an image on a light receiving surface (pixel region) of the solid-state imaging device 1002 .

[0126] The solid-state imaging device 1002 includes the CMOS image sensor of the first embodiment described above and converts the amount of incident light imaged on the light receiving surface by the lens group 1001 into an electrical signal in units of pixels and supplies the electrical signal to the DSP circuit 1003 as a pixel signal.

[0127] The DSP circuit 1003 performs predetermined image processing on the pixel signal supplied from the solid-state imaging device 1002. Furthermore, the DSP circuit 1003 supplies the image signal subjected to the image processing to the frame memory 1004 frame by frame to temporarily store the image signal in the frame memory 1004.

[0128] The monitor 1005 includes, for example, a panel-type display device such as a liquid crystal panel or an organic electroluminescent (EL) panel, etc. The monitor 1005 displays an image (moving image) of a subject based on frame-by-frame pixel signals temporarily stored in the frame memory 1004 .

[0129] The memory 1006 includes a DVD, a flash memory, etc. The memory 1006 reads and records the pixel signals for each frame temporarily stored in the frame memory 1004 .

[0130] Note that the electronic device to which the solid-state imaging device 1 can be applied is not limited to the imaging device 1000, and can also be applied to other electronic devices. In addition, although the solid-state imaging device 1 according to the first embodiment is used as the solid-state imaging device 1002 in the above-mentioned configuration, other configurations may be adopted. For example, in other possible configurations, other light detection devices to which the present technology is applicable, such as the solid-state imaging device 1 according to the modified example, are used.

[0131] Note that the present technology can also adopt the following configurations.

[0132] (1) A light detection device comprising:

[0133] Semiconductor substrates;

[0134] A groove portion that divides the semiconductor substrate into a plurality of device regions;

[0135] a photoelectric conversion portion formed in each of the element regions and generating and accumulating electric charge according to an amount of light reception;

[0136] a charge holding portion which is formed in each of the element regions and holds the charge generated in the photoelectric conversion portion; and

[0137] a transfer transistor that transfers the charge accumulated in the photoelectric conversion portion to the charge holding portion, wherein

[0138] The charge holding portion is formed to reach a predetermined depth within the element region from a first surface of the element region, the first surface being a surface opposite to a light incident surface of the element region, and

[0139] The transfer transistor has a gate electrode, which continuously covers at least a portion of the first surface of the element region that avoids the first region and at least a portion of the second surface, the first region is a region where the charge holding portion is formed, and the second surface is a surface on the groove portion side of the element region.

[0140] (2) The photodetection device according to (1) above, wherein the charge holding portion is formed at a center portion of the element region when viewed in a thickness direction of the semiconductor substrate.

[0141] (3) The photodetection device according to (1) above, wherein the charge holding portion is formed at a corner of the element region when viewed in the thickness direction of the semiconductor substrate.

[0142] (4) The light detection device according to (3) above, wherein

[0143] The element region is in the shape of a cube having four second faces, and

[0144] The gate electrode covers three second surfaces among the four second surfaces of the device region.

[0145] (5) The light detection device according to (3) above, wherein

[0146] The element region is in the shape of a cube having four second faces, and

[0147] The gate electrode covers two second surfaces among the four second surfaces of the device region.

[0148] (6) The light detection device according to (3) above, wherein

[0149] The element region is in the shape of a cube having four second faces, and

[0150] The gate electrode covers one second surface among the four second surfaces of the device region.

[0151] (7) The photodetection device according to any one of (1) to (6) above, wherein each of the charge holding portions and each of the gate electrodes are electrically connected to a contact arranged facing the first surface of the element region.

[0152] (8) The light detection device according to any one of (3) to (7) above, comprising:

[0153] a first shared connection portion electrically connected to the charge holding portions of two or more of the element regions; and

[0154] A first electrode electrically connected to a first shared connection, wherein

[0155] The first shared connection portion is arranged to overlap each of the two or more charge holding portions at a position facing the first surface of the element region, or to be arranged between the two or more charge holding portions.

[0156] (9) The light detection device according to any one of (1) to (8) above,

[0157] The photoelectric conversion unit has a well region of a first conductivity type and a second conductivity type region of a second conductivity type forming a pn junction with the well region.

[0158] The well region is exposed on the light incident surface side of the element region,

[0159] providing a well electrode, the well electrode being formed to face the light incident surface of the element region and being arranged along the groove portion so that the well electrode closes an opening on the light incident surface side of the groove portion, and

[0160] The well electrode is electrically connected to a portion of the well region exposed on the light incident surface side of the element region.

[0161] (10) The light detection device according to any one of (1) to (8) above,

[0162] The photoelectric conversion unit has a well region of a first conductivity type and a second conductivity type region of a second conductivity type forming a pn junction with the well region.

[0163] The well region is exposed on the light incident surface side of the element region, and

[0164] A well contact is provided, the well contact being formed to face the light incident surface of the element region and being electrically connected to a portion of the well region exposed on the light incident surface side of the element region.

[0165] (11) The light detection device according to any one of (1) to (8) above,

[0166] The photoelectric conversion unit has a well region of a first conductivity type and a second conductivity type region of a second conductivity type forming a pn junction with the well region.

[0167] The well region is exposed on the first surface side of the element region, and

[0168] The gate electrode is formed on the first surface of the element region so as to avoid not only the first region but also the second region which is a part of the region where the well region is formed.

[0169] (12) The photodetection device according to (11) above, wherein each of the well regions is electrically connected to a well contact arranged facing the first surface of the element region.

[0170] (13) The light detection device according to (11) above, comprising:

[0171] a second shared connection portion electrically connected to the well region of two or more of the element regions; and

[0172] A second electrode electrically connected to the second shared connection portion, wherein

[0173] The second shared connection portion is arranged to overlap each of the two or more well regions at a position facing the first surface of the element region, or is arranged between the two or more well regions.

[0174] (14) The photodetection device according to any one of (11) to (13) above, wherein an area of ​​the second region is larger than an area of ​​the first region.

[0175] (15) The photodetection device according to any one of (1) to (14) above, wherein the gate electrode has a vertical electrode portion extending from the first surface of the element region to a predetermined depth within the element region.

[0176] (16) The photodetection device according to any one of (1) to (15) above, wherein the gate electrode extends from the first surface of the semiconductor substrate to a position deeper than an end portion on the second surface side of the charge holding portion.

[0177] (17) A light detection device according to any one of (1) to (15) above, wherein the groove width of a portion of the side wall surface of the groove portion covered by the gate electrode is greater than the groove width of a portion of the side wall surface of the groove portion not covered by the gate electrode.

[0178] (18) The light detection device according to any one of (1) to (17) above, comprising:

[0179] a first substrate having the semiconductor substrate; and

[0180] a second substrate stacked on the first substrate, the second substrate having a pixel transistor for reading out the charge held in the charge holding portion of the semiconductor substrate, wherein

[0181] The charge holding portion and the pixel transistor are electrically connected to each other via an electrode extending in the thickness direction of the first substrate and reaching from the first substrate to the second substrate.

[0182] (19) The light detection device according to any one of (1) to (17) above, comprising:

[0183] a first substrate having the semiconductor substrate; and

[0184] a second substrate stacked on the first substrate, the second substrate having a pixel transistor for reading out the charge held in the charge holding portion of the semiconductor substrate, wherein

[0185] The first substrate has a wiring layer arranged on a surface of the semiconductor substrate on the second substrate side, and

[0186] The charge holding portion and the pixel transistor are electrically connected to each other via wiring in the wiring layer of the first substrate and an electrode extending in the thickness direction of the first substrate and reaching the second substrate from the wiring layer.

[0187] (20) The light detection device according to any one of (1) to (17) above, comprising:

[0188] a first substrate having the semiconductor substrate; and

[0189] a second substrate stacked on the first substrate, the second substrate having a pixel transistor for reading out the charge held in the charge holding portion of the semiconductor substrate, wherein

[0190] The charge holding portion and the pixel transistor are electrically connected to each other via a plurality of first electrode pads arranged on a surface of the first substrate on the second substrate side and a plurality of second electrode pads arranged on a surface of the second substrate on the first substrate side and joined to the corresponding first electrode pads.

[0191] (21) A light detection device according to any one of (1) to (20) above, wherein when a predetermined voltage is applied, the gate electrode causes the potential in the entire element region except for the region where the charge holding portion is formed to become deeper at a depth position where the gate electrode is configured.

[0192] (22) An electronic device comprising:

[0193] A light detection device, the light detection device comprising

[0194] Semiconductor substrates,

[0195] a groove portion that divides the semiconductor substrate into a plurality of element regions,

[0196] a photoelectric conversion unit which is formed in each of the element regions and generates and accumulates electric charge according to the amount of light received,

[0197] a charge holding portion which is formed in each of the element regions and holds the charge generated in the photoelectric conversion portion, and

[0198] a transfer transistor that transfers the charge accumulated in the photoelectric conversion portion to the charge holding portion, wherein

[0199] The charge holding portion is formed to reach a predetermined depth within the element region from a first surface of the element region, the first surface being a surface opposite to a light incident surface of the element region, and

[0200] The transfer transistor has a gate electrode, which continuously covers at least a portion of the first surface of the element region that avoids the first region and at least a portion of the second surface, the first region is a region where the charge holding portion is formed, and the second surface is a surface on the groove portion side of the element region.

[0201] Reference numerals list

[0202] 1: Solid-state imaging device

[0203] 2: Pixel area

[0204] 3: Vertical drive circuit

[0205] 4: Column signal processing circuit

[0206] 5: Horizontal drive circuit

[0207] 6: Output circuit

[0208] 7: Control circuit

[0209] 8: Pixel

[0210] 9: Pixel drive line

[0211] 10: Vertical signal line

[0212] 11: Horizontal signal line

[0213] 12: Photoelectric conversion unit

[0214] 12a: Well region

[0215] 12b: Second conductivity type region

[0216] 13: Transfer transistor

[0217] 14: Reset transistor

[0218] 15: Amplifier transistor

[0219] 16: Select transistor

[0220] 17: FD

[0221] 18: Transmission Line

[0222] 19: Reset line

[0223] 20: Select Line

[0224] 21: Pixel transistor

[0225] 22: Logic Circuit

[0226] 23: Color Filters

[0227] 24: Microlens

[0228] 25: Semiconductor substrate

[0229] 26: Insulation film

[0230] 27: Flattening film

[0231] 28: Wiring layer

[0232] 28a: Wiring

[0233] 28b: first electrode pad

[0234] 29: Groove

[0235] 30: Component area

[0236] 31: Contact

[0237] 32: Gate insulation film

[0238] 33: Gate electrode

[0239] 34: Surface electrode

[0240] 35: Side electrode

[0241] 36: First Opening

[0242] 37: Sidewall

[0243] 38: Area where the potential is modulated

[0244] 39: Contact

[0245] 40: Well electrode

[0246] 41: Pixel sharing unit

[0247] 42: Pad

[0248] 42a: Connecting vias

[0249] 43: Through electrode

[0250] 44: Side contact

[0251] 45: Through electrode

[0252] 46: Well contact

[0253] 47: First Area

[0254] 48: Second Area

[0255] 48a: Connecting vias

[0256] 49: Pad

[0257] 50: Through electrode

[0258] 51: Side contact

[0259] 52: Through electrode

[0260] 53: Vertical electrode part

[0261] 54: Through electrode

[0262] 55: Polysilicon

[0263] 56: Etching mask

[0264] 57: Doped polysilicon

[0265] 100: First substrate

[0266] 200: Second substrate

[0267] 200S: Semiconductor layer

[0268] 200T: Wiring layer

[0269] 200Ta: Wiring

[0270] 200Tb: Second electrode pad

[0271] 201: Electrode pad

[0272] 300: The third substrate

[0273] 300S: Semiconductor layer

[0274] 300T: Wiring layer

[0275] 301: Electrode pad

[0276] 1000: Imaging device

[0277] 1001: Lens group

[0278] 1002: Solid-state imaging device

[0279] 1003: DSP circuit

[0280] 1004: Frame memory

[0281] 1005: Monitor

[0282] 1006: Memory

[0283] 1007: Bus

Claims

1. A light detection device, comprising: Semiconductor substrates; A groove portion that divides the semiconductor substrate into a plurality of device regions; a photoelectric conversion portion formed in each of the element regions and generating and accumulating electric charge according to an amount of light reception; a charge holding portion formed in each of the element regions and holding charges generated in the photoelectric conversion portion; and a transfer transistor that transfers the charge accumulated in the photoelectric conversion portion to the charge holding portion, wherein The charge holding portion is formed to reach a predetermined depth within the element region from a first surface of the element region, the first surface being a surface opposite to a light incident surface of the element region, and The transfer transistor has a gate electrode, which continuously covers at least a portion of the first surface of the element region that avoids the first region and at least a portion of the second surface, the first region is a region where the charge holding portion is formed, and the second surface is a surface on the groove portion side of the element region. 2 . The light detecting device according to claim 1 , wherein the charge holding portion is formed at a central portion of the element region when viewed in a thickness direction of the semiconductor substrate. 3 . The light detecting device according to claim 1 , wherein the charge holding portion is formed at a corner of the element region when viewed in a thickness direction of the semiconductor substrate.

4. The light detection device according to claim 3, wherein The element region is in the shape of a cube having four second faces, and The gate electrode covers three second surfaces among the four second surfaces of the device region.

5. The light detection device according to claim 3, wherein The element region is in the shape of a cube having four second faces, and The gate electrode covers two second surfaces among the four second surfaces of the device region.

6. The light detection device according to claim 3, wherein The element region is in the shape of a cube having four second faces, and The gate electrode covers one second surface among the four second surfaces of the device region. 7 . The light detecting device according to claim 1 , wherein each of the charge holding portions and each of the gate electrodes are electrically connected to a contact arranged facing the first surface of the element region.

8. The light detection device according to claim 3, comprising: a first shared connection portion electrically connected to the charge holding portions of two or more of the element regions; and A first electrode electrically connected to a first shared connection, wherein The first shared connection portion is arranged to overlap each of the two or more charge holding portions at a position facing the first surface of the element region, or to be arranged between the two or more charge holding portions.

9. The light detection device according to claim 1, wherein The photoelectric conversion unit has a well region of a first conductivity type and a second conductivity type region of a second conductivity type forming a pn junction with the well region. The well region is exposed on the light incident surface side of the element region, providing a well electrode, the well electrode being formed to face the light incident surface of the element region and being arranged along the groove portion so that the well electrode closes an opening on the light incident surface side of the groove portion, and The well electrode is electrically connected to a portion of the well region exposed on the light incident surface side of the element region.

10. The light detection device according to claim 1, wherein The photoelectric conversion unit has a well region of a first conductivity type and a second conductivity type region of a second conductivity type forming a pn junction with the well region. The well region is exposed on the light incident surface side of the element region, and A well contact is provided, the well contact being formed to face the light incident surface of the element region and being electrically connected to a portion of the well region exposed on the light incident surface side of the element region.

11. The light detection device according to claim 1, wherein The photoelectric conversion unit has a well region of a first conductivity type and a second conductivity type region of a second conductivity type forming a pn junction with the well region. The well region is exposed on the first surface side of the element region, and On the first surface of the element region, the gate electrode is formed so as to avoid not only the first region but also a second region which is a part of the region where the well region is formed. 12 . The light detecting device according to claim 11 , wherein each of the well regions is electrically connected to a well contact arranged facing the first surface of the element region.

13. The light detection device according to claim 11, comprising: a second shared connection portion electrically connected to the well region of two or more of the element regions; and A second electrode electrically connected to the second shared connection, wherein The second shared connection portion is arranged to overlap each of the two or more well regions at a position facing the first surface of the element region, or is arranged between the two or more well regions. The light detecting device according to claim 11 , wherein an area of ​​the second region is larger than an area of ​​the first region. 15 . The photodetecting device according to claim 1 , wherein the gate electrode has a vertical electrode portion extending from the first surface of the element region to a predetermined depth within the element region. 16 . The light detecting device according to claim 1 , wherein the gate electrode reaches from the first surface of the semiconductor substrate to a position located deeper than an end portion on the second surface side of the charge holding portion. 17 . The photodetection device according to claim 1 , wherein a groove width of a portion of the side wall surface of the groove portion covered by the gate electrode is larger than a groove width of a portion of the side wall surface of the groove portion not covered by the gate electrode.

18. The light detection device according to claim 1, comprising: A first substrate having the semiconductor substrate; and a second substrate stacked on the first substrate, the second substrate having a pixel transistor for reading out the charge held in the charge holding portion of the semiconductor substrate, wherein The charge holding portion and the pixel transistor are electrically connected to each other via an electrode extending in the thickness direction of the first substrate and reaching from the first substrate to the second substrate.

19. The light detection device according to claim 1, comprising: A first substrate having the semiconductor substrate; and a second substrate stacked on the first substrate, the second substrate having a pixel transistor for reading out the charge held in the charge holding portion of the semiconductor substrate, wherein The first substrate has a wiring layer arranged on a surface of the semiconductor substrate on the second substrate side, and The charge holding portion and the pixel transistor are electrically connected to each other via wiring in the wiring layer of the first substrate and an electrode extending in the thickness direction of the first substrate and reaching the second substrate from the wiring layer.

20. The light detection device according to claim 1, comprising: A first substrate having the semiconductor substrate; and a second substrate stacked on the first substrate, the second substrate having a pixel transistor for reading out the charge held in the charge holding portion of the semiconductor substrate, wherein The charge holding portion and the pixel transistor are electrically connected to each other via a plurality of first electrode pads arranged on a surface of the first substrate on the second substrate side and a plurality of second electrode pads arranged on a surface of the second substrate on the first substrate side and joined to the corresponding first electrode pads.

21. The photodetecting device according to claim 1, wherein when a predetermined voltage is applied, the gate electrode deepens a potential in the entire element region except for a region where the charge holding portion is formed at a depth position where the gate electrode is arranged.

22. An electronic device, comprising: A light detection device, the light detection device comprising Semiconductor substrates, a groove portion that divides the semiconductor substrate into a plurality of element regions, a photoelectric conversion unit which is formed in each of the element regions and generates and accumulates electric charge according to the amount of light received, a charge holding portion which is formed in each of the element regions and holds the charge generated in the photoelectric conversion portion, and a transfer transistor that transfers the charge accumulated in the photoelectric conversion portion to the charge holding portion, wherein The charge holding portion is formed to reach a predetermined depth within the element region from a first surface of the element region, the first surface being a surface opposite to a light incident surface of the element region, and The transfer transistor has a gate electrode, which continuously covers at least a portion of the first surface of the element region that avoids the first region and at least a portion of the second surface, the first region is a region where the charge holding portion is formed, and the second surface is a surface on the groove portion side of the element region.

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