Signal channel self-diagnosis method, circuit and chip of ultrasonic radar chip

Abstract

The embodiment of the invention provides a signal path self-diagnosis method and circuit of an ultrasonic radar chip and the ultrasonic radar chip, and the method comprises the steps: transmitting a first test signal to a first test path which is used for detecting a measurement system according to the first test signal, the measuring system is an ultrasonic radar measuring system; sending a second test signal to a second test channel, wherein the second test channel is used for detecting the digital signal generation unit, the driving stage unit, the analog input circuit and the digital input circuit according to the second test signal; and sending a third test signal to a third test path, wherein the third test path is used for detecting the digital signal generation unit and the digital input circuit according to the third test signal. According to the invention, independent detection and accurate fault positioning of each module can be realized, and the function safety, the self-test capability and the reliability of the ultrasonic radar chip are improved.

Description

Technical Field

[0001] The present application relates to the field of image formation technology, and in particular to a signal path self-diagnosis method, a self-diagnosis circuit and an ultrasonic radar chip of an ultrasonic radar chip. Background Art

[0002] In modern automotive electronic systems, especially in autonomous driving and advanced driver assistance systems (ADAS), ultrasonic sensors are not only used for automatic parking, but also for blind spot detection, lane keeping assistance, collision warning and other functions. In order to ensure that these system functions have high reliability and safety on the basis of meeting relevant functional safety requirements, self-testing and diagnostic functions become particularly important, that is, the system must be able to detect potential faults or errors. However, traditional ultrasonic sensor testing methods often cannot meet these high requirements, especially in complex automotive electronic environments, where signal interference and environmental changes may lead to inaccurate test results.

[0003] Traditional ultrasonic sensor testing methods rely on feedback from the overall circuit and can only diagnose whether the path export results of the loop meet the requirements. However, when the results are abnormal, they can only locate the loop error but cannot locate which core module has an error. Targeted detection of core modules composed of single modules and their signal-related circuits has limitations and cannot accurately locate the problem. Summary of the invention

[0004] In view of this, the present application provides a signal path self-diagnosis method, a self-diagnosis circuit and an ultrasonic radar chip for an ultrasonic radar chip to solve the problem that faults cannot be accurately located in the prior art.

[0005] In a first aspect, an embodiment of the present application provides a signal path self-diagnosis method for an ultrasonic radar chip, the method comprising:

[0006] Sending a first test signal to a first test channel, wherein the first test channel is used to detect a measurement system according to the first test signal, wherein the measurement system is an ultrasonic radar measurement system;

[0007] Sending a second test signal to a second test channel, wherein the second test signal includes a first detection signal and a second detection signal, and the second test channel includes a first sub-test channel and a second sub-test channel;

[0008] The first sub-test path includes a digital signal generating unit, a driving stage unit and a driving stage monitoring unit; wherein,

[0009] The digital signal generating unit is used to output a first digital signal according to the first detection signal, the driving stage unit is used to output a first driving output signal according to the first digital signal, and the driving stage monitoring unit is used to output a first response signal according to the first driving output signal;

[0010] The second sub-test path includes an analog test unit, an analog multiplexer, an analog input circuit, a first digital multiplexer and a digital input circuit; wherein,

[0011] The analog test unit is used to output an analog test signal according to the second detection signal, the analog multiplexer is used to output a first analog input signal according to the analog test signal, the analog input circuit is used to output a first analog output signal according to the first analog input signal, the first digital multiplexer is used to output a first digital input signal according to the first analog output signal, and the digital input circuit is used to output a second response signal according to the first digital input signal;

[0012] Sending a third test signal to a third test channel, the third test signal comprising a third detection signal and a fourth detection signal, the third test channel comprising a third sub-test channel and a fourth sub-test channel;

[0013] The third sub-test path includes a digital signal generating unit and a signal generation monitoring unit; wherein,

[0014] The digital signal generating unit is used to output a second digital signal according to the third detection signal, and the signal generation monitoring unit is used to output a third response signal according to the second digital signal;

[0015] The fourth sub-test path includes a digital test unit, a first digital multiplexer and a digital input circuit; wherein,

[0016] The digital test unit is used to output a first digital test signal according to the fourth detection signal, the first digital multiplexer is used to output a second digital input signal according to the first digital test signal, and the digital input circuit is used to output a fourth response signal according to the second digital input signal.

[0017] The embodiment of the present application implements detection of the measurement system through the first test path, detects the digital signal generating unit, the driving level unit, the analog input circuit and the digital input circuit through the second test path, and detects the digital signal generating unit and the digital input circuit through the third test path, that is, the embodiment of the present application can implement targeted detection of the core module, so that when a fault occurs in the signal path of the ultrasonic radar chip, the faulty module can be accurately located, and the faulty module can be debugged separately, thereby improving the functional safety, self-testing capability and reliability of the system, and meeting the high requirements for ultrasonic sensors in the automotive electronics field.

[0018] In a possible implementation, the first test path includes a digital signal generating unit, a driving stage unit, a measuring system, an analog multiplexer, an analog input circuit, a first digital multiplexer and a digital input circuit; wherein,

[0019] The digital signal generating unit is used to output a third digital signal according to the first test signal, the driving stage unit is used to output a second driving output signal according to the third digital signal, the measuring system is used to output a measuring signal according to the second driving output signal, the analog multiplexer is used to output a second analog input signal according to the measuring signal, the analog input circuit is used to output a second analog output signal according to the second analog input signal, the first digital multiplexer is used to output a third digital input signal according to the second analog output signal, and the digital input circuit is used to output a fifth response signal according to the third digital input signal

[0020] In a possible implementation, the first test path includes a digital test unit, a driver unit, a measurement system, an analog multiplexer, an analog input circuit, a first digital multiplexer and a digital input circuit; wherein,

[0021] The digital test unit is used to output a second digital test signal according to the first test signal, the driving stage unit is used to output a second driving output signal according to the second digital test signal, the measurement system is used to output a measurement signal according to the second driving output signal, the analog multiplexer is used to output a second analog input signal according to the measurement signal, the analog input circuit is used to output a second analog output signal according to the second analog input signal, the first digital multiplexer is used to output a third digital input signal according to the second analog output signal, and the digital input circuit is used to output a fifth response signal according to the third digital input signal.

[0022] In a possible implementation, the measurement system includes a transformer and an ultrasonic transducer, and the measurement system is used to output a measurement signal according to the second drive output signal, including:

[0023] The transformer is used to output a voltage-changing signal according to the second driving output signal, the ultrasonic transducer is used to output an ultrasonic measurement signal to a measurement channel according to the voltage-changing signal, and receive an ultrasonic reflection signal returned from the measurement channel, and the ultrasonic transducer is also used to output a receiving signal according to the ultrasonic reflection signal;

[0024] The measuring system outputs the transformed signal and the received signal as measurement signals.

[0025] The embodiment of the present application can confirm whether there is a fault in the measurement system through the first test path, and realize independent detection of the measurement system, so that when the measurement system has a fault, the measurement system can be debugged separately.

[0026] In a possible implementation, the first sub-test channel also includes a second digital multiplexer, and the driver level monitoring unit is electrically connected to the signal generation monitoring unit through the second digital multiplexer; at this time, the driver level monitoring unit is used to output a driver monitoring signal according to the first driver output signal, the first digital multiplexer is used to output a first monitoring input signal according to the driver monitoring signal, and the signal generation monitoring unit is used to output a first response signal according to the first monitoring input signal.

[0027] In a possible implementation, the third sub-test path also includes a second digital multiplexer, and the digital signal generating unit is electrically connected to the signal generation monitoring unit through the second digital multiplexer; at this time, the digital signal generating unit is used to output a second digital signal according to the third detection signal, the second digital multiplexer is used to output a second monitoring input signal according to the second digital signal, and the signal generation monitoring unit is used to output a third response signal according to the second monitoring input digital signal.

[0028] In a possible implementation, the second sub-test path further includes a digital test unit, and the digital test unit is arranged at the input end of the analog test unit. In this case, the analog test unit is a digital-to-analog converter;

[0029] The analog test unit is used to output an analog test signal according to the second detection signal, including:

[0030] The digital test unit is used to output a third digital test signal according to the second detection signal, and the analog test unit is used to output an analog test signal according to the third digital test signal.

[0031] In a possible implementation manner, the digital test unit has the same circuit function as the digital signal generating unit.

[0032] In one possible implementation, the digital test unit shares part of the circuit structure with the digital signal generating unit, wherein the digital signal generating unit includes a first register configuration module and a first logic unit electrically connected in sequence, and the digital test unit includes a second register configuration module and a first logic unit electrically connected in sequence.

[0033] In a possible implementation manner, the digital test unit is electrically connected to a digital channel simulation unit, and the first digital test signal, the second digital test signal, or the third digital test signal is output through the digital channel simulation unit.

[0034] In a possible implementation manner, the analog test unit has the same circuit function after being electrically connected to the digital signal generating unit and the driving stage unit.

[0035] In a possible implementation, the analog test unit shares part of the circuit structure with the circuit after the digital signal generating unit and the driving stage unit are electrically connected, wherein the circuit after the digital signal generating unit and the driving stage unit are electrically connected includes a first register configuration module, a first logic unit and a second logic unit connected in sequence, and the analog test unit includes a third register configuration module, a first logic unit and a second logic unit connected in sequence.

[0036] In a possible implementation manner, the analog test unit has the same circuit function as the driving stage unit.

[0037] In a possible implementation, the analog test unit and the driving stage unit share part of the circuit structure, wherein the driving stage unit includes a second logic unit, and the analog test unit includes a second logic unit.

[0038] In a possible implementation manner, the analog test unit is electrically connected to an analog channel simulation unit, and the analog test signal is output through the analog channel simulation unit.

[0039] In a second aspect, an embodiment of the present application provides a signal path self-diagnosis circuit for an ultrasonic radar chip, wherein the circuit includes a signal path self-diagnosis method for an ultrasonic radar chip as described in any one of the first aspects.

[0040] In a third aspect, an embodiment of the present application provides an ultrasonic radar chip, comprising a signal path self-diagnosis circuit of the ultrasonic radar chip as described in the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0042] Figure 1 A schematic diagram of an application scenario provided for an embodiment of the present application;

[0043] Figure 2 A schematic diagram of the module structure of a signal path self-diagnosis circuit of an ultrasonic radar chip provided in an embodiment of the present application;

[0044] Figure 3 A schematic diagram of the module structure of a signal path self-diagnosis circuit of another ultrasonic radar chip provided in an embodiment of the present application;

[0045] Figure 4 A schematic diagram of the module structure of a signal path self-diagnosis circuit of another ultrasonic radar chip provided in an embodiment of the present application;

[0046] Figure 5 A schematic diagram of the module structure of a signal path self-diagnosis circuit of another ultrasonic radar chip provided in an embodiment of the present application;

[0047] Figure 6 A schematic diagram of the module structure of a signal path self-diagnosis circuit of another ultrasonic radar chip provided in an embodiment of the present application;

[0048] Figure 7 Schematic diagram of the module structure of another signal path self-diagnosis circuit of an ultrasonic radar chip provided in an embodiment of the present application

[0049] Figure 8 A schematic diagram of the structure of a normal operating path of a signal path self-diagnosis circuit of an ultrasonic radar chip provided in an embodiment of the present application;

[0050] Fig. 9 A schematic diagram of the structure of a first test path of a signal path self-diagnosis circuit of an ultrasonic radar chip provided in an embodiment of the present application;

[0051] Fig.10 A schematic diagram of the structure of a first test path of a signal path self-diagnosis circuit of another ultrasonic radar chip provided in an embodiment of the present application;

[0052] Fig.11 A schematic diagram of the structure of a second test path of a signal path self-diagnosis circuit of an ultrasonic radar chip provided in an embodiment of the present application;

[0053] Fig.12 A schematic diagram of the structure of a second test path of a signal path self-diagnosis circuit of another ultrasonic radar chip provided in an embodiment of the present application;

[0054] Fig.13 A schematic diagram of the structure of a second test path of a signal path self-diagnosis circuit of another ultrasonic radar chip provided in an embodiment of the present application;

[0055] Fig.14 A schematic diagram of the structure of a third test path of a signal path self-diagnosis circuit of an ultrasonic radar chip provided in an embodiment of the present application;

[0056] Fig.15 A schematic diagram of the structure of a third test path of a signal path self-diagnosis circuit of an ultrasonic radar chip provided in an embodiment of the present application;

[0057] Fig.16 A schematic diagram of the structure of an ultrasonic radar chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0058] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0059] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0060] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0061] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0062] In modern automotive electronic systems, especially in autonomous driving and ADAS, ultrasonic sensors are used not only for automatic parking but also for functions such as blind spot detection, lane keeping assist and collision warning.

[0063] See also Figure 1 , is a schematic diagram of an application scenario provided by an embodiment of the present application. Figure 11 and an obstacle 200 are shown in the figure, wherein a plurality of ultrasonic transducers 101 are provided at the rear of the vehicle 100. When the user (or the case of automatic driving) controls the vehicle 100 to reverse (or any scenario of parallel parking or front obstacle recognition), the ultrasonic transducer 101 can emit ultrasonic waves and receive echo signals (the ultrasonic transducer can be two independent devices including an ultrasonic transmitting transducer and an ultrasonic receiving transducer, or can be a device having both the functions of transmitting and receiving ultrasonic waves). Then, the distance between the ultrasonic transducer 101 (i.e., the vehicle 100) and the obstacle 200 can be calculated, and corresponding prompt information can be provided to the user (for example, outputting a warning sound through a buzzer or displaying the obstacle distance through a display screen, etc.), so as to assist the user in driving safely.

[0064] It should be pointed out that Figure 1 This is only one possible application scenario listed in the embodiments of the present application, and it should not be used as a limitation on the scope of protection of the present application. For example, in addition to being used for obstacle detection in vehicles to assist in automatic parking, blind spot detection, and collision warning, ultrasonic ranging may also be used in application scenarios such as lane keeping when the vehicle is driving. In other application scenarios, obstacles may also be referred to as "detected objects"; in addition to being set at the rear of the vehicle, ultrasonic transducers may also be set at the side or front of the vehicle to detect obstacles on the side or front of the vehicle; in addition to setting 4 ultrasonic transducers, more or fewer ultrasonic transducers may be set, etc., and the embodiments of the present application do not impose specific limitations on this.

[0065] In order to ensure that these system functions meet the relevant functional safety requirements and have high reliability and safety, self-testing and diagnostic functions become particularly important, that is, the system must be able to detect potential faults or errors. Traditional ultrasonic sensor testing methods often cannot meet these high requirements, especially in complex automotive electronic environments, where signal interference and environmental changes may lead to inaccurate test results.

[0066] Existing ultrasonic sensor tests rely on feedback from the overall circuit and can only diagnose whether the path export results of the loop meet the requirements. However, when the results are abnormal, they can only locate the loop error but cannot locate which core module has an error. There are limitations to the targeted detection of core modules composed of single modules and their signal-related circuits, and it is impossible to accurately locate the problem and debug the modules individually.

[0067] In view of the above problems, the embodiments of the present application provide a signal path self-diagnosis method, a self-diagnosis circuit and an ultrasonic radar chip of an ultrasonic radar chip. The embodiments of the present application can realize targeted detection of core modules by setting a first test path, a second test path and a third test path, and can accurately locate the faulty module when a fault occurs in the signal path of the ultrasonic radar chip, and realize separate debugging of the faulty module, thereby improving the functional safety, self-testing capability and reliability of the system, and meeting the high requirements of the automotive electronics field for ultrasonic sensors.

[0068] A detailed description is given below with reference to the accompanying drawings.

[0069] See also Figure 2 , is a schematic diagram of the module structure of a signal path self-diagnosis circuit of an ultrasonic radar chip provided in an embodiment of the present application. Figure 2 As shown, the self-diagnosis circuit includes a first test path 100, a second test path 200 and a third test path 300, wherein the first test path 100 is used to receive a first test signal S0Ta, and detect a measurement system 120 according to the first test signal S0Ta, and the measurement system 120 is an ultrasonic radar measurement system; the second test path 200 includes a first sub-test path 210 and a second sub-test path 220, the second test signal S0Tb includes a first detection signal S0Tb1 and a second detection signal S0Tb2, the first sub-test path 210 is used to receive the first detection signal S0Tb1, and detect a digital signal generating unit and a driver stage unit (Driver Stage, DR) according to the first detection signal S0Tb1, the second sub-test path 220 is used to receive the second detection signal S0Tb2, and detect an analog input circuit (Anal ogI nput Ci rcuit, AS) and a digital input circuit (Digita l I nput Ci rcu it, DS) according to the second detection signal S0Tb1. I) for detection; the third test path 300 includes a third sub-test path 310 and a fourth sub-test path 320, the third test signal S0Tb includes a third detection signal S0Tc1 and a fourth detection signal S0Tc2, the third sub-test path 310 is used to receive the third detection signal S0Tc1, and detect the digital signal generating unit (Digita l Signal Generator, DSO) according to the third detection signal S0Tc1, the fourth sub-test path 320 is used to receive the fourth detection signal S0Tc2, and detect the digital input circuit DSI according to the fourth detection signal S0Tc1.

[0070] The embodiment of the present application can detect the measurement system through the first test path, detect DSO, DR, AS and DSI through the second test path, and detect DSO and DSI through the third test path, so as to accurately locate the fault when the signal path of the ultrasonic chip fails.

[0071] The first test path, the second test path and the third test path are further introduced below with reference to the accompanying drawings.

[0072] See also Figure 3 , for the embodiments of this application Figure 2 A schematic diagram of the module structure of another signal path self-diagnosis circuit of an ultrasonic radar chip is provided based on FIG. Figure 3 As shown, the self-diagnosis circuit includes a control unit (Control Unit, CTR) 110, a first output end of the CTR 110 is electrically connected to an input end of a DSO 111, a first output end of the DSO 111 is electrically connected to an input end of a DR 112, a first output end of the DR 112 is electrically connected to an input end of a measurement system 120, an output end of the measurement system 120 is electrically connected to a first input end of an AMX 114, an output end of the AMX 114 is electrically connected to an input end of an AS 115, an output end of the AS 115 is electrically connected to a first input end of a first DMX (Digital Multi exer, DMX) 116, an output end of the first DMX 116 is electrically connected to an input end of a DSI 117, an output end of the DSI 117 is electrically connected to a second input end of the CTR 110, a second output end of the CTR 110 is electrically connected to an input end of an analog test unit 221, an output end of the analog test unit 221 is electrically connected to a second input end of the AMX 114, and the CTR A third output terminal of the CTR 110 is electrically connected to an input terminal of the digital test unit 113, an output terminal of the digital test unit 113 is electrically connected to a second input terminal of the first DMX 116, a second output terminal of the DR 112 is electrically connected to an input terminal of the DR monitoring unit 212, an output terminal of the DR monitoring unit 212 is electrically connected to a first input terminal of the CTR 110, a second output terminal of the DSO 111 is electrically connected to an input terminal of the signal monitoring unit 214, and an output terminal of the signal monitoring unit 214 is electrically connected to a third input terminal of the CTR 110.

[0073] In a specific implementation, the control unit (CTR) 110 is responsible for controlling the operation and coordination of various parts of the system to ensure the correct generation and processing of signals. Specifically, the CTR 110 can obtain a control program or control instruction from a host or upper computer connected to it, or can control the signal path self-diagnosis circuit of the ultrasonic radar chip according to the control program or control instruction pre-stored in the CTR 110. At the same time, the CTR 110 will also receive the detection signal or detection result output by the self-diagnosis circuit, and process the detection signal, or send the detection signal or detection result to the host or upper computer.

[0074] DSO 111 is used to receive the control signal sent by CTR 110, and generate various digital signals according to the control signal. The generated digital signals are used for signal testing and drive control of the self-diagnosis circuit. Specifically, when there is no fault in the signal path of the ultrasonic radar chip, the self-diagnosis circuit is in a normal working mode. At this time, the digital signal generated by DSO 111 is used for drive control of DR112. When the signal path of the ultrasonic radar chip fails, the self-diagnosis circuit enters the test mode. At this time, the digital signal generated by DSO 111 is used for signal testing of the first sub-test path 210 and the third sub-test path 310.

[0075] DR 112 is used to amplify and shape the input signal so as to drive the subsequent circuit or device to ensure that the signal strength is sufficient. Specifically, DR 112 is controlled by CTR 110 and can output the amplified and shaped signal to different modules in different circuit working modes, such as outputting the signal to the measurement system 120 in the normal working mode of the self-diagnosis circuit, outputting the signal to the measurement system 120 in the first test path in the test mode of the self-diagnosis circuit, and outputting the signal to the DR monitoring unit 212 in the second test path.

[0076] AMX 114 is used to select and send one of the multiple analog signals to an output terminal for signal processing. Specifically, AMX 114 can send the analog signal sent by the measurement system 120 or the analog signal sent by the analog test unit 221 to AS115.

[0077] AS115 is used to receive and process input signals from sensors or other analog signal sources, and usually includes signal amplification and filtering functions. Specifically, AS115 is used to receive analog signals sent by AMX 114, process the analog signals, and convert the analog signals into digital signals for output.

[0078] The first DMX 116 is used to output the digital signal sent by the digital test unit 111 or the digital signal sent by the AS 115 to the DSI 117 under the control of the CTR 110 .

[0079] The DS I 117 is used to receive and process digital signals. Specifically, after receiving the digital signals, the DS I 117 can perform different processes on different digital signals under the control of the CTR 110 and send the processing results (detection results) to the CTR 110.

[0080] The digital test unit 113 is used to receive the control signal sent by the CTR 110, and generate various digital signals according to the control signal, and the generated digital signals are used for the signal test of the self-diagnosis circuit. Specifically, when the signal path of the ultrasonic radar chip fails, the digital test unit 113 sends different digital signals according to the received control signals, so as to be used for the signal test of the first test path, the second test path or the third test path (the signal test of the first test path and the second test path will be described in detail below).

[0081] The analog test unit 221 is used to output an analog test signal according to an input signal to perform a circuit signal test. Specifically, the analog test unit 221 can simulate the output signal of the measurement system 120 according to the input signal to perform a signal test on the AS115 and the DSI 117 in the second test path.

[0082] The DR monitoring unit 212 is used to monitor the signal output by the DR 112 and send the monitoring result to the CTR 110 .

[0083] The signal generation monitoring unit 214 is used to receive and process digital signals. Specifically, after receiving the digital signals, the signal generation monitoring unit 214 can perform different processing on different digital signals under the control of the CTR 110, and send the processing results (detection results) to the CTR 110. Of course, in actual applications, the signal generation monitoring unit 214 can also be set in the CTR 110 as a module in the CTR 110.

[0084] The measurement system 120 includes a transformer (UEB) 121 and an ultrasonic transducer (TR) 122, wherein the UEB 121 is used to increase or decrease the voltage during the signal transmission process, and the TR 122 is used to output an ultrasonic measurement signal according to the input signal and receive an ultrasonic reflection signal. Specifically, after receiving the analog signal, the UEB 121 performs a voltage boost operation on the analog signal, and sends the boosted analog signal (transformed signal) to the TR 122. Under the excitation of the boosted analog signal, the TR 122 sends an ultrasonic measurement signal to the measurement channel (Measurement Channel, CN), receives the ultrasonic reflection signal returned through the CN, and outputs a reception signal according to the ultrasonic reflection signal. When the signal path of the ultrasonic radar chip is faulty, the measurement signal output by the measurement system 120 is the reception signal. When the signal path of the ultrasonic radar chip is faulty, the measurement signal output by the measurement system 120 includes the boosted analog signal and the reception signal.

[0085] In one possible implementation, Figure 4 As shown, it can also be Figure 3 A second DMX 213 is set based on the DR monitoring unit 212. At this time, the output end of the DR monitoring unit 212 is electrically connected to the first input end of the second DMX 213, the output end of the second DMX 213 is electrically connected to the input end of the signal generation monitoring unit 214, the output end of the signal generation monitoring unit 214 is electrically connected to the third input end of the CTR 110, and the second output end of the DSO 111 is electrically connected to the second input end of the second DMX 213.

[0086] In a possible implementation, it is also possible to Figure 3 or Figure 4 Based on the above, the output end of the digital test unit 113 is adjusted to be a first output end and a second output end, wherein the first output end is electrically connected to the input end of the DR 112, and the second output end is electrically connected to the second input end of the first DMX 116, so as to provide a driving control signal to the DR 112 through the digital test unit 113 during the self-diagnosis process. Figure 4 For example, the adjusted structure is as follows Figure 5 As shown,.

[0087] Or in another possible implementation, it is also possible to Figure 3 or Figure 4The output end of the digital test unit 113 is adjusted to be a first output end, a second output end and a third output end, wherein the first output end is electrically connected to the input end of the DR 112, the second output end is electrically connected to the second input end of the first DMX 116, and the third output end is electrically connected to the input end of the analog test unit 221, that is, the input end of the analog test unit 221 is electrically connected to the third output end of the CTR 110 through the digital test unit 113, so that in the self-diagnosis process, the digital test unit 113 is also used to provide a driving control signal to the DR 112 and a test signal to the analog test unit 221, so as to Figure 4 For example, the adjusted structure is as follows Figure 6 shown.

[0088] When the first output terminal of the digital test unit 113 is electrically connected to the input terminal of the DR 112, in order to ensure the accurate flow of the circuit signal, a third DMX 118 can be set at the input terminal of the DR 112, such as Figure 7 As shown, the first input end of the third DMX 118 is electrically connected to the output end of the DSO 111 (at this time, the DSO 111 only needs one output end), the second input end of the third DMX 118 is electrically connected to the first output end of the digital test unit 113, the first output end of the third DMX 118 is electrically connected to the input end of the DR 112, and the second output end of the third DMX 118 is electrically connected to the second input end of the second DMX 213 (when there is no second DMX 213, the second output end of the third DMX 118 is electrically connected to the input end of the signal generation monitoring unit 214), so that in the self-diagnosis process, the signal output by the DSO 111 is controlled to flow to the second DMX 213 (signal generation monitoring unit 214) or DR 112 according to different test paths, and the signal output by the digital test unit 113 is controlled to flow to the DR 112. It should be noted that the third DMX 118 only plays a role in controlling the flow of signals in the self-diagnosis circuit and does not change the signal.

[0089] Of course, in practical applications, Figure 3 or Figure 4 The output end of the digital test unit 113 is adjusted to be the second output end and the third output end, wherein the second output end is electrically connected to the second input end of the first DMX 116, and the third output end is electrically connected to the input end of the analog test unit 221, that is, the input end of the analog test unit 221 is electrically connected to the third output end of the CTR 110 through the digital test unit 113, so that a test signal is also provided to the analog test unit 221 through the digital test unit 113 during the self-diagnosis process.

[0090] In the specific implementation, when the signal path of the ultrasonic radar chip is fault-free, the self-diagnosis circuit is in the normal working mode. At this time, the operation path of the self-diagnosis circuit is as follows: Figure 8 As shown by the bold lines in FIG. 1 , it includes DSO 111 , DR 112 , UEB 121 , TR 122 , AMX 114 , AS 115 , first DMX 116 and DS I 117 . The input end of DSO 111 is electrically connected to the first output end of CTR 110, and is used to receive the working signal S0 output by CTR 110, and output the digital signal S1 based on the working signal S0; the input end of DR 112 is electrically connected to the first output end of DSO 111, and is used to receive the digital signal S1, and output the analog signal S2 according to the digital signal S1; the input end of UEB 121 is electrically connected to the first output end of DR 112, and is used to receive the analog signal S2, and output the voltage-changing signal according to the analog signal S2; the first input end of TR 122 is electrically connected to the first output end of UEB 121, and is used to receive the voltage-changing signal, and output the ultrasonic measurement signal MS to CN through the second output end according to the voltage-changing signal, and receive the ultrasonic reflection signal ES returned through CN through the second input end, and output the received signal through the first output end based on ES. At this time, the received signal is the measurement signal S3 output by the measurement system 120. It should be noted that the received signal can be output to the outside of the measurement system by the first output end of TR 122. At this time, AMX The first input end of AMX 114 is electrically connected to the second output end of UEB 121 and the first output end of TR 122, and is used to receive the measurement signal S3. The measurement signal S3 can also be sent by TR 122 to UEB 121 and then output to the outside of the measurement system by the second output end of UEB 121. At this time, the first input end of AMX 114 is electrically connected to the second output end of UEB 121 to receive the measurement signal S3; after receiving the measurement signal S3, AMX 114 outputs an analog signal S4 according to the measurement signal S3; the input end of AS115 is electrically connected to the output end of AMX 114, and is used to receive the analog signal S4 and output a digital signal S5 according to the analog signal S4; the first input end of the first DMX 116 is electrically connected to the output end of AS115, and is used to receive the digital signal S5 and output a digital signal S6 according to the digital signal S5; the input end of DS I 117 is electrically connected to the output end of the first DMX 116, and is used to receive the digital signal S6 and output a response signal S7 according to the digital signal S6.

[0091] After the first input end of CTR 110 receives the response signal S7, it can determine whether the signal path of the ultrasonic radar chip is faulty according to the response signal S7. When the response signal S7 meets expectations, it is confirmed that the signal path of the ultrasonic radar chip is not faulty, and the self-diagnosis path continues to operate in the normal working mode. When the response signal S7 does not meet expectations, it is confirmed that the signal path of the ultrasonic radar chip is faulty, and the self-diagnosis path enters the test mode.

[0092] See also Fig. 9 , is a schematic diagram of the structure of a first test path of a signal path self-diagnosis circuit of an ultrasonic radar chip provided in an embodiment of the present application, wherein the first test path is as follows Fig. 9 As shown by the bold black line in FIG. 1 , when the first test channel is working, the CTR 110 outputs the first test signal S0Ta to the first test channel.

[0093] Specifically, the first test path includes a DSO 111, a DR 112, a UEB 121, a TR 122, an AMX 114, an AS 115, a first DMX 116, and a DSI 117. The input end of the DSO 111 is electrically connected to the first output end of the CTR 110, and is used to receive the first test signal S0Ta output by the CTR 110, and output a third digital signal S1Ta based on the first test signal S0Ta; the input end of the DR 112 is electrically connected to the first output end of the DSO 111, and is used to receive the third digital signal S1Ta, and output a second drive output signal S2Ta according to the third digital signal S1Ta; the input end of the UEB 121 is electrically connected to the first output end of the DR 112, and is used to receive the second drive output signal S2Ta, and output a voltage-changing signal according to the second drive output signal S2Ta; the first input end of the TR 122 is electrically connected to the UEB 1 ... first test signal S0Ta output by the CTR 110, and output a third digital signal S1Ta based on the first test signal S0Ta; the input end of the DR 112 is electrically connected to the first output end of the DSO 111, and is used to receive the third digital signal S1Ta, and output a second drive output signal S2Ta according to the third digital signal S1Ta; the input end of the UEB 121 is electrically connected to the first output end of the DR 112, and is used to receive the second drive output signal S2Ta, and output a voltage-changing signal according to the second drive output signal S2Ta; the first input end of the TR 12 The first output terminal of TR 121 is electrically connected to receive a voltage-changing signal, and outputs an ultrasonic measurement signal MS to CN through the second output terminal according to the voltage-changing signal, and receives an ultrasonic reflection signal ES returned through CN through the second input terminal, and outputs a received signal through the first output terminal based on ES. At this time, the voltage-changing signal and the received signal are the measurement signal S3Ta output by the measurement system 120; it should be noted that the received signal can be output to the outside of the measurement system by the first output terminal of TR 122. At this time, the first input terminal of AMX 114 is electrically connected to the second output terminal of UEB 121 and the first output terminal of TR 122 to receive the measurement signal S3Ta, or it can be sent to UEB 121 by TR 122 and then output to the outside of the measurement system by the second output terminal of UEB 121. At this time, the first input terminal of AMX 114 is electrically connected to the second output terminal of UEB 121 to receive the measurement signal S3Ta; AMX After receiving the measurement signal S3Ta, AS114 outputs a second analog input signal S4Ta according to the measurement signal S3Ta; an input end of AS115 is electrically connected to an output end of AMX 114, for receiving the second analog input signal S4Ta, and outputting a second analog output signal S5Ta according to the second analog input signal S4Ta; a first input end of the first DMX 116 is electrically connected to an output end of AS115, for receiving the second analog output signal S5Ta, and outputting a third digital input signal S6Ta according to the second analog output signal S5Ta; an input end of DS117 is electrically connected to an output end of the first DMX 116, for receiving the third digital input signal S6Ta, and outputting a fifth response signal S7Ta according to the third digital input signal S6Ta.

[0094] Since the fifth response signal S7Ta includes the response result to the voltage transformation signal and the response result to the received signal, when the first input end of CTR 110 receives the fifth response signal S7Ta, it can be determined whether the measurement system has a fault according to the fifth response signal S7Ta. When the response result to the voltage transformation signal in the fifth response signal S7Ta meets expectations, but the response result to the received signal does not meet expectations, it is confirmed that the measurement system has a fault, and the fault can be repaired by debugging the module of the measurement system. When the response result to the voltage transformation signal in the fifth response signal S7Ta does not meet expectations, it is confirmed that there are faulty modules in DSO 111, DR 112, AS115 and DSI 117, and the self-diagnosis path enters the second test path.

[0095] The embodiment of the present application can confirm whether there is a fault in the measurement system through the first test path, and realize independent detection of the measurement system, so that when the measurement system has a fault, the measurement system can be debugged separately.

[0096] In the specific implementation, when the structure of the signal path self-diagnosis circuit of the ultrasonic radar chip is as follows Figure 5-7 As shown, there is another first test path. Figure 7 Take this as an example to illustrate.

[0097] See also Fig.10 , which is based on the embodiments of this application Figure 7 A schematic diagram of the structure of a first test path of a signal path self-diagnosis circuit of another ultrasonic radar chip is provided, wherein the first test path is as follows Fig.10 Specifically, the first test channel includes a digital test unit 113, a third DMX 118, a DR 112, a UEB 121, a TR 122, an AMX 114, an AS 115, a first DMX 116 and a DS I 117. Among them, the input end of the digital test unit 113 is electrically connected to the third output end of the CTR 110, and is used to receive the first test signal S0Ta output by the CTR 110, and output the second digital test signal S8Ta based on the first test signal S0Ta; the second input end of the third DMX 118 is electrically connected to the first output end of the digital test unit 113, and is used to receive the second digital test signal S8Ta, and output the digital signal S9Ta based on the second digital test signal S8Ta; the input end of the DR 112 is electrically connected to the first output end of the third DMX 118, and is used to receive the digital signal S9Ta, and output the second drive output signal S2Ta according to the digital signal S9Ta; the circuit connection relationship of other UEB 121, TR 122, AMX 114, AS115, the first DMX 116 and the DSI 117 can be referred to. Fig. 9For the sake of brevity, the embodiments of the present application will not be described in detail here.

[0098] In the embodiment of the present application, the digital test unit 113 can directly output the second digital test signal to the DR 112, thereby controlling the first test path to perform fault detection of the measurement system, thereby avoiding interference with the line test when the DSO 111 has a fault.

[0099] In the embodiment of the present application, since the function of the digital test unit 113 is the same as that of the DSO 111, the digital test unit 113 can have the same circuit structure as that of the DSO 111. On this basis, in order to save costs and reduce circuit area, the digital test unit 113 can share part of the circuit structure with the DSO 111. Specifically, the digital test unit 113 can share a logic unit with the DSO 111, that is, the circuit structure of the DSO 111 includes a first register configuration module and a first logic unit that are electrically connected in sequence, and the circuit structure of the digital test unit 113 includes a second register configuration module and a first logic unit that are electrically connected in sequence, wherein the first register configuration module can also be called a working register, and the second register configuration module can also be called a test register.

[0100] See also Fig.11 , is a schematic diagram of the structure of a second test path of a signal path self-diagnosis circuit of an ultrasonic radar chip provided in an embodiment of the present application, wherein the second test path is as follows Fig.11 As shown by the bold black line in FIG. 1 , when the second test path is working, the CTR 110 outputs a second test signal S0Tb to the second test path, and the second test signal S0Tb includes a first detection signal S0Tb1 and a second detection signal S0Tb2.

[0101] Specifically, the second test path includes a first sub-test path and a second sub-test path. The first sub-test path includes a DSO 111, a DR 112 and a DR monitoring unit 212. The input end of the DSO 111 is electrically connected to the first output end of the CTR 110, and is used to receive the first detection signal S0Tb1 output by the CTR 110, and output a first digital signal S1Tb based on the first detection signal S0Tb1; the input end of the DR 112 is electrically connected to the first output end of the DSO 111, and is used to receive the first digital signal S1Tb, and output a first drive output signal S2Tb according to the first digital signal S1Tb; the input end of the DR monitoring unit 212 is electrically connected to the second output end of the DR 112, and is used to receive the first drive output signal S2Tb, and output a first response signal S12Tb according to the first drive output signal S2Tb.

[0102] After the first input end of CTR 110 receives the first response signal S12Tb, it can be determined whether the DSO 111 and DR 112 modules are faulty according to the first response signal S12Tb. When the first response signal S12Tb meets expectations, it is confirmed that the DSO 111 and DR 112 modules are not faulty. When the first response signal S12Tb does not meet expectations, it is confirmed that there are faulty modules in DSO 111 and DR 112, and the self-diagnosis path enters the third test path.

[0103] In the embodiment of the present application, a DR monitoring unit 212 is provided to monitor the first drive output signal S2Tb, and convert it into a drive monitoring signal S10Tb (digital signal), and sends it to the signal generation monitoring unit 214 for correctness judgment, so as to realize the diagnosis of DSO 111 and DR 112 and ensure the accurate positioning of the fault.

[0104] Continue reading Fig.11 The second sub-test path includes the analog test unit 221 , the AMX 114 , the AS 115 , the first DMX 116 , and the DSI 117 . The input end of the analog test unit 221 is electrically connected to the second output end of the CTR 110, and is used to receive the second detection signal S0Tb2 output by the CTR 110, and output the analog test signal S13Tb based on the second detection signal S0Tb2; the second input end of the AMX 114 is electrically connected to the output end of the analog test unit 221, and is used to receive the analog test signal S13Tb, and output the first analog input signal S4Tb according to the analog test signal S13Tb; the input end of the AS115 is electrically connected to the output end of the AMX 114, and is used to receive the first analog input signal S4Tb, and output the first analog output signal S5Tb according to the first analog input signal S4Tb; the first input end of the first DMX 116 is electrically connected to the output end of the AS115, and is used to receive the first analog output signal S5Tb, and output the first digital input signal S6Tb according to the first analog output signal S5Tb; the input end of the DS I 117 is electrically connected to the first DMX The output end of 116 is electrically connected to receive the first digital input signal S6Tb and output a second response signal S7Tb according to the first digital input signal S6Tb.

[0105] After the second input end of CTR 110 receives the second response signal S7Tb, it can be determined whether the AS115 and DSI 117 modules are faulty according to the second response signal S7Tb. When the second response signal S7Tb meets expectations, it is confirmed that the AS115 and DSI 117 modules are not faulty. When the second response signal S7Tb does not meet expectations, it is confirmed that there are faulty modules in AS115 and DSI 117, and the self-diagnosis path enters the third test path.

[0106] The embodiment of the present application can diagnose AS115 and DSI 117 by simulating the measurement signal output by the measurement system through the simulation test unit 221, thereby ensuring the accurate positioning of the fault.

[0107] In the specific implementation, when the structure of the signal path self-diagnosis circuit of the ultrasonic radar chip is as follows Figure 4-6 As shown, there is another second test path. Figure 4 Take this as an example to illustrate.

[0108] See also Fig.12 , which is based on the embodiments of this application Figure 4 A schematic diagram of the structure of a second test path of a signal path self-diagnosis circuit of another ultrasonic radar chip is provided, wherein the second test path is as follows Fig.12 As shown in the bold black line.

[0109] Specifically, the first sub-test channel includes a DSO 111 , a DR 112 , a DR monitoring unit 212 , a second DMX 213 , and a signal generation monitoring unit 214 . The input end of the DSO 111 is electrically connected to the first output end of the CTR 110, and is used to receive the first detection signal S0Tb1 output by the CTR 110, and output the first digital signal S1Tb based on the first detection signal S0Tb1; the input end of the DR 112 is electrically connected to the first output end of the DSO 111, and is used to receive the first digital signal S1Tb, and output the first drive output signal S2Tb according to the first digital signal S1 Tb; the input end of the DR monitoring unit 212 is electrically connected to the second output end of the DR 112, and is used to receive the first drive output signal S2Tb, and output the drive monitoring signal S10Tb according to the first drive output signal S2Tb; the first input end of the second DMX 213 is electrically connected to the output end of the DR monitoring unit 212, and is used to receive the drive monitoring signal S10Tb, and output the first monitoring input signal S11 Tb according to the drive monitoring signal S10Tb; the input end of the signal generation monitoring unit 214 is electrically connected to the second DMX The output end of 213 is electrically connected to receive the first monitoring input signal S11Tb and output a first response signal S12Tb according to the first monitoring input signal S11Tb.

[0110] In the specific implementation, when the structure of the signal path self-diagnosis circuit of the ultrasonic radar chip is as follows Figure 7 As shown, there is also another second test path.

[0111] See also Fig.13 , which is based on the embodiments of this application Figure 7 A schematic diagram of the structure of a second test path of a signal path self-diagnosis circuit of another ultrasonic radar chip is provided, wherein the second test path is as follows Fig.13 As shown in the bold black line.

[0112] Specifically, with Fig.12 The first subtest path in is different in that Fig.13 The first sub-test path in the embodiment further includes a third DMX 118, wherein a first input terminal of the third DMX 118 is electrically connected to an output terminal of the DSO 111, and a first output terminal of the third DMX 118 is electrically connected to an input terminal of the DR 112, so as to receive a first digital signal S1Tb output by the DSO 111, and output a digital signal S9Tb to the DR 112 according to the first digital signal S1Tb, and the DR 112 outputs a first driving output signal S2Tb according to the digital signal S9Tb.

[0113] Specifically, with Fig.12 The second subtest path in is different in that Fig.13 The second sub-test path in the circuit further includes a digital test unit 113, an input end of the digital test unit 113 is electrically connected to the third output end of the CTR 110, and is used to receive the second detection signal S0Tb2 output by the CTR 110, and output a third digital test signal S14Tb based on the second detection signal S0Tb2, and an input end of the analog test unit 221 is electrically connected to the third output end of the digital test unit 113, and is used to receive the third digital test signal S14Tb, and output an analog test signal S13Tb according to the third digital test signal S14Tb.

[0114] In the embodiment of the present application, the digital test unit can directly generate a third digital test signal, and the analog test unit can generate an analog test signal based on the third digital signal to perform fault diagnosis of AS115 and DSI 117, thereby providing multiple test circuits for fault diagnosis of AS115 and DSI117.

[0115] In the embodiment of the present application, when the input end of the analog test unit 221 is directly electrically connected to the second output end of the CTR 110, the circuit structure of the analog test unit 221 can be the same as the circuit structure after the DSO 111 and the DR 112 are electrically connected, that is, the circuit structure after the DSO 111 and the DR 112 are electrically connected can be copied to obtain the analog test unit 221. On this basis, in order to save costs and reduce circuit area, the analog test unit 221 can share part of the circuit structure with the circuit after the DSO 111 and the DR 112 are electrically connected. Specifically, the analog test unit 221 can share a logic unit with the DSO 111 and the DR 112 respectively, that is, the circuit after the DSO 111 and the DR 112 are electrically connected includes a first register configuration module, a first logic unit, and a second logic unit connected in sequence, and the analog test unit circuit includes a third register configuration module, a first logic unit, and a second logic unit connected in sequence.

[0116] When the input terminal of the analog test unit 221 is electrically connected to the third output terminal of the digital test unit 113, since the circuit structure of the digital test unit 113 is the same as that of the DSO 111, the circuit structure of the analog test unit 221 is the same as that of the DR 112. On this basis, in order to save costs and reduce circuit area, the analog test unit 221 and the DR 112 can share part of the circuit structure. Specifically, the analog test unit 221 and the DR 112 can share a logic unit, that is, the DR 112 includes a second logic unit, and the analog test unit 221 includes a second logic unit.

[0117] See also Fig.14 , is a schematic diagram of the structure of a third test path of a signal path self-diagnosis circuit of an ultrasonic radar chip provided in an embodiment of the present application, wherein the third test path is as follows Fig.14 As shown by the bold black line in FIG. 1 , when the third test path works, the CTR 110 outputs a third test signal S0Tc to the third test path, and the third test signal S0Tc includes a third detection signal S0Tc1 and a fourth detection signal S0Tc2.

[0118] Specifically, the third test path includes a third sub-test path and a fourth sub-test path. The third sub-test path includes DS0 111 and a signal generation monitoring unit 214. The input end of DS0 111 is electrically connected to the first output end of CTR 110, and is used to receive the third detection signal S0Tc1 output by CTR 110, and output the second digital signal S1 Tc based on the third detection signal S0Tc1; the input end of the signal generation monitoring unit 214 is electrically connected to the second output end of DS0111, and is used to receive the second digital signal S1Tc, and output the third response signal S12Tc based on the second digital signal S1 Tc.

[0119] In a specific implementation, when the second DMX 213 exists, the structure of the third sub-test path can also be as follows: Fig.15 Specifically, the input end of the DSO 111 is electrically connected to the first output end of the CTR 110, for receiving the third detection signal S0Tc1 output by the CTR 110, and outputting the second digital signal S1 Tc based on the third detection signal S0Tc1; the second input end of the second DMX 213 is electrically connected to the second output end of the DSO 111, for receiving the second digital signal S1Tc, and outputting the second monitoring input signal S11 Tc according to the second digital signal S1 Tc; the input end of the signal generation monitoring unit 214 is electrically connected to the output end of the second DMX 213, for receiving the second monitoring input signal S11Tc, and outputting the third response signal S12Tc according to the second monitoring input signal S11Tc.

[0120] After the first input end of CTR 110 receives the third response signal S12Tc, it can be determined whether the DSO 111 module is faulty according to the third response signal S12Tc. When the third response signal S12Tc meets expectations, it is confirmed that the DSO 111 module is not faulty. When the third response signal S12Tc does not meet expectations, it is confirmed that the DSO 111 module is faulty. At this time, the DSO 111 module can be debugged separately to repair the DSO 111 module.

[0121] It can be understood that when the DSO 111 module has no fault, since the first response signal S12Tb does not meet expectations, it can be confirmed that the DR 112 module has a fault. At this time, the DR 112 module can be debugged separately to repair the DR 112 module. When the DSO 111 module has a fault, after the DSO 111 module is repaired, a signal test can be performed through the first sub-test path. If at this time, the first response signal S12Tb meets expectations, it is confirmed that the DR 112 module has no fault. If the first response signal S12Tb does not meet expectations, it is confirmed that the DR 112 module has a fault, and the DR 112 module can be debugged separately to repair the DR112 module.

[0122] The embodiment of the present application uses the signal generation monitoring unit 214 to enable the self-diagnosis circuit to perform signal monitoring during the signal generation stage, so as to detect abnormalities in a timely manner and handle them, thereby enhancing the stability of the signal path of the ultrasonic radar chip. At the same time, the embodiment of the present application can automatically identify potential errors during operation by monitoring the digital signal generating device 211, reduce human intervention, and improve overall functional safety. The embodiment of the present application makes the test process more systematic and automated, which is convenient for subsequent quality control and verification.

[0123] Continue reading Fig.14 The fourth sub-test path includes a digital test unit 113, a first DMX 116, and a DS I 117. The input end of the digital test unit 113 is electrically connected to the third output end of the CTR 110, for receiving the fourth detection signal S0Tc2 output by the CTR 110, and outputting a first digital test signal S14Tc based on the fourth detection signal S0Tc2; the second input end of the first DMX 116 is electrically connected to the output end of the digital test unit 113, for receiving the first digital test signal S14Tc, and outputting a second digital input signal S6Tc according to the first digital test signal S14Tc; the input end of the DS I 117 is electrically connected to the output end of the second DMX 116, for receiving the second digital input signal S6Tc, and outputting a fourth response signal S7Tc according to the second third digital input signal S6Tc.

[0124] After the second input end of CTR 110 receives the fourth response signal S7Tc, it can be determined whether the DSI 117 module is faulty according to the fourth response signal S7Tc. When the fourth response signal S7Tc meets expectations, it is confirmed that the DSI 117 module is not faulty. When the fourth response signal S7Tc does not meet expectations, it is confirmed that there is a fault in the module of DSI 117. At this time, the DSI 117 module can be debugged separately to repair the DSI 117 module.

[0125] It can be understood that when the DS I 117 module has no fault, since the second response signal S7Tb does not meet expectations, it can be confirmed that the AS115 module has a fault. At this time, the AS115 module can be debugged separately to repair the AS115 module. When the DS I 117 module has a fault, after repairing the DS I 117 module, a signal test can be performed through the second sub-test path. If at this time, the second response signal S7Tb meets expectations, it is confirmed that the AS115 module has no fault. If the second response signal S7Tb does not meet expectations, it is confirmed that the AS115 module has a fault, and the AS115 module can be debugged separately to repair the AS115 module.

[0126] The digital test unit 113 of the embodiment of the present application generates a test signal under the control of CTR, and transmits the signal to DS I 117 via the second DMX 116. By controlling the digital test unit 113, digital channels such as envelope processing can be tested.

[0127] It can be understood that in the embodiment of the present application, when the response result to the voltage transformation signal in the fifth response signal S7Ta does not meet expectations, and the response result to the received signal also does not meet expectations, the faulty module in DSO 111, DR 112, AS115 and DSI 117 can be first determined through the second test path and the third test path, and the faulty module can be debugged and repaired, and then the signal detection is re-performed through the first test path to determine whether there is a fault in the measurement system. If at this time, the response result to the voltage transformation signal and the response result to the received signal in the fifth response signal S7Ta are both as expected, it is confirmed that the measurement system has no fault. If the response result to the voltage transformation signal in the fifth response signal S7Ta meets expectations, and the response result to the received signal does not meet expectations, it is confirmed that the measurement system has a fault, and the fault can be repaired by debugging the module of the measurement system.

[0128] It should be noted that, in the embodiment of the present application, the digital test unit 113 can directly generate the first digital test signal, the second digital test signal or the third digital test signal, or can be electrically connected to the digital channel simulation unit to output the first digital test signal, the second digital test signal or the third digital test signal through the digital channel simulation unit. The analog test unit 221 can directly generate an analog test signal, or can be electrically connected to the analog channel simulation unit to output the analog test signal through the analog channel simulation unit.

[0129] The embodiment of the present application can independently detect each module through the first test path, the second test path and the third test path, so that when there is a problem in the signal path of the ultrasonic radar chip, the faulty module can be accurately identified and debugged separately, thereby reducing the safety hazards caused by system failures. The embodiment of the present application saves a lot of debugging time and cost through accurate signal monitoring.

[0130] Corresponding to the above embodiment, the embodiment of the present application also provides a structural schematic diagram of an ultrasonic radar chip.

[0131] See also Fig.16 , is a schematic diagram of the structure of an ultrasonic radar chip provided in an embodiment of the present application. Fig.16 As shown, the ultrasonic radar chip 1600 includes: a signal path self-diagnosis circuit 1610 of the ultrasonic radar chip. The specific content of the signal path self-diagnosis circuit 1610 of the ultrasonic radar chip can be referred to above. Figures 2 to 15 The description of the embodiments in the foregoing description will not be repeated here for the sake of brevity.

[0132] Corresponding to the above embodiment, the embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium may store a program, wherein when the program is running, the device where the computer-readable storage medium is located may be controlled to execute some or all of the steps in the above method embodiment. In a specific implementation, the computer-readable storage medium may be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM).

[0133] Corresponding to the above-mentioned embodiment, the embodiment of the present application further provides a computer program product, which includes executable instructions. When the executable instructions are executed on a computer, the computer executes some or all of the steps in the above-mentioned method embodiment.

[0134] In the embodiments of the present application, "at least one" refers to one or more, and "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent the existence of A alone, the existence of A and B at the same time, and the existence of B alone. Among them, A and B can be singular or plural. The character " / " generally indicates that the previous and subsequent associated objects are in an "or" relationship. "At least one of the following" and similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b and c can be represented by: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0135] Those of ordinary skill in the art will appreciate that the various units and algorithm steps described in the embodiments disclosed herein can be implemented in a combination of electronic hardware, computer software, and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0136] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0137] In several embodiments provided in the present application, if any function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc., various media that can store program codes.

[0138] The above is only a specific implementation of the present application. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. The protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A signal path self-diagnosis method for an ultrasonic radar chip, characterized in that: The method comprises: Sending a first test signal to a first test channel, wherein the first test channel is used to detect a measurement system according to the first test signal, wherein the measurement system is an ultrasonic radar measurement system; Sending a second test signal to a second test channel, wherein the second test signal includes a first detection signal and a second detection signal, and the second test channel includes a first sub-test channel and a second sub-test channel; The first sub-test path includes a digital signal generating unit, a driving stage unit and a driving stage monitoring unit; wherein, The digital signal generating unit is used to output a first digital signal according to the first detection signal, the driving stage unit is used to output a first driving output signal according to the first digital signal, and the driving stage monitoring unit is used to output a first response signal according to the first driving output signal; The second sub-test path includes an analog test unit, an analog multiplexer, an analog input circuit, a first digital multiplexer and a digital input circuit; wherein, The analog test unit is used to output an analog test signal according to the second detection signal, the analog multiplexer is used to output a first analog input signal according to the analog test signal, the analog input circuit is used to output a first analog output signal according to the first analog input signal, the first digital multiplexer is used to output a first digital input signal according to the first analog output signal, and the digital input circuit is used to output a second response signal according to the first digital input signal; Sending a third test signal to a third test channel, the third test signal comprising a third detection signal and a fourth detection signal, the third test channel comprising a third sub-test channel and a fourth sub-test channel; The third sub-test path includes a digital signal generating unit and a signal generation monitoring unit; wherein, The digital signal generating unit is used to output a second digital signal according to the third detection signal, and the signal generation monitoring unit is used to output a third response signal according to the second digital signal; The fourth sub-test path includes a digital test unit, a first digital multiplexer and a digital input circuit; wherein, The digital test unit is used to output a first digital test signal according to the fourth detection signal, the first digital multiplexer is used to output a second digital input signal according to the first digital test signal, and the digital input circuit is used to output a fourth response signal according to the second digital input signal.

2. The method according to claim 1, characterized in that The first test path includes a digital signal generating unit, a driving stage unit, a measuring system, an analog multiplexer, an analog input circuit, a first digital multiplexer and a digital input circuit; wherein, The digital signal generating unit is used to output a third digital signal according to the first test signal, the driving stage unit is used to output a second driving output signal according to the third digital signal, the measuring system is used to output a measuring signal according to the second driving output signal, the analog multiplexer is used to output a second analog input signal according to the measuring signal, the analog input circuit is used to output a second analog output signal according to the second analog input signal, the first digital multiplexer is used to output a third digital input signal according to the second analog output signal, and the digital input circuit is used to output a fifth response signal according to the third digital input signal.

3. The method according to claim 1, characterized in that The first test path includes a digital test unit, a driver unit, a measurement system, an analog multiplexer, an analog input circuit, a first digital multiplexer and a digital input circuit; wherein, The digital test unit is used to output a second digital test signal according to the first test signal, the driving stage unit is used to output a second driving output signal according to the second digital test signal, the measurement system is used to output a measurement signal according to the second driving output signal, the analog multiplexer is used to output a second analog input signal according to the measurement signal, the analog input circuit is used to output a second analog output signal according to the second analog input signal, the first digital multiplexer is used to output a third digital input signal according to the second analog output signal, and the digital input circuit is used to output a fifth response signal according to the third digital input signal.

4. The method according to claim 2 or 3, characterized in that: The measuring system includes a transformer and an ultrasonic transducer, and the measuring system is used to output a measuring signal according to the second driving output signal, including: The transformer is used to output a voltage-changing signal according to the second driving output signal, the ultrasonic transducer is used to output an ultrasonic measurement signal to a measurement channel according to the voltage-changing signal, and receive an ultrasonic reflection signal returned from the measurement channel, and the ultrasonic transducer is also used to output a receiving signal according to the ultrasonic reflection signal; The measuring system outputs the transformed signal and the received signal as measurement signals.

5. The method according to claim 1, characterized in that The first sub-test channel also includes a second digital multiplexer, and the driver level monitoring unit is electrically connected to the signal generation monitoring unit through the second digital multiplexer; at this time, the driver level monitoring unit is used to output a driver monitoring signal according to the first driver output signal, the first digital multiplexer is used to output a first monitoring input signal according to the driver monitoring signal, and the signal generation monitoring unit is used to output a first response signal according to the first monitoring input signal.

6. The method according to claim 5, characterized in that The third sub-test path also includes a second digital multiplexer, and the digital signal generating unit is electrically connected to the signal generating monitoring unit through the second digital multiplexer; at this time, the digital signal generating unit is used to output a second digital signal according to the third detection signal, the second digital multiplexer is used to output a second monitoring input signal according to the second digital signal, and the signal generating monitoring unit is used to output a third response signal according to the second monitoring input digital signal.

7. The method according to claim 1, characterized in that The second sub-test path further includes a digital test unit, which is arranged at the input end of the analog test unit. In this case, the analog test unit is a digital-to-analog converter; The analog test unit is used to output an analog test signal according to the second detection signal, including: The digital test unit is used to output a third digital test signal according to the second detection signal, and the analog test unit is used to output an analog test signal according to the third digital test signal.

8. The method according to claim 3 or 7, characterized in that: The circuit function of the digital test unit is consistent with that of the digital signal generating unit.

9. The method according to claim 3 or 7, characterized in that: The digital test unit shares part of the circuit structure with the digital signal generating unit, wherein the digital signal generating unit comprises a first register configuration module and a first logic unit electrically connected in sequence, and the digital test unit comprises a second register configuration module and a first logic unit electrically connected in sequence.

10. The method according to claim 1 or 7, characterized in that: The digital test unit is electrically connected to a digital channel simulation unit, and outputs the first digital test signal, the second digital test signal or the third digital test signal through the digital channel simulation unit.

11. The method according to claim 1, characterized in that The analog test unit has the same circuit function as the digital signal generating unit and the driving stage unit after being electrically connected.

12. The method according to claim 1, characterized in that The analog test unit shares part of the circuit structure with the circuit after the digital signal generating unit and the driving stage unit are electrically connected, wherein the circuit after the digital signal generating unit and the driving stage unit are electrically connected includes a first register configuration module, a first logic unit and a second logic unit connected in sequence, and the analog test unit includes a third register configuration module, a first logic unit and a second logic unit connected in sequence.

13. The method according to claim 7, characterized in that The analog test unit has the same circuit function as the driving stage unit.

14. The method according to claim 7, characterized in that The analog test unit and the driving stage unit share part of the circuit structure, wherein the driving stage unit includes a second logic unit, and the analog test unit includes a second logic unit.

15. The method according to claim 1 or 7, characterized in that: The analog test unit is electrically connected to the analog channel simulation unit, and outputs the analog test signal through the analog channel simulation unit.

16. A signal path self-diagnosis circuit for an ultrasonic radar chip, characterized in that: The circuit includes the signal path self-diagnosis method of the ultrasonic radar chip according to any one of claims 1-15.

17. An ultrasonic radar chip, characterized in that: Comprising the signal path self-diagnosis circuit as claimed in claim 16.

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