Electronic digital system comprising serializer / deserializer module, serializer / deserializer module and control method

Abstract

The invention relates to an electronic digital system including a serializer-deserializer module, a serializer-deserializer module and a control method. An electronic digital system includes a digital core and a serializer / deserializer module. The FIFO device of the core reads and writes on a set of buses coupled to the serializer / deserializer module. A serializer deserializer module transmits data read from the FIFO architecture device on a set of buses as a corresponding serial signal transmitted by the transmitter. Serial signals and corresponding transmitters are logically grouped. The transmitter includes a PLL circuit that generates a PLL clock and a low frequency clock obtained by the PLL clock using, as a reference, a cluster transmitter reference clock common to the respective transmitter clusters, the cluster transmitter reference clock controlling a frequency of the serialization operation, according to one or more groups corresponding to the bus groups.

Description

[0001] Priority claim

[0002] This application claims priority from Italian Patent Application No. 102023000022986, filed on October 31, 2023, the contents of which are hereby incorporated by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] The present description relates to an electronic digital system including a digital core and a serializer-deserializer module.

[0004] The digital core includes at least one device with a FIFO architecture, in particular a FIFO memory, which is written with a write clock and is configured to transmit data read from at least one FIFO architecture device with a read clock on multiple buses in parallel to a serializer deserializer module.

[0005] The serializer-deserializer module is configured to transmit data over a plurality of paths as a corresponding plurality of serial signals transmitted by a corresponding plurality of transmitters, the serial signals and the corresponding transmitters being logically grouped according to one or more groups or clusters, wherein the plurality of transmitters operate with a corresponding transmitter clock signal, an independent PLL circuit locally associated with each of the transmitters determining the frequency and / or phase of the clock signal starting from a cluster common local transmitter reference.

[0006] One or more embodiments may be applied to data center network applications or to high-speed interfaces in communication networks. Background Art

[0007] High-speed interfaces of systems such as system-on-chip (SoC) rely on systems that receive / transmit serial data. Typically, this can be embodied by a serializer-deserializer (SerDes) architecture to receive, manage, and transmit high data rate electrical serial data, typically in network applications. A system-on-chip including a SerDes and a digital core can receive data from a receiver (e.g., an optical receiver) and pass such data to multiple transmitters through a FIFO (first-in, first-out architecture). SerDes can be constructed with multiple serial data paths, one path for each transmitter. For example, before the SerDes transmits the decomposed serial data on each path, parallel data can be received, for example, as optical aggregate data. A SerDes device can transmit more than one electrical data stream (all belonging to the same aggregate optical data) as output. Therefore, a system including a SerDes can be required to autonomously match the transmission frequency of the output transmitter. Doing so requires maintaining a bounded phase relationship between all data streams (i.e., paths).

[0008] Known solutions require the use of a phase interpolator with closed loop control for each data path to maintain a bounded phase relationship across all transmitters. This solution with phase interpolators has been used for lower data rate SerDes.

[0009] Solutions using phase interpolators are subject to system nonlinear errors due to the inherent nonlinear behavior of the interpolation itself.

[0010] This error, also known as integral nonlinearity, can harm the overall bit error rate performance, especially for higher data rate SerDes devices.

[0011] There is a need in the art to contribute to solving several problems that exist in the context discussed above. Summary of the invention

[0012] One or more embodiments may be directed to a system.

[0013] One or more embodiments may be directed to corresponding serializer-deserializer modules and control methods.

[0014] As mentioned above, various embodiments of the present disclosure relate to an electronic digital system, which includes a digital core and a serializer deserializer module. The digital core includes at least one FIFO architecture device (particularly a FIFO memory) which is written with a write clock on a set of buses to the serializer deserializer module and is configured to transmit parallel data read from the at least one FIFO architecture device with a read clock. The serializer deserializer module is configured to transmit the data read from the at least one FIFO architecture device as a set of corresponding serial signals transmitted by a corresponding set of transmitters on a set of buses, wherein the set of serial signals and the corresponding set of transmitters are logically grouped according to one or more groups or clusters, particularly corresponding to one or more groups of buses.

[0015] The group of transmitters includes corresponding independent PLL circuits, which use the cluster transmitter reference clock shared by the corresponding transmitter cluster as a reference to emit corresponding PLL clock signals and a group of low-frequency clock signals obtained from the PLL clock signal (especially by frequency division). The cluster transmitter reference clock controls the frequency of operation (especially serialization) of the transmitter.

[0016] The system also includes a digital frequency correction module configured to supply a data strobe encoded frequency correction signal specifying a frequency correction command to each independent PLL circuit, the frequency correction command being derived from a phase error detected between a write clock and a read clock detected by an error detection module included in the digital core, the read clock corresponding to one of the PLL low frequency clock signals.

[0017] The digital frequency correction module comprises one or more cluster digital frequency correction submodules corresponding to the corresponding clusters, which are clocked by the corresponding cluster clock signal corresponding in particular to the transmitter cluster reference clock, and are configured to receive and process the corresponding data-selection coded cluster frequency correction including the frequency correction obtained from the detected phase error, output the corresponding correction signal, and obtain the data-selection coded frequency correction signal for each of the transmitters from the corresponding correction signal in particular by demultiplexing.

[0018] Each of the transmitters is configured to assert a corresponding acknowledgement signal upon receipt of the corresponding data strobe encoded frequency correction signal specifying a frequency correction command.

[0019] Each cluster digital frequency correction submodule includes a handshake module, which receives a group of confirmation signals, especially on a bus, issued by the corresponding transmitter, and the confirmation signal is resynchronized with the cluster clock signal. The handshake module is configured to issue the output data selection encoding frequency correction signal that is validated to command the frequency correction of the corresponding transmitter after receiving a group of failure confirmation signals resynchronized with the cluster clock signal from all enabled transmitters of the cluster. The transmitter is configured to disable (de-assert) the confirmation signal after completing a certain number of cycles of frequency correction of the frequencies of all independent PLL circuits of the corresponding cluster.

[0020] In an embodiment, said transmitters of a cluster are programmable with the same number of cycles, and they are configured to assert respective acknowledgement signals from all enabled transmitters for a duration corresponding to said number of cycles.

[0021] In an embodiment, the handshake module is configured to repeatedly transmit the asserted data strobe encoded frequency correction signal to command frequency correction of transmitters of the cluster.

[0022] In an embodiment, the handshake module is configured to send the data strobe encoded frequency correction signal asserted once to command frequency correction of the corresponding transmitter, and the transmitter performs frequency correction over the programmed number of cycles.

[0023] In an embodiment, after receiving the set of valid resynchronization confirmation signals from all enabled transmitters of the cluster, confirming that frequency correction is performed on the frequencies of all independent PLL circuits of the corresponding cluster, the handshake module is configured to also implement a handshake communication protocol with the digital core module, the digital core module sends the frequency correction obtained from the detected phase error to the cluster digital frequency correction submodule, the handshake module sends a corresponding cluster frequency correction confirmation signal to the core module, and the cluster frequency correction submodule confirmation signal enables the core to send the next frequency correction.

[0024] In an embodiment, the write clock is a recovered clock signal recovered from data received upstream from the FIFO architecture device.

[0025] In an embodiment, the PLL circuit is implemented by a fractional Sigma-Delta PLL circuit, which includes a corresponding Sigma-Delta modulator, and the Sigma-Delta modulator includes a corresponding handshake module, which is configured to receive the data selection encoded frequency correction signal that specifies a frequency correction command for each of the transmitter signals, and the Sigma-Delta modulator is configured to modify its input to the PLL loop of the PLL circuit with the frequency correction.

[0026] In an embodiment, each frequency correction submodule comprises a synchronizer for synchronizing the set, in particular the confirmation signal on the bus, with the cluster clock signal.

[0027] In an embodiment, each frequency correction submodule further comprises a synchronizer, which is used to synchronize the frequency correction signal from the digital core with the cluster clock signal, in particular to synchronize the gating of the frequency correction signal.

[0028] In an embodiment, each frequency correction submodule comprises a filter (particularly an IIR filter) which filters the resynchronized frequency correction signal before entering the handshake module.

[0029] In an embodiment, the cluster digital frequency correction submodule group is configured to send the data selection encoding output signal to the cluster to the logical data slice cross bar, and the cross bar is configured to, under the control of a configuration bus signal, issue the data selection encoding frequency correction request signal to the transmitter based on the grouping of the transmitter, and the configuration bus signal indicates which cluster each data slice belongs to, and the configuration bus signal is issued by the register map, which is particularly programmable.

[0030] In an embodiment, the digital frequency correction module includes a mapping register module storing the groupings in clusters.

[0031] In an embodiment, the phase error is supplied as a frequency correction between such signals by a proportional-integral phase correction module which applies a proportional-integral correction with the phase difference as input, whereupon the frequency correction module issues the data strobe encoded frequency correction signal.

[0032] In an embodiment, the digital frequency correction module comprises a configuration manager configured to, for each cluster, indicate based on a setting signal which transmitter is active, to which cluster each transmitter belongs, and to indicate based on the setting signal which transmitter is enabled relative to the corresponding frequency correction submodule.

[0033] In an embodiment, the transmitter cluster reference clock is selected among a set of available clock signals and the cluster digital frequency correction submodule is clocked by a clock selected among the set of available clock signals, specifically corresponding to the transmitter reference clock selected for the corresponding cluster.

[0034] In an embodiment, the solution also relates to a serializer deserializer module, which is configured to receive parallel data read from at least one FIFO architecture device with a read clock on a set of buses to the serializer deserializer module. The serializer deserializer module is configured to transmit the data read from the at least one FIFO architecture device on a set of buses as a corresponding set of serial signals transmitted by a corresponding set of transmitters, the set of serial signals and the corresponding transmitters are logically grouped according to one or more groups or clusters, which specifically correspond to one or more groups of the buses.

[0035] The group of transmitters includes corresponding independent PLL circuits, which use the cluster transmitter reference clock shared by the transmitters as a reference to emit corresponding PLL clock signals and a group of low-frequency clock signals obtained from the PLL clock signals (in particular, by frequency division), and the cluster transmitter reference clock controls the frequency of operation (in particular, serialization) of the transmitters, wherein the serializer / deserializer module is configured to operate in the system according to an embodiment.

[0036] In an embodiment, the solution also relates to a method for controlling a system according to any one of the preceding embodiments, comprising: supplying a data strobe coded frequency correction signal to each independent PLL circuit, the signal specifying a frequency correction command obtained from a detected phase error between a write clock and a read clock included in the digital core, the read clock corresponding to one of the PLL low-frequency clock signals; performing reception and processing of a corresponding data strobe coded cluster frequency correction at a corresponding one or more cluster digital frequency correction submodules corresponding to a corresponding cluster, and also receiving a corresponding clock signal, in particular a transmitter reference clock selected for the corresponding cluster; upon receiving a specified When the data-selection-encoded frequency correction signal of the frequency correction command is issued, the corresponding confirmation signal is enabled at each of the transmitters; and at the corresponding one or more cluster digital frequency correction submodules, a group of confirmation signals, especially on the bus, which are sent by all enabled transmitters of the cluster and resynchronized with the cluster clock signal are received. After a group of failure confirmation signals of resynchronization are received from all enabled transmitters of the cluster, the data-selection-encoded cluster frequency correction signal that is enabled to command the frequency correction of the corresponding cluster transmitter is issued, and the confirmation signal is disabled after a certain number of cycles of frequency correction are completed for the frequencies of all independent PLL circuits of the corresponding cluster. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0038] Figure 1 Schematically represent the electronic system;

[0039] Figure 2 is a schematic diagram of a frequency correction module included in the system;

[0040] Figure 3 is a schematic diagram of a cluster frequency correction module included in the frequency correction module;

[0041] Figure 4 is a schematic diagram of one of the cluster frequency correction modules for each cluster;

[0042] Figure 5 is a schematic diagram of a filter included in one such submodule;

[0043] Figure 6 is a schematic diagram of a crossbar switch included in a frequency correction module;

[0044] Figure 7 is a time plot of a signal from a frequency correction module; and

[0045] Figure 8is a schematic diagram of a configuration manager module included in a frequency correction module. DETAILED DESCRIPTION

[0046] In the following description, one or more specific details will be explained to provide a deeper understanding of the examples of the embodiments of the present specification. The embodiments can be obtained without one or more of the specific details, or can be obtained with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not explained or described in detail so as not to obscure certain aspects of the embodiments.

[0047] References to "an embodiment" or "an embodiment" in the framework of this specification are intended to indicate that a particular configuration, structure, or feature described in conjunction with the embodiment is included in at least one embodiment. Thus, phrases that may appear in one or more points of this specification (such as "in an embodiment" or "in an embodiment") do not necessarily refer to the same embodiment. Furthermore, particular configurations, structures, or features may be combined in any appropriate manner in one or more embodiments.

[0048] The references used herein are provided for convenience only and do not define the scope or scope of the embodiments.

[0049] Figure 1 An embodiment of a serial data link architecture is schematically illustrated.

[0050] Digital electronic system 11 (eg, system on chip) includes a serializer / deserializer device 60 (also referred to as a SerDes module) that transmits serial data at a high data rate to implement a high-speed interface for system 11. System 11 also includes a digital core 50, which may correspond to a network communication device.

[0051] The digital core 50 comprises at least a device having a first-in-first-out (FIFO) architecture 13, or a FIFO architecture device, in particular a FIFO memory or buffer, written with a write clock DRC supplied at a write clock input WC, in particular the write clock being a data recovery clock obtained from input data received upstream of the FIFO architecture 13, and configured to transmit parallel data read from the FIFO architecture 13 with a read clock on a plurality of buses B1, ..., B m The read clock is supplied at the read clock input RC and is transmitted to the serializer deserializer module 50. m As described in more detail below, TC m Indicates the PLL clock low frequency or divided frequency selected in the SerDes 60. As indicated, since the solution described herein involves the SerDes 60 for the multiple buses B1, ..., B mThe data is serialized and controlled by the function, so Figure 1 In the embodiment, the digital core 50 is only partially represented with reference to components, modules, and signals related to the solution described herein, such as outputting a plurality of buses B1, ..., B m FIFO memory 13.

[0052] In addition, the SerDes 60 only refers to the bus from which it will be from the plurality of buses B1, ..., B m 1 and 12. The embodiment of the present invention is shown in the transmit portion (i.e., transmitter portion 14) of the parallel data serialization, which operates under the control of the solution described herein (i.e., digital frequency correction module 30 or DFM 30, preferably included in the digital core 50, as described below).

[0053] Therefore, the serializer deserializer 60 is configured to transmit data between the plurality of buses B1, ..., B m The parallel data is transmitted as a plurality of transmitters 141, ..., 14 m The corresponding multiple serial signals T1,…,T m to transfer.

[0054] According to one aspect of the solution described herein, the serial signals T1, ..., T m and corresponding transmitters according to one or more groups or clusters CLT k logical grouping, k is the cluster index, which can vary between 1 and p. This logical grouping means that the serial signals T1,…,T m The DFM 30 logically maps the CLT to correspond to different clusters. k The total serial signals T1, ..., T m A portion of the data slice is also indicated as a logical data slice. Figure 1 Only the serial signals T1, ..., T m In the example shown, m=8, however, there may generally be more clusters (or equivalently, more SerDes represented by a corresponding cluster). In other words, the SerDes 60 may include corresponding serial signal groups T1, ..., T m Multiple clusters of CLTs operated by groups k (the value of m can vary from cluster to cluster), and each transmitter 14 i can be regarded as a part of the corresponding SerDes, that is, in this figure, the SerDes 60 can be regarded as including m SerDes modules, each module on bus B i Operate and output serial signal T iIn addition, the transmitter 14 corresponding to the SerDes i It is also called data slice, and the corresponding PLL frequency division output clock TC i It is called digital data slicing clock.

[0055] Low frequency or divided frequency output clock TC i Indicates for transmitter 14 i The digital part of the clock, and in this example, it is used as the PLL high frequency output HF i Therefore, it is the low-frequency PLL clock TC i , instead of high frequency clock HF i In an embodiment, the low frequency output clock TC i It is through the high frequency clock HF i The high frequency output HF is obtained by frequency division, but other methods (such as frequency multiplication) can also be used to obtain the high frequency clock and the low frequency clock from the phase-locked loop (PLL). i Instead, it is used for the output serial (analog) data so that a clear distinction can be made between the analog and digital parts of the data slice. For example, the FIFO TF inside the transmitter i The digital clock (i.e., the divided output clock TC i ) is clocked, while the transmitter serial output buffer (for example, PS i ) sends serial data in the form of a high-speed analog waveform, which is output by the PLL high frequency or the PLL high frequency output HF i To time.

[0056] It should also be emphasized that the FIFO architecture 13 may include a FIFO for each cluster, with the divided or low-frequency clock signal TC from the corresponding cluster. m As read clocks, that is, there are as many read clocks as clusters.

[0057] SerDes 60, or by the corresponding transmitter 14 i Each of the indicated m SerDes modules typically includes a serializer portion (serializing each received parallel data signal and including a transmitter 14) and a deserializer portion (which receives a serial signal, for example, from an external communication node, typically from another SerDes), and parallelizes each of them into a corresponding parallel data stream. Parallel data is bits or symbols that are processed in parallel simultaneously with a low-frequency digital clock and correspond to the number of serial data symbols each processed with a high-frequency PLL clock. This number is also proportional to the division ratio of the low-frequency clock obtained from the high-frequency clock. However, in Figure 1 For simplicity, only the transmitting part 14 (ie, the receiving bus B1, ..., B mpart), serializes the data therein and transmits it as a serial signal T1,…,T m to transfer.

[0058] The i-th (i=1, ..., to m) transmitter 14 i (In the figure, transmitters i=1 and i=8 are shown, indicating a group of transmitters 141, ..., 14 m The two ends of the PLL circuit include a PLL loop PL i . Figure 1 The PLL loop is not fully displayed in i , however it can be a standard loop, for example, receiving a reference clock Tx_REF_CLK(k) (i.e., a common reference clock for cluster k), and supplying the error or difference, for example through a difference block, to a loop filter and then to a voltage controlled oscillator (VCO), outputting a PLL output clock HF i frequency, which is usually used for serializers or parallel-to-serial converters PS i As mentioned above, the PLL output clock HF i The frequency (depending on the reference frequency Tx_REF_CLK(k)) is supplied to the serializer PS i The high-frequency clock can be higher than the PLL low-frequency clock TC i The PLL loop PL i It is based on a high frequency VCO (e.g., 28 GHz) that is divided down (e.g., by a divide-by-16 ratio, i.e., 28 GHz / 16 = 1.75 GHz) to run the digital portion of the transmitter. i The external PLL low frequency clock TC is executed and output i In this figure, for simplicity, this frequency divider is not shown, so the PLL low frequency clock TC i is shown as derived from the PLL PL i block. PLL output clock frequency HF i Also in the loop PL i Through the crossover FD i is fed back to the difference block to be subtracted from the reference frequency Tx_REF_CLK(k). This frequency divider FD i From the Sigma-Delta Modulator SM iReceiving the corrected average frequency division value ND+DFRV, the modulator receives as input the nominal frequency division value ND, for example from a control logic not shown in the system or digital core. DFRV indicates the frequency correction value, i.e. the correction value calculated by block 57k, sent from the corresponding cluster module 311k. The term "average" refers to the fact that the frequency divider FD i is just an integer divider that is dynamically modulated according to its integer division ratio in order to obtain a divided clock output that has an "average" frequency according to its dynamic modulation frequency, just as if the divider FD i In fact, it is driven by ND+DFRV.

[0059] Frequency Divider FD i In PLL PL i internal, and do not compare it with the output PLL low frequency clock TC i The external divider of the PLL is not confused, but a comparison clock is generated, which is used as the PLL PL i One of the two inputs of the difference block in , is also used as a Sigma-Delta modulator SM i 's clock, as discussed below.

[0060] Therefore, the Sigma-Delta modulator SM i is configured as a divider FD i The nominal frequency division value ND and the frequency correction average value DFRV are supplied as the set value. Since the corrected average frequency division value ND+DFRV may and usually is not an integer, the Sigma-Delta modulator SM i and PLL loop PL i A Sigma-Delta based fractional phase locked loop is provided. The frequency correction value DFRV may be a cumulative value of the current and previous frequency correction requests. For example, after the first frequency correction request has been correctly applied, as long as the write clock WC moves further due to any external reason (such as temperature change), a new phase error is detected relative to the previous stable state and therefore needs to be added to the previous correction in order to provide the correct frequency correction value DFRV for it to be added to the fixed value of the nominal division value ND, the low frequency clock TC i It runs relative to the write clock WC without phase error (steady state).

[0061] exist Figure 1 Sigma-Delta Modulator SM i Includes transmitter handshake module HS i , which will be better described below. As indicated, the module with the i subscript refers to the i-th transmitter 14 i At the i-th transmitter 14i The corresponding FIFO memory TF is also shown in i , which can be used to receive the corresponding bus B i The data on the i , Serializer PS i The serial signal is obtained by the transmitter 14 i Drive by DR i Output is serial signal T i .

[0062] In the following, when referring to the PLL circuit, for simplicity, reference is made to the output PLL clock (ie, the high frequency PLL clock HF i ) of the PLL loop PL i , however, the PLL circuit can usually be considered to include at least the Sigma-Delta modulator SM i and therefore includes a transmitter handshake module HS i As an example of implementation, the classic Sigma-Delta MASH III block can be modified to allow input correction and handshaking mechanisms.

[0063] The data recovery clock DRC operates in a corresponding clock domain (write clock domain).

[0064] Then, the read output of FIFO 13 is determined by the transmitter digital clock signal (ie, the PLL low frequency clock TC m ) timing, the clock signal is taken from the output transmitter 14 (specifically 141 to 14 m ) of the PLL low-frequency clock signal TC1,…,TC m The output transmitter 14 receives the signal at the output of the read output of the FIFO 13 and uses a signal that depends on the PLL clock signal (i.e., the PLL PL i Send out high frequency HF1,…,HF serialized with operation data m ) of the high data rate clock to transmit the serial data T1,…,T m The modules (eg, network modules) are coupled to the SerDes transmitters 141, ..., 14 through communication channels or paths. m The output of the SerDes transmitter 141,…,14 m Receives the same transmitter common cluster local reference clock Tx_Ref_Clock(k) as the PLL PL i The reference clock of the output clock signal is the same as the related digital (low frequency) clock TC1,…,TC mThe clock frequency value of is controlled by a digital frequency correction module 30, which is also called a Delta Frequency Manager (DFM) module, wherein a Delta indication is applied to one or more of such output clock signals, or equivalently to the PLL clocks TC1, ..., TC m The frequency difference or correction for the kth cluster is DFRV (i.e., DFRV k ) can be considered as the fractional part added to the corresponding division ratio (i.e., the nominal division value ND), resulting in the PLL high frequency output HF i and its external frequency-divided counterpart (PLL low-frequency clock TC i It should be emphasized here that the nominal frequency division value ND can be an integer, or it can also be an average fraction ratio due to Sigma-Delta modulation.

[0065] Then, in Figure 1 In the phase detector 55 k The receive data recovery clock DRC (i.e., the write clock of FIFO 13), and the transmitter digital clock TC selected as the read clock of FIFO 13 m (Here for simplicity, it is indicated as the mth clock TC m , but it can be any clock TC1,…,TC in the cluster m ), to the frequency correction module 57 k The output phase error PE (i.e., the error PE between the write clock and the read clock of the FIFO 13). The index k of the modules 55k and 57k indicates that an instance of such a module is provided for each k-th cluster. The frequency correction module 57k sends a data strobe code frequency correction DFR(k), DFR_STB(k) signal to the cluster digital frequency correction module 311k (i.e., for the corresponding k-th cluster). As described below, the cluster digital frequency correction module 311k k is included in the digital frequency correction module 30, in particular, as Figure 3 As shown in FIG. 1 , it is included in the cluster group digital frequency correction module 31 , however, the module 31 can be regarded as accommodating the cluster group digital frequency correction module 311 k The logical container.

[0066] The data strobe encoded frequency correction DFR(k), DFR_STB(k) signal includes a data signal, a frequency correction signal DFR(k) sent on a signal bus line, and its strobe frequency correction signal DFR_STB(k) sent on another signal line, which together represent a data strobe or D / S encoded signal using two signals such as data and strobe lines. Hereinafter, when referring to a data strobe encoded signal, reference will be made to such a signal having two signals on two lines, for example, unless the description refers to a specific use of one of the two signals (data or strobe).

[0067] The frequency correction module 57k can be operated to perform a proportional integral correction on the phase error PE and then differentiate to obtain a correction value DFRV in the data selection code frequency correction DFR(k), DFR_STB(k). The code frequency correction data signal DFR(k) can be a signal that is equal to zero when the detected phase error PE is zero, or equal to the value DFRV when the detected phase error PE is not zero. Once detected, the kth value DFRV of the kth cluster is k The signal DFR(k) is placed on the bus line, and after it has stabilized on all the bits that make up the bus, a strobe is issued on the code frequency correction strobe DFR_STB(k) single-bit line, which will carry the kth value DFRV k The signal is marked as stable. During the high level of the strobe, no changes are allowed to the coding frequency correction data signal DFR(k) line bus. For this reason, among other things, an acknowledgement signal DFM_DFR_ACK(k) can be used to send a flag to the core 50 indicating that the coding frequency correction strobe pulse DFR_STB(k) can be reset. If the acknowledgement signal DFM_DFR_ACK(k) is not used, the strobe pulse DFR_STB(k) can be reset based on a predetermined setting, such as a delay introduced by the DFM and data slice handshake (e.g., their sum). In this example and preferably, such a module 55k-57k is included in the digital core 50, which is, for example, part of the system 11 (in this example, a system on a chip that also includes a SerDes 60 (i.e., implementing a high-speed interface for the system 11)).

[0068] In the following, it will be remembered that each k index corresponds to m indices from 1 to i to m. These m indices are referenced to the kth cluster by the crossbar switch 32 demultiplexing operation, reference Figure 6 Described in detail.

[0069] As described in more detail below, each cluster digital frequency correction module 311 is configured to receive a plurality of digital frequency correction modules 311 through demultiplexing operated by the crossbar switch 32. k To the corresponding transmitter 14i Or data slice sends the corresponding frequency correction request signal DFM_DFR[i] and the corresponding frequency correction request selection signal DFM_DFR_STB[i], specifically to the Sigma-Delta modulator SD i When receiving the corresponding frequency correction request signal DFM_DFR[i] and the corresponding frequency correction request strobe signal DFM_DFR_STB[i] to specify the command for frequency correction DFRV (the data value on the data line DFM_DFR[i] and the strobe valid DFM_DFR_STB[i]), the transmitter handshake module HS i The frequency correction request signal is a data strobe or D / S coded signal using two signals such as data and strobe lines.

[0070] Transmitter Handshake Module HS i Receive the cycle value CY, which can be referenced Figure 2 The data slice register map 34 is programmed and indicates the frequency divider FD i How many cycles of the PLL clock at the output (for the Sigma-Delta modulator SM i and transmitter handshake module HS i The transmitter handshake module his maintains the corresponding confirmation signal DS_DFR_ACK[i] valid during the same duration and maintains the corresponding value DRFV (especially for the Sigma-Delta modulator SM i DFRV i ).

[0071] Now, based on the reference Figure 1 The system described above, the associated data recovery clock DRC may be different from the SerDes transmitter digital clock, the PLL divided clock signal TC1, ..., TC m , which is generated by a local independent phase-locked loop (PLL) PLi and starts from a common local reference clock (ie, Tx_REF_CLK). In particular, if the data written to FIFO 13 arrives from different physical (eg, geographical) locations. In fact, by way of non-limiting example, although in Figure 11, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 79, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110 m Outputs PLL low-frequency divided clock signals TC1,…,TC that usually belong to another clock domain m The other clock domain can be obtained by dividing the FD i The output of a set of sigma modulators SM i Clock composition.

[0072] As stated, this is not a limiting example, as there may be other reasons or architectures that determine that the write clock is different from the SerDes PLL divided clock signal. Typically, the write clock can be different from the SerDes divided clock due to physical changes that the data undergoes at the remote transmitter before being sent into the optical fiber, i.e., it is related to physical changes over time.

[0073] Therefore, it is necessary to detect the data recovery clock DRC and the SerDes transmitter clock, PLL low frequency division clock signal TC1,…,TC m The difference between the two, and by resynchronizing all transmitters 141,…,14 m To compensate, these transmitters should read data at the same rate while avoiding any phase drift. In fact, such drift would prevent data from being correctly transferred across the FIFO buffer or memory 13.

[0074] According to one aspect of the solution described herein, block 55k is only for one of the PLL low-frequency divided clock signals (in this example, the m-th PLL low-frequency divided clock signal TC m , in this example m=8, so TC8) and detect the phase error PE, and based on this phase error PE, the corresponding cluster digital frequency correction module 311 k And the compensation (ie, the frequency correction request signal DFM_DFR) is applied to all high frequency PLL outputs HF by the demultiplexing block 32. i , thus applied to the transmitters 141,…,14 of the kth cluster mAll output PLL low frequency divided clock signals TC1,…,TC m .

[0075] However, compensating for the frequency error may not be sufficient to correctly read the data because bounded phase differences across all transmitters 14, ..., 14n cannot be guaranteed due to misalignment in applying the compensation.

[0076] Therefore, according to the solution described herein, the cluster digital frequency correction module 311 in the transmitter handshake module and DFM 30 k A handshake mechanism (described below) is implemented as a solution to ensure that frequency compensation is applied for the same duration, thereby ensuring frequency updates and bounded phase differences in this way. As will be shown, essentially, when the slave core 50 (e.g., module 57 k ) applies a set of values ​​DFRV to DFM 30 (DFRV[k] is a single value for the cluster with the kth index), for each kth cluster, module 311 in DFM 30 k The selection signal DFR_OUT_STB[k] is validated, and the correction value DFRV[k] is processed to output the DFR_OUT[k] signal. Then, because it performs signal demultiplexing from the cluster to the appropriate logical data slice (i.e., the i-th transmitter or the basic SerDes), the crossbar switch 32 (or the cluster to logical data slice crossbar switch) is configured to send a corresponding frequency correction request signal DFM_DFR[i] and a corresponding frequency correction request selection signal DFM_DFR_STB[i] (i.e., D / S encoded signal) to the transmitter 14 of the corresponding cluster. Then, in the cluster digital frequency correction module 311, k At, waiting for data slices (ie, transmitters 141, ..., 14 m ) rises to invalidate the selection signal DFR_OUT_STB[k]. Then, the set of confirmation signals DS_DFR_ACK[k] waiting for the data slice falls (i.e., invalidates), for example, becomes a logic 0. In particular, the set of confirmation signals is a bus including DS_DFR_ACK[i] signals, whose index i is from 1 to m, belonging to the kth cluster.

[0077] It should be emphasized that the frequency correction command (ie, DFR_OUT[k], DFR_OUT_STB[k]) can be generated by the cluster module 311 in the DFM 30. k Repeatedly apply (i.e., repeatedly gate) to the corresponding cluster CLT k The transmitters belong to the same cluster CLT kAll transmitters (i.e., data slices) of the cluster operate at the new desired frequency. This repetition allows for a steady state in reaching the new frequency of PLL operation. k Each repetition of the same duration of the PLL in the PLL allows operation without accumulating unbounded phase differences. A null command time gap is inserted between the repetitions. This gap null command time gap allows a delay of all signals rising or falling in a group of DS_DFR_ACK[i] signals before DFR_OUT_STB[k] fails or is newly validated respectively. The gap is actually the duration between the failure and the new validation of DFR_OUT_STB[k].

[0078] When the cluster digital frequency correction module 311 k When a new command (ie, signal DFR[k], DFR_STB[k]) is provided, this will be applied according to the delay, the larger part of which is usually the transmitter 14 i delay.

[0079] If the transmitter 14 i busy executing the previous command (ie, the previous frequency correction), then the transmitter 14 i When idle (e.g., its DS_DFR_ACK[i] is invalid (delayed)), the new command DFM_DFR[i], DFM_DFR_STB[i] is applied immediately. If the command rate is too high, the new command may be lost. If the transmitter 14 i Idle, the new command DFM_DFR[i], DFM_DFR_STB[i] is applied by making its selection signal effective.

[0080] Expected command rates may be 10-100kHz. Higher frequency noise filtering with bandwidth programmability is provided.

[0081] The implementation depends on the number of clusters p and the number of data slices m. Cluster DFM module 311 representing the command interface k The number of transmitters is p. i The number is m, each transmitter 14 i The corresponding SerDes within the SerDes 60 may be represented.

[0082] In view of this implementation, it is necessary to provide a setting configuration to the DFM 30 so as to control the cluster CLT with the corresponding cluster DFM module 311k. k ; and providing a "Delta-Frequency" command, ie, DFR[k], from the core 50 to each cluster DFM module 311k.

[0083] As a specific use case implementation: p=1, m=N, i.e., there is only one cluster with multiple N data slices.

[0084] According to another aspect of the solution, a Sigma-Delta based fractional phase locked loop (eg, Figure 1 The circuit described above is a circuit for synthesizing high-resolution electrical oscillations, which is used as an independent phase-locked loop circuit PL i (or Sigma-Delta Modulator SM i and PLL loop PL i combination) and issue a high frequency PLL output HF i , which outputs the clock signals TC1,…,TC through a dedicated external divider. m The module 311k in the digital frequency correction module 30 represents the transmission of the transmitter 141, ..., 14 m All independent phase-locked loops PL1,…,PL m A digital block that supplies frequency correction DFRV (ie frequency value update).

[0085] Therefore, the DFM 30 controls the PLL internal frequency divider FD via the input modified by the Sigma-Delta modulator (ie, the nominal frequency divider ratio ND modified by the frequency correction DFRV). i The frequency correction DFRV, Q-6.20 fixed point symbol, is added to the nominal divider ratio ND, for example with the following specifications: LSB = 1 / 32ppm; Range = + / -512ppm; Minimum delay = 128 cycles (i.e., Sigma-Delta handshake module HS i In busy state, ie, DS_DFR_ACK[i]=1, to achieve this minimum latency; and a programmable number of cycles CY (from 128 to 8192, powers of 2 only).

[0086] In particular, the fractional Sigma-Delta PLL circuits SM1,…,SM m is configured to perform frequency synthesis with a full-precision division ratio, in particular, including an unsigned number (U6.20 fixed-point representation, where the letter "U" stands for "unsigned" number), where the integer part has 6 bits and the fractional part has 20 bits, according to the following model formula for the division ratio: Nint+FRAC / MOD, where Nint is the integer part of the division ratio, FRAC / MOD: the fractional part, and FRAC <MOD=2^20–1。

[0087] As the Q-6.20 correction value is a 20-6 = 14 bit number, with another bit for the sign (the letter "Q" indicates this), the Sigma-Delta PLL circuit should also take into account the negative correction. And, if this negative correction is sufficient to require a change in Nint, the circuit should also perform that change. Therefore, the correction is a 15-bit signed number (Q-6.20: 1 bit for the sign and 14 bits for the absolute correction), which is added to the nominal U6.20 value according to the rules of signed arithmetic.

[0088] The frequency correction DFRV is applied to all PLLs in a cluster with the same cycle number CY, such as Figure 1 As shown in Figure 2, CY is in the Sigma-Delta modulator SM. i and repeats until a new command is available.

[0089] As mentioned above, the time gap between repetitions ensures that all data slices in the cluster (ie, transmitters 14 i ) has terminated the number of programming cycles CY, so new commands can be processed again for the programming cycle CY.

[0090] Therefore, based on the Figure 1 The digital frequency correction module 30 passes the PLL high frequency output through the circuits PL1, ..., PL m The external divider divides the clock signals TC1,…,TC m The output frequency of each divider receives a common local reference clock, i.e., Tx_REF_CLK. This is for each data slice (i.e., transmitter 141, ..., 14 m , output serial signal T1,…,T m , grouped in a given cluster k) based on the read clock (e.g., TC m ) and a write clock (e.g., DRC). This frequency alignment control is used to avoid glitches when reading and writing data streams from and to the FIFO architecture 13, respectively. Any misalignment (e.g., temperature variation of the remote optical transmitter) is phase detected, resulting in a phase error PE, and then a frequency correction DFRV is generated (e.g., by a proportional-integral controller, e.g., a block that may also be included or permitted to block 57k), and then differentiated (e.g., in block 57k) to provide the digital frequency correction module 30 with a cumulative frequency correction DFRV in a data strobe encoded frequency correction DFR(k), DFR_STB(k) signal.

[0091] Cluster-based CLT kThe number p of the digital core 50 sends the corresponding frequency correction value DFR(k) and its selection signal DFR_STB(k) to the corresponding cluster digital frequency correction module 311 in the digital frequency correction module 30 through the corresponding port of this module 30. k These signals are corrected by the digital frequency correction module 30 (ie, each cluster digital frequency correction module 311 k ) and the crossbar switch 32 for managing the corresponding cluster transmitter 14 i The PLL circuit PL i Generate corresponding request / select signal, select code frequency correction request signal DFM_DFR[i], DFM_DFR_STB[i]. For all its serial signals (for example, T1, ..., T belonging to the cluster), m , i.e., all data slices of the cluster), each k-th cluster manages the same corresponding frequency correction request DFR_OUT[k], DFR_OUT_STB[k]. As shown in the figure, the D / S-coded frequency correction request DFM_DFR[i], DFM_DFR_STB[i] is sent to each transmitter 14. i Each transmitter handshake module HS in (i=1 to m) i was received.

[0092] kth cluster digital frequency correction module 311 k From each transmitter (ie, from each transmitter handshake module HS i ) receives the confirmation signals DS_DFR_ACK[1], ..., DS_DFR_ACK[m], and resynchronizes each confirmation signal with respect to the local clock DFM_CLK[k], thereby sending a handshake signal to the cluster DFM module 3113 k Provide resynchronization signal DS_DFR_ACK_RES[i], cluster DFM handshake module 3113 k Wait for the latest resynchronization signal DS_DFR_ACK_RES[i] to be asserted or deasserted in order to deassert or newly assert the frequency correction request strobe DFR_OUT_STB[k], respectively.

[0093] Cluster DFM module 3113 on the transmitter side (ie, SerDes side) k It is configured to validate the frequency correction request strobe pulse DFR_OUT_STB[k] to signal that data is present and generally stable on each line of the bus that constitutes the frequency correction request DFR_OUT[k]. When the confirmation signal DS_DFR_ACK_RES for resynchronization of the entire group, especially the bus, is validated, the frequency correction request strobe pulse DFR_OUT_STB[k] is disabled, so that it can freely accept the signal from the filter 3112.k This is the handshake mechanism on the transmitter side (i.e., in the cluster DFM handshake module 3113). k Handshake module HS with transmitter i In addition, the cluster DFM handshake module 3113 k A signal may be sent to the core 50 as in the exemplary embodiment, indicating that a new frequency correction request DFR[k], DFR_STB[k] may be provided. Hereinafter, it is referred to as an acknowledgement signal ACK (such as DS_DFR_ACK[m]), which is valid if activated. When a signal is valid (meaning it is active), it is performing the operation indicated by its designation, for example, an acknowledgement signal acknowledges: for example, when logic high, or for example, when a reset signal RESET is active (e.g., high), the reset signal is validated. Validation describes the state of active high and active low signals.

[0094] The described handshake mechanism is asynchronous on both sides, the cluster DFM module 311 k To the transmitter 14 and the cluster DFM module 311 k to core 50, because each handshake module HS in the kth cluster i Acknowledge (eg, set high) the responses DS_DFR_ACK[i], which are asynchronous with respect to the k-th cluster clock signal DFM_CLK[k] to which they belong (in addition, due to the frequency divider FD i In the same way, the digital core 50 asynchronously sends the strobe pulse DFR_STB[k] for a new request, which means that the strobe pulse DFR_STB[k] is raised according to the transition of the clock that is asynchronous with respect to the k-th cluster clock DFM_CLK[k].

[0095] Figure 1 It is also shown that a plurality of PLL reference clock signals CSF, CSA, CSC are provided, and the system 11 is configured to select one of them as the PLL PL for a given cluster. i In the same way, under the control of the selection signal CLK_SEL(k) sent by the system 11, the multiplexer 312k selects the kth cluster clock signal DFM_CLK[k] from the multiple PLL reference clock signals CSF, CSA, and CSC. The cluster clock signal is the digital frequency correction submodule 311. k Timing.

[0096] The reference clock signals CSF, CSC, and CSA represent programmable clock reference signals having the same or different frequencies. i Or the data slice may be placed closer or farther away from the core 50, so for similar reasons, the cluster's reference clock TX_REF_CLK(k) can select between the following two: in this example, the reference clock signal CSC close to the core 50, and the reference clock signal CSF far away from the core 50, CSA indicates an auxiliary reference clock signal.

[0097] For example, for physical design reasons, a given reference clock signal (e.g., CSF) is selected as the PLL reference clock TX_REF_CLK(k) of cluster k, which is the reference clock of all PLL loops in the cluster. i The PLL reference clock.

[0098] DFM 30 and its submodules also receive the same reference clock signals CSF, CSC and CSA, and each submodule 311 k Preferably, each k-th cluster PLL loop PL i The reference clock selects the same clock, although this is not mandatory. The selected clock (e.g., CSF) is usually referred to as DFM_CLK[k], and can also be indicated as DFM_CLT_CLK64(k), with the number 64 indicating 64 unit intervals (UI), which means that a period of DFM_CLT_CLK64 lasts for 64 periods of serial transmission (e.g., 64UI; meaning that if the transmission data rate is 56GBaud, 1UI=1 / (56E9)=17.857ps).

[0099] Figure 2 A block diagram showing in detail the digital frequency correction module 30 is shown. The module 30 may include one or more cluster digital frequency correction modules 311. k , such as module 311 represented as a whole by the cluster group digital frequency correction module 31 k The D / S coding frequency correction signal DFR[k], DFR_STB[k] is received by the group. This D / S coding frequency correction DFR[k], DFR_STB[k] on the data line contains the frequency correction value DFRV.

[0100] 311 per module k The confirmation signal DFM_DFR_ACK[k] is sent back to the core 50 (specifically to the corresponding k-th module 57k), and the confirmation signal bus DS_DFR_ACK is received from the transmitter 14 (each bus line signal is DS_DFR_ACK[i], the i-th index ranges from 1 to the number of data slices in the k-th cluster).

[0101] The digital frequency correction module 30 then includes a local register map 34 that can be accessed for programming, which outputs a configuration bus setting DFM_CLT_DS_CFG[i] to the crossbar switch 32, i.e., indicating or setting each data slice (e.g., 14 i , i is the data slice index from 1 to m) belongs to which cluster CLT k Therefore, the local register map 34 sends an enable setting DS_EN[i] to the configuration manager module 33 which also receives the setting DFM_CLT_DS_CFG[i], which indicates which data slice (ie, the transmitter 14 i Based on this setting, the configuration manager module 33 sends an active slice setting DFM_DS_ACT[k] to the cluster group digital frequency correction module 31, indicating which data slice is active for each k-th cluster. The module 31 also receives a mode setting CLT_DPR_MODE[k] from the register map 34 and to each cluster module 311. k The selection setting CLK_SEL[k]. The mode setting CLT_DPR_MODE[k] enables Delta-Phase mode when active. The operation of this mode disables the repetition of the correction requests DFR_OUT[k] and DFR_OUT_STB[k], thus enabling the phase correction operation (the command is still a frequency command, but it is not repeated. It does not allow the PLL to reach a new frequency stable state, i.e., the frequency returns to its nominal value after the phase correction is completed).

[0102] When a data slice belonging to a cluster is inactive, the active slice setting DFM_DS_ACT[k] does not need to wait for its acknowledgment signal DS_DFR_ACK[i], so as not to let the module's handshake operation wait for it indefinitely. This is a setting for each cluster, and a data slice belongs to only one cluster, so it is disabled in all other clusters.

[0103] The cluster digital frequency correction module 31 receives a plurality of PLL reference clock signals CSF, CSC, CSA.

[0104] Figure 3 A cluster group digital frequency correction module 31 is shown which manages a set of frequency correction request signals DFR_OUT, DFR_OUT_STB arranged in parallel paths, each referring to a D / S encoded frequency request signal DFR(k) DFR_STB(k) of a corresponding cluster k, indexed from 1 to p.

[0105] This cluster group digital frequency correction module 31 includes a digital frequency correction submodule group, from 3111 to 311 p , p is the total number of clusters.

[0106] Each k-th digital frequency correction submodule 311 k Receive the D / S coded frequency request signal DFR(k) DFR_STB(k) of the corresponding cluster k, which is the corresponding part of the frequency request signal DFR and the corresponding incremental frequency request selection signal DFR_STB for the kth cluster. Each digital frequency correction submodule 311 k With the corresponding multiplexer 312 k Under the control of the selection signal CLK_SEL(k), the multiplexer selects a clock from the multiple clock signals CSF, CSA, and CSC, that is, the digital frequency correction submodule 311 k The k-th cluster clock signal DFM_CLK[k] is clocked.

[0107] As shown in the figure, in addition to the corresponding selection signal CLK_SEL(k), the kth digital frequency correction module cluster 311 k A corresponding active slice signal DFM_DS_ACT(k) and a corresponding mode signal CLT_DPR_MODE(k) are also received.

[0108] Then, the kth digital frequency correction module cluster 311 k The output signal DFR_OUT(k) is output to the crossbar switch 32 together with the corresponding output signal strobe DFR_OUT_STB(k) corresponding to the k-th cluster.

[0109] The mode signal CLT_DPR_MODE(k) sends a signal indicating the operating mode of the interface, that is, if the PLL circuit PL i The phase must be updated instead of the frequency, i.e. Delta Phase, whose operation disables the repetition of the correction requests DFR_OUT[k] and DFR_OUT_STB[k], also indicated later as One-Shot (as opposed to Delta Frequency, i.e., with repetitive, or continuous, mode of correction requests)

[0110] In the case of a transmitter from the kth cluster (e.g., 141,…,14 m ) After receiving all the confirmation signals DS_DFR_ACK[1]…DS_DFR_ACk[m], each k-th cluster digital frequency correction module 311 kA corresponding confirmation is also sent for each cluster signal DFM_DFR_ACK[k], which indicates that a confirmation signal for a set of data slices for a specific cluster (i.e., the kth cluster) is sent to the digital core 50. As mentioned above, for the handshake on the core side, sending the confirmation signal DFM_DFR_ACK[k] may be optional, and such a signal may be used by the core 50 to implement a watchdog. The confirmation signal DFM_DFR_ACK[k] is actually confirmed when the latest confirmation signal DS_DFR_ACK[i] from the cluster has been confirmed.

[0111] Figure 4 The k-th digital frequency correction submodule 311 is shown in detail. k , which is used to process a given group of transmitters (e.g., 141, ..., 14 m )(i.e., a frequency correction (i.e., a frequency update request) of a ) (i.e., a cluster).

[0112] This k-th digital frequency correction submodule 311 k Includes core DFR resynchronizer 3111 k The resynchronizer receives each corresponding cluster frequency correction signal DFR(k) and the corresponding selection signal DFR_STB(k), and specifically synchronizes the selection signal DFR_STB(k) with the selected k-th cluster clock signal DFM_CLK[k] (k-th digital frequency correction submodule 311). k Also receives this signal) resynchronizes, and the output is used as a low-pass filter 3112 k The input resynchronization signal DFR_RES(k) is used as the low-pass filter. In this example, the low-pass filter 3112 is an IIR (infinite impulse response) filter. k A set of filter parameters are received, which may include a maximum value DFR_MAX(k), a minimum value DFR_MIN(k), a time constant related value CLT_MU(k), an IIR enable CLT_IIR_EN(k), and an IIR reset bar CLT_IIR_RSTB(k), the reset bar indicating a negative reset, meaning that when the reset bar CLT_IIR_RSTB(k) is at its low level, the reset is active and a reset occurs. In addition to a set of monitoring signals DFR_LPF_MON, the low pass filter 3112 k The filter signal DFR_LPF_OUT[K] is also output to the handshake block 3113 kThe set of monitoring signals FR_LPF_MON includes: output related measurements, such as the maximum value of the output signal DFR_LPF_OUT_MAX_HLD[k], the minimum value of the output signal DFR_LPF_OUT_MIN_HLD[k], and the output signal itself DFR_LPF_OUT[k]; and input related measurements, such as the maximum value of the input signal DFR_LPF_IN_MAX_HLD[k], the minimum value of the input signal DFR_LPF_IN_MIN_HLD[k], and the input signal itself DFR_LPF_IN[k]=DFR_RES[k].

[0113] Low pass filter 3112 k By passing through the divider block 3115 k The obtained divided k-th cluster clock signal DFM_CLK_DIV[k] is clocked, the divider block 3115 k The k-th cluster clock signal DFM_CLK[k] is received and divided by the value set by the selection signal DFR_LPF_CLK_DIV_SEL[k], thereby setting the value of the low-pass filter 3112 k The sampling frequency of the IIR digital filter is shown. k Used to filter unwanted noise at the filter input.

[0114] Handshake block 3113 k The receiving resynchronization confirmation signal DS_DFR_ACK_RES[i] is a data slice confirmation signal DS_DFR_ACK[i] resynchronized with the k-th cluster clock signal DFM_CLK[k] selected in the data slice confirmation of each cluster resynchronization module 3114k. In addition, the handshake block 3113 k Receive the active slice signal DFM_DS_ACT[k].

[0115] Handshake block 3113 k Setup signals are also received as mode selection DPR_MODE[k] (internal signal name of CLT_DPR_MODE[k]), cluster enable DFM_CLT_EN[k], and cluster bar reset CLT_RSTB[k].

[0116] Then, the handshake block 3113 kThe output signal DFR_OUT[k] of cluster k and the output signal strobe DFR_OUT_STB[k] of cluster k represent the common request command of the data slice of the cluster, while DFR_OUT_STB[k] represents the strobe signal in accordance with the command. As mentioned above, the configurable demultiplexing matrix, crossbar 32, can be used in DFM 30.

[0117] As previously mentioned, according to relevant aspects of the solution, the DFM 30 may reassert the command depending on the CLT DPR_MODE signal setting.

[0118] When all active confirmation DS_DFR_ACK signals of the corresponding k-th cluster are invalid (switch to 0), the DFM handshake block 3113 k The command may be reiterated, i.e., the assertion of the strobe signal DFR_OUT_STB[k] may be repeated. Thus, the repeated deactivation of all active acknowledgement signals DS_DFR_ACK[i] indicates to the DFM 30 that the frequency correction request strobe DFR_OUT_STB[k] is repeated, while on the digital core side, the assertion of all active acknowledgement signals DS_DFR_ACK[i] tells the DFM 30 that the acknowledgement DFM_DFR_ACK[k] is asserted, however, it is specified that the assertion occurs only once per assertion of the frequency correction request strobe DFR_STB[k] (i.e., regardless of whether the assertion of all active acknowledgement signals DS_DFR_ACK[i] is repeated).

[0119] Each data acknowledgement DS_DFR_ACK[i] signal remains high for a given number of clock cycles CY, which, as mentioned above, can be set in the data slice handshake block HS. i This number is expressed in Sigma-Delta SM i The duration of the frequency correction command at the input to the PLL PL i Frequency Divider FD i The output clock cycle count is in units. It should be noted that the frequency correction request DFM_DFR[i], DFM_DFR_STB[i] of the i-th transmitter is repeated, but what is actually saved for several CY cycles is the Sigma-Delta modulator SM i The handshake block outputs the summing node (not shown) internally to the Sigma-Delta modulator SM i , where the stored value is added to the nominal ratio ND, i.e., this summing node is composed of the Sigma-Delta modulator SM i Management to enable the Sigma-Delta Modulator SM iThe average value of the output is equal to NDi+DFRV i For each repetition of the frequency correction request DFM_DFR[i], DFM_DFR_STB[i], the duration of the stored value is equal to the CY cycle.

[0120] On any new request (e.g., on input DFM handshake block 3113 k In the signals DFR[k], DFR_STB[k], as the filtering signal DFR_LPF_OUT[k]), before the DFM handshake block 3113 k The repetition of the request (eg, D / S coded signal DFR_OUT[k], DFR_OUT_STB[k]) at the Sigma-Delta modulator SM means that the effective frequency correction is slightly reduced in duty cycle by the reiterated command waveform. i The handshake block outputs to the Sigma-Delta modulator SM i At the internal summing node input, for example, the duty cycle is ∼99%, since the number of cycles CY is much higher than the gap period inserted between repetitions, and the jitter increase is negligible. For each i-th transmitter repetition frequency correction request DFM_DFR[i], DFM_DFR_STB[i], and in the same way for module 311 k The output k-th cluster frequency correction request DFR_OUT[k], DFR_OUT_STB[k] is repeated, and its characteristic is that the incremental frequency request value is not maintained for CY cycles, but is only maintained for several cycles from the time when the enable pulse DFR_OUT_STB[k] takes effect and the enable pulse DFM_DFR_STB[i] is sent to the i-th data slice, to the time when the effective resynchronization signal DS_DFR_ACK_RES[i] is received and both enable pulses are invalidated.

[0121] Figure 5 The low pass filter 3112 is shown k The filter is configured to filter high rate frequency update requests for a given group of data paths. Due to the correctness of the expected request rate relative to the specified typical parameters of the filter, the effect of the filtering is actually to smooth out any unwanted noise on the filter input.

[0122] This low-pass filter 3112 k Basically includes IIR filter 3112a k , the IIR filter receives input (ie, the resynchronization signal DFR_RES(k)), and its output is supplied to the output saturation block 3112b kThe output saturation block receives the maximum and minimum values ​​of each cluster frequency request signal DFR(k) as input settings to ultimately set limits on the dynamic settings of the output signal (ie, the filtered signal DFR_LPF_OUT[k]). Low pass filter 3112 k Includes input min-max calculation block 3112c k And output minimum and maximum calculation block 3112d k , which receive the resynchronization signal DFR-RES(k) and the filtered signal DFR_LPF_OUT[k] as input respectively. The minimum and maximum values ​​calculated by these blocks are then filtered by the low-pass filter 3112 k Output in the monitoring signal group DFR_LPF_MON, as shown in Figure 4 As indicated, together with the input (resynchronization signal DFR-RES(k)) and the output (filtered signal DFR_LPF_OUT[k]).

[0123] Low pass filter 3112 k All blocks of are clocked by the divided k-th cluster clock signal DFM_CLK_DIV[k].

[0124] Figure 6 Crossbars 32 are shown, including a first crossbar 32a, where m=36 and p=36, so the inputs are DFR_OUT[1] through DFR_OUT[p], one per cluster, and the outputs are DFM_DFR[1] through DFM_DFR[m], one per data slice.

[0125] The configuration bus signals DFM_CLT_DS_CFG are DFM_CLT_DS_CFG[1] to DFM_CLT_DS_CFG[m].

[0126] All parallel processed requests are provided to the data path depending on their grouping.

[0127] Each frequency correction request DFR_OUT[k] is actually coupled to all data slices 14 belonging to the kth cluster. i This is achieved by controlling the m output multiplexers (by setting the DFM_CLT_DS_CFG[i] value via each configuration bus).

[0128] Then, a second cross-switch structure 32b can also be used to select the bus DFR_OUT_STB[k], where k ranges from 1 to p, the purpose of which is to independently mark new requests (i.e., frequency corrections) as available from 1 to p, receive DFR_OUT_STB[1] to DFR_OUT_STB[p] in parallel as inputs, and output DFM_DFR_STB[1] to DFM_DFR_STB[m].

[0129] The datapath services are configurable via the configuration bus settings DFM_CLT_DS_CFG and the configuration manager 33, which respectively set: which datapaths the crossbar switch 32 (including the strobe signal) connects to the assigned processed requests DFR_OUT (this depends on which datapaths belong to the group or cluster); this information is given in the DFM_CLT_DS_CFG[i] settings, one per data slice, and which is also an input to the configuration manager 33; and which datapaths are enabled in each group request processing block (so as to ignore acknowledgement signals from datapaths that do not belong to the group or cluster). This information is given in the active slice signal DFM_DS_ACT[k], one per cluster.

[0130] Therefore, the configuration manager 33 is configured to indicate the signal DFM_DS_ACT[k] to indicate for each cluster which transmitter is active based on the setting signal DFM_CLT_DS_CFG, which indicates that each transmitter or data slice 14 i belongs to which cluster and indicates which transmitter is enabled based on the setting signal DFM_DS_EN.

[0131] Figure 7 is a time diagram showing an example of a multi-clock domain handshake protocol according to the handshake protocol implemented by the digital frequency correction module 30, i.e., the transitions of some of the signals described so far. The time t is expressed in arbitrary units. It refers to an example where a cluster includes two data slices (i.e., two transmitters T1 and T2).

[0132] The signals are, from top to bottom, the frequency correction DFR signal from the core 50 to the module 30 and its selection signal DFR_STB, the confirmation signal DFM_DFR_ACK from the cluster group digital frequency correction module 31 to the core 50, the confirmation signals DS_DFR_ACK[1] and DS_DFR_ACK[2] of each data slice, the frequency correction request selection signals DFM_DFR_STB[1] and DFM_DFR_STB[2] of each data slice, and the frequency correction DFM_DFR[1] and DFM_DFR[2]. The columns of values ​​near the labels indicate their initial or initialized logical values. The initialization value of DFR_STB in the figure is 0, which is different from the 1 at the beginning of the enlarged figure.

[0133] The frequency correction DFR signal is set to a value, for example, correction value DFRV1 (DFRV k, k=1, there is only one cluster in this example), and the frequency correction selection signal DFR_STB is set to 1 (i.e., effective). At a second time t2=500, the two confirmation signals DS_DFR_ACK[1] and DS_DFR_ACK[2] fail (the synchronization in this figure may not be consistent with the actual situation and is irrelevant at this point in the timeline). They are pre-initialized as effective signals. Their failure drives the effectiveness of the selection signals DFM_DFR_STB[1] and DFM_DFR_STB[2] at a third time t3=503a.u., at which time the frequency correction DFM_DFR is sent to the two data slices by sending the correction value DFRV1 in the requests DFM_DFR[1] and DFM_DFR[2] of the data slices i=1 and 2. More generally, the latest failure between the acknowledgement signals DS_DFR_ACK[1] and DS_DFR_ACK[2] drives the assertion of the frequency correction request strobe signals DFM_DFR_STB[1] and DFM_DFR_STB[2] for each data slice. These assertions are always synchronized with each other and with the initial transitions of the correction values ​​DFRV1 held in the requests DFM_DFR[1] and DFM_DFR[2], since these transitions share the same cluster clock DFM_CLK[1]. Therefore, the corresponding transmitter handshake modules HS1 and HS2 must react so that their Sigma-Delta converters SM1 and SM2 modify the inputs to add the correction value DFRV1 to the divider average nominal value ND of the dividers FD1 and FD2 of their PLL loops PL1 and PL2. Then, at two subsequent (due to clock asynchrony) times t3 (504 a.u.) and t4 (506 a.u.), the acknowledgement signals DS_DFR_ACK[1] and DS_DFR_ACK[2] for each data slice are issued, and then later (due to block 3114 kThe confirmation signal DFM_DFR_ACK to the core 50 is asserted (i.e., set to logic 1) at time t5 due to the delay of resynchronization of the confirmation signal DS_DFR_ACK at the core 50, and due to the asynchronous cluster clock DFM_CLK[1] relative to the transition of the confirmation signal DS_DFR_ACK, so that if a new phase error PE is detected, the digital core 50 can send a new frequency correction. In particular, if the confirmation DFM_DFR_ACK to the core is asserted, the core 50 can invalidate its own frequency correction request strobe DFR_STB (i.e., from the core 50 to the DFM 30) to prepare for sending a new request, and as a more stringent requirement, a new request can be sent by raising its own frequency correction request strobe DFR_STB after the confirmation DFM_DFR_ACK is invalidated. The invalidation of the frequency correction request strobe DFR_STB is driving the invalidation of the confirmation DFM_DFR_ACK to the core. At time t5 (509 a.u.), the frequency correction signals DFM_DFR[1] and DFM_DFR[2] and the frequency correction request strobe signals DFM_DFR_STB[1] and DFM_DFR_STB[2] are deactivated, i.e., are set back to logic 0 (which means that the DFM handshake module 3113 k The output signals DFR_OUT[k] and DFR_OUT_STB[k] have been invalidated. k The blocks share the same cluster clock DFM_CLK[1] (i.e., the same transitions), so these failures can be synchronized with the assertion of the acknowledgement DFM_DFR_ACK to the core. At a later time, the enable signal DFR_STB (t6=512 a.u.) is also set to 0, and then finally (at t7=515 a.u.), the acknowledgement signal DFM_DFR_ACK is set back to logic 0. The data slices or transmitters 141 and 142 maintain their acknowledgement signals DS_DFR_ACK[1] and DS_DFR_ACK[2] for the programming cycle number CY. Then, even if there is no correction value DFRV, i.e., DFRV=0 (DFRV1 in the figure), their latest failures drive the enable pulses DFM_DFR_STB_1 and DFM_DFR_STB_2 to assert, thereby reaffirming the validation / invalidation protocol between the data slice and the module 30 (for DPR_MODE=0, reaffirming the enable).

[0134] Figure 8 The configuration manager 33 shown in FIG. 1 is a logic block that operates to output such an active slice setting DFM_DS_ACT based on the configuration bus setting DFM_CLT_DS_CFG, which is configured by a one hot converter (HC) 331 (see Figure 8) is converted in the conversion matrix DS_CFG and passed to the configuration block 332, which generates the cluster configuration setting CLT_CFG, which is ANDed with the data slice enable setting DFM_DS_EN from the mapping register 34 in the logic block 333, and the mapping register indicates which data slices DS are enabled.

[0135] The purpose of the configuration manager 33 is to convert the format of the input numbers so that such numbers per data slice are compatible with the AND operation for each cluster. Therefore, the unsigned input numbers are first converted to one-hot representation output numbers at one-hot converter 331, one number per data slice; then, the m×p matrix DS_CFG (the matrix is ​​built row by row with m one-hot numbers, one per data slice, each number having a width of p bits) is passed through block 332, which simply reads the matrix DS_CFG column by column, emitting p numbers with a width of m bits. The AND for each cluster (there are p AND operators) operates across an m-bit width bus, i.e., for cluster k, it performs an AND between the first bit of CLT_CFG[k] and the first bit of DFM_DS_EN, and so on, until the mth bit.

[0136] Regarding the handshake procedure implemented by the DFR 30, the digital frequency correction module 30 operates by default in a so-called "continuous mode" option (DPR_MODE[k]=0 for each k index from 1 to p) so as to repeatedly gate the request, e.g., for each cluster, to the data slice 14. i , DFR_OUT[k], DFR_OUT_STB[k], thereby processing the requested frequency update. For any cluster, this repetition continues until a new frequency update request DFR[k], DFR_STB[k] is gated from the core 50 to the DFM 30. Since the repetition of such a request (e.g., DFR_OUT[k], DFR_OUT_STB[k]) from the digital frequency correction module 30 to the data slice implies that the data slice acknowledgment (e.g., DS_ACK[i]) is also repeated, only the first repetition is monitored to detect the latest acknowledgment in the data slice acknowledgment DS_ACK[i] and sent to the digital core 50 as the acknowledgment DFM_DFR_ACK[k]. Alternatively, when DPR_MODE[k]=1 for each k index, the digital frequency correction module 30 operates in the "One-Shot" mode option, which means that it does not repeat the request DFR_OUT[k], DFR_OUT_STB[k] to the data slice 14 i, thus the phase updates associated with the DFR[k] stage integration are processed over the number of data slice clock cycles CY that are programmed in the data slice register map 34. Completely independent DPR_MODE[k] settings allow for maximum flexibility.

[0137] It should be emphasized that by assigning the same number of data slice clock cycles CY to all data slices or transmitters in a cluster, it can be ensured that the phase accumulation of each transmitter or data slice of the same cluster is not arbitrary, but depends on the value of the frequency correction DFRV or update and its time length (i.e., the number of cycles CY). Otherwise, since each cluster only extracts one PLL divided clock (e.g., TC m ), and it represents only one transmitter in the data slice in the cluster (i.e., 14 m ), and since the frequency correction DFR[k] is commanded to update all frequencies of all data slices in the cluster according to the phase error PE detected by the phase detector 55k, there is a risk that other data slices that do not form a closed loop with the FIFO 13 write clock (actually there is only one phase detector 55k) will accumulate arbitrary phase shifts during the application of the command due to the independence between the Sigma-Delta modulator clocks. In the long run, the accumulation of these arbitrary phase shifts will lead to the fact that the data slices in the cluster that have not passed the phase detector 55k will accumulate arbitrary phase shifts during the application of the command. k Phase drift of the closed loop data slice. With regard to a unique FIFO 13 write clock, even for a closed loop that can be used for each data slice, and the FIFO 13 read clock corresponds to only one correspondingly selected PLL low-frequency clock TC m As long as frequency type correction is involved, arbitrary phase shifts will still be possible without the need for the CY cycle number counting feature, since the Sigma-Delta modulators clock the commands independently (i.e. asynchronously). m Reading data from FIFO 13 may result in bus B i With transmitter 14 i where i ranges from 1 to m-1 (value m of index i is excluded because it is aligned to read FIFO 13).

[0138] Therefore, the transmitter handshake module HS i is configured in a mode to ensure that the Sigma-Delta modulator SM iThe frequency correction DFRV (i.e., ND+DFRV) applied at the input is equal for all transmitters or data slices of the same cluster. Furthermore, the DFM 30 reiterates the same request DFR_OUT[k] with the same correction value DFRVk until a new erroneous PE is detected by the detector 55k. Then, the Sigma-Delta modulators in the same cluster are connected to the DFM 30 (i.e., the relevant cluster DFM module 311). k ) ensures that the reaffirmation of the correction value is applied only when all Sigma-Delta modulators have completed cycle CY. Without handshaking, this would not be possible, since the clock transitions of the different Sigma-Delta modulators in the cluster are independent.

[0139] According to this view, it is important to emphasize that handshake does not need to be performed between the kth cluster and the cluster DFM 311 k The same choice is made between the reference clocks CSC, CSA, CSF, because in practice it ensures that the communication works even if there are different clock domains. However, for the kth cluster and the cluster DFM 311 k Selecting the same reference clock can minimize the difference.

[0140] Despite this minimization, the clock domains are not reduced to one domain for cluster k, since each Sigma-Delta modulator has its own clock domain. This is why the number of cycles CY is counted. Although the clock of each Sigma-Delta modulator as an average period is equal to the period of the PLL reference clock Tx_REF_CLK (e.g., k), due to the modulation of the Sigma-Delta clock, two observed periods without averaging are different, which is why each data slice will undergo arbitrary phase accumulation if not controlled in the above manner.

[0141] Therefore, the DFM 30 operates asynchronously on both sides and for each cluster, ie, for each cluster on the data slice side, there is a sigma modulator SM i clock domain, while on the core 50 side, there is a clock domain used to assert / disable the frequency correction request strobe DFR_STB[k]; both sides are asynchronous with respect to the cluster clock DFM_CLK[k].

[0142] Therefore, in summary, based on the above, the solution described herein refers to an electronic digital system (e.g., 11), such as a system on a chip including a digital core (e.g., 50) and a serializer deserializer module (e.g., 60). The digital core of the system can basically correspond to the system 11 without the SerDes part.

[0143] Such a digital core (e.g., 50) includes at least one FIFO architecture device (e.g., 13), in particular a FIFO memory, which is written with a write clock (e.g., a recovered clock DRC) and is configured to transmit data on a set of buses (e.g., B1, ..., B2). m ) will be read from the FIFO architecture device (eg, 13) using a read clock (eg, a PLL low frequency divided clock TC m The parallel data read by one of the FIFO architecture devices (e.g., 13) is transmitted to the serializer deserializer module (e.g., 60). As mentioned above, the serializer module 60 can also be viewed as including a group of SerDes, outputting different numbers of serial signals, because a single serialization chain sending a single serial signal can also embody the serializer deserializer module (e.g., 60), that is, this group includes only one element. In general, for m aggregated data buses, there will be m SerDes in the module 60.

[0144] Therefore, the serializer / deserializer module (eg, 60) is configured to transmit data on a set of buses (eg, B1, . . . , B m ) reads data from the FIFO architecture device (e.g., 13) as a corresponding set of transmitters (e.g., 141, ..., 14 m ) corresponding to a set of serial signals (e.g., T1,…,T m ) for transmission, this set of serial signals (for example, T1,…,T m ) and a corresponding set of transmitters (e.g., 141,…,14 m ) according to one or more groups or clusters (e.g., CLT k ) are logically grouped, the one or more groups or clusters specifically corresponding to one or more groups of buses (e.g., B1, ..., B m ). Different grouping choices can be performed, for example, a SerDes can contain only one cluster or only one transmitter or SerDes. It is important to point out that if there are more clusters, a transmitter can only belong to one cluster, which is the reason behind configuring the one-hot symbol.

[0145] This group of transmitters (e.g., 141,…,14 m ) includes corresponding independent PLL circuits (e.g., PL1, ..., PL m ), the PLL circuit uses a cluster transmitter reference clock (eg, the transmitter (eg, 141, ..., 14 m , for example, Tx_Ref_Clock shared by transmitters in the same cluster) is used as a reference to emit corresponding PLL clock signals and corresponding external low-frequency (especially divided frequency) clocks (for example, TC1, ..., TC m), controlling the transmitter (e.g., 141, ..., 14 m ) operation (particularly serialization) (e.g., serializer PS i frequency).

[0146] According to the solution described herein, such a system, for example, 11, comprises:

[0147] The digital frequency correction module, indicated at 30 in the exemplary embodiment, is configured to provide each independent PLL circuit (eg, PL1, . . . , PL m ) supplies a data strobe encoding frequency correction signal (e.g., DFM_DFR, DFM_DFR_STB) specifying a command for frequency correction, for example, such as detected by 57k from (particularly by an error detection module (e.g., 55k) included in the digital core (e.g., 50) at a difference between a write clock (e.g., DRC) and a read clock (e.g., TC m ), the read clock corresponds to one of such PLL low frequencies, in particular a divided clock signal, for example, TC1, ..., TC m ;

[0148] The digital frequency correction module 30 includes a corresponding cluster (eg, CLT k ) of one or more cluster digital frequency correction submodules (e.g., 311 k ), clocked by a corresponding cluster clock signal (e.g., DFM_CLK[k]), configured to receive and process a corresponding data strobe encoded cluster frequency correction, for example, receiving and processing a request DFR[k], DFR_STB[k] from the core 50 and issuing a request DFR_OUT[k], DFR_OUT_STB[k] to the cluster, and after the crossbar 32, issuing DFM_DFR[i], DFM_DFR_STB[i] for each data slice, each transmitter (e.g., 141, ..., 14 m ) is configured to assert a corresponding acknowledgement signal (e.g., DS_DFR_ACK_i) upon receipt of the data strobe coded cluster frequency correction (e.g., DFM_DFR[k], DFM_DFR_STB[k] signal specifying a command for frequency correction (e.g., DFR)). As described, this is accomplished by the Sigma-Delta modulator SM i The modulator comprises in particular a transmitter handshake module HS for this purpose. i .

[0149] In turn, each cluster digital frequency correction submodule (e.g., 311 k ) includes a handshake module (for example, 3113k ), the handshake module receives a set of confirmation signals (eg, DS_DFR_ACK) on the bus, which are from corresponding transmitters (eg, 141, ..., 14 m ) (in particular, all transmitters, even those not in the cluster, which are ignored by virtue of the active slice signal DFM_DS_ACT[k] setting), these acknowledgement signals are resynchronized with the cluster clock DFM_CLK[k] (i.e., a set of resynchronized acknowledgement signals, e.g., the resynchronization signal DS_DFR_ACK_RES[i]), such a handshake module (e.g., 3113 k ) is configured to be used when the cluster (e.g., CLT k ) of the signal DFM_DS_ACT (e.g., 141, ..., 14 m ) from all especially indicated as handshake module 3113 k After receiving a set of failed resynchronization confirmation signals for resynchronization, the active transmitter sends a command to the corresponding cluster transmitter (for example, 141, ..., 14 m ) of the frequency correction of the data strobe encoding frequency correction signal (e.g., DFR_OUT[k], DFR_OUT_STB[k]), in other words, each cluster digital frequency correction submodule (such as 311 k ) receives the full set of signals DS_DFR_ACK, so that the setting of the signal DFM_DS_ACT[k] relative to the k-th cluster allows only the CLT specific to the k-th cluster to be considered k A subset of a set of signals DS_DFR_ACK - the transmitters 141, ..., 14 m Or the data slice is configured to be in the corresponding cluster (for example, CLT k ) of all independent PLL circuits PL1,…,PL m The frequency (e.g., HF1,…,HF m ) to complete a certain number (especially CY) of frequency correction cycles (for example, ND+DFR, especially ND+DFRV k ), the confirmation signal is disabled, that is, sent by the transmitter and in the handshake module (for example, 3113 k ) is resynchronized as the confirmation signal DS_DFR_ACK of DS_DFR_ACK_RES[i].

[0150] In addition, the transmitters of the cluster (e.g., 141, ..., 14 m) are programmable with the same number of cycles (e.g., CY), and they are configured to maintain power from all enabled transmitters (e.g., 141, ..., 14 m )’s corresponding confirmation signal (e.g., DS_DFR_ACK) takes effect.

[0151] In addition, the handshake module (for example, 3113 k ) is configured to repeatedly send the validated data strobe coding frequency correction signal (e.g., DFR_OUT[k], DFR_OUT_STB[k]) to command the corresponding cluster transmitters (e.g., 141, ..., 14 m ) frequency correction.

[0152] In addition, the handshake module (for example, 3113 k ) may alternatively be configured to send the data strobe coding frequency correction signal (eg, DFR_OUT[k], DFR_OUT_STB[k]) validated once to command the corresponding cluster transmitters (eg, 141, ..., 14 m ) of the transmitter, the transmitter performing frequency correction over the programmed number of cycles (e.g., CY).

[0153] In addition, in the slave cluster (e.g., CLT k ) of all enabled transmitters (e.g., 141,…,14 m ) receives the set of valid confirmation signals (e.g., DS_DFR_ACK), confirms the corresponding cluster (e.g., CLT k ) of all independent PLL circuits (e.g., PL1, ..., PL m ) performs frequency correction (e.g., ND+DFR) at the frequency, the handshake module (e.g., 3113 k ) is configured to also implement a handshake communication protocol with the digital core module (e.g., 50), the digital core module sending the frequency correction (e.g., DFR obtained by 57k from the detected phase error (e.g., PE)) to the handshake module (e.g., 3113 k ), sends a corresponding cluster frequency correction confirmation signal (e.g., DFM_DFR_ACK[k]) to the core module (e.g., 50), and the cluster frequency correction submodule confirmation signal (e.g., DFM_DFR_ACK[k]) enables the core (e.g., 50) to send the next frequency correction (e.g., DFR).

[0154] As mentioned above, another aspect relates to implementing the PLL circuit (eg, PL1, ..., PLm ), the fractional Sigma-Delta PLL circuit includes a corresponding Sigma-Delta modulator (e.g., SM1, ..., SM m ), the modulator includes a corresponding handshake module HS i , the handshake module HS i The Sigma-Delta modulator SM is configured to receive the data strobe encoded data slice frequency correction DFM_DFR[i], DFM_DFR_STB[i] signal of the command frequency correction DFRV. i is configured to modify its input (particularly with respect to said cycle number (CY)) with said frequency correction DFRV, either repeatedly or non-repeatedly, in particular, a Sigma-Delta modulator SM i is configured to modify its input with the frequency correction DFRV, in particular as a result, the Sigma-Delta modulator SM i The modified integer division ratio pseudo-random sequence is output to the PLL circuit PL1, ..., PL m The corresponding PLL loop PL i , for example, to the loop divider FD i Sends a modified sequence of integer values ​​whose average value corresponds to the nominal value ND added to the frequency correction DFRV, this sum being the Sigma-Delta modulator SM i The average effect of the operation, the sequence of integer values ​​is received in the data slice frequency correction DFM_DFR[i], DFM_DFR_STB[i] signal of the data strobe encoding that commands frequency correction.

[0155] In addition, the frequency correction submodule 311 k May include synchronizer 3114 k , used to synchronize the group, especially the confirmation signal DS_DFR_ACK on the bus, with a cluster clock signal (for example, a cluster clock signal selected from a group of clocks (for example, CSF, CSA, CSC)).

[0156] Another synchronizer (e.g., 3111 k ) is used to synchronize the frequency correction signals DFR[k], DFR_STB[k] sent from the digital core 50 with the cluster clock signal (for example, the cluster clock signal selected in the clock groups CSF, CSA, CSC), especially to synchronize the selection pulses of the frequency correction signals DFR[k], DFR_STB[k].

[0157] It should be emphasized that the gap insertion is usually not set, but derived by the handshake protocol based on the cycle number CY, that is, when the latest confirmation signal DS_DFR_ACK[i] expires the cycle number CY, it fails, and this will drive all the strobe pulses DFM_DFR_STB[i] in the cluster to be valid. Since the cycle number is much higher than 1, each validation is separated from the previous failure of the strobe DFM_DFR_STB[i] by a long time gap, with a minimum of 128 cycles. These corresponding strobe DFM_DFR_STB[i] validations in turn drive the confirmation signal DS_DFR_ACK[i] to be newly valid (only a few cycles after its previous failure).

[0158] From the above description, the advantages of the solution are evident.

[0159] The solution described here can reduce area consumption because the digital frequency correction block serves all data paths instead of having phase interpolators dedicated to the paths.

[0160] Furthermore, the solution described here can reduce power consumption because the digital frequency correction block is a low-frequency digital block. The phase interpolator manages the high-speed clock. This also allows for higher data rates and lower complexity. Therefore, the solution described here saves costs due to lower area and power consumption.

[0161] Furthermore, the solution described in this paper minimizes latency with low complexity. The digital frequency correction block receives input from only one detection loop, while each phase interpolator is controlled by a dedicated data path loop.

[0162] Furthermore, the solution determines negligible additional noise injection.

[0163] Furthermore, the solution described herein allows frequency and phase updates to be intrinsically managed.

[0164] Solutions using phase interpolators are subject to system nonlinearity errors due to the inherent nonlinear behavior of interpolation. This error, also known as integral nonlinearity, can compromise the overall bit error rate performance, especially for higher data rate SerDes devices.

[0165] The solution proposed here instead relies on frequency correction evaluated by closed-loop control, which is targeted at only one data path and applied to all data paths. In this solution, unexpected behavior may occur when a series of frequency correction commands are applied to many PLLs at possibly different times and for different durations, resulting in PLL independent phase shifts that may accumulate into unbounded phase differences between PLLs. In order to ensure bounded phase differences between PLLs, the frequency command duration is controlled and common to all PLLs (i.e., controlled phase shifts), and another mechanism (such as the handshake proposed here) is adopted. Ensuring a bounded phase difference allows data consistency to be maintained between the data read and write ports of the FIFO architecture in the digital core. This data consistency allows reading aggregated data, i.e., data aggregated into clusters for consistency.

[0166] The digital frequency correction module with its clock domain for each cluster (e.g. DFM_CLK[k]) is able to use the clock to raise the strobe from the core (e.g. DFR_STB(k)) and to use the clock adopted to clock the Sigma-Delta modulator to engage the asynchronous subsystem (which in turn comprises many clock subdomains, due to the independent transitions of the different Sigma-Delta modulator clocks of the clusters). For the clock domain to raise the strobe from the core (e.g. DFR_STB(k)), it can be based on a recovered clock (e.g. DRC) or another clock local to the digital core 50. In any case, the digital frequency correction module according to the described solution is able to engage these asynchronous domains, regardless of their exact frequencies, in particular through the handshaking mechanism of the strobe / acknowledgement on both sides (the first on the core interface and the second on the data slice, or transmitter, Sigma-Delta interface).

[0167] Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what is described merely by way of example, without departing from the scope of protection.

[0168] The solution described here can be used with any number of transmitters at the SerDes output.

[0169] High speed and high data rate generally refer to speeds and data rates at which the above problems can be determined and solved by the present solution. In this example, a Gbit / s data rate is indicated, but the solution is not limited to this range and can of course also be used at lower data rates.

[0170] The claims are an integral part of the technical disclosure of the embodiments provided herein.

[0171] The scope of protection is defined by the appended claims.

Claims

1. An electronic digital system comprising: Digital Core; Serializer-deserializer module; The digital core includes a first-in-first-out FIFO architecture device that is written to with a write clock on a set of buses to the serializer deserializer module and is configured to transmit parallel data and read from the FIFO architecture device with a read clock; The serializer-deserializer module is configured to transmit the data read from the FIFO architecture device as a corresponding set of serial signals transmitted by a corresponding set of transmitters, the set of serial signals and the corresponding set of transmitters being logically grouped according to one or more groups or clusters corresponding to one or more groups of the bus; The set of transmitters includes corresponding independent phase-locked loop (PLL) circuits, which use a cluster transmitter reference clock common to the cluster of corresponding transmitters as a reference to emit corresponding PLL clock signals and a set of low-frequency clock signals obtained by frequency division of the PLL clock signals, wherein the cluster transmitter reference clock controls the frequency of the serialized operation of the transmitters; a digital frequency correction module configured to supply a data strobe encoded frequency correction signal to each independent PLL circuit, the data strobe encoded frequency correction signal specifying a frequency correction depending on a phase error detected between the write clock and the read clock corresponding to one of the PLL low frequency clock signals; The digital frequency correction module comprises one or more cluster digital frequency correction submodules, each cluster digital frequency correction submodule corresponding to a respective cluster, being clocked by a respective cluster clock signal corresponding to the cluster transmitter reference clock, being configured to receive and process a respective data strobe coded cluster frequency correction including the frequency correction obtained from the detected phase error, output a respective correction signal, and obtain a data strobe coded frequency correction signal for each of the transmitters from the respective correction signal by demultiplexing; wherein each of said transmitters is configured to: assert a corresponding acknowledgement signal upon receipt of said corresponding data strobe encoded frequency correction signal specifying a frequency correction; Each cluster digital frequency correction submodule includes a handshake module, which receives a set of confirmation signals issued by the transmitters of the cluster, and the confirmation signals are resynchronized with the cluster clock signal. The handshake module is configured to issue the output data selection code frequency correction signal that is asserted to specify the frequency correction of the corresponding transmitter after receiving a set of de-assertion confirmation signals resynchronized with the cluster clock signal from all enabled transmitters of the cluster, and the transmitter is configured to de-assert the confirmation signal after completing a certain number of cycles of frequency correction of the frequencies of all independent PLL circuits of the corresponding cluster.

2. The system of claim 1, wherein the frequency correction is obtained from a detected phase error detected by an error detection module included in the digital core.

3. The system of claim 1, wherein the transmitters of a cluster are programmable for the same number of cycles and are configured to maintain the respective acknowledgement signals from all enabled transmitters asserted for a duration corresponding to the number of cycles.

4. The system of claim 1, wherein the handshake module is configured to repeatedly transmit the data strobe encoded frequency correction signal asserted to specify frequency correction of the transmitters of a cluster.

5. The system of claim 1 , wherein the handshake module is configured to send the data strobe encoded frequency correction signal asserted once to specify frequency correction of the corresponding transmitter, the transmitter performing the frequency correction over the programmed number of cycles.

6. The system of claim 1 , wherein upon receiving the set of asserted resynchronization confirmation signals from all enabled transmitters of the cluster, confirming that frequency correction is performed on the frequencies of all independent PLL circuits of the corresponding cluster, the handshake module is configured to also implement a handshake communication protocol with the digital core module, the digital core module sends the frequency correction obtained based on the detected phase error to the cluster digital frequency correction submodule, the handshake module sends a corresponding cluster frequency correction confirmation signal to the core module, and the cluster frequency correction submodule confirmation signal enables the core to send the next frequency correction.

7. The system of claim 1, wherein the write clock is a recovered clock signal recovered from data received upstream from the FIFO architecture device.

8. The system of claim 1 , wherein the PLL circuit is implemented by a fractional Sigma-Delta PLL circuit, the fractional Sigma-Delta PLL circuit comprising a corresponding Sigma-Delta modulator, the Sigma-Delta modulator comprising a corresponding handshake module, the handshake module being configured to receive the data strobe encoded frequency correction signal specifying a frequency correction for each of the transmitters, the Sigma-Delta modulator being configured to modify its input with the frequency correction, in particular for the number of cycles, either repeatedly or non-repeatedly.

9. The system of claim 1, wherein each of the frequency correction submodules comprises a synchronizer to synchronize the set of acknowledgement signals with the cluster clock signal.

10. The system of claim 1, wherein each of the frequency correction submodules further comprises a synchronizer to synchronize the frequency correction signal from the digital core with the cluster clock signal by synchronizing the gating of the frequency correction signal.

11. The system of claim 1, wherein each of the frequency correction submodules comprises a filter that filters the resynchronized frequency correction signal before entering the handshake module.

12. The system of claim 1 , wherein the set of cluster digital frequency correction submodules is configured to send data strobe encoding output signals to a cluster-to-logic data slice crossbar switch, the crossbar switch being configured to, under the control of a configuration bus signal, issue the data strobe encoding frequency correction request signal to the transmitter based on the grouping of the transmitter, the configuration bus signal indicating to which cluster each data slice belongs, the configuration bus signal being issued by the register map, the register map being particularly programmable.

13. The system of claim 1, wherein the digital frequency correction module comprises a mapping register module, the groupings in the clusters being stored in the mapping register module.

14. The system of claim 1, wherein the phase error is supplied as a frequency correction between these signals by a proportional-integral phase correction module that applies a proportional-integral correction with the phase error as input, then differentiates, and issues the data strobe encoded frequency correction signal.

15. The system of claim 1, wherein the digital frequency correction module includes a configuration manager configured to indicate which transmitter is active for each cluster based on a setup signal indicating which cluster each transmitter belongs to and based on a setup signal indicating which transmitter is enabled.

16. The system of claim 1, wherein the transmitter reference clock is selected from a set of available clock signals, and the cluster digital frequency correction submodule is clocked by a clock selected from the set of available clock signals that corresponds to the transmitter reference clock selected for the corresponding cluster.

17. A serializer deserializer module configured to receive parallel data read from a first-in-first-out FIFO architecture device with a read clock on a set of buses to the serializer deserializer module; wherein the serializer-deserializer module is configured to transmit the data read from the FIFO architecture device over a set of buses as a set of corresponding serial signals transmitted by a set of corresponding transmitters, the set of serial signals and the corresponding transmitters being logically grouped according to one or more groups or clusters corresponding to one or more groups of the buses; The set of transmitters includes corresponding independent PLL circuits, which use a cluster transmitter reference clock common to the cluster of corresponding transmitters as a reference to emit corresponding PLL clock signals and a set of low-frequency clock signals obtained by dividing the PLL clock signals, wherein the cluster transmitter reference clock controls the frequency of the serialized operation of the transmitters; and Wherein the SerDes module is configured to operate in the system according to claim 1.

18. A method for controlling the system according to claim 1, comprising: supplying a data strobe encoded frequency correction signal to each independent PLL circuit, the data strobe encoded frequency correction signal specifying a frequency correction obtained based on a detected phase error between the write clock and the read clock, the read clock corresponding to one of the PLL low frequency clock signals; performing receiving and processing a corresponding data strobe encoded cluster frequency correction at a corresponding one or more cluster digital frequency correction submodules corresponding to a corresponding cluster, and also receiving a corresponding clock signal, in particular a transmitter reference clock selected for said corresponding cluster; asserting a corresponding acknowledgement signal at each of said transmitters when said data strobe encoded frequency correction signal specifying a frequency correction is received; as well as At the corresponding one or more cluster digital frequency correction submodules, a set of confirmation signals, in particular a bus, for resynchronizing the cluster clock signal through all enabled transmitters of the cluster is received, and after receiving a set of de-asserted confirmation signals for resynchronization from all enabled transmitters of the cluster, the data-select encoded cluster frequency correction signal that is asserted to command frequency correction of the corresponding cluster transmitter is issued, and the confirmation signal is de-asserted after a certain number of cycles of frequency correction of the frequencies of all independent PLL circuits of the corresponding cluster are completed.

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