SOC chip clock calibration method based on 2.4 GHz signal in air

Abstract

The invention discloses an SOC chip clock calibration method based on an air 2.4 GHz signal, and belongs to the technical field of chip clock calibration. The SOC chip clock calibration method based on the air 2.4 GHz signal comprises the following specific steps: step 1, 2.4 GHz signal receiving and preprocessing: adopting a miniaturized ceramic patch antenna, and using an integrated LNA (low noise amplifier) to amplify the signal to be more than-20dBm, the noise coefficient is less than or equal to 3dB, the 2.4 GHz carrier wave is down-converted to a base band through an orthogonal frequency mixer, and mirror image interference is inhibited through a 10MHz low-pass filter. According to the method, SOC chip clock calibration is carried out through 2.4 GHz signals, external crystal oscillator design is not needed, clock synchronization is achieved completely depending on air wireless signals, meanwhile, multi-protocol compatibility is tested, 2.4 GHz protocols such as Wi-Fi 802.11 b / g / n, Bluetooth 5.0 and ZigBee are supported, and the calibration period and the compensation strategy are automatically adjusted according to signal quality.

Description

Technical Field

[0001] The invention belongs to the technical field of chip clock calibration, and in particular relates to a SOC chip clock calibration method based on an air 2.4 GHz signal. Background Art

[0002] SOC chip clock calibration refers to the process of adjusting the clock frequency or phase inside the system-on-a-chip through specific technical means to achieve the design target or synchronize with the external reference signal. This technology is crucial to ensure the timing consistency and performance stability of various chip modules (such as CPU, wireless communication, peripheral interfaces, etc.).

[0003] The limitations of traditional clock calibration methods include: reliance on external crystal oscillators or temperature-compensated crystal oscillators (TCXOs), which increases system cost and volume; crystal oscillators are easily affected by environmental factors such as temperature and voltage, resulting in frequency drift; additional circuit compensation is required in complex scenarios, and SOC integration is reduced; at the same time, calibration methods based on wired reference signals are not suitable for wireless terminal devices; traditional wireless calibration methods have problems such as high power consumption and response delay. Summary of the invention

[0004] The technical problem to be solved by the present invention is to overcome the disadvantages of the above-mentioned prior art and provide a SOC chip clock calibration method based on an air 2.4 GHz signal.

[0005] The technical solution adopted to solve the above technical problems is: a SOC chip clock calibration method based on an air 2.4GHz signal, including the following specific steps: Step 1: 2.4GHz signal reception and preprocessing: Adopt miniaturized ceramic patch antenna, use integrated LNA (low noise amplifier) ​​to amplify the signal to above -20dBm, with noise figure ≤3dB, down-convert 2.4GHz carrier to baseband through orthogonal mixer, and suppress image interference through 10MHz low-pass filter; Step 2: Timestamp extraction and synchronization sequence detection: Use sliding correlator to match the preamble and output the peak position , calculate the signal propagation delay and correct the timestamp; Step 3: Phase error calculation and frequency deviation estimation: Establish a phase model, generate the clock phase by DCO, reference signal phase, and then calculate the phase error; Step 4: Adaptive clock frequency adjustment: The PID control algorithm is used for adjustment, and the constraint condition is that the frequency after adjustment must meet ; Calculate the signal-to-noise ratio through the received signal strength indication and perform SNR detection; Step 5: Anti-interference and robustness enhancement: The signal strength is converted into linear power, the phase error is integrated, and then the outliers are removed through sliding average filtering; Step 6: Calibration result feedback and verification: Update the DCO control code according to Calculate the DAC value and update the system clock divider parameters synchronously to ensure that the operating frequency of each module is consistent. Then perform calibration accuracy verification, continuously collect 100 sets of calibration data, and calculate the standard deviation of frequency deviation.

[0006] Through the above technical solution, there is no need to rely on an external crystal oscillator or temperature compensated crystal oscillator (TCXO), which reduces system cost and volume, does not cause frequency drift, improves the integration of SOC, and has low power consumption and fast response.

[0007] Furthermore, the step 2 includes: Wi-Fi Beacon frame processing: detect the frame header signature, then parse the MAC address field and extract the Timestamp; Bluetooth advertising packet processing: identifying access address and extracting synchronization word.

[0008] Furthermore, the output peak position in step 2 The following specific formula is used: ; in is the preamble sequence stored locally, N=128 is the sequence length; The timestamp is modified using the following specific formula: Calculate signal propagation delay (d is the sending and receiving distance, c is the speed of light), the corrected timestamp is: .

[0009] Through the above technical solution, the accuracy of the timestamp is greatly improved and errors are avoided.

[0010] Furthermore, the clock phase generated by the DCO in step 3 is: ; The reference signal phase is: ,in is the carrier frequency; The phase error is calculated using the following formula: In timestamp The phase error at is: ; By calibrating the time stamp on both sides and Calculate the frequency deviation: .

[0011] Furthermore, the frequency update formula of the PID control algorithm in step 4 is: , in, , , .

[0012] Furthermore, the SNR detection adopts the following formula: ; Where B=20MHz is the channel bandwidth.

[0013] Furthermore, the linear power conversion formula is as follows: ; in is the signal strength.

[0014] Furthermore, the frequency deviation standard deviation in step 6 adopts the following formula: ; Test Results .

[0015] Through the above technical solution, anti-interference calibration can be achieved through signal quality monitoring, greatly improving the overall accuracy.

[0016] The beneficial effects of the present invention are as follows: the present invention performs SOC chip clock calibration through 2.4GHz signals without the need for external crystal oscillator design, and completely relies on air wireless signals to achieve clock synchronization. At the same time, it experiments with multi-protocol compatibility: supports 2.4GHz protocols such as Wi-Fi802.11b / g / n, Bluetooth 5.0, ZigBee, and automatically adjusts the calibration cycle and compensation strategy according to the signal quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a flow chart of the present invention. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0019] like Figure 1As shown, the SOC chip clock calibration method based on the air 2.4 GHz signal of this embodiment includes the following specific steps: Step 1: 2.4GHz signal reception and preprocessing: Adopt miniaturized ceramic patch antenna, use integrated LNA (low noise amplifier) ​​to amplify the signal to above -20dBm, with noise figure ≤3dB, down-convert 2.4GHz carrier to baseband through orthogonal mixer, and suppress image interference through 10MHz low-pass filter; Step 2: Timestamp extraction and synchronization sequence detection: Use sliding correlator to match the preamble and output the peak position , calculate the signal propagation delay and correct the timestamp; Step 3: Phase error calculation and frequency deviation estimation: Establish a phase model, generate the clock phase by DCO, reference signal phase, and then calculate the phase error; Step 4: Adaptive clock frequency adjustment: The PID control algorithm is used for adjustment, and the constraint condition is that the frequency after adjustment must meet ; Calculate the signal-to-noise ratio through the received signal strength indication and perform SNR detection; Step 5: Anti-interference and robustness enhancement: The signal strength is converted into linear power, the phase error is integrated, and then the outliers are removed through sliding average filtering; Step 6: Calibration result feedback and verification: Update the DCO control code according to Calculate the DAC value and synchronously update the system clock divider parameters to ensure that the operating frequency of each module is consistent. Then perform calibration accuracy verification, continuously collect 100 sets of calibration data, and calculate the standard deviation of frequency deviation. There is no need to rely on an external crystal oscillator or temperature compensated crystal oscillator (TCXO), which reduces system cost and volume, does not cause frequency drift, and improves the integration of SOC. At the same time, it has low power consumption and fast response.

[0020] The second step comprises: Wi-Fi Beacon frame processing: detect the frame header signature, then parse the MAC address field and extract the Timestamp; Bluetooth advertising packet processing: identifying access address and extracting synchronization word.

[0021] The output peak position in step 2 The following specific formula is used: ; in is the preamble sequence stored locally, N=128 is the sequence length; The timestamp is modified using the following specific formula: Calculate signal propagation delay (d is the sending and receiving distance, c is the speed of light), the corrected timestamp is: ; Greatly improves the accuracy of timestamp and avoids errors.

[0022] The clock phase generated by the DCO in step 3 is:

[0023] The reference signal phase is: ,in is the carrier frequency; The phase error is calculated using the following formula: In timestamp The phase error at is: ; By calibrating the time stamp on both sides and Calculate the frequency deviation: .

[0024] The frequency update formula of the PID control algorithm in step 4 is: ; in, , , .

[0025] The SNR detection adopts the following formula: ; Where B=20MHz is the channel bandwidth.

[0026] The linear power conversion formula is as follows: ; in is the signal strength.

[0027] The frequency deviation standard deviation in step 6 adopts the following formula: ; Test Results , anti-interference calibration can be achieved through signal quality monitoring, greatly improving the overall accuracy.

[0028] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention.

Claims

1. A SOC chip clock calibration method based on 2.4GHz signals in the air, characterized in that: The specific steps include: Step 1: 2.4GHz signal reception and preprocessing: Adopt miniaturized ceramic patch antenna, use integrated LNA to amplify the signal to above -20dBm, noise figure ≤3dB, down-convert 2.4GHz carrier to baseband through orthogonal mixer, and suppress image interference through 10MHz low-pass filter; Step 2: Timestamp extraction and synchronization sequence detection: Use sliding correlator to match the preamble and output the peak position , calculate the signal propagation delay and correct the timestamp; Step 3: Phase error calculation and frequency deviation estimation: Establish a phase model, generate the clock phase by DCO, reference signal phase, and then calculate the phase error; Step 4: Adaptive clock frequency adjustment: The PID control algorithm is used for adjustment, and the constraint condition is that the frequency after adjustment must meet ; Calculate the signal-to-noise ratio through the received signal strength indication and perform SNR detection; Step 5: Anti-interference and robustness enhancement: The signal strength is converted into linear power, the phase error is integrated, and then the outliers are removed through sliding average filtering; Step 6: Calibration result feedback and verification: Update the DCO control code according to Calculate the DAC value and update the system clock divider parameters synchronously to ensure that the operating frequency of each module is consistent. Then perform calibration accuracy verification, continuously collect 100 sets of calibration data, and calculate the standard deviation of frequency deviation.

2. The SOC chip clock calibration method based on the 2.4 GHz signal in the air according to claim 1 is characterized in that: The second step comprises: Wi-Fi Beacon frame processing: detect the frame header signature, then parse the MAC address field and extract the Timestamp; Bluetooth advertising packet processing: identifying access address and extracting synchronization word.

3. The SOC chip clock calibration method based on the 2.4 GHz signal in the air according to claim 1 is characterized in that: The output peak position in step 2 The following specific formula is used: ； in is the preamble sequence stored locally, N=128 is the sequence length; The timestamp is modified using the following specific formula: Calculate signal propagation delay , where d is the sending and receiving distance, c is the speed of light, and the corrected timestamp is: 。 4. The SOC chip clock calibration method based on the 2.4 GHz signal in the air according to claim 1, characterized in that: The clock phase generated by the DCO in step 3 is: ； The reference signal phase is: ,in is the carrier frequency; The phase error is calculated using the following formula: In timestamp The phase error at is: ； By calibrating the time stamp on both sides and Calculate the frequency deviation: 。 5. The SOC chip clock calibration method based on 2.4 GHz signal in the air according to claim 1, characterized in that: The frequency update formula of the PID control algorithm in step 4 is: ,in, , , .

6. The SOC chip clock calibration method based on 2.4 GHz signal in the air according to claim 1, characterized in that: The SNR detection adopts the following formula: ； Where B=20MHz is the channel bandwidth.

7. The SOC chip clock calibration method based on 2.4 GHz signal in the air according to claim 1, characterized in that: The linear power conversion formula is as follows: ； in is the signal strength.

8. The SOC chip clock calibration method based on 2.4 GHz signal in the air according to claim 1, characterized in that: The frequency deviation standard deviation in step 6 adopts the following formula: ； Test Results .

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