IIC communication slave low-power-consumption dormancy digital implementation method

Abstract

The invention discloses an IIC communication slave low-power-consumption dormancy digital implementation method. The method comprises the specific steps that S1, a host sends a control instruction through an IIC communication bus; s2, the IIC decoding unit analyzes the data of the IIC communication bus; the data type is confirmed, and if the data is a sleep instruction, the data is sent to the IIC sleep wake-up control unit; if the instruction is an application control instruction, the data is sent to a system application control unit; meanwhile, setting 1 high level output to control the wake-up decoding unit and the master control unit; the small circuit module has good pit interference performance, false triggering of awakening work during normal work is prevented, and the method adopted by the invention is as follows: during normal work, an awakening small circuit does not participate in decoding work and is in a reset state; the sleep power consumption of the chip digital module can be reduced to the maximum extent, meanwhile, good anti-interference performance and good applicability are achieved, and a system can be effectively made to sleep or awaken.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a low-power sleep digital implementation method for an IIC communication slave. Background Art

[0002] With the popularity of mobile devices, more and more devices rely on battery power. In order to increase the battery life and service life, the power consumption requirements of the chip are getting higher and higher. The low-power design of the corresponding chip puts forward higher requirements, and the low-power design is a difficulty in the digital design of the chip. To this end, the present invention proposes a digital implementation method for low-power sleep of an IIC communication slave, which can make the chip consume extremely low power after entering low-power sleep, thereby improving the battery life and service life. Summary of the invention

[0003] The object of the present invention is to provide a digital implementation method for low-power sleep of an IIC communication slave to solve the problems raised in the above background technology.

[0004] To achieve the above object, the present invention provides the following technical solution: a digital implementation method for low-power sleep of an IIC communication slave, the specific steps comprising: S1: the host sends a control instruction via the IIC communication bus;

[0005] S2: The IIC decoding unit parses the data of the IIC communication bus and confirms the data type. If it is a sleep instruction, the data is sent to the IIC sleep / wake-up control unit; if it is an application control instruction, the data is sent to the system application control unit;

[0006] S3: After receiving the sleep command, the IIC sleep / wake-up control unit notifies the system application control unit to exit the application control to prevent the disorder of application control; at the same time, it sets the high level output control to wake up the decoding unit and the main control unit;

[0007] S4: The output control signal of the IIC sleep / wake-up control unit is the reset control signal of the wake-up decoding unit; when the output control signal is low, the sleep control unit is always in the reset state; when the system is in normal working state, the wake-up decoding unit is in the reset state; when the system enters sleep, the reset signal is set to high level, and the wake-up decoding unit is enabled at this time; it means that the wake-up unit circuit is enabled only after entering sleep; this can effectively reduce the interference of the system;

[0008] S5: When the wake-up decoding unit is reset, the wake-up control unit is controlled to output a high level. When the chip is working normally and not in sleep mode, the wake-up control unit outputs a high level and maintains a high level output. Only when the wake-up decoding unit is in the activated working state and receives a wake-up working instruction, the output is set to a low level.

[0009] S6: Since the wake-up control unit outputs a high level and the IIC sleep\wake-up control unit outputs a high level at this time, the general control unit outputs a high level. When the general control unit is at a high level, the general control unit outputs a signal that is an enable signal for the RC system clock. When the RC system clock is at a high level, the clock is disabled and the clock is turned off. Since there is no clock drive at this time, the flip rate is a low level, thereby reducing the system power consumption. When the slave is in sleep mode, when the host IIC communication bus does not need to wake up the slave, the IIC communication bus communication signal is not flipped at this time, and the wake-up decoding unit is also not clock driven.

[0010] S7: When wake-up is required, the host sends data. At this time, since the wake-up decoding unit is driven by the IIC communication bus, other units are not clock-driven, so only the wake-up decoding unit participates in the decoding work. When the wake-up decoding unit parses the wake-up instruction, it controls the wake-up control unit to a low level;

[0011] S8: is the general control unit of the AND gate controller. Since the wake-up control unit outputs a low level, the general control unit outputs a low level, and the RC system clock starts working at this time;

[0012] S9: Since the RC system clock starts working at this time, the IIC decoding unit is driven by the clock, and can parse the wake-up command sent by the host through the IIC communication bus; after receiving the wake-up command, the IIC sleep\wake-up control unit is controlled to output a low level, reset the wake-up decoding unit, and at the same time output a low level to control the main control unit to output a low level. When the main control unit outputs a low level, the RC system clock is enabled, so that the entire system can work normally.

[0013] Preferably, the overall control unit is an AND gate controller, which means that when the inputs are all at a high level, the output is at a high level.

[0014] Preferably, the RC system clock provides a driving clock for the entire application system, drives the IIC decoding unit to decode data and interact with the host, drives the IIC sleep / wake-up control unit to perform sleep or wake-up control, and can also drive the system application control unit to perform application control.

[0015] Preferably, the wake-up decoding unit is only driven by an IIC communication bus signal.

[0016] Preferably, the system modules used in the method include an RC system clock, an IIC communication bus, an IIC decoding unit, an IIC sleep / wake-up control unit, a wake-up decoding unit, a wake-up control unit, a system application control unit, a total control unit, and a host.

[0017] Compared with the prior art, the beneficial effects of the present invention are as follows: the present invention adopts a simple small circuit module as a clock wake-up module of a complex circuit, monitors the host signal in real time, wakes up the system clock with a simple small circuit module, and adopts a communication signal as a driving clock; the frequency of the communication signal is lower than the system frequency, which brings less power consumption, and this module is only involved in the work when the system is dormant. In addition, after the slave enters dormancy, the host does not need to communicate with the slave for a long time, so the communication signal can be turned off as the driving clock, so that the driving frequency of this simple small circuit module is 0Hz, so that the entire system has no clock drive, which can greatly reduce the power consumption of the system dormancy;

[0018] In addition, the small circuit module of the present invention has good interference resistance, which can prevent the wake-up work from being triggered incorrectly during normal operation. The method adopted by the present invention is that during normal operation, the wake-up small circuit does not participate in the decoding work and is in a reset state; it can minimize the sleep power consumption of the chip digital module, and at the same time has good anti-interference and good applicability, and can effectively put the system to sleep or wake up. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic diagram of the process of the present invention. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] Example 1

[0022] See also Figure 1 , which is the first embodiment of the present invention, and this embodiment provides a technical solution: a digital implementation method for low-power sleep of an IIC communication slave, the specific steps include: S1: the host sends a control instruction through the IIC communication bus;

[0023] S2: The IIC decoding unit parses the data of the IIC communication bus and confirms the data type. If it is a sleep instruction, the data is sent to the IIC sleep / wake-up control unit; if it is an application control instruction, the data is sent to the system application control unit;

[0024] S3: After receiving the sleep command, the IIC sleep / wake-up control unit notifies the system application control unit to exit the application control to prevent the disorder of application control; at the same time, it sets the output control to 1 (high level) to wake up the decoding unit and the main control unit;

[0025] S4: The output control signal of the IIC sleep / wake-up control unit is the reset control signal of the wake-up decoding unit; when the output control signal is 0 (low level), the sleep control unit is always in the reset state; when the system is in normal working state, the wake-up decoding unit is in the reset state; when the system enters sleep, the reset signal is set to 1 (high level), and the wake-up decoding unit is enabled at this time; it means that the wake-up unit circuit is enabled only after entering sleep; this can effectively reduce the interference of the system;

[0026] S5: When the wake-up decoding unit is reset, the wake-up control unit is controlled to output 1 (high level). When the chip is working normally and not in sleep mode, the wake-up control unit outputs 1 (high level); and maintains 1 (high level) output. Only when the wake-up decoding unit is in the activated working state and receives the wake-up working instruction, the output is set to 0 (low level).

[0027] S6: Since the wake-up control unit outputs 1 (high level) and the IIC sleep\wake-up control unit outputs 1 (high level) at this time, the total control unit outputs 1 (high level). When the total control unit is 1 (high level), the RC system clock fails and the clock is turned off; since there is no clock drive at this time, the flip rate is 0 (low level), which reduces the system power consumption; when the slave is dormant, when the host IIC communication bus does not need to wake up the slave, the IIC communication bus communication signal is not flipped at this time, and the wake-up decoding unit is also not clock driven;

[0028] S7: When wake-up is required, the host sends data. At this time, since the wake-up decoding unit is driven by the IIC communication bus, other units are not clock-driven, and only the wake-up decoding unit participates in the decoding work. When the wake-up decoding unit parses the wake-up instruction, the wake-up control unit is controlled to be set to 0 (low level);

[0029] S8: is the general control unit of the AND gate controller. Since the wake-up control unit outputs 0 (low level), the general control unit outputs 0 (low level), and the RC system clock starts working at this time;

[0030] S9: Since the RC system clock starts working at this time, the IIC decoding unit is driven by the clock, and can parse the wake-up command sent by the host through the IIC communication bus; after receiving the wake-up command, the IIC sleep\wake-up control unit is controlled to output 0 (low level), reset the wake-up decoding unit, and at the same time output 0 (low level) to control the main control unit to output a low level. When the main control unit outputs 0 (low level), the RC system clock is enabled, so that the entire system can work normally.

[0031] In this embodiment, preferably, the total control unit is an AND gate controller, which means that when the inputs are all 1 (high level), the output is 1 (high level).

[0032] In this embodiment, preferably, the RC system clock provides a driving clock for the entire application system, drives the IIC decoding unit to decode data and interact with the host, drives the IIC sleep / wake-up control unit to perform sleep or wake-up control, and can also drive the system application control unit to perform application control.

[0033] In this embodiment, preferably, the wake-up decoding unit is only driven by the IIC communication bus signal.

[0034] In this embodiment, preferably, the system modules used in the method include an RC system clock, an IIC communication bus, an IIC decoding unit, an IIC sleep / wake-up control unit, a wake-up decoding unit, a wake-up control unit, a system application control unit, a total control unit, and a host.

[0035] Although embodiments of the present invention have been shown and described (see the above detailed description for details), it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to these embodiments without departing from the principles and spirit of the present invention, and the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A digital implementation method for low power sleep of an IIC communication slave, characterized in that: The specific steps include: S1: the host sends a control instruction via the IIC communication bus; S2: The IIC decoding unit parses the data of the IIC communication bus and confirms the data type. If it is a sleep instruction, the data is sent to the IIC sleep / wake-up control unit; if it is an application control instruction, the data is sent to the system application control unit; S3: After receiving the sleep command, the IIC sleep / wake-up control unit notifies the system application control unit to exit the application control; at the same time, it sets the high level output to control the wake-up decoding unit and the main control unit; S4: The output control signal of the IIC sleep / wake-up control unit is the reset control signal of the wake-up decoding unit; when the output control signal is low, the sleep control unit is always in the reset state; when the system is in normal working state, the wake-up decoding unit is in the reset state; when the system enters sleep, the reset signal is set to high level, and the wake-up decoding unit is enabled at this time; S5: When the wake-up decoding unit is reset, the wake-up control unit is controlled to output a high level. When the chip is working normally and not in sleep mode, the wake-up control unit outputs a high level and maintains a high level output. Only when the wake-up decoding unit is in the activated working state and receives a wake-up working instruction, the output is set to a low level. S6: Since the wake-up control unit outputs 1 high level and the IIC sleep\wake-up control unit outputs 1 high level at this time, the general control unit outputs 1 high level. When the general control unit of the AND gate controller is at a high level, the general control unit outputs a signal that is an enable signal for the RC system clock. When the RC system clock is at a high level, the clock is turned off; since there is no clock drive at this time, the flip rate is low, thereby reducing the system power consumption; when the slave is in sleep mode, when the host IIC communication bus does not need to wake up the slave, the IIC communication bus communication signal is not flipped at this time, and the wake-up decoding unit is also not clock driven; S7: When wake-up is required, the host sends data. At this time, since the wake-up decoding unit is driven by the IIC communication bus, other units are not clock-driven, so only the wake-up decoding unit participates in the decoding work. When the wake-up decoding unit parses the wake-up instruction, it controls the wake-up control unit to a low level; S8: is the general control unit of the AND gate controller. Since the wake-up control unit outputs a low level, the general control unit outputs a low level, and the RC system clock starts working at this time; S9: Since the RC system clock starts working at this time, the IIC decoding unit is driven by the clock, and can parse the wake-up command sent by the host through the IIC communication bus; after receiving the wake-up command, the IIC sleep\wake-up control unit is controlled to output a low level, reset the wake-up decoding unit, and at the same time output a low level to control the main control unit to output a low level. When the main control unit outputs a low level, the RC system clock is enabled, and the entire system can work normally.

2. A digital implementation method for low power sleep of an IIC communication slave according to claim 1, characterized in that: The overall control unit is an AND gate controller, which means that when the inputs are all high level, the output is high level.

3. A digital implementation method for low power sleep of an IIC communication slave according to claim 1, characterized in that: The RC system clock provides a driving clock for the entire application system, drives the IIC decoding unit to decode data and interact with the host, drives the IIC sleep / wake-up control unit to perform sleep or wake-up control, and can also drive the system application control unit to perform application control.

4. A digital implementation method for low power sleep of an IIC communication slave according to claim 3, characterized in that: The wake-up decoding unit is only driven by the IIC communication bus signal.

5. A digital implementation method for low power sleep of an IIC communication slave according to claim 4, characterized in that: The system modules used in the method include an RC system clock, an IIC communication bus, an IIC decoding unit, an IIC sleep / wake-up control unit, a wake-up decoding unit, a wake-up control unit, a system application control unit, a general control unit, and a host.

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