Acceleration method and control device applied to SSD (Solid State Disk) controller
By introducing a hardware acceleration module into the SSD controller, it automatically detects and processes the write operations of read and write LBA, and solves the problems of long CPU processing time and poor performance, and achieves more efficient read and write command processing capabilities.
Patent Information
- Application Number
- CN202510110839.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-23
- Publication Date
- 2025-05-02
AI Technical Summary
In the prior art, the CPU needs to process a large number of read and write commands, resulting in a long processing time of the CPU and the retrieval time is proportional to the number of table items, limiting the write performance of the SSD and increasing cost and structural complexity.
By introducing a hardware acceleration module into the SSD controller, it automatically detects whether there are write operations in processing by reading and writing LBA. The search module completes the search and update of the LBA write status table, and searches multiple data items in parallel to accelerate processing.
It reduces the CPU processing cycle, reduces the overall processing time of commands, improves the ability of the SSD controller to process read and write commands, and reduces the CPU's workload and cost.
Smart Images
Figure CN119917027A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of computer technology, and more particularly to an acceleration method and a control device applied to an SSD controller. Background Art
[0002] The prior art has the following problems: 1. Long CPU processing time. In addition to the CPU time consumed by updating the table, the CPU needs to retrieve the entire table for each read and write command. The retrieval time is proportional to the number of table entries.
[0003] 2. Poor performance. Since the retrieval time is proportional to the number of table entries, the table entries cannot be too many, otherwise the table retrieval operation will not be completed; this will limit the number of write commands sent to the NVM, which will also limit the write performance of the SSD.
[0004] The prior art requires the CPU to directly process, which results in high cost and slow response speed. In addition, the structure is complicated due to the problem of table entries to be retrieved. Summary of the invention
[0005] The purpose of the present invention is to address the deficiencies of the prior art and to provide an acceleration method and control device for use in an SSD controller that uses hardware accelerated processing to overall reduce the time of a single processing and reduce CPU overhead.
[0006] An acceleration method applied to an SSD controller comprises the following steps: (1) Reading process steps: The CPU reads the L2PT operation, which triggers the retrieval module to determine whether there is an ongoing write operation on the LBA; (2) The steps of the write process, the retrieval and update of the LBA write status table are completely completed by the retrieval module; (3) Adding table entries: using a record table to save the LBA of the write operation being processed, and adding the LBA information to the table when there is a new LBA write operation; (4) Deleting table entries: If the write operation corresponding to a table entry has been completed, the table entry should be deleted from the table; (5) Search for accelerated steps and retrieve multiple data in parallel for acceleration.
[0007] As a further improvement and supplement to the above solution, the present invention also includes the following additional technical features: In the steps of the read process, the CPU reads F2PT to obtain the PBA of one LBA; the LBA value is written into the search module, and the search module checks whether there is a write operation being processed for the LBA.
[0008] In the step of adding a table entry, the method is as follows: (1) Temporarily stop searching for table items; (2) Decompose the LBA range value of the write command into several corresponding independent LBAs; (3) Write each LBA and the corresponding control information into the table; (4) Resume the search table item operation.
[0009] In the step of deleting the table entries, update logic is used to invalidate all the table entries to be deleted.
[0010] The step of adding table entries uses FIFO to manage table information.
[0011] In the step of accelerating the search, the search module reads out multiple table entries while searching for table entries, and compares the table entry values in multiple comparators at the same time, so that multiple comparisons of multiple values can be completed at the same time.
[0012] In the step of searching for acceleration, the processing method is as follows: (1) The CPU fills the LBA information to be compared into the available comparison modules; information can be filled into multiple comparison modules at the same time.
[0013] (2) The comparison module generates a comparison request; (3) The table lookup logic detects a pending comparison request and starts reading the table until the retrieval is completed; (4) The comparison module checks multiple information output by the table lookup logic at the same time until the check result is obtained or no matching item is found but the search for all table items is completed.
[0014] (5) If the current operation is a write operation, the following operation is also required: mark the matching table entry as invalid.
[0015] The control device applied to the SSD controller includes LBA, PBA, L2PT, write cache, NVM and hardware transmission path, and also includes an acceleration module, which reads out multiple table items at the same time and compares these table item values in multiple comparators at the same time; it can complete multiple comparisons of multiple values at the same time to accelerate processing.
[0016] The following beneficial effects can be achieved by using the present invention: Use hardware to automatically detect whether the currently read or written LBA has a write operation in progress, reducing the CPU processing cycle; Use multiple methods to speed up the retrieval process and reduce the overall command processing time.
[0017] By handing over some of the work that is originally done by the CPU to the hardware, on the one hand, the workload of the CPU can be reduced and the processing capability of the CPU can be improved, and on the other hand, higher processing efficiency and capability can be achieved by parallel processing in the hardware circuit. The present invention can improve the ability of the SSD controller to process read and write commands. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Figure 1 It is a structural schematic diagram of the present invention.
[0019] Figure 2 It is a structural schematic diagram of the reading process steps in the present invention.
[0020] Figure 3 It is a structural schematic diagram of the writing process steps in the present invention.
[0021] Figure 4 It is a structural diagram of the step of adding table entries in the present invention.
[0022] Figure 5 It is a structural schematic diagram of the search acceleration step in the present invention. DETAILED DESCRIPTION
[0023] The specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0024] like Figure 1-5 As shown, the present invention is an acceleration method and a control device applied in an SSD controller.
[0025] The sub-modules in the figure are described as follows: LBA: Address information used by a host (such as a PC) to read and write an SSD (solid state drive).
[0026] PBA: The actual address where the SSD stores data in the NVM; generally, PBA is different from LBA.
[0027] L2PT: Since LBA and PBA are generally different, the SSD uses the L2PT mapping table to record the PBA corresponding to each LBA.
[0028] Write cache: When the host writes data to the SSD, the SSD controller first saves the data to the write cache and then saves the data to the NVM; the write cache can be the SRAM in the SSD controller or a separate SDRAM (such as DDR or LPDDR).
[0029] NVM: independent storage medium chip, such as Nand Flash.
[0030] Hardware transmission path: The hardware logic that completes data transmission between the host and NVM media with the cooperation of the CPU (located inside the SSD controller) and other modules.
[0031] The acceleration method applied to the SSD controller described in this embodiment includes the following steps: (1) Reading process steps: The CPU reads the L2PT operation, which triggers the retrieval module to determine whether there is an ongoing write operation on the LBA; (2) The steps of the write process, the retrieval and update of the LBA write status table are completely completed by the retrieval module; (3) Adding table entries: using a record table to save the LBA of the write operation being processed, and adding the LBA information to the table when there is a new LBA write operation; (4) Deleting table entries: If the write operation corresponding to a table entry has been completed, the table entry should be deleted from the table; (5) Search for accelerated steps and retrieve multiple data in parallel for acceleration.
[0032] Furthermore, in the steps of the read process, the CPU reads the L2PT to obtain the PBA of one LBA; the LBA value is written into the search module, and the search module checks whether there is a write operation being processed for the LBA.
[0033] In the present invention, the CPU's operation of reading L2PT triggers the hardware to determine whether there is an ongoing write operation on LBA. Figure 2 The steps of processing a read command in the present invention are given; specifically as follows: (1) The CPU reads F2PT and obtains the PBA of 1 LBA; (2) The LBA value is written to the lookup module, which checks whether there is a write operation in progress for that LBA; (3) The hardware waits for the PBA value returned by L2PT and the search module result; (4) If there is no ongoing write operation for LBA, the value returned is the value pointing to NVM obtained from L2PT; if there is an ongoing write operation for LBA, the value returned is the value pointing to the write cache.
[0034] In the present invention, the retrieval and update of the LBA write status table are completed by the retrieval module, thereby reducing CPU processing operations. Figure 3 The relevant processing is given as follows: (1) The CPU starts the table retrieval and update operations.
[0035] (2) The retrieval logic performs a check and returns the result to the CPU; then the retrieval logic updates the table entry.
[0036] (3) The CPU completes subsequent processing based on the retrieval results; (4) The retrieval logic completes the update of the table items.
[0037] Furthermore, in the step of adding an entry, Figure 4 It is the logical structure of the record table. The next delete item points to the location of the item to be deleted, and the next add item points to the write location.
[0038] If the current operation is a write operation, the LBA information of the current write operation needs to be filled into the table after the table entry retrieval is completed; The method is as follows: (1) Temporarily stop searching for table items; (2) Decompose the LBA range value of the write command into several corresponding independent LBAs; (3) Write each LBA and the corresponding control information into the table; (4) Resume the search table item operation.
[0039] Furthermore, in the step of deleting the table entries, update logic is used to invalidate all the table entries to be deleted.
[0040] If the write operation corresponding to a table entry has been completed, the table entry should be deleted from the table; the process of deleting a table entry is as follows: (1) Temporarily stop searching for table items; (2) The update logic invalidates all entries to be deleted. Since the data that enters the write cache first is generally written to the NVM first, the entries to be deleted will be the first entries written to the table. Therefore, the entries to be deleted can be invalidated by updating the start position of the search.
[0041] (3) Resume the search table item operation.
[0042] Furthermore, the step of adding table entries uses FIFO management table information. The present invention uses a record table to save the LBA of the write operation being processed. When there is a new LBA write operation, the LBA information is added to the table; when there is a completed LBA write operation, the corresponding table entry is deleted. In SSD, the data written to the write cache first will always be written to NVM first; correspondingly, the table entry to be deleted will be the table entry added to the table first, so the information of the FIFO management table is used.
[0043] Furthermore, in the step of accelerating the search, Figure 5 A method for checking a table. The retrieval module retrieves a table item and reads out multiple table items at the same time ( Figure 5 N), and simultaneously sum these table entry values in multiple comparators ( Figure 5 By comparing M values, multiple comparisons of multiple values can be completed at the same time.
[0044] Furthermore, in the step of accelerating the search, the processing method is as follows: (1) The CPU fills the LBA information to be compared into the available comparison modules; information can be filled into multiple comparison modules at the same time.
[0045] (2) The comparison module generates a comparison request; (3) The table lookup logic detects a pending comparison request and starts reading the table until the retrieval is completed; (4) The comparison module checks multiple information output by the table lookup logic at the same time until the check result is obtained or no matching item is found but the search for all table items is completed.
[0046] (5) If the current operation is a write operation, the following operation is also required: mark the matching table entry as invalid.
[0047] That is, multiple data are retrieved in parallel for acceleration.
[0048] Furthermore, a control device used in an SSD controller, Figure 1 As shown, it includes LBA, PBA, L2PT, write cache, NVM and hardware transmission path, and also includes an acceleration module, which reads out multiple table entries at the same time and compares these table entry values in multiple comparators at the same time; it can complete multiple comparisons of multiple values at the same time to accelerate the processing.
[0049] The above are preferred embodiments of the present invention, which do not limit the protection scope of the present invention. Any modifications and improvements made by those skilled in the art based on the design ideas of the present invention should be regarded as within the protection scope of the present invention.
Claims
1. An acceleration method applied to an SSD controller, characterized in that: The following steps are involved: (1) Reading process steps: The CPU reads the L2PT operation, which triggers the retrieval module to determine whether there is an ongoing write operation on the LBA; (2) The steps of the write process, the retrieval and update of the LBA write status table are completely completed by the retrieval module; (3) Adding table entries: using a record table to save the LBA of the write operation being processed, and adding the LBA information to the table when there is a new LBA write operation; (4) Deleting table entries: If the write operation corresponding to a table entry has been completed, the table entry should be deleted from the table; (5) Search for accelerated steps and retrieve multiple data in parallel for acceleration.
2. The acceleration method applied to an SSD controller according to claim 1, characterized in that: In the steps of the read process, the CPU reads F2PT to obtain the PBA of one LBA; the LBA value is written into the search module, and the search module checks whether there is a write operation being processed for the LBA.
3. The acceleration method applied to the SSD controller according to claim 1, characterized in that: In the step of adding a table entry, the operation is as follows: (1) Temporarily stop searching for table items; (2) Decompose the LBA range value of the write command into several corresponding independent LBAs; (3) Write each LBA and the corresponding control information into the table; (4) Resume the search table item operation.
4. The acceleration method applied to an SSD controller according to claim 1, characterized in that: In the step of deleting the table entries, update logic is used to invalidate all the table entries to be deleted.
5. The acceleration method applied to an SSD controller according to claim 3, characterized in that: The step of adding table entries uses FIFO to manage table information.
6. The acceleration method applied to an SSD controller according to claim 1, characterized in that: In the step of accelerating the search, the search module reads out multiple table entries while searching for table entries, and compares the table entry values in multiple comparators at the same time, so that multiple comparisons of multiple values can be completed at the same time.
7. The acceleration method applied to an SSD controller according to claim 6, characterized in that: In the step of searching for acceleration, the processing method is as follows: (1) The CPU fills the LBA information to be compared into the available comparison modules; information can be filled into multiple comparison modules at the same time. (2) The comparison module generates a comparison request; (3) The table lookup logic detects a pending comparison request and starts reading the table until the retrieval is completed; (4) The comparison module checks the multiple information output by the table lookup logic at the same time until the check result is obtained or no matching item is found but the search for all table items is completed. (5) If the current operation is a write operation, the following operation is also required: mark the matching table item as invalid.
8. The control device applied to the SSD controller according to claim 1, comprising LBA, PBA, L2PT, write cache, NVM and hardware transmission path, characterized in that: It also includes an acceleration module, which reads out multiple table entries at the same time and compares the table entry values in multiple comparators at the same time; it can complete multiple comparisons of multiple values at the same time to accelerate the processing.