Signed number multiply-accumulate operation circuit, CIM chip and electronic device

Abstract

This application relates to a signed number multiply-accumulate operation circuit, a CIM chip, and an electronic device. Among them, the signed number multiply-accumulate operation circuit includes: a weight storage array, which includes a number of storage modules distributed in rows and columns. Each storage module includes a storage unit, and NMOS transistors N5 and N6. The gate and drain of N5 are respectively connected to the storage node QB of the storage unit and the source of N6. The sources of N5 in the same column are connected to the same bit line BL. The gates of N6 in the same row are connected to the same calculation word line IWL. The drains of N6 in the same column are connected to the same bit line SL. The bit line BL is also connected to a reference voltage, and the bit line SL is also connected to the ground terminal VSS. The multi-bit weight W is encoded to form w =2 W +1 and then stored row by row in the weight storage array. This circuit realizes in-memory computing of signed data MAC with lower time, area, and power consumption overheads, and solves the problem of low multiply-accumulate calculation efficiency of the current signed number multiply-accumulate operation circuit.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and particularly to a signed number multiply-accumulate operation circuit, a CIM chip, and an electronic device. Background Art

[0002] In iterative computing scenarios such as deep neural networks, when unsigned numbers process negative weights, offset compensation (such as +128 zero offset) is required, resulting in the offset being amplified multiple times during the accumulation process, and finally an additional subtraction operation is needed for correction. While signed numbers directly retain the weight sign information, systematically eliminating biases at the algorithm level and reducing inference errors.

[0003] Data processing based on deep learning algorithms involves a large number of multiply-accumulate (MultiplyAccumulate, MAC) tasks. Taking a convolutional neural network as an example, the sliding window calculation during feature map generation involves intensive multiply-accumulation of positive and negative weights and activation values. Using a signed number architecture can directly process the retention of negative values after ReLU activation (such as the h-swish function in MobileNet V3), while the unsigned scheme needs to introduce absolute value conversion and sign bit separation, resulting in an increase in the complexity of the computational graph, and this advantage is more prominent in the in-memory computing architecture.

[0004] Existing various CIM circuits based on SRAM with MAC functions are highly efficient in integer operations. However, when traditional CIM circuits perform signed data operations, in order to implement a complete convolution operation, a large number of cross switches need to be introduced in the computing unit, or more computing cycles are required, which greatly increases the circuit overhead and reduces the efficiency of performing signed number multiply-accumulate calculations.

[0005] Aiming at the problem of low multiply-accumulate calculation efficiency of the current signed number multiply-accumulate operation circuit, no effective solution has been proposed yet. Summary of the Invention

[0006] In the present invention, a signed number multiply-accumulate operation circuit, a CIM chip, and an electronic device are provided to solve the problem of low multiply-accumulate calculation efficiency of the current signed number multiply-accumulate operation circuit.

[0007] In a first aspect, the present invention provides a signed number multiply-accumulate operation circuit, including:

[0008] A weight storage array, which includes a number of storage modules distributed in rows and columns. Each storage module includes a storage cell, and NMOS transistors N5 and N6. The gate and drain of N5 are respectively connected to the storage node QB of the storage cell and the source of N6. The source of N5 in the same column is connected to the same bit line BL. The gate of N6 in the same row is connected to the same computing word line IWL. The drain of N6 in the same column is connected to the same bit line SL. The bit line BL is also connected to the reference voltage Vref, and the bit line SL is also connected to the ground terminal VSS. For multi-bit weights W are encoded to form w =2 W +1 and then stored row by row in the weight storage array;

[0009] A plurality of input encoding circuits respectively corresponding to each row of storage modules. The output of each input encoding circuit is fed into the computing word line IWL of the corresponding row. The input encoding circuit encodes each bit of the n-bit input in sequence and feeds the encoding result into the computing word line IWL. The encoding method is:

[0010]

[0011] wherein, a i represents the output of the i-th encoding of the input encoding circuit, A n-1 ...A 2 A 1 A 0 represents the n-bit input, A n-1 is the sign bit, A n-2 ...A 2 A 1 A 0 are the digital bits;

[0012] A plurality of voltage clamping current mirror circuits respectively corresponding to each column of storage modules. Each voltage clamping current mirror circuit includes a first voltage clamping circuit and two first current mirror circuits. The output of the first voltage clamping circuit is the input of the two current mirror circuits. The outputs of the two first current mirror circuits are respectively grounded through a first capacitor and a second capacitor. The input of the first voltage clamping circuit is the bit line BL of the corresponding column. The capacitance difference between the first capacitor and the second capacitor is used to characterize the multiply-accumulate result.

[0013] In a second aspect, a CIM chip is provided in the present invention, which integrates the signed number multiply-accumulate operation circuit described in the first aspect.

[0014] In a third aspect, an electronic device is provided in the present invention, which is built-in with the CIM chip described in the second aspect and realizes the convolutional operation of deep learning through this CIM chip.

[0015] Compared with related technologies, the present invention provides a new circuit architecture and operating logic for a signed number fast arithmetic circuit. In this circuit solution, a brand-new weight mapping scheme, signed number XNOR operation, and bit counting calculation scheme are applied. The multiplication and accumulation calculation results of positive and negative numbers can be divided into four parts, so that each part can be accumulated separately during the calculation process, and finally the difference between two calculation capacitors is quantified to calculate the final result. This reduces the introduction of a large number of cross switches in the calculation unit of traditional analog signed numbers, saves the calculation cycle, and further realizes the in-memory calculation of signed data MAC with lower time, area, and power consumption overhead, solving the problem of low multiplication and accumulation calculation efficiency of the current signed number multiplication and accumulation operation circuit.

[0016] Details of one or more embodiments of this application are set forth in the following drawings and description to make other features, objects, and advantages of this application more concise and understandable. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is the architecture diagram of the signed number multiplication and accumulation operation circuit provided in this embodiment;

[0018] Figure 2 is the structural diagram of the input encoding circuit provided in this embodiment;

[0019] Figure 3 is the schematic diagram of the XNOR operation of the weight storage array provided in this embodiment;

[0020] Figure 4 is the circuit diagram of the 6T storage cell provided in this embodiment;

[0021] Figure 5 is the circuit diagram of the voltage clamping current mirror circuit and the compensation circuit provided in this embodiment;

[0022] Figure 6 is the charging schematic diagram of the calculation capacitor during the multiplication and accumulation calculation process in this embodiment;

[0023] Figure 7 is the timing diagram of the multiplication and accumulation calculation process in this embodiment;

[0024] Figure 8 is the schematic diagram of the calculation result quantization process in this embodiment;

[0025] Figure 9 is the overall timing diagram of the signed number multiplication and accumulation operation circuit provided in this embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0026] To understand the purpose, technical solution, and advantages of this application more clearly, the following describes and explains this application in conjunction with the drawings and embodiments.

[0027] Unless otherwise defined, technical terms or scientific terms involved in this application shall have the general meanings understood by those with ordinary skills in the technical field to which this application belongs. In this application, words such as "a", "an", "one kind", "the", "these" and the like do not indicate a limitation in quantity, and they can be singular or plural. Terms such as "include", "comprise", "have" and any variants thereof involved in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product or device including a series of steps or modules (units) is not limited to the listed steps or modules (units), but may include unlisted steps or modules (units), or may include other steps or modules (units) inherent in these processes, methods, products or devices. Words such as "connect", "be connected", "couple" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether directly connected or indirectly connected. "Multiple" involved in this application means two or more. "And / or" describes the association relationship of associated objects and indicates that three relationships can exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, and B exists alone. Usually, the character " / " indicates that the objects associated before and after are in an "or" relationship. Terms such as "first", "second", "third" and the like involved in this application only distinguish similar objects and do not represent a specific sorting for the objects.

[0028] In this embodiment, a signed number multiplication and accumulation operation circuit is provided. Figure 1 is the architecture diagram of the signed number multiplication and accumulation operation circuit provided in this embodiment, as Figure 1 shown. The signed number multiplication and accumulation operation circuit includes a weight storage array, a plurality of input encoding circuits respectively corresponding to each row storage module, and a plurality of voltage clamping current mirror circuits respectively corresponding to each column storage module.

[0029] The weight storage array includes several storage modules distributed in rows and columns. Each storage module includes a storage unit and NMOS transistors N5 and N6. The gate and drain of N5 are respectively connected to the storage node QB of the storage unit and the source of N6. The sources of N5 in the same column are connected to the same bit line BL. The gates of N6 in the same row are connected to the same calculation word line IWL. The drains of N6 in the same column are connected to the same bit line SL. The bit line BL is also connected to the reference voltage Vref, and the bit line SL is also connected to the ground terminal VSS. The multi-bit weight W is encoded to form w =2 W +1 and then stored in the weight storage array row by row.

[0030] Specifically, the weight storage array can be divided into multiple banks (one bank includes multiple rows of storage modules). Each bank stores a set of multi-bit weights. Each storage module in the same row is used to store one bit of the multi-bit weight. The number of columns of each bank is reasonably allocated according to the number of bits of the signed numbers to be calculated in the actual operation process. The n-bit signed number weight requires n columns of SRAM cells.

[0031] In this embodiment, in order to satisfy the multiply-accumulate calculation, for each multi-bit weight, it needs to be encoded and stored in a row of storage modules. The specific encoding method is as follows: w =2 W +1. W is the multi-bit weight before encoding, w is the multi-bit weight after encoding. Exemplarily, for the four-bit weight w each bit of which needs to satisfy:

[0032]

[0033] wherein, w j represents w the j-th bit in

[0034] For the storage unit used to store the j-th bit weight, when its stored value is 1 (Q = 1, QB = 0), it represents w j = 1; when its stored value is 0 (Q = 0, QB = 1), it represents w j = -1. The multi-bit weight is encoded into multiple columns of storage modules in the weight storage array. Taking 4 columns as an example, for the weight "0010" (+2), it is mapped from the MSB (Most Significant Bit) to the LSB (Least Significant Bit), and the encoded result is: "1 0 1 0"; for "1010" (-2), the encoded result is: "0 1 1 0". The truth table of the four-bit weights of the four-bit signed number is as follows:

[0035] Table 1 Truth Table of Four-bit Weights of Four-bit Signed Numbers

[0036]

[0037] Furthermore, for each storage module, the storage cells therein can adopt 6T storage cells. Referring to Figure 4 , in this embodiment, the 6T storage cell includes PMOS transistors P1 and P2 and NMOS transistors N1, N2, N3, and N4. The specific connection relationship of each device in each storage module is as follows:

[0038] The sources of P1 and P2 are connected to VDD; the drain of P1 is connected to the gates of P2, N2, and the drains of N1 and N3, and serves as the storage node QB; the drain of P2 is connected to the gates of P1, N1, N5, and the drains of N2 and N4, and serves as the inverted storage node Q; the sources of N3 and N5 are connected to the bit line BL; the source of N4 is connected to the bit line BLB; the gates of N3 and N4 are connected to the word line WL; the drain of N5 is connected to the source of N6; the gate of N6 is connected to IWL, and the drain of N6 is connected to the bit line SL. Among them, the P1 - P2, N1 - N4 parts in the storage module form a 6T storage cell, and the 6T storage cell in the storage module is used to implement the data storage function in the storage mode and to pre - store one of the weights in the calculation module.

[0039] The input encoding circuit encodes each bit of the n - bit input in sequence and feeds the encoding result into the calculation word line IWL. The encoding method is as follows:

[0040]

[0041] Among them, a i represents the output of the i - th encoding of the input encoding circuit (the encoding result of the i - th bit in the n - bit input), A n-1 ...A 2 A 1 A 0 represents the n - bit input, where A n-1 is the sign bit.

[0042] During the calculation process, the n - bit input A n-1 ...A 2 A 1 A 0 is encoded into n - 1 inputs: a n-2 、…、 a 1 and a 0. Each input waveform a k is encoded based on the sign bit A n-1 . Each input waveform a k can be serially fed into the corresponding calculation word line IWL within n - 1 cycles. For example, first feed the lowest - order a 0 into the calculation word line IWL to perform the multiplication calculation with the corresponding weight bit, and then feed the higher - order a 1 into the calculation word line IWL to perform the multiplication calculation with the corresponding weight, and so on. Finally, feed the highest - order a n-2It is fed into the computational word line IWL to implement the multiplication calculation with the corresponding weights. The feeding order is the same as the encoding order of each bit in the n-bit input by the input encoding circuit.

[0043] Exemplarily, a 4-bit input A 3 A 2 A 1 A 0 is encoded into 3 inputs (3 outputs of the input encoding circuit): a 2, a 1 and a 0. Each input waveform a k is encoded based on the sign bit A 3, and the input waveform a k can be serially fed within 3 cycles. The specific encoding rules are as follows in the table:

[0044] Table 2 Encoding truth table of the input

[0045]

[0046] Specifically, the n-bit input A n-1 ...A 2 A 1 A 0 is divided into n - 1 cycles as the input. The sign bit is encoded into each bit of the input, and the encoding results '1', '0', and '-1' are directed to the corresponding input encoding circuits, which generate a bipolar pulse signal (input signal) of "low_high", "low_low", and "high_low" for the input word line IWL according to the input data, corresponding to the encoded values of 01 / 00 / 10 respectively. If the input value is +1, the first stage of the input signal is high level and the second stage is low level (high_low). If the input value is -1, the first stage is low level and the second stage is high level (low_high). If the input value is 0, both the first stage and the second stage of the input signal are low level (low_low). For example, for the positive input "+2", the three outputs (from low to high) of the input encoding circuit are respectively: "low_low low_high low_low"; for "-2", the three outputs (from low to high) of the input encoding circuit are respectively: "low_low high_low low_low". The output of the input encoding circuit is input into the 8T - SRAM (storage module) as IWL. The input encoding circuit is used to encode the signed input bit by bit into a bipolar pulse signal, thus dividing the calculation into two steps, which is beneficial to separating several partial results of the convolution during the later calculation process.

[0047] Reference Figure 2 , each input encoding circuit consists of an inverter, two AND gates and a multiplexer. The input signal X ( A n-2 ...A 2 A 1 A one bit of 0) and the clock signal CLK are connected to the multiplexer through one of the AND gates. At the same time, the inverted signal of the input signal X (obtained by inverting through the inverter) and the clock signal CLK are connected to the multiplexer through the other AND gate. The control terminal of the multiplexer is connected to the sign bit A n-1 . The result of the multiplexer depends on the sign bit A n-1 and the input data X. If X is high level and the sign bit A n-1 is 1, then IWL is activated when CLK is at high level. At the same time, when the sign bit A n-1 is 0, IWL is activated when CLK is at low level; when X is low level, IWL is always in the disabled state.

[0048] From the above description of the weight storage array and the input encoding circuit, for a certain storage cell, if its storage node QB = 1, then N5 controlled by it conducts. At this time, if the corresponding IWL is activated, then the corresponding N6 conducts, and then the bit line BL and the bit line SL conduct, and thus there is current on the bit line from BL to SL. When the storage node QB of the storage cell is 0 or IWL is not activated, then the bit line BL and the bit line SL do not conduct, and thus there is no current on the bit line from BL to SL. Therefore, the calculation result between the single-bit input and the corresponding bit weight can be characterized by the magnitude of the current on the bit line BL. Furthermore, the multiplication result of the multi-bit input and the multi-bit weight can be obtained based on the currents of each bit line BL. Further, it can be implemented by the voltage-clamped current mirror circuit in this embodiment.

[0049] Among them, the operation logic of the storage cell cooperating with N5 and N6 to implement the multiplication operation is as follows:

[0050] 1. The encoded weights are pre-stored in the storage cell: when Q is at high level and QB is at low level, it means that the corresponding bit of the encoded weight part is "1"; when Q is at low level and QB is at high level, it means that the corresponding bit of the encoded weight part is "0".

[0051] 2. Pre-charge the bit line BL to a high level, and then receive the input double-pulse signal through the computed word line IWL: when IWL is "low_high", it indicates that the corresponding bit of the mantissa part of the input operand is "-1"; when IWL is "high_low", it indicates that the corresponding bit of the mantissa part of the input operand is "+1"; when IWL is "low_low", it indicates that the corresponding bit of the mantissa part of the input operand is "0".

[0052] 3. Output the final XNOR operation and bit count according to the current change on BL (specifically introduced later).

[0053] Refer to Figure 5 , each voltage clamp current mirror circuit VCCM includes a first voltage clamp circuit VC1 and two first current mirror circuits CM1. The output of the first voltage clamp circuit VC1 is the input of the two first current mirror circuits CM1. The outputs VOUT1 and VOUT2 of the two first current mirror circuits CM1 are grounded through the first capacitor C1 and the second capacitor C2 respectively. The input of the first voltage clamp circuit VC1 is the bit line BL of the corresponding column. The capacitance difference between the first capacitor C1 and the second capacitor C2 is used to characterize the multiply-accumulate result. Among them, the first capacitor C1 and the second capacitor C2 form a group of computing capacitors. When there is current on the bit line BL, charges will accumulate on the two computing capacitors (accumulating two different parts of the convolution calculation respectively). Therefore, the computing capacitors have the function of accumulating the currents of each bit line BL.

[0054] In this embodiment, there is a storage module in the weight storage array where a column of storage nodes QB is always 1, which is defined as a redundant column; the signed number multiply-accumulate operation circuit further includes: a plurality of compensation circuits respectively corresponding to each column of storage modules, which include two second current mirror circuits CM2, and the outputs of the two second current mirror circuits CM2 are respectively coupled to the outputs VOUT1 and VOUT2 of the two first current mirror circuits CM1; and further includes a second voltage clamp circuit VC2, whose output is the input of the two second current mirror circuits CM2, and whose input is the bit line BL of the redundant column.

[0055] As Figure 5As shown, the structures of VC1 and VC2 are the same. Both are composed of two PMOS transistors connected in series (source-drain connection) and an amplifier. The positive terminal of the amplifier is connected to the bit line BL and the power supply voltage through two PMOS transistors connected in series. The negative terminal is connected to the reference voltage Vref. The gate of the PMOS transistor connected to the power supply is connected to the output terminal of the amplifier and provides the clamping voltage Vf (the output of the voltage clamping circuit). The gate of the other PMOS transistor is connected to the control signal VCM; the structures of CM1 and CM2 are the same. Both are composed of two PMOS transistors connected in series (source-drain connection). The source of one POMS transistor is connected to the power supply and the gate serves as the input terminal of the current mirror circuit. The source of the other PMOS transistor serves as the output terminal of the current mirror circuit and the gate is connected to the control signal. The control signals of the two CM1 are SAMP1 and SAMP2 respectively, and the control signals of the two CM2 are PRE1 and PRE2 respectively.

[0056] Furthermore, in order to discharge the two computing capacitors, a NMOS transistor is connected in parallel to each of the first capacitor and the second capacitor. The gate control signals of the two NMOS transistors are CLR1 and CLR2 respectively.

[0057] It should be noted that the above-mentioned multiple voltage clamping current mirror circuits and multiple compensation circuits correspond to multiple columns of the memory module respectively, and thus form a row of voltage clamping current mirror circuits and compensation circuits. A row of voltage clamping current mirror circuits and compensation circuits are commonly connected to a group of computing capacitors, which can only support the calculation of one row of memory modules (storing one multi-bit weight) at the same time. If parallel calculation of multiple rows of memory modules is to be realized, that is, to support the multiplication calculation of multiple multi-bit inputs and multiple multi-bit weights, multiple rows of voltage clamping current mirror circuits and compensation circuits need to be set. The same group of computing capacitors commonly connected by each row of voltage clamping current mirror circuits and compensation circuits are used to output the multiplication calculation results of the corresponding multi-bit inputs and multi-bit weights.

[0058] Furthermore, a plurality of auxiliary capacitors are connected in parallel to both the first capacitor and the second capacitor. The sizes of the auxiliary capacitors are the same as those of the computing capacitors. When the encoded results of different bits are fed into the computing word line IWL, the number of turned-on auxiliary capacitors is different, so that the charges accumulated by the first capacitor and the second capacitor during the feeding period have weights corresponding to the number of bits of the encoded results. Specifically, the number of auxiliary capacitors is determined by the number of bits of the input operand (multi-bit input). An n-bit input operand requires (2^ (n-2) -1) auxiliary capacitors. The auxiliary capacitors are turned on and shared with the computing capacitors during different calculation periods, so as to distribute the weights of the input data. Specifically, for an n-bit input operand, it is fed in (n - 1) periods. The lowest bit is fed in the first period, and (2^ (n-2) -1) auxiliary capacitors are shared with the computing capacitors to represent that the weight of the lowest bit of the input is (2^ 0), and so on. The most significant bit of the input is fed in during the (n - 1)th cycle. All auxiliary capacitors are turned off, indicating that the weight of the most significant bit of the input is (2^ (n-1) ).

[0059] Specifically, in this embodiment, if the input operand is 4 bits, each computing capacitor needs to be equipped with 3 auxiliary capacitors. The input needs to be fed in three cycles. The size of the auxiliary capacitor is equal to that of the computing capacitor. In the first cycle, the least significant bit of the input is fed in, and all auxiliary capacitors are turned on. The cumulative value of the computing capacitor corresponds to the weight 2^ 0 of the input; in the second cycle, the second least significant bit of the input is fed in, sharing the computing charge with one auxiliary capacitor. The cumulative value of the computing capacitor corresponds to the weight 2^ 1 of the input; in the third cycle, the most significant bit of the input is fed in and does not need to share with the auxiliary capacitor. The cumulative value of the computing capacitor corresponds to 2^ 2 of the input weight.

[0060] As described above, the specific structure of the signed number multiply-accumulate operation circuit provided in this embodiment and the encoding description of the n-bit input and n-bit weight are explained. Next, the calculation process of this signed number multiply-accumulate operation circuit will be described.

[0061] The signed number multiply-accumulate operation circuit divides the convolution operation into four parts, taking the convolution of the first input a 0 and the weight of the least significant bit w 0 as an example.

[0062] The convolution operation is divided into:[[]]

[0063] m: The part where the input is +1 multiplied by the weight +1; n: The part where the input is +1 multiplied by the weight -1; p: The part where the input is -1 multiplied by the weight +1; q: The part where the input is -1 multiplied by the weight -1; m + n is the part where the input is +1, and p + q is the part where the input is -1. The following equation is satisfied:

[0064]

[0065] After derivation, it can be obtained that:

[0066]

[0067] Therefore, the convolution operation is converted into calculating ∑ q (-1)×(-1) and |∑ n (+1)×(-1)| and I +1 and I -1 .

[0068] Calculate ∑ q (-1)×(-1) and |∑ n(+1)×(-1) is obtained through XNOR operation and bit counting, referring to Figure 3 , and the specific steps of XNOR operation and bit counting in the weight storage array are as follows:

[0069] Preparation stage: Pre-charge the bit line BL to a stable voltage ( V ref , the reference voltage for stabilizing the BL voltage), set the bit line SL to a low voltage, give a high pulse to CLR1 / CLR2, and clear the charge in the calculation capacitor.

[0070] First stage: The input encoding circuit sets all IWLs corresponding to the input signal of -1 to high level. If the weight in the storage cell is -1, that is, the stored value in the storage cell is 0, i.e., Q = 0, QB = 1, then the storage cell forms a discharge path and generates I H current. If the stored value in the storage cell is 1, i.e., Q = 1, QB = 0, the storage cell does not form a discharge path. In this stage, the BL current is given by q×I H , and after charge sharing, the calculation of ∑ q (-1)×(-1) is achieved.

[0071] Second stage: The input encoding circuit activates the IWL corresponding to the +1 weight. Only when the stored value in the storage cell is 0, i.e., Q = 0, QB = 1, can a discharge path be formed. At this time, the BL current is approximately n×I H , and after charge sharing, the calculation of ∣∑ n (+1)×(-1)∣ is achieved.

[0072] After these two calculation stages, the convolution ∑ q (-1)×(-1) and ∣∑ n (+1)×(-1)∣ partial results are obtained.

[0073] Use a voltage-clamped current mirror circuit (VCCM) to ensure the linearity of the calculation and convert the calculated current signal into a voltage. The voltage-clamped current mirror circuit consists of a first voltage-clamping circuit and two current mirror circuits, and the outputs of the two current mirror circuits are connected to the first capacitor C1 and the second capacitor C2 (which are specifically introduced above). The VCCM circuit is divided into groups of n columns (the VCCM circuits in the same row are in a group), and it configures the current mirror for the storage module. The ratio of MSB to LSB is (2^ n :…:4:2:1). The calculation process of the voltage-clamped current mirror circuit is as follows:

[0074] The second voltage clamping circuit VC2 can stabilize the bit line BL voltage according to a preset reference voltage Vref. During the calculation process, the PRE signal is set to a low value to connect BL to VC2; in addition, to turn on VC2, VCM is set to a lower value. The feedback signal from the amplifier is used to dynamically adjust the BL voltage to keep it stable. Refer to Figure 6 , SAMP1 and SAMP2 are at a low level in the first stage and the second stage respectively to activate the current replication path. The voltage of C1 represents ∑ in the convolution result q (-1)×(-1). The corresponding electric quantity is expressed as Q 1. The voltage of C2 represents ∣∑ in the convolution result n (+1)×(-1)∣. The electric quantity in C2 is represented by Q 2. Convert the convolution result into a form represented by the electric charge quantity S:

[0075]

[0076] where, Q - and Q + represent respectively I -1 and I +1 of the electric charge quantity.

[0077] Furthermore, the binary-based compensation circuit in this embodiment can obtain the electric charge quantity S . That is I -1 and I +1 part, the charges Q - and Q + can be obtained through a compensation circuit.

[0078] The compensation circuit allows each calculation capacitor C1 and C2 to have two current accumulation paths: one for the first current mirror circuit and the other for the second current mirror circuit. The current generated by the second current mirror circuit is copied from the redundant column, and the size of the PMOS transistor in the first current mirror circuit is twice the size of the PMOS transistor in the second current mirror circuit.

[0079] Continue to refer to Figure 6 and Figure 7 , the operation of the compensation circuit is as follows:

[0080] First stage: After the "-1" signal is input to the computational word line IWL of the weight storage array, SAMP1 and PRE2 are set to a low voltage, thereby forming a computational current path connected to capacitor C1 and a compensation current path connected to capacitor C2 to generate charges on capacitors C1 and C2. Q 1 and ( Q - / 2).

[0081] Second stage: After the "+1" signal is input to the computational word line IWL of the weight storage array, SAMP2 and PRE1 are set to a low voltage, thereby forming a compensation current path connected to capacitor C1 and a computational current path connected to capacitor C2 to generate Q 1 + ( Q + / 2) and ( Q - / 2) + Q the electric charges of 2.

[0082] According to the formula above, the final convolution result only needs to be quantized Q 1 + ( Q + / 2) and ( Q - / 2) + Q the difference between 2. To obtain an n-bit quantization result, the compensation circuit is multiplexed for charge compensation, the voltages of C1 and C2 are fed into the sense amplifier SA for comparison, and an n-bit result is generated after n comparison steps.

[0083] Refer to Figure 8 , in the first step, determine the sign bit: if C1 > C2, the sign bit is set to positive, and the subsequent output result is taken from OUT+ (i.e., the level of OUT+ represents the calculation result); on the contrary, if C1 ≤ C2, the sign bit is negative, and the subsequent output result is taken from OUT- (i.e., the level of OUT+ represents the calculation result); in the second step, all redundant rows are activated, and the charge ( Q max / 2) is transferred to the capacitor with less charge between C1 and C2. Then a comparison is performed in the sense amplifier SA. In the third step, half of the redundant rows are activated, and the charge ( Q max / 4) is transferred to the capacitor with less charge, and then another comparison is performed in the sense amplifier SA. In the fourth step, one-quarter of the redundant rows are activated, and the charge ( Q max( / 8) is transferred to the capacitor with less charge and the final comparison is performed in the sense amplifier SA. By operating in such a cycle, an n-bit calculation result can be obtained. Among them, the positive plate of the calculation capacitor C1 is connected to the positive input terminal of the sense amplifier SA, the positive plate of the calculation capacitor C2 is connected to the negative input terminal of the sense amplifier SA, and the positive output OUT+ of the sense amplifier SA. When the voltage at the positive input terminal is greater than the voltage at the negative input terminal, OUT+ is at a high level (1); when the voltage at the positive input terminal is less than the voltage at the negative input terminal, OUT+ is at a low level (0); the negative output OUT- of the sense amplifier SA. When the voltage at the positive input terminal is greater than the voltage at the negative input terminal, OUT- is at a high level (0); when the voltage at the positive input terminal is less than the voltage at the negative input terminal, OUT- is at a high level (1); among them, the redundant row refers to the row of the storage module in the weight storage array that does not participate in the signed multiplication and accumulation operation this time.

[0084] Refer to Figure 9 , which is the overall timing diagram. The following takes a 4-bit signed number and a 4-bit signed number weight as an example to explain the overall timing.

[0085] Calculation stage:

[0086] The 4-bit signed input-encoded input values are input in 3 cycles, and each cycle is divided into two stages.

[0087] For the row where the input of the storage unit is, -1, IWL is set to a high level, and the calculated Q1 charge is used to charge C1. At the same time, C2 is charged with the compensation charge of Q - / 2.

[0088] Second stage:

[0089] For the row where the input of the storage unit is +1, IWL is set to a high level, and the calculated Q2 charge is used to charge C2. At the same time, C1 is charged with the compensation charge of Q+ / 2.

[0090] After 3 cycles, the calculation result can be obtained.

[0091] Quantization stage:

[0092] To obtain a 4-bit quantization result, the voltages of C1 and C2 are fed into the sense amplifier for comparison, and a 4-bit result is generated after 4 comparison steps.

[0093] First stage:

[0094] Determine the sign bit: If C1 > C2, the sign bit is set to positive, and OUT+ is used as the output result. On the contrary, if C1 ≤ C2, the sign bit is negative, and OUT- is used as the output result.

[0095] Second stage: All redundant rows are activated, and the charge (Q max / 2) is transferred to the capacitor with less charge between C1 and C2. Then, a comparison is performed in the sense amplifier.

[0096] In the third stage, half of the redundant rows are activated, and the charge (Q max / 4) is transferred to the capacitor with less charge, and then another comparison is performed in the sense amplifier.

[0097] In the fourth stage, one - quarter of the redundant rows are activated, and the charge (Q max / 8) is transferred to the capacitor with less charge, and a final comparison is performed in the sense amplifier.

[0098] After the comparison is completed, all the multiply - accumulate operations are finished.

[0099] In summary, this embodiment provides a signed - number multiply - accumulate fast operation circuit based on SRAM, which is designed based on an SRAM array, VCCM, BCC, computing capacitors, auxiliary capacitors, and peripheral circuits, and is used to implement the multiply - accumulate operation between multiple groups of multi - bit signed - number operands and multi - bit signed - number weights. The signed - number multiply - accumulate fast operation circuit in this embodiment has two working modes: storage and calculation, and the function switching of the circuit is controlled by a mode - switching module. Among them, the peripheral circuit of the SRAM array refers to the relevant circuits and modules related to data reading, writing, and saving using the SRAM array.

[0100] As Figure 1 shown, in order to implement the operation function, in the solution of this embodiment, the operation circuit architecture consists of a weight array, an input encoding circuit, a voltage - clamped current - mirror array, SA, two computing capacitors, auxiliary capacitors, and a memory control circuit.

[0101] The weight array can be divided into multiple banks. Each bank stores a group of weights (a group of weights includes multiple cells), and the number of columns of each bank is reasonably allocated according to the number of bits of the signed number to be calculated in the actual operation process. The weights of an n - bit signed number require n columns of SRAM cells; for example, for a 4 - bit signed number, each bank has 4 columns.

[0102] In practical applications, the encoded operand weights are input bit - by - bit to the same row of the array, and the same cell in the array stores one of them. Different rows are used to store different multi - bit weights. On this basis, the maximum number of groups of signed - number operands or weights that the signed - number fast operation circuit provided in this embodiment can support for the multiply - accumulate operation is determined by the number of rows of the SRAM array. For example, in a circuit with a weight - array scale of 64×4×16, it can support up to 64×16 multiply - accumulate operations between signed - number operands and 64×16 signed - number weights.

[0103] As described above, the signed number multiply-accumulate operation circuit and its calculation process provided in this embodiment are as follows. From the above description, it can be seen that the present invention provides a new circuit architecture and operation logic for a signed number fast operation circuit. In this circuit solution, a brand-new weight mapping scheme, signed number XNOR operation, and bit counting calculation scheme are applied. The multiplication-accumulation calculation results of positive and negative numbers can be divided into four parts, so that each part can be accumulated separately during the calculation process. Finally, the difference between two calculation capacitors is quantified to calculate the final result, reducing the large number of cross switches introduced by traditional analog signed numbers in the calculation unit, saving the calculation cycle, and further realizing in-memory calculation of signed data MAC with lower time, area, and power consumption overhead, solving the problem of low multiplication-accumulation calculation efficiency of the current signed number multiply-accumulation operation circuit.

[0104] In this embodiment, a CIM chip is also provided, which integrates the signed number multiply-accumulation operation circuit provided in this embodiment.

[0105] In this embodiment, an electronic device is also provided, which is built-in with the CIM chip provided in this embodiment and realizes the convolutional operation of deep learning through this CIM chip.

[0106] It should be understood that the specific embodiments described here are only used to explain this application, rather than to limit it. According to the embodiments provided in this application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of this application.

[0107] Obviously, the drawings are only some examples or embodiments of this application. For those of ordinary skill in the art, this application can also be applied to other similar situations based on these drawings without creative work. In addition, it can be understood that although the work done during the development process here may be complex and time-consuming, for those of ordinary skill in the art, some design, manufacturing, or production changes based on the technical content disclosed in this application are only conventional technical means and should not be regarded as insufficient disclosure of this application.

Claims

1. A signed number multiply-accumulate operation circuit, characterized in that, Including: A weight storage array, which includes a number of storage modules distributed in rows and columns. Each storage module includes a storage cell and NMOS transistors N5 and N6. The gate and drain of N5 are respectively connected to the storage node QB of the storage cell and the source of N6. The source of N5 in the same column is connected to the same bit line BL. The gate of N6 in the same row is connected to the same calculation word line IWL. The drain of N6 in the same column is connected to the same source line SL. The bit line BL is also connected to a reference voltage, and the source line SL is also connected to the ground terminal VSS. For multi-bit weights W are encoded to form w =2 W +1 and then stored row by row in the weight storage array; A plurality of input encoding circuits respectively corresponding to each row storage module. The output of each input encoding circuit is fed into the corresponding row's computing word line IWL. The input encoding circuit encodes each bit of the n-bit input in sequence and feeds the encoding result into the computing word line IWL. The encoding method is as follows: Among them, a i represents the output of the i-th encoding of the input encoding circuit, A n-1 ...A 2 A 1 A 0 represents an n-bit input, A n-1 is the sign bit, A n-2 ...A 2 A 1 A 0 are the digit bits; A plurality of voltage clamping current mirror circuits respectively corresponding to each column storage module. Each voltage clamping current mirror circuit includes a first voltage clamping circuit and two first current mirror circuits. The output of the first voltage clamping circuit is the input of the two current mirror circuits. The outputs of the two first current mirror circuits are grounded through a first capacitor and a second capacitor respectively. The input of the first voltage clamping circuit is the bit line BL of the corresponding column. The capacitance difference between the first capacitor and the second capacitor is used to represent the multiply-accumulate result; The input encoding circuit includes an inverter, two AND gates, and a multiplexer; the input signal X and the clock signal CLK are connected to the multiplexer through one of the AND gates, and the inverted signal of the input signal X and the clock signal CLK are connected to the multiplexer through the other AND gate. The control terminal of the multiplexer is connected to the sign bit A n-1 , and the input signal X is A n-2 ...A 2 A 1 A one of 0. The inverted signal of the input signal X is obtained by inverting through the inverter. The output terminal of the multiplexer is connected to the computational word line IWL.

2. The signed number multiply-accumulate operation circuit according to claim 1, wherein There is a storage module in the weight storage array where a column of storage nodes QB is always 1, which is defined as a redundant column; The signed number multiply-accumulate operation circuit further includes: A plurality of compensation circuits respectively corresponding to each column storage module, which includes two second current mirror circuits. The outputs of the two second current mirror circuits are respectively coupled to the outputs of the two first current mirror circuits; A second voltage clamping circuit, whose output is the input of the two second current mirror circuits, and whose input is the bit line BL of the redundant column.

3. The signed number multiply-accumulate operation circuit according to claim 2, wherein Both the first current mirror circuit and the second current mirror circuit are composed of two PMOS transistors, and the size of the PMOS transistors in the first current mirror circuit is twice the size of the PMOS transistors in the second current mirror circuit.

4. The signed number multiplication and accumulation operation circuit according to claim 1, wherein The storage unit is a 6T storage unit, and the 6T storage unit includes PMOS transistors P1 and P2 and NMOS transistors N1, N2, N3, and N4; The sources of P1 and P2 are connected to VDD; the drain of P1 is connected to the gates of P2 and N2 and the drains of N1 and N3, and serves as the storage node QB; the drain of P2 is connected to the gates of P1, N1, and N5 and the drains of N2 and N4, and serves as the inverted storage node Q; the sources of N3 and N5 are connected to the bit line BL; the source of N4 is connected to the bit line BLB; the gates of N3 and N4 are connected to the word line WL; the drain of N5 is connected to the source of N6; the gate of N6 is connected to IWL, and the drain of N6 is connected to the source line SL.

5. The signed number multiply-accumulate operation circuit according to claim 1, wherein The output of the input encoding circuit is a bidirectional pulse signal; When the first stage of the bidirectional pulse signal is high level and the second stage is low level, it represents +1; When the first stage of the bidirectional pulse signal is low level and the second stage is high level, it represents -1; When both the first stage and the second stage of the bidirectional pulse signal are low level, it represents 0.

6. The signed multiplication and accumulation operation circuit according to claim 1, characterized in that Both the first capacitor and the second capacitor are connected in parallel with a plurality of auxiliary capacitors, and the size of the auxiliary capacitors is the same as that of the computing capacitor; When the encoding results of different bits are fed into the computing word line IWL, the number of enabled auxiliary capacitors is different, so that the charges accumulated by the first capacitor and the second capacitor during the feeding period have weights corresponding to the number of bits of the encoding result.

7. The signed number multiplication and accumulation operation circuit according to claim 1, wherein The multiply-accumulate result is obtained by comparing the voltages of the first capacitor and the second capacitor fed into the sense amplifier.

8. A CIM chip, characterized in that, Integrated with the signed number multiply-accumulate operation circuit described in any one of claims 1-7, and the CIM chip is an in-memory computing chip.

9. An electronic device, characterized in that, It is built-in with the CIM chip described in claim 8, and realizes the convolutional operation of deep learning through this CIM chip.

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