Matrix processing circuit, method, device and system

Abstract

The invention provides a matrix processing circuit, method, device and system, and relates to the field of matrix processing, and the circuit comprises a control module which is connected with a register block module and a data selector, and the register block module is connected with a transposition module. The transpose module can convert the received matrix data into transpose matrix data and send the transpose matrix data to the register block module, so that the matrix processing circuit can complete storage of the matrix data and can also complete storage of the transpose matrix data. The control module can determine to write the matrix data or the transposed matrix data into the target register block according to the input data enable signal and can also output a selection signal to the data selector, and the selection signal can enable the data selector to determine to read the matrix data or the transposed matrix data in the target register block. Therefore, the matrix processing circuit provided by the invention can achieve the effect of supporting efficient carrying of a common matrix and a transposed matrix.

Description

Technical Field

[0001] The present application relates to the field of matrix handling, and in particular to a matrix processing circuit, method, device and system. Background Art

[0002] Transformer is a model architecture used in the field of Natural Language Processing (NLP). It is widely used in tasks such as translation, summarization, question-answering, and dialogue. Therefore, it has been widely used in the fields of neural machine translation and natural language understanding, and has achieved good results. Transformer does not need to process the input sequence sequentially like traditional recurrent neural networks (RNN) or convolutional neural networks (CNN). Instead, it uses a method based on the attention mechanism to process each word in the input sequence at the same time, thereby greatly improving the computational efficiency and parallel processing capabilities. Therefore, Transformer is not only used in the field of NLP, but can also be applied to image processing, speech recognition, and many other fields.

[0003] There are a lot of matrix calculations in Transformer. Currently, artificial intelligence (AI) processors generally support matrix operations, so it is particularly important to move matrices efficiently. Summary of the invention

[0004] The present application provides a matrix processing circuit, method, device and system for efficiently supporting the transfer of ordinary matrices and transposed matrices.

[0005] The technical solution is as follows:

[0006] In a first aspect, a matrix processing circuit is provided, the circuit comprising: a transposition module, a control module, a register group module and a data selector.

[0007] The control module is connected to the register group module and the data selector respectively, and the register group module is also connected to the transposition module.

[0008] The transposition module is used to process the received matrix data into transposed matrix data.

[0009] The register group module includes multiple register groups, and the multiple register groups are used to store matrix data or transposed matrix data.

[0010] The control module is used to control the register group module to write the matrix data or the transposed matrix data into the target register group among the multiple register groups according to the input data enable signal. The control module is also used to output a selection signal to the data selector.

[0011] The data selector is used to read out the matrix data or transposed matrix data stored in the target register group according to the selection signal.

[0012] In the matrix processing circuit of the present application, it includes: a transposition module, a control module, a register group module and a data selector. The control module is connected to the register group module and the data selector respectively, and the register group module is also connected to the transposition module. The transposition module can convert the received matrix data into transposed matrix data and send it to the register group module, so the matrix processing circuit can complete the storage of matrix data and the storage of transposed matrix data. Since the control module can determine to write the matrix data or transposed matrix data into the target register group according to the input data enable signal, it can also output a selection signal to the data selector, and the selection signal can enable the data selector to determine to read the matrix data or transposed matrix data in the target register group, so the transportation of the matrix data or transposed matrix data can be completed, so the matrix processing circuit of the present application can achieve the effect of supporting the efficient transportation of ordinary matrices and transposed matrices.

[0013] In a possible implementation of the present application, when matrix data needs to be transposed, and the format of the matrix data is that the number of rows and the number of columns are not equal, the register group module is used to write the spliced ​​transposed matrix data multiple times, and the multiple spliced ​​transposed matrix data constitute the transposed matrix data. The data selector is used to read out the spliced ​​transposed matrix data multiple times.

[0014] In a possible implementation of the present application, the control module includes an input control module, an output control module, a first register and a second register. The input control module is connected to the first register and the second register, and is used to control the first register or the second register to send a first indication information to the register group module according to an input data enable signal. The first indication information is used to instruct the register group module to write matrix data or transposed matrix data into a target register group. The input control module is also used to control the first register and the second register to send an output data enable signal to the output control module according to the input data enable signal. The output control module is connected to the first register and the second register, and is used to control the first register or the second register to send a second indication information to a data selector according to the output data enable signal. The second indication information is used to instruct the data selector to read out the matrix data or transposed matrix data in the target register group.

[0015] In a possible implementation of the present application, the input control module is connected to the register group module and is used to output a write enable signal to the register group module. The write enable signal is used to determine the target register group for writing matrix data or transposing matrix data. The output control module is connected to the data selector and is used to output a selection signal to the data selector, and the selection signal is used to determine the target register group for reading matrix data or transposing matrix data.

[0016] In a possible implementation of the present application, the input control module or the output control module includes a control counter, a pipeline number, a flag register and an output register. The control counter and the flag register are connected to the output register, and the output register is used to send a write enable signal to the register group module, or send a selection signal to the data selector according to the value of the control counter and the status bit of the flag register. The control counter is used to receive an input data enable signal or an output data enable signal, and when the input data enable signal or the output data enable signal is a first signal, the control counter increases a first preset value. When the value of the control counter is equal to the difference between the pipeline number and the second preset value, the pipeline number is used to reset the control counter to zero, and to control the flag bit of the flag register to flip. The flag bit of the flag register is used to control the first register or the second register to indicate the write / read mode of the matrix data or the transposed matrix data in the target register.

[0017] In a possible implementation of the present application, when the flag register in the input control module is a first signal, the first register indicates that the matrix data or the transposed matrix data is written to the target register in a first manner. When the flag register in the input control module is a second signal, the second register indicates that the matrix data or the transposed matrix data is written to the target register in a second manner. When the flag register in the output control module is a first signal, the first register indicates that the matrix data or the transposed matrix data in the target register is read out in a first manner. When the flag register in the output control module is a second signal, the second register indicates that the matrix data or the transposed matrix data in the target register is read out in a second manner.

[0018] In a second aspect, an embodiment of the present application provides a matrix processing method, which is applied to a matrix processing circuit, and the method includes: a control module receives an input data enable signal. The control module controls the matrix data or the transposed matrix data processed by the transposition module of the matrix processing circuit to be written into a target register group according to the input data enable signal. The control module outputs a selection signal to a data selector in the matrix processing circuit to control the data selector to read out the matrix data or the transposed matrix data in the target register.

[0019] In the matrix transport method of the present application, the matrix processing circuit receives a data enable signal, the control module writes the matrix data or the transposed matrix data into the target register group according to the input data enable signal, and outputs a selection signal to the data selector, and the data selector reads the matrix data or the transposed matrix data in the target register group according to the selection signal. Because the control module selects the target register group, there is no efficiency loss in the transport of the transposed matrix, so the matrix processing circuit of the present application can achieve the effect of supporting the efficient transport of ordinary matrices and transposed matrices.

[0020] In a possible implementation of the present application, the method provided by the embodiment of the present application further includes: when the matrix data needs to be transposed, and the format of the matrix data is that the number of rows and the number of columns are not equal, the control module controls the register group module to write the spliced ​​transposed matrix data multiple times. Multiple spliced ​​transposed matrix data constitute the transposed matrix data. The control module controls the data selector to read out the spliced ​​transposed matrix data multiple times.

[0021] In a third aspect, an embodiment of the present application provides a matrix processing device, which includes the above-mentioned matrix processing circuit.

[0022] In a fourth aspect, an embodiment of the present application provides a matrix processing system, the system comprising a storage module, a computing module, and a matrix processing device as described in the third aspect above.

[0023] Among them, the storage module is used to store matrix data, the matrix processing device is used to transfer the matrix data or the transposed matrix data converted from the matrix data to the calculation module, and the calculation module is used to operate on the matrix data or the transposed matrix data.

[0024] In a fifth aspect, an embodiment of the present application provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the matrix processing method as described in any one of the second aspects is implemented.

[0025] In a sixth aspect, an embodiment of the present application provides a storage medium, wherein the storage medium stores a computer program, and when the computer program is executed by a processor, the matrix processing method as described in the second aspect is implemented.

[0026] It can be understood that the beneficial effects of the second, third, fourth and fifth aspects can be found in the relevant description of the first aspect above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0028] Figure 1 It is a schematic diagram of a matrix processing circuit structure provided in an embodiment of the present application;

[0029] Figure 2 is a specific structural diagram of a matrix processing circuit provided in an embodiment of the present application;

[0030] Figure 3 It is a schematic diagram of splicing matrix data provided in an embodiment of the present application;

[0031] Figure 4 This is a schematic diagram of an input and output data pipeline provided by an embodiment of the present application;

[0032] Figure 5 is a schematic diagram of a data selector structure provided in an embodiment of the present application;

[0033] Figure 6 It is a structural schematic diagram of a matrix processing circuit and a control module provided in an embodiment of the present application;

[0034] Figure 7 is a specific structural diagram of a control module provided in an embodiment of the present application;

[0035] Figure 8 It is a flowchart of a matrix processing method provided in an embodiment of the present application;

[0036] Fig. 9 It is a structural schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0038] It should be understood that the "multiple" mentioned in this application refers to two or more. In the description of this application, unless otherwise specified, " / " means or, for example, A / B can mean A or B; "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in order to facilitate the clear description of the technical solution of this application, the words "first" and "second" are used to distinguish between the same items or similar items with basically the same functions and effects. Those skilled in the art can understand that the words "first" and "second" do not limit the quantity and execution order, and the words "first" and "second" do not limit them to be different.

[0039] Before explaining the embodiments of the present application in detail, the application scenarios of the embodiments of the present application are first described.

[0040] Matrix operations include ordinary matrix operations and transposed matrix operations. Matrix operations are generally completed through computing units. Before the operation, there is a process of moving the matrix to the computing unit. Usually, the matrix data corresponding to the matrix is ​​moved to the computing unit in a fixed storage format. However, since matrix calculations involve both ordinary matrices and transposed matrices, the matrix moving efficiency is low. Therefore, how to efficiently move normal matrices and transposed matrices is a problem that needs to be solved.

[0041] Based on the above problems, the present application proposes a matrix processing circuit, which determines the registers that need to be read and the registers that need to be written in the splicing register group module through the write enable signal and the read enable signal output by the control module, so that efficient transportation can be achieved when transporting ordinary matrices and transposed matrices.

[0042] A matrix processing circuit provided in an embodiment of the present application is explained in detail below.

[0043] Figure 1 A matrix processing circuit is provided, comprising: a transposition module 101, a control module 102, a register group module 103 and a data selector 104. The control module 102 is connected to the register group module 103 and the data selector 104 respectively, and the register group module 103 is also connected to the transposition module 101.

[0044] Among them, the transposition module 101 is used to process the received matrix data into transposed matrix data, and send the transposed matrix data to the register group module 103. The register group module 103 includes multiple register groups, and the multiple register groups are used to store matrix data or transposed matrix data. The control module 102 is used to determine whether to write the matrix data or transposed matrix data into the target register group according to the input data enable signal, and the control module 102 is also used to output a selection signal to the data selector 104. The data selector 104 is used to read out the matrix data or transposed matrix data in the target register group according to the selection signal.

[0045] In a possible implementation of the present application, the register group module 103 includes multiple input terminals, such as three input terminals, such as a first input terminal, a second input terminal and a third input terminal. The first input terminal of the register group module 103 is connected to the output terminal of the transposition module 101. The second input terminal of the register group module 103 is used to receive matrix data. The third input terminal of the register group module 103 is connected to the first output terminal of the control module 102.

[0046] The input end of the transposition module 101 is used to receive matrix data. The output end of the transposition module 101 is connected to the first input end of the register group module 103. The transposition module 101 is used to convert the matrix data received by the input end into transposed matrix data, and store the transposed matrix data in the register group module 103 through the output end of the transposition module 101.

[0047] The first input terminal of the control module 102 is used to receive an input data enable signal. The first output terminal of the control module 102 is connected to the third input terminal of the register group module 103 .

[0048] The second output terminal of the control module 102 is connected to the first input terminal of the data selector 104. The output terminal of the register group module 103 is connected to the second input terminal of the data selector 104. The output terminal of the data selector 104 is used to output matrix data or transposed matrix data.

[0049] Among them, matrix data is usually expressed as R×C, where R represents the rows of the matrix and C represents the columns of the matrix. When the matrix is ​​transposed, the rows and columns are exchanged, and the format of the transposed matrix is ​​C×R.

[0050] For example, take matrix A as a matrix of 3 rows×4 columns. The transposition module 101 transposes matrix A to obtain matrix B, which is a matrix of 4 rows×3 columns.

[0051] It can be understood that matrix data is different from the matrix format R×C. Matrix data is usually stored in a fixed format. For example, the storage format of matrix data is R1×C×R0, where R1 represents the ratio of the number of matrix rows to the preset number of rows rounded upward, that is, R1=ceil(R / R0), and R0 represents the preset number of rows.

[0052] For example, matrix C is a matrix of 3 rows × 4 columns, and the preset number of rows R0 is 2. The storage format of the matrix data of matrix C is ceil(3 / 2)×4×2=2×4×2, which can be understood as dividing the matrix C into two matrices of 2 rows and 4 columns for storage. The first matrix is ​​the first 2 rows of data of matrix C, and the second matrix is ​​the 3rd row of data.

[0053] It is worth noting that the preset number of rows R0 may be 1. When the preset number of rows R0 is equal to 1, the storage format of the matrix data is the same as the matrix format.

[0054] Among them, the control module 102 is used to control the register group module 103 to write the received matrix data (for example, the third input end of the register group module 103 receives the matrix data) or the transposed matrix data (for example, the first input end of the register group module 103 receives the transposed matrix data) into the target register group among the multiple register groups according to the input data enable signal.

[0055] For example, the register group module 103 includes multiple register groups. After the matrix data or transposed matrix data is written, it can occupy any number of register groups. For example, it can occupy only one register group, and the register group is the target register group. It can also occupy all register groups, and all register groups are target register groups.

[0056] The number of register groups in the register group module 103 depends on the capability of the computing unit connected to the matrix processing circuit.

[0057] For example, the calculation unit can simultaneously perform the operation of matrix A×matrix B, matrix A is a matrix of X rows and Y columns, and matrix B is a matrix of Y rows and Z columns. The storage format of matrix data is generally R0=Y. After the matrix data is written into the register group module 103, for matrix A, if it is necessary to transpose matrix A, it can be directly transmitted. If it is necessary to non-transpose matrix A, it is necessary to set multiple register groups in the register group module 103 for splicing and transmission. For matrix B, if it is necessary to non-transpose matrix B, it can be directly transmitted. If it is necessary to transpose matrix B, it is necessary to set multiple register groups in the register group module 103 for splicing and transmission.

[0058] Optionally, the second input end of the register group module 103 and the first input end of the splicing register group module 103 may also be the same port.

[0059] For example, when the matrix data needs to be transposed, the transposition module 101 transposes the matrix data and then sends the transposed matrix data to the first input terminal of the register group module 103; when the matrix data does not need to be transposed, the matrix data is sent to the first input terminal of the register group module 103. It can be understood that the register group module 103 can receive the matrix data or the transposed matrix data from one input terminal or from two different input terminals, which is not limited here.

[0060] The data selector 104 may be a multiple-to-one selector, such as an 8-to-1 selector, a 4-to-1 selector, etc., which is specifically determined according to the number of register groups in the register group module 103 .

[0061] For example, there are 4×4 register groups in the register group module 103 , and there are 8 situations when the matrix data or transposed matrix data is read out, including 4 horizontal situations and 4 vertical situations, so the data selector 104 needs an 8-to-1 selector.

[0062] In the matrix processing circuit of the present application, it includes: a transposition module 101, a control module 102, a register group module 103 and a data selector 104. The control module 102 is connected to the register group module 103 and the data selector 104 respectively, and the register group module 103 is also connected to the transposition module 101. The transposition module 101 can convert the received matrix data into transposed matrix data and send it to the register group module 103, so the matrix processing circuit can complete the storage of matrix data and the storage of transposed matrix data. Since the control module 102 can determine to write the matrix data or transposed matrix data into the target register group according to the input data enable signal, it can also output a selection signal to the data selector 104, and the selection signal can make the data selector 104 determine to read out the matrix data or transposed matrix data in the target register group, so the transportation of the matrix data or transposed matrix data can be completed, so the matrix processing circuit of the present application can achieve the effect of supporting the efficient transportation of ordinary matrices and transposed matrices.

[0063] In one implementation of the present application, when matrix data needs to be transposed and the format of the matrix data is that the number of rows and the number of columns are not equal, the register group module is used to write the spliced ​​transposed matrix data multiple times, and the multiple spliced ​​transposed matrix data constitute the transposed matrix data, and the data selector is used to read out the spliced ​​transposed matrix data multiple times.

[0064] As an example, when the matrix data needs to be transposed and the storage format is N=R0, the data selector 104 directly reads the transposed matrix data in the target register in the register group module 103. When the matrix data needs to be transposed and the storage format is N!=R0, the transposed matrix data needs to be spliced, and the control module 102 reads out a plurality of spliced ​​transposed matrix data in sequence by controlling the data selector 104, and then splices the plurality of spliced ​​transposed matrix data into the transposed matrix data.

[0065] The following describes several matrix processing situations that can be performed by the matrix processing circuit, taking the example that the calculation module connected to the matrix processing circuit can perform a matrix multiplication operation of R0 row × N column per clock cycle:

[0066] Case 1: The matrix needs to be moved but does not need to be transposed. The storage format of the matrix data is N×R0. The matrix data is transmitted to the register group module 103. The control module 102 does not need to select the target register group. The matrix data is directly written into the register group (such as register group 0_x) in the register group module 103. Then the control module 102 enables the data selector 104 to read out the matrix data through the selection signal, and the format is N×R0.

[0067] Case 2: The matrix needs to be moved and transposed. The storage format of the matrix data is N×R0, and N=R0. First, the matrix data is transmitted to the transposition module 101, and the transposition module 101 is used to transform the matrix data into transposed matrix data. The storage format of the transposed matrix data is R0×N. Since N=R0, the transposed matrix data is transmitted to the register group module 103. The control module 102 does not need to select the target register group. The transposed matrix data is written into the register group (such as register group 0_x) in the register group module 103. Then, the control module 102 enables the data selector 104 to read the transposed matrix data through the selection signal, and the format is R0×N.

[0068] Case 3: The matrix needs to be moved and transposed. The storage format of the matrix data is N×R0, and N!=R0. Since the storage of the matrix in the previous storage does not meet the requirement of one-time transposition, splicing is required.

[0069] As an example, taking R0×4=N as an example, the register group in the register group module 103 is as follows: Figure 2 shown.

[0070] First, the storage format of the matrix data is N×R0, which is transmitted to the transposition module 101. The transposition module 101 is transposed to become transposed matrix data, and the storage format is R0×N. The transposed matrix data is transmitted to the register group module 103. The control module 102 determines to write the spliced ​​transposed matrix data into the register group 0_x, 1_x, 2_x, and 3_x according to the input data enable signal. After 4 cycles, 4×N rows and 4×R0 columns of data are obtained, such as Figure 3 shown.

[0071] Secondly, the control module 102 outputs a selection signal to the data selector 104, so that the data selector 104 reads out the concatenated transposed matrix data in the register groups 0_x, 1_x, 2_x, and 3_x, and writes the transposed matrix data into the register groups x_0, x_1, x_2, and x_3 when reading out the data.

[0072] Finally, the control module 102 outputs a selection signal to the data selector 104, so that the data selector 104 reads out the concatenated transposed matrix data of the register groups 0_x, 1_x, 2_x, and 3_x, and writes the data into the register groups 0_x, 1_x, 2_x, and 3_x when reading out the data. The transposed matrix data can be obtained by repeating the above steps.

[0073] Figure 4 This is a pipeline for input data (matrix data) and output data (second transposed matrix data). As can be seen from the figure, except for the delay of one clock cycle at the beginning, the other clock cycles are used to read in and write out data at the same time, and there is no loss in efficiency.

[0074] Among them, the data selector 104 is as follows Figure 5 As shown, the read data includes Regfile0_x, Regfile1_x, Regfile2_x, Regfile3_x, Regfilex_0, Regfilex_1, Regfilex_2, and Regfilex_3.

[0075] Figure 6 A schematic diagram of the circuit structure of the control module 102 provided in the embodiment of the present application is shown in FIG. Figure 6As shown, the control module includes an input control module 601, an output control module 602, a first register 603 and a second register 604. The input control module 601 is connected to the first register 603 and the second register 604, and is used to control the first register 603 and the second register 604 to send a first indication information to the register group module 103 according to the input data enable signal. The first indication information is used to instruct the register group module 103 to write the matrix data or the transposed matrix data into the target register group. The input control module 601 is also used to control the first register 603 and the second register 604 to send an output data enable signal to the output control module 602 according to the input data enable signal. The output control module 602 is connected to the first register 603 and the second register 604, and is used to control the first register 603 or the second register 604 to send a second indication information to the data selector 104 according to the output data enable signal. The second indication information is used to instruct the data selector 104 to read out the matrix data or the transposed matrix data in the target register group.

[0076] As an example, the input control module 601 controls the first register 603 and the second register 604 to be set to 1. When the first register 603 or the second register 604 is 1, the first register 603 or the second register 604 outputs an output data enable signal.

[0077] The first register 603 and the second register 604 respectively indicate two ways of writing / reading matrix data or transposed matrix data. For example, the first register 603 indicates that the matrix data or transposed matrix data is written / read vertically, and the second register 604 indicates that the matrix data or transposed matrix data is written / read horizontally.

[0078] For example, the input control module 601 receives an input data enable signal, and according to the input data enable signal, sets the first register 603 to 1, and after the first register 603 is set to 1, sends the first indication information to the register group module 103, which is used to indicate that the matrix data is written into the target register in a vertical writing manner. At the same time, since the first register 603 is set to 1, the first register 603 sends an output data enable signal to the output control module 602, and the output control module 602 sets the second register to 0 according to the output data enable signal, and after the second register 604 is set to 0, sends the second indication information to the register group module 103, which is used to indicate that the matrix data is read out in a horizontal reading manner.

[0079] In the above embodiment, the premise that the first register 603 or the second register 604 indicates the writing / reading of matrix data or transposed matrix data is to know which register groups are to be written or read from. Therefore, the register group module 103 and the data selector 104 also need to receive a write enable signal and a selection signal to determine which register groups the matrix data or transposed matrix data are to be written into or from which register groups the matrix data or transposed matrix data are to be read.

[0080] In one embodiment of the present application, Figure 6 As shown, the input control module 601 is connected to the register group module 103, and is used to output a write enable signal to the register group module 103. The write enable signal is used to determine the target register group for writing matrix data or transposing matrix data. The output control module 602 is connected to the data selector 104, and is used to output a selection signal to the data selector 104. The selection signal is used to determine the target register group for reading matrix data or transposing matrix data.

[0081] It can be understood that the write enable signal has been sent to the register group module 103. When the input control module 601 does not receive the input data enable signal, although the register group module 103 determines the target register group to write data, it does not receive the instruction to write and will not write. Similarly, the selection signal has been sent to the data selector 104. When the output control module 602 does not receive the output data enable signal, although the data selector 104 determines the target register group to read data, it does not receive the instruction to read and will not.

[0082] In one embodiment of the present application, the input control module 601 or the output control module 602 includes a control counter, a pipeline number, a flag register and an output register. The control counter and the flag register are connected to the output register. The output register is used to send a write enable signal to the register group module 103, or send a selection signal to the data selector 104 according to the value of the control counter and the status bit of the flag register. When the input data enable signal or the output data enable signal is a first signal, the control counter increases the first preset value. When the value of the control counter is equal to the difference between the pipeline number and the second preset value, the pipeline number is used to reset the control counter to zero, and to control the flag bit of the flag register to flip. The flag bit of the flag register is used to control the first register or the second register to indicate the matrix data or transposed matrix data write / read mode in the target register.

[0083] The output end of the output register is connected to the register group module 103 or the data selector 104. The input end of the control counter receives the input data enable signal or the output data enable signal, the output end is connected to the input end of the pipeline stage, the output end of the pipeline stage is connected to the input end of the flag register, the first output end of the flag register is connected to the first register 603, and the second output end is connected to the second register 604.

[0084] Among them, the counter is used for adding and subtracting counts. For example, when the counter receives a high level signal, the counter increases by 1. The pipeline stage is used to control the level signal of the flag register.

[0085] In a possible implementation of the present application, Figure 7 As shown, the input control module 601 includes an input control counter 6011 , a first pipeline stage 6012 , a write direction flag register 6013 and a first output register 6014 .

[0086] The input control counter 6011 and the write direction flag register 6013 are connected to the first output register 6014 , and the first output register 6014 is connected to the register group module 103 for outputting a write enable signal according to the value of the input control counter 6011 and the status bit of the write direction flag register 6013 .

[0087] As an example, the first output register 6014 is a write enable register, and the write enable register is a multi-bit register.

[0088] For example, Figure 2 Taking the register group module 103 in as an example, when the first pipeline stage number is set to 4, the register write enable signal output by the write enable register is as shown in Table 1.

[0089] Table 1

[0090]

[0091] For example, when the write direction flag register 6013 is 0 and the input control counter 6011 is 0, the state of the write enable register is shown in the second row of Table 1, indicating that the target register group is register group 0_0, register group 0_1, register group 0_2, and register group 0_3. When the write direction flag register 6013 is 1 and the value of the input control counter 6011 is 0, the state of the write enable register is shown in the sixth row of Table 1, indicating that the target register group is register group 0_3, register group 1_3, register group 2_3, and register group 3_3. And so on, other examples are not repeated here.

[0092] For example, take the first preset value as 1 and the second preset value as 1 as an example. Figure 7As shown, when the input data enable signal is a high-level signal, the value of the input control counter 6011 is increased by 1. When the value of the input control counter 6011 is equal to the first pipeline stage number 6012 minus 1, the value of the input control counter 6011 is set to 0, and the flag bit of the write direction flag register 6013 is flipped.

[0093] In a possible implementation of the present application, Figure 7 As shown, the output control module 602 includes an output control counter 6021 , a second pipeline stage 6022 , a read direction flag register 6023 and a second output register 6024 .

[0094] The output control counter 6021 and the read direction flag register 6023 are connected to the second output register 6024 , and the second output register 6024 is connected to the data selector 104 for outputting a selection signal according to the value of the output control counter 6021 and the status bit of the read direction flag register 6023 .

[0095] For example, the data selector 104 is Figure 5 The 8-to-1 data selector shown in the figure takes the pipeline number of 4 as an example, and the selection signal sent by the output control module 602 to the data selector 104 is shown in Table 2:

[0096] Table 2

[0097] Read direction flag register Output Control Counter Register output data selection signal 0 0 4 0 1 5 0 2 6 0 3 7 1 0 0 1 1 1 1 2 2 1 3 3

[0098] For example, when the read direction flag register 6023 is 0 and the output control counter 6021 is 0, the selection signal output by the second register 6024 is 4, indicating that the data selector selects the register group of the fifth row to read out the matrix data or transpose the matrix data, that is, register group 3_0, register group 2_0, register group 1_0, register group 0_0. And so on, other examples are not repeated here.

[0099] For example, take the first preset value as 1 and the second preset value as 1 as an example. Figure 7 As shown, Figure 7 As shown, when the output data enable signal is a high-level signal, the output control counter 6021 in the output control module 602 is increased by 1. When the value of the output control counter 6021 is equal to the second pipeline stage number 6022 minus 1, the output control counter 6021 is set to 0 and the flag bit of the read direction flag register 6023 is flipped.

[0100] The first pipeline stage 6012 or the second pipeline stage 6022 may be set according to whether matrix data or transposed matrix data need to be spliced.

[0101] As an example, when the transported matrix data does not need to be spliced, the pipeline stage number 606 is set to 1, and there is no need to switch the flag register, that is, one register group is always written and one register group is always read in the register group module 103.

[0102] As another example, when the transported matrix data needs to be spliced, the pipeline number is set according to the splicing needs. Taking Case 3 in the above embodiment as an example, the maximum pipeline number can be set to 4.

[0103] It is worth noting that when the first register 603 is high or the second register 604 is high, and the input control counter 6011 is equal to the first pipeline stage number 6012 minus 1, the first register 603 or the second register 604 outputs a feedback signal, and the feedback signal is used to reverse the previous stage.

[0104] The back pressure front stage indicates that the front stage module does not send data to the matrix processing circuit. It is understandable that if the back stage module (the computing module connected to the matrix processing circuit) is blocked, causing the matrix processing circuit to be unable to send data, the control module 102 sends a feedback signal.

[0105] As an example, Figure 7 As shown, when the first register 603 is 1 or the second register 604 is 1, and the input control counter 6011 minus 1 is equal to the first pipeline stage number 6012, a feedback signal is output to indicate that the register is fully loaded (for example, the feedback signal is Regfile_full=1), which back-pressures the previous stage.

[0106] In one embodiment of the present application, when the flag register in the input control module 601 is a first signal, the first register 603 indicates that the matrix data or the transposed matrix data is written to the target register in a first manner. When the flag register in the input control module 601 is a second signal, the second register indicates that the matrix data or the transposed matrix data is written to the target register in a second manner.

[0107] As an example, when the write direction flag register 6013 is 1 (first signal), the first register 603 is controlled to indicate that the matrix data or transposed matrix data is written into the target register in a horizontal writing manner (first manner). When the write direction flag register 6013 is 0 (second signal), the second register 604 is controlled to indicate that the matrix data or transposed matrix data is written into the target register in a vertical writing manner (second manner).

[0108] For example, combining Figure 2 and Figure 7, wherein the register group module 103 includes register group 0_x (register group 0_0, register group 0_1, register group 0_2, register group 0_3), register group 1_x (register group 1_0, register group 1_1, register group 1_2, register group 1_3), register group 2_x (register group 2_0, register group 2_1, register group 2_3, register group 2_3), register group 3_x (register group 3_0, register group 3_1, register group 3_2, register group 3_3). When the write direction flag register 6013 is 1, the first register 603 is controlled to instruct the register group module 103 to write matrix data or transpose matrix data vertically, for example, the matrix data is written into the register group in the order of register group 0_3, register group 1_3, register group 2_3, and register group 3_3. When the write direction flag register 6013 is 0, the second register 604 is controlled to instruct the register group module 103 to write matrix data horizontally or transpose matrix data. For example, the register group module 103 writes matrix data into register group 0_0, register group 0_1, register group 0_2, and register group 0_3.

[0109] In one embodiment of the present application, when the flag register in the output control module 602 is a first signal, the first register 603 indicates that the matrix data or the transposed matrix data in the target register is read out in a first manner. When the flag register in the output control module 602 is a second signal, the second register 604 indicates that the matrix data or the transposed matrix data in the target register is read out in a second manner.

[0110] As an example, Figure 7 As shown, when the read direction flag register 6023 is 1 (first signal), the first register 603 is controlled to indicate that the matrix data or transposed matrix data is read out from the target register in a horizontal manner (first manner). When the read direction flag register 6023 is 0 (second signal), the second register 604 is controlled to indicate that the matrix data or transposed matrix data is read out from the target register in a vertical manner (second manner).

[0111] For example, combining Figure 2 and Figure 7When the read direction flag register 6023 is 1, the data selector 104 is instructed to read out the matrix data horizontally or transpose the matrix data. For example, the data selector 104 reads out the matrix data in register group 0_0, register group 0_1, register group 0_2, and register group 0_3 in sequence. When the read direction flag register 6023 is 0, the second register 604 is controlled to instruct the data selector 104 to read out the matrix data vertically or transpose the matrix data. For example, the data selector 104 reads out the matrix data in register group 0_0, register group 1_0, register group 2_0, and register group 3_0 in sequence.

[0112] Figure 8 A schematic diagram of a flow chart of a matrix processing method provided in an embodiment of the present application, the method is applied to a matrix processing circuit. The method provided in an embodiment of the present application includes:

[0113] Step 801: The control module receives an input data enable signal.

[0114] Step 802: The control module determines to write the matrix data or the transposed matrix data into the target register group according to the input data enable signal, and outputs a selection signal to the data selector.

[0115] The target register group is one or more register groups in the register group module.

[0116] As an example, the control module receives an input data enable signal and sends a register group write enable signal to the register group module, and the register group write enable signal is used to determine a target register group.

[0117] As an example, the control module receives an input data enable signal and sends a selection signal to the data selector to determine whether the data selector reads out the matrix data or the transposed matrix data in the target register.

[0118] Step 803: The control module outputs a selection signal to a data selector in the matrix processing circuit to control the data selector to read out the matrix data or transposed matrix data in the target register.

[0119] As an example, the control module receives an input data enable signal and sends a selection signal to the data selector to determine whether the data selector reads out the matrix data or the transposed matrix data in the target register.

[0120] The transposition of the matrix data is implemented by a transposition module in the matrix processing circuit. The specific implementation method is referred to the above embodiment and will not be described in detail here.

[0121] In one embodiment of the present application, the method provided by the embodiment of the present application also includes: when matrix data needs to be transposed, and the format of the matrix data is that the number of rows and the number of columns are not equal, controlling the data selector in the matrix processing circuit to read out multiple spliced ​​transposed matrix data, and the multiple spliced ​​transposed matrix data constitute transposed matrix data.

[0122] The specific embodiments are described with reference to the above embodiments and will not be described in detail here.

[0123] An embodiment of the present application provides a matrix processing device, which includes the matrix processing circuit described in the above embodiment.

[0124] An embodiment of the present application provides a matrix processing system, which includes a storage module, a computing module and the above-mentioned matrix processing device.

[0125] Among them, the storage module is used to store matrix data, the matrix processing device is used to transfer the matrix data or the transposed matrix data converted from the matrix data to the calculation module, and the calculation module is used to operate on the matrix data or the transposed matrix data.

[0126] The embodiment of the present application further provides a computer-readable storage medium, which stores a computer program. The computer program is executed by a processor to implement the steps in the above-mentioned matrix transfer method embodiment.

[0127] An embodiment of the present application provides a computer program product. When the computer program product is run on a mobile terminal, the mobile terminal implements the steps in the above-mentioned matrix transfer method embodiment when executing the computer program product.

[0128] Fig. 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Fig. 9 As shown, the electronic device 901 includes: a processor 9011, a memory 9012, and a computer program 9013 stored in the memory 9012 and executable on the processor 9011. When the processor 9011 executes the computer program 9013, the steps in the method in the above embodiment are implemented.

[0129] The electronic device 901 may be a general-purpose computer device or a dedicated computer device. In a specific implementation, the electronic device 901 may be a desktop computer, a portable computer, a network server, a PDA, a mobile phone, a tablet computer, a wireless terminal device, a communication device or an embedded device. The embodiment of the present application does not limit the type of the electronic device 901. Those skilled in the art will appreciate that Fig. 9This is merely an example of the electronic device 901 and does not constitute a limitation on the electronic device 901 . The electronic device 901 may include more or fewer components than shown in the figure, or a combination of certain components, or different components, such as input and output devices, network access devices, etc.

[0130] The processor 9011 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0131] In some embodiments, the memory 9012 may be an internal storage unit of the electronic device 901, such as a hard disk or memory of the electronic device 901. In other embodiments, the memory 9012 may also be an external storage device of the electronic device 901, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the electronic device 901. Further, the memory 9012 may also include both an internal storage unit of the electronic device 901 and an external storage device. The memory 9012 is used to store an operating system, an application program, a boot loader, data, and other programs. The memory 9012 may also be used to temporarily store data that has been output or is to be output.

[0132] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above method embodiments, which can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor, the steps of the above method embodiments can be implemented. Among them, the computer program includes computer program code, which can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may at least include: any entity or device that can carry the computer program code to the camera / terminal device, recording medium, computer memory, ROM (Read-Only Memory), RAM (Random Access Memory), CD-ROM (Compact Disc Read-Only Memory), magnetic tape, floppy disk and optical data storage device. The computer-readable storage medium mentioned in the present application can be a non-volatile storage medium, in other words, it can be a non-transient storage medium.

[0133] It should be understood that all or part of the steps for implementing the above-mentioned embodiments may be implemented by software, hardware, firmware or any combination thereof. When implemented by software, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. The computer instructions may be stored in the above-mentioned computer-readable storage medium. In the above-mentioned embodiments, the description of each embodiment has its own emphasis. For the part that is not described or recorded in detail in a certain embodiment, please refer to the relevant description of other embodiments.

[0134] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0135] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A matrix processing circuit, characterized in that: The circuit comprises: a transposition module, a control module, a register group module and a data selector, wherein the control module is connected to the register group module and the data selector respectively, and the register group module is also connected to the transposition module; The transposition module is used to convert the received matrix data into transposed matrix data; The register group module includes a plurality of register groups, and the plurality of register groups are used to store the matrix data or the transposed matrix data; The control module is used to control the register group module to write the matrix data or the transposed matrix data into a target register group among the multiple register groups according to the input data enable signal, and the control module is also used to output a selection signal to the data selector; The data selector is used to read out the matrix data or transposed matrix data stored in the target register group according to the selection signal.

2. The circuit according to claim 1, characterized in that When the matrix data needs to be transposed, and the format of the matrix data is that the number of rows and the number of columns are not equal, The register group module is used to write the spliced ​​transposed matrix data multiple times, and a plurality of the spliced ​​transposed matrix data constitute the transposed matrix data. The data selector is used to read out the splicing transposed matrix data multiple times.

3. The circuit according to claim 1, characterized in that The control module includes an input control module, an output control module, a first register and a second register; The input control module is connected to the first register and the second register, and is used to control the first register or the second register to send first indication information to the register group module according to the input data enable signal, wherein the first indication information is used to instruct the register group module to write the matrix data or the transposed matrix data into the target register group. The input control module is further used to control the first register and the second register to send an output data enable signal to the output control module according to the input data enable signal; The output control module is connected to the first register and the second register, and is used to control the first register or the second register to send second indication information to the data selector according to the output data enable signal, and the second indication information is used to instruct the data selector to read out the matrix data or the transposed matrix data in the target register group.

4. The circuit according to claim 3, characterized in that The input control module is connected to the register group module and is used to output a write enable signal to the register group module, wherein the write enable signal is used to determine a target register group for writing the matrix data or the transposed matrix data; The output control module is connected to the data selector and is used to output a selection signal to the data selector, wherein the selection signal is used to determine a target register group for reading out the matrix data or the transposed matrix data.

5. The circuit according to claim 4, characterized in that The input control module or the output control module includes a control counter, a pipeline stage, a flag register and an output register, The control counter and the flag register are connected to the output register, and the output register is used to send the write enable signal to the register group module or send the selection signal to the data selector according to the value of the control counter and the status bit of the flag register; The control counter is used to receive the input data enable signal or the output data enable signal, and when the input data enable signal or the output data enable signal is a first signal, the control counter increases a first preset value; When the value of the control counter is equal to the difference between the pipeline stage number and a second preset value, the pipeline stage number is used to reset the control counter to zero, and to control the flag bit of the flag register to flip, and the flag bit of the flag register is used to control the first register or the second register to indicate the write / read mode of the matrix data or the transposed matrix data in the target register.

6. The circuit according to claim 5, characterized in that In the case where the flag register in the input control module is a first signal, the first register indicates that the matrix data or the transposed matrix data is written into the target register in a first manner; In the case where the flag register in the input control module is a second signal, the second register indicates that the matrix data or the transposed matrix data is written into the target register in a second manner; In the case where the flag register in the output control module is a first signal, the first register indicates that the matrix data or the transposed matrix data in the target register is read out in a first manner; When the flag register in the output control module is a second signal, the second register indicates that the matrix data or the transposed matrix data in the target register is read out in a second manner.

7. A matrix processing method, characterized in that: Applied to a matrix processing circuit, the method comprises: receiving an input data enable signal; Controlling the matrix data or the transposed matrix data processed by the transposition module of the matrix processing circuit to write into the target register group according to the input data enable signal; A selection signal is output to a data selector in the matrix processing circuit to control the data selector to read out the matrix data or the transposed matrix data in the target register.

8. The method according to claim 7, characterized in that The method further comprises: When the matrix data needs to be transposed, and the format of the matrix data is that the number of rows and the number of columns are not equal, the register group module is controlled to write the spliced ​​transposed matrix data multiple times, and the multiple spliced ​​transposed matrix data constitute the transposed matrix data, The data selector is controlled to read out the concatenated transposed matrix data multiple times.

9. A matrix processing device, characterized in that: The device comprises the matrix processing circuit as claimed in any one of claims 1 to 8.

10. A matrix processing system, characterized in that: The system comprises a storage module, a computing module and a matrix processing device as claimed in claim 9. The storage module is used to store matrix data, the matrix processing device is used to transfer the matrix data or the transposed matrix data converted from the matrix data to the calculation module, and the calculation module is used to operate on the matrix data or the transposed matrix data.

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