Memory and task processing method

Abstract

The invention provides a memory and a task processing method, and the memory comprises a main control module which is used for receiving a host task; the command queue module is used for storing and distributing the host tasks; the hardware acceleration module is used for executing the allocated host tasks; wherein the command queue module is used for distributing part or all of the host tasks to the hardware acceleration module for execution according to the host task execution capability of the hardware acceleration module, and distributing the remaining undistributed host tasks to the main control module for execution. According to the memory and the task processing method provided by the invention, the task processing efficiency of the memory can be improved.

Description

Technical Field

[0001] The present invention relates to the field of storage, and in particular to a storage device and a task processing method. Background Art

[0002] With the widespread application of memory in consumer electronic devices such as smart TVs, set-top boxes, and mobile terminals, data reliability and stability have become core requirements. The memory is composed of an ARM-based main control module and a NAND Flash flash memory module. The main control module implements key functions such as bad block management, garbage collection (GC), performance optimization, and life maintenance of the storage module by running firmware.

[0003] The execution, calculation and query of various tasks of the existing memory are all processed by the main control module, which leads to excessive load on the main control module and delays in some tasks, thus affecting the performance of the memory. Therefore, there is room for improvement. Summary of the invention

[0004] The object of the present invention is to provide a memory and a task processing method, which can improve the task processing efficiency of the memory.

[0005] In order to solve the above technical problems, the present invention is achieved through the following technical solutions: The present invention provides a memory, comprising: The main control module is used to receive host tasks; A command queue module, used for storing and distributing the host tasks; Hardware acceleration module, used to execute assigned host tasks; The command queue module is further used to allocate part or all of the host tasks to the hardware acceleration module for execution according to the capability of the hardware acceleration module to execute the host tasks, and allocate the remaining unallocated host tasks to the main control module for execution.

[0006] In one embodiment of the present invention, the host task includes at least one of a logic operation task, a data search task, and a data movement task; and the hardware acceleration module includes: An acceleration control unit, used for receiving assigned logic operation tasks, assigned data search tasks, and assigned data movement tasks; A logic operation unit, used to perform assigned logic operation tasks; A data search unit, used to perform assigned data search tasks; The data migration unit is used to execute the assigned data migration tasks.

[0007] In one embodiment of the present invention, the main control module has a CPU core; the command queue module allocates host tasks according to the following steps: Determine the type of the host task: When the host task is one of a logic operation task, a data search task, and a data migration task, the host task is split into a plurality of subtasks, and some or all of the subtasks are assigned to the task queues of the corresponding logic operation unit, the data search unit, and the data migration unit, and the remaining unassigned subtasks are assigned to the task queue of the main control module; When the host tasks are at least two of the logical operation tasks, the data search tasks, and the data movement tasks, all host tasks are allocated to the task queues of the corresponding logical operation unit, the data search unit, and the data movement unit.

[0008] In one embodiment of the present invention, the command queue module allocates subtasks according to the following steps: Obtain and determine the task queues of the logic operation unit, the data search unit, and the data moving unit that match the subtask: When the task queue is in an idle state, the subtask is assigned to the task queues of the logic operation unit, the data search unit, and the data moving unit that match the subtask until the task queue is in a full state; When the task queue is in a fully loaded state, the remaining unassigned subtasks are assigned to the task queue of the main control module.

[0009] In one embodiment of the present invention, the main control module has multiple CPU cores; the command queue module allocates host tasks according to the following steps: Each type of host task is split into multiple subtasks of corresponding types, and some or all of the subtasks are assigned to the task queues of the corresponding logic operation unit, the data search unit, and the data movement unit, and the remaining unassigned subtasks are assigned to the task queue of the main control module.

[0010] In one embodiment of the present invention, the command queue module allocates subtasks according to the following steps: Obtain and determine the task queues of the logic operation unit, the data search unit, and the data moving unit that match the subtask: When the task queue is in an idle state, the subtask is assigned to the task queues of the logic operation unit, the data search unit, and the data moving unit that match the subtask until the task queue is in a full state; When the task queue is in a fully loaded state, the remaining unassigned subtasks are assigned to different task queues of the main control module; and different task queues of the main control module correspond to different CPU cores.

[0011] In one embodiment of the present invention, the command queue module allocates the remaining unallocated subtasks according to the following steps: Obtain the number of idle CPU cores in the main control module: create a corresponding task queue according to the idle number; Assign the remaining unassigned subtasks to the corresponding task queues according to their types.

[0012] In one embodiment of the present invention, the command queue module allocates the remaining unallocated subtasks to the corresponding task queues according to their types according to the following steps: Determine the number of types of the remaining unassigned subtasks: When the number of types is less than or equal to the number of task queues, allocating the remaining unallocated subtasks to different task queues according to type; When the number of types is greater than the number of task queues, the remaining unallocated subtasks are evenly distributed to all task queues.

[0013] In one embodiment of the present invention, the main control module is used to generate and send operation start instructions, search start instructions, and move start units, the logic operation unit is used to start according to the operation start instructions, the data search unit is used to start according to the search start instructions, and the data move unit is used to start according to the move start unit.

[0014] The present invention also provides a memory task processing method, the memory includes a main control module and a hardware acceleration module, the task processing method includes: Receive and assign host tasks; According to the capability of the hardware acceleration module to execute host tasks, part or all of the host tasks are allocated to the hardware acceleration module for execution, and the remaining unallocated host tasks are allocated to the main control module for execution.

[0015] As described above, the present invention provides a memory and task processing method, which significantly improves the system operation efficiency by introducing a hardware acceleration module and adopting a fine task division strategy. The command queue module dynamically monitors the load of the hardware acceleration module and adopts different allocation strategies according to the task type and quantity: subtasks are preferentially allocated to the hardware acceleration module to make full use of its efficient processing capabilities. When the hardware acceleration module is overloaded, the remaining tasks are flexibly allocated to the main control module. By allocating tasks by type, dynamically creating task queues, and evenly allocating unallocated tasks, efficient task allocation and load balancing are achieved.

[0016] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for describing the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 is a schematic diagram of a memory in one embodiment of the present invention; Figure 2 FIG. 4 is a schematic diagram of a hardware acceleration module in an embodiment of the present invention.

[0019] In the figure: 10, power module; 20, interface module; 30, main control module; 40, read-only storage module; 50, random access storage module; 60, command queue module; 70, read cache module; 80, write cache module; 90, mapping table module; 100, flash memory module; 110, hardware acceleration module; 111, bus interface unit; 112, input cache unit; 113, acceleration control unit; 114, logic operation unit; 115, data search unit; 116, data movement unit; 117, output cache unit. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] See also Figure 1 The present invention provides a memory, which may be an embedded multimedia card (Embedded MultiMedia Card, eMMC) or a universal flash storage (UFS). The memory may communicate with an electronic device through a CMD line and a DATA0~7 line, and receive instructions from the electronic device to perform operations such as reading, writing, and erasing. The electronic device may send instructions through the CMD line and transmit data through the DATA0~7 lines. The communication protocol between the memory and the electronic device may follow the JEDEC protocol. The memory may include an interface module 20, a main control module 30, a read-only storage module 40, a random access storage module 50, a command queue module 60, a read cache module 70, a write cache module 80, a mapping table module 90, a flash memory module 100, and a hardware acceleration module 110.

[0022] In some embodiments, the power module 10 may be a power supply of an electronic device, and the power module 10 may be used to provide a core power supply (VCC) and an interface power supply (VCCQ) to a memory.

[0023] In some embodiments, the interface module 20 (interface) can be a transmission interface and a power supply interface between the memory and the electronic device. The interface module 20 can receive instructions from the electronic device and return data or status information to the electronic device. The interface module 20 can receive instructions from the electronic device through the CMD line and the DATA line, and return the result data or execution status to the electronic device through the DATA line. The interface module 20 can also be used to receive the core power supply (VCC) and the interface power supply (VCCQ) provided by the electronic device.

[0024] In some embodiments, the main control module 30 may be a microcontroller unit (MCU). The main control module 30 may be used to perform specific control tasks, such as reading data, processing instructions from electronic devices, etc. The CPU core of the main control module 30 may be designed based on the RISC-V architecture to perform various control and computing tasks. The main control module 30 may have one CPU core or multiple CPU cores. The CPU core is the basic unit for executing instructions and operations in the main control module 30. Each CPU core can perform tasks independently and has its own registers, ALU (arithmetic logic unit) and cache.

[0025] In some embodiments, the read-only memory module 40 may be a non-volatile memory (ROM) for long-term data storage. The read-only memory module 40 may store a program, such as firmware. The program may be a set of pre-written instructions that instruct the main control module 30 on how to start and run. These instructions include device initialization, peripheral configuration, and a possible boot loader. The boot loader may be used to load an updated program or operating system, etc.

[0026] In some embodiments, the random access memory module 50 may be a volatile memory (Random Access Memory, RAM) for temporarily storing data and program codes. The random access memory module 50 may be used to temporarily store data. When the control module 30 executes a program, the program code may be loaded from the read-only storage module 40 into the random access memory module 50 for execution.

[0027] In some embodiments, the command queue module 60 (CMDQ) can be a buffer for temporarily storing memory access requests / host tasks from different hardware modules, and sorting and scheduling these requests / host tasks according to certain rules (such as priority, sequence or optimization strategy), and then sending them to other modules for execution.

[0028] In some embodiments, the read cache module 70 (ReadBuffer) and the write cache module 80 (WriteBuffer) can be used as a high-speed temporary storage area between the main control module 30 and the flash memory module 100 to store data and instructions frequently accessed by the main control module 30 to achieve the function of accelerating data transmission. The read cache module 70 is mainly used to increase the speed of data reading and reduce the access to the flash memory module 100; while the write cache module 80 is mainly used to improve the efficiency of data writing and optimize the performance of write operations.

[0029] In some embodiments, the mapping table module 90 (MemoryMappingTableModule) can be used to manage the mapping relationship between virtual memory and physical memory. The mapping table module 90 converts the virtual address (used by the program) into the physical address (used by the hardware) by maintaining the mapping table, thereby realizing efficient management and protection of the memory. The mapping table can be a hierarchical structure (such as a page table) for recording the correspondence between the virtual address and the physical address. For example, in the paging mechanism, the virtual address is divided into a page number (PageNumber) and an offset within the page (Offset), and the mapping table searches for the corresponding physical page frame by the page number. When the program accesses a virtual address, the main control module 30 queries the mapping table to find the corresponding physical address. If there is no corresponding entry in the mapping table (i.e., a page is missing), a page missing exception will be triggered, and the main control module 30 is responsible for loading the required data from the disk to the physical memory and updating the mapping table.

[0030] In some embodiments, the flash memory module 100 may be a physical unit (nand) for storing data in a memory. The flash memory module 100 may be composed of a plurality of storage blocks. Each storage block may contain a plurality of pages. Each page is the minimum unit of a read / write operation, and a block is the minimum unit of an erase operation. Data is usually read and written in units of pages, and the entire block needs to be erased when erasing.

[0031] See also Figure 1 and Figure 2In some embodiments, the hardware acceleration module 110 (Hardware Acceleration, HACC) can be a dedicated hardware circuit newly added inside the memory, which accelerates the processing of specific tasks through hardware-level optimization, thereby reducing the burden of the main control module 30 and improving the overall system performance. The hardware acceleration module 110 may include a bus interface unit 111, an input cache unit 112, an acceleration control unit 113, a logic operation unit 114, a data search unit 115, a data move unit 116, an output cache unit 117, etc.

[0032] In some embodiments, the bus interface unit 111 can be used to convert different bus protocols within the memory, such as converting and adapting protocols such as AXI (Advanced Xtensible Interface), AHB (Advanced High-performance Bus), and APB (Advanced Peripheral Bus), so as to achieve efficient communication between different modules. The bus interface unit 111 can be connected to different functional modules, such as the main control module 30, the random access storage module 50, the command queue module 60, the read cache module 70, the write cache module 80, the mapping table module 90, the flash memory module 100, etc., to adapt to hardware acceleration in different scenarios.

[0033] In some embodiments, the input cache unit 112 can be used to temporarily cache data in the main control module 30, the random storage module 50, the command queue module 60, the read cache module 70, the write cache module 80, the mapping table module 90, and the flash memory module 100, as well as to cache logical operation tasks and their subtasks, data search tasks and their subtasks, and data movement tasks and their subtasks, so that the logical operation unit 114, the data search unit 115, the data movement unit 116, etc. can be processed.

[0034] In some embodiments, the acceleration control unit 113 can be used to receive various instructions from the main control module 30, such as operation start instructions, search start instructions, and move start units. When hardware acceleration needs to be implemented through the hardware acceleration module 110, the main control module 30 is used to generate and send operation start instructions, search start instructions, and move start units. The acceleration control unit 113 can be used to send the operation start instruction to the logic operation unit 114, and the logic operation unit 114 can be started according to the operation start instruction. The acceleration control unit 113 can be used to send the search start instruction to the data search unit 115, and the data search unit 115 can be started according to the search start instruction. The acceleration control unit 113 can be used to send the move start unit to the data move unit 116, and the data move unit 116 can be started according to the move start unit.

[0035] In some embodiments, the logic operation unit 114 can be used to process logic operation tasks. The logic operation unit 114 can process a variety of arithmetic and logical operations, including arithmetic operations, logical operations, and data comparisons. Arithmetic operations include addition, subtraction, multiplication, and division. Logical operations include AND, OR, NOT, XOR, XNOR, ANDN, ORN, and the like. Data comparisons include greater than, less than, and equal to. The logic operation unit 114 can replace the main control module 30 to perform logic operations on a large amount of data, such as AND / OR / NOT operations on batch data. By configuring the logic operation unit 114, the main control module 30 can send logic operation tasks to the logic operation unit 114 for processing, thereby freeing up resources to process other tasks and realize parallel multi-tasking.

[0036] In some embodiments, the data search unit 115 can be used to process data search tasks. The data search unit 115 can search for specified characters or any combination of characters, and can implement: maximum value (Max), minimum value (Min) search; specified data feature search: for example, the length of the number is from 1 to n; specified range search: can search within the specified Die, Plane, Block, Page range; support firmware running algorithm search query, including maximum value, minimum value, specified feature character query, any combination of feature character query; can search within the specified NAND LBA (Logical Block Address) range. The data search unit 115 can perform data search tasks through hardware acceleration to reduce the burden on the main control module 30.

[0037] In some embodiments, the data moving unit 116 can be used to process data moving tasks. The data moving unit 116 can accelerate data moving between the read cache module 70, the write cache module 80 and the flash memory module 100. The data moving unit 116 can realize the functions of data filling and data moving. Data filling refers to specifying any starting LBA address + LBA length + fixed value or random value; specifying any LBA internal address + LBA internal length + fixed value or random value. Data moving refers to moving from any LBA address + LBA arbitrary length, and can be moved from the cache of the main control module 30 to the read cache module 70, write cache module 80, or from the read cache module 70, write cache module 80 to the cache of the main control module 30. The data moving unit 116 executes data moving tasks through hardware acceleration, reducing the occupancy time of the main control module 30.

[0038] In some embodiments, the output cache unit 117 can be used to send the data processed by the logic operation unit 114, the data search unit 115, and the data movement unit 116, and can be sent to the main control module 30, the random storage module 50, the command queue module 60, the read cache module 70, the write cache module 80, the mapping table module 90, the flash memory module 100, etc.

[0039] In some embodiments, the host task sent by the electronic device is used as an example for explanation. The host task may include at least one of a logical operation task, a data search task, and a data movement task, and the number of each type of task may also be at least one. The logical operation task may include operations such as addition, subtraction, multiplication, division, and, or, and negation. The data search task may include tasks such as finding the maximum value, the minimum value, or the specified characteristic data. The data movement task may include tasks such as moving data between the read cache module 70 and the flash memory module 100, and between the write cache module 80 and the flash memory module 100. The main control module 30 may receive the host task sent by the host. The command queue module 60 may be used to store the host task and assign the task to the hardware acceleration module 110 and / or the main control module 30 for execution according to a certain strategy. For example, the command queue module 60 may assign some or all of the host tasks to the task queue of the hardware acceleration module 110 according to the ability of the hardware acceleration module 110 to execute the host task, so as to wait for the hardware acceleration module 110 to execute; and assign the remaining unassigned host tasks to the task queue of the main control module 30 to wait for the main control module 30 to execute. The task queue may be created in advance by the command queue module 60 , and different task queues may be created for different modules or units.

[0040] In some embodiments, when the main control module 30 has one CPU core, the command queue module 60 can determine the type of host task: when the host task is one of the following types: logic operation task, data search task, and data movement task, the command queue module 60 can split the host task into multiple subtasks, and assign some or all of the subtasks to the corresponding logic operation unit 114, data search unit 115, and data movement unit 116 for execution, and assign the remaining unassigned subtasks to the main control module 30 for execution; when the host task is at least two of the following types: logic operation task, data search task, and data movement task, the command queue module 60 assigns all host tasks to the corresponding logic operation unit 114, data search unit 115, and data movement unit 116 for execution.

[0041] In some embodiments, the command queue module 60 can adopt different allocation strategies according to the type of host task. When the host task is a type of logic operation task, data search task or data movement task, the command queue module 60 can split the host task into multiple subtasks. The command queue module 60 can assign some or all of the subtasks to the corresponding hardware acceleration unit for execution: the subtasks of the logic operation task can be processed by the logic operation unit 114; the subtasks of the data search task can be processed by the data search unit 115; the subtasks of the data movement task can be processed by the data movement unit 116; the remaining unassigned subtasks can be assigned to the main control module 30 for processing. The logic operation unit 114, the data search unit 115, and the data movement unit 116 efficiently process suitable tasks, and use the main control module 30 to process the remaining tasks, so as to achieve load balancing.

[0042] In some embodiments, when the host tasks are at least two of the following types: logic operation tasks, data search tasks, or data movement tasks, there is no need to split the tasks, and all host tasks are directly assigned to the corresponding logic operation unit 114, data search unit 115, and data movement unit 116 for execution according to the task type. By making full use of the parallel processing capability of the hardware acceleration module 110, the burden of the main control module 30 is avoided, and the overall efficiency is improved.

[0043] In some embodiments, when the command queue module 60 splits the host task into multiple sub-tasks, the command queue module can obtain and determine the status of the task queues of the logical operation unit 114, the data search unit 115, and the data movement unit 116 that match the sub-tasks: when the task queue is in an idle state, the sub-task is assigned to the task queues of the logical operation unit 114, the data search unit 115, and the data movement unit 116 that match it until the task queue is full; when the task queue is full, the remaining unassigned sub-tasks are assigned to the task queue of the main control module 30.

[0044] In certain embodiments, the idle state of task queue refers to that the quantity of pending tasks in the task queue does not exceed the task threshold. For example, the task threshold can be set to 100, and when the quantity of pending tasks in the task queue is 30, it is explained that 70 tasks can also be added in this task queue. The fully loaded state of task queue refers to that the quantity of pending tasks in the task queue reaches the task threshold, if continue to distribute new tasks in this task queue at this moment, may cause the problem that the delay duration of task execution is longer, therefore, when task queue is in fully loaded state, can no longer distribute new tasks to it. Wherein, the size of the task threshold of different task queues can be unrestricted.

[0045] In some embodiments, when assigning subtasks, the command queue module 60 can dynamically monitor the load of the hardware acceleration module (logic operation unit 114, data search unit 115, data move unit 116), and decide how to assign tasks based on the number of tasks to be executed and the task threshold. Specifically, the command queue module 60 can obtain the number of tasks to be executed of the hardware acceleration module 110 that matches the subtask: the number of tasks to be executed of the logic operation unit 114; the number of tasks to be executed of the data search unit 115; the number of tasks to be executed of the data move unit 116. The command queue module 60 compares the number of tasks to be executed with the task threshold. The task threshold is a preset value that indicates the maximum number of tasks that the logic operation unit 114, the data search unit 115, and the data move unit 116 in the hardware acceleration module 110 can efficiently handle.

[0046] In some embodiments, the command queue module 60 may adopt different allocation strategies according to the relationship between the number of tasks to be executed and the task threshold: when the number of tasks to be executed in the logic operation unit 114, the data search unit 115, and the data moving unit 116 is less than the task threshold, the command queue module 60 preferentially allocates the subtasks to the logic operation unit 114, the data search unit 115, and the data moving unit 116 that match it, and the allocation process continues until the number of tasks to be executed in the logic operation unit 114, the data search unit 115, and the data moving unit 116 is equal to the task threshold. When the number of tasks to be executed in the logic operation unit 114, the data search unit 115, and the data moving unit 116 is greater than or equal to the task threshold, the command queue module 60 allocates the remaining unallocated subtasks to the main control module 30 for execution.

[0047] In some embodiments, when the main control module 30 has multiple CPU cores, the command queue module 60 can split each type of host task into multiple subtasks of corresponding types, and assign some or all of the subtasks to the task queues of the corresponding logic operation unit 114, data search unit 115, and data moving unit 116 to wait for execution; and assign the remaining unassigned subtasks to the task queue of the main control module 30 to wait for execution. Through such allocation, efficient task allocation and resource utilization can be achieved, and the performance advantages of the hardware acceleration module 110 can be fully utilized. At the same time, the remaining tasks are processed by the main control module 30 to ensure the load balancing of the system and the efficiency of task completion.

[0048] In some embodiments, when allocating subtasks, the command queue module 60 dynamically monitors the status of the task queue of the hardware acceleration module (logical operation unit 114, data search unit 115, data movement unit 116): when the task queue is in an idle state, the subtask is allocated to the task queue of the matching logical operation unit 114, data search unit 115, and data movement unit 116 until the task queue is fully loaded; when the task queue is fully loaded, the remaining unallocated subtasks are allocated to different task queues of the main control module 30; different task queues of the main control module 30 correspond to different CPU cores.

[0049] In some embodiments, the command queue module 60 can obtain and determine the number of tasks to be executed in the logic operation unit 114, the data search unit 115, and the data moving unit 116 that match the subtask: when the number of tasks to be executed is less than the task threshold, the subtask is preferentially assigned to the corresponding logic operation unit 114, the data search unit 115, and the data moving unit 116 until the number of tasks to be executed is equal to the task threshold; when the number of tasks to be executed is greater than or equal to the task threshold, the remaining unassigned subtasks are assigned to different CPU cores of the main control module 30 for execution. When the hardware acceleration module is not overloaded, the subtask is preferentially assigned to the hardware acceleration module 110 to make full use of its efficient processing capabilities. When the hardware acceleration module 110 is overloaded, the remaining unassigned subtasks are assigned to different CPU cores of the main control module 30 to ensure that the tasks can be completed efficiently.

[0050] In some embodiments, when allocating the remaining unallocated subtasks, the command queue module 60 will dynamically monitor the number of idle CPU cores in the main control module 30, create corresponding task queues based on these idle CPU cores, and then allocate the remaining unallocated subtasks to the corresponding task queues according to type. By making full use of the multi-core processing capability of the main control module 30, efficient parallel processing and load balancing of tasks can be achieved. Specifically, the command queue module 60 can obtain the number of idle CPU cores in the main control module 30: create corresponding task queues based on the number of cores; match each idle CPU core with a task queue; and allocate the remaining unallocated subtasks to the corresponding task queues according to type. Among them, an idle CPU core refers to a CPU core that currently has no tasks being executed. By allocating subtasks to different task queues, parallel execution of tasks can be achieved, thereby improving system efficiency.

[0051] In some embodiments, for example, the main control module has 3 idle CPU cores, and the remaining unassigned subtasks may include 5 subtasks of logic operation tasks, 4 subtasks of data search tasks, and 3 subtasks of data movement tasks. The command queue module 60 obtains that the main control module has 3 idle CPU cores, and creates 3 task queues, which match the 3 idle CPU cores respectively. Subsequently, the remaining unassigned subtasks can be assigned to the corresponding task queues according to type: the first task queue can process 5 subtasks of logic operation tasks, the second task queue can process 4 subtasks of data search tasks, and the third task queue can process 3 subtasks of data movement tasks.

[0052] In some embodiments, the command queue module 60 can determine the number of types of remaining unallocated subtasks: when the number of types is less than or equal to the number of task queues, the remaining unallocated subtasks are allocated to different task queues according to type; when the number of types is greater than the number of task queues, the number of tasks of each type of remaining unallocated subtasks is counted, and the remaining unallocated subtasks are evenly distributed to the task queues. The command queue module 60 adopts different allocation strategies according to the number of types of remaining unallocated subtasks and the number of task queues, thereby achieving efficient allocation and load balancing of tasks. When the number of types is less than or equal to the number of task queues, tasks are allocated by type and idle task queues are deleted; when the number of types is greater than the number of task queues, unallocated tasks are evenly distributed to all task queues. This design can make full use of the resources of the task queues, ensure that tasks can be efficiently executed, and avoid waste of resources.

[0053] It can be seen that in the above scheme, by introducing the hardware acceleration module and adopting the task fine division strategy, the system operation efficiency is significantly improved. The command queue module dynamically monitors the load of the hardware acceleration module and adopts different allocation strategies according to the task type and quantity: priority is given to allocating subtasks to the hardware acceleration module to make full use of its efficient processing capabilities. When the hardware acceleration module is overloaded, the remaining tasks are flexibly allocated to the main control module. By allocating tasks by type, dynamically creating task queues, and evenly allocating unassigned tasks, efficient task allocation and load balancing are achieved.

[0054] The present invention also provides a memory task processing method, which can be applied to the above-mentioned memory, and the task processing method includes: Receive and assign host tasks; the host tasks include at least one of logical operation tasks, data search tasks, and data migration tasks; According to the ability of the hardware acceleration module to execute host tasks, some or all of the host tasks are assigned to the hardware acceleration module for execution, and the remaining unassigned host tasks are assigned to the main control module for execution.

[0055] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A memory, characterized in that: include: The main control module is used to receive host tasks; A command queue module, used for storing and distributing the host tasks; Hardware acceleration module, used to execute assigned host tasks; The command queue module is further used to allocate part or all of the host tasks to the hardware acceleration module for execution according to the capability of the hardware acceleration module to execute the host tasks, and allocate the remaining unallocated host tasks to the main control module for execution.

2. The memory according to claim 1, characterized in that: The host task includes at least one of a logic operation task, a data search task, and a data movement task; the hardware acceleration module includes: An acceleration control unit, used for receiving assigned logic operation tasks, assigned data search tasks, and assigned data movement tasks; A logic operation unit, used to perform assigned logic operation tasks; A data search unit, used to perform assigned data search tasks; The data migration unit is used to execute the assigned data migration tasks.

3. The memory according to claim 2, characterized in that: The main control module has a CPU core; the command queue module allocates host tasks according to the following steps: Determine the type of the host task: When the host task is one of a logic operation task, a data search task, and a data migration task, the host task is split into a plurality of subtasks, and some or all of the subtasks are assigned to the task queues of the corresponding logic operation unit, the data search unit, and the data migration unit, and the remaining unassigned subtasks are assigned to the task queue of the main control module; When the host tasks are at least two of the logical operation tasks, the data search tasks, and the data movement tasks, all host tasks are allocated to the task queues of the corresponding logical operation unit, the data search unit, and the data movement unit.

4. The memory according to claim 3, characterized in that: The command queue module allocates subtasks according to the following steps: Obtain and determine the task queues of the logic operation unit, the data search unit, and the data moving unit that match the subtask: When the task queue is in an idle state, the subtask is assigned to the task queues of the logic operation unit, the data search unit, and the data moving unit that match the subtask until the task queue is in a full state; When the task queue is in a fully loaded state, the remaining unassigned subtasks are assigned to the task queue of the main control module.

5. The memory according to claim 2, characterized in that: The main control module has multiple CPU cores; the command queue module allocates host tasks according to the following steps: Each type of host task is split into multiple subtasks of corresponding types, and some or all of the subtasks are assigned to the task queues of the corresponding logic operation unit, the data search unit, and the data movement unit, and the remaining unassigned subtasks are assigned to the task queue of the main control module.

6. The memory according to claim 5, characterized in that: The command queue module allocates subtasks according to the following steps: Obtain and determine the task queues of the logic operation unit, the data search unit, and the data moving unit that match the subtask: When the task queue is in an idle state, the subtask is assigned to the task queues of the logic operation unit, the data search unit, and the data moving unit that match the subtask until the task queue is in a full state; When the task queue is in a fully loaded state, the remaining unassigned subtasks are assigned to different task queues of the main control module; and different task queues of the main control module correspond to different CPU cores.

7. The memory according to claim 6, characterized in that: The command queue module allocates the remaining unallocated subtasks according to the following steps: Obtain the number of idle CPU cores in the main control module: create a corresponding task queue according to the idle number; Assign the remaining unassigned subtasks to the corresponding task queues according to their types.

8. The memory according to claim 7, characterized in that: The command queue module allocates the remaining unallocated subtasks to the corresponding task queues according to their types according to the following steps: Determine the number of types of the remaining unassigned subtasks: When the number of types is less than or equal to the number of task queues, allocating the remaining unallocated subtasks to different task queues according to type; When the number of types is greater than the number of task queues, the remaining unallocated subtasks are evenly distributed to all task queues.

9. The memory according to claim 2, characterized in that: The main control module is used to generate and send operation start instructions, search start instructions, and move start units. The logic operation unit is used to start according to the operation start instructions. The data search unit is used to start according to the search start instructions. The data move unit is used to start according to the move start unit.

10. A memory task processing method, characterized in that: The memory includes a main control module and a hardware acceleration module, and the task processing method includes: Receive and assign host tasks; According to the capability of the hardware acceleration module to execute host tasks, part or all of the host tasks are allocated to the hardware acceleration module for execution, and the remaining unallocated host tasks are allocated to the main control module for execution.

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