Multi-core CPU data driving task deployment method and system

Abstract

The invention provides a multi-core CPU data-driven task deployment method and system, and the method comprises the steps: task input and output data are one or more data objects, and the buffer structures of the data objects are queues; the multi-task scheduling is used for circularly executing tasks meeting conditions in the task input queue buffer area; the multi-core CPU high-capacity off-chip memory space configuration comprises the step of configuring a high-capacity off-chip memory space for deploying queue data; the multi-core multi-task deployment comprises the steps of calling queue data from a high-capacity off-chip memory space of the multi-core CPU, and deploying a plurality of tasks corresponding to each core. According to the method, targeted design is carried out according to the characteristics of the data driving task, operation system support is not needed, direct deep coupling with multi-core CPU hardware is achieved, implementation is easy, and the resource utilization rate is high.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a multi-core CPU data-driven task deployment method and system. Background Art

[0002] The main characteristics of data-driven tasks are: task execution is driven by the generation of input data, rather than based on system time or planning cycle; when new data is available, the task execution is triggered to perform calculations or processing operations; when there is no input data, the task will wait or block. The rhythm of task execution is completely determined by the rate of input data flow.

[0003] Patent document CN116483545A discloses a multi-tasking execution method, device and equipment, including determining first-class global variables and second-class global variables divided according to the access frequency of global variables and the position of the variable setting stage; determining differentiated threading templates constructed for the first-class global variables and the second-class global variables respectively; performing environmental isolation processing on the first-class global variables and the second-class global variables according to thread local storage and threading templates to obtain corresponding thread local variables; and performing multi-threaded multi-tasking execution according to the corresponding thread local variables.

[0004] However, patent document CN116483545A is based on the operating system and task scheduling under general circumstances. For example, patent "A method for implementing task scheduling in a multi-core embedded system, patent number: 201410086704", patent "A method and system for task scheduling in a multi-task environment, patent number: 201710380203.1", patent "An embedded resource management method based on multi-core DSP, patent number: 202010601344", patent "A multi-task development model and method based on a multi-core platform, patent number: 201811080482.0" are all based on the operating system and task scheduling under general circumstances, which are complex to implement and consume resources. Summary of the invention

[0005] In view of the defects in the prior art, the object of the present invention is to provide a multi-core CPU data-driven task deployment and monitoring method and system.

[0006] A multi-core CPU data-driven task deployment method provided by the present invention includes: task input and output data structure, multi-task scheduling, multi-core CPU large-capacity memory space configuration and multi-core multi-task deployment;

[0007] The data input and output of the task are all one or more data objects, and the buffer structures of the data objects are all queues; the multi-task scheduling is used to cyclically execute the tasks that meet the conditions in the task input queue buffer; the multi-core CPU large-capacity off-chip memory space configuration includes configuring a large-capacity off-chip memory space for deploying queue data; the multi-core multi-task deployment includes retrieving queue data from the multi-core CPU large-capacity off-chip memory space and deploying multiple tasks corresponding to each core;

[0008] Preferably, the multi-task scheduling comprises the following steps:

[0009] Step S1: initialization;

[0010] Step S2: Set the initialization completion flag;

[0011] Step S3: Detecting other core initialization completion flags;

[0012] Step S4: judging whether all other core initializations are completed according to the initialization completion flag, if so, executing step S5; if not, returning to step S3;

[0013] Step S5: query the next task input queue buffer according to the set rules;

[0014] Step S6: Determine whether the data in the task input queue buffer area meets the conditions for executing the current task. If so, execute the task; if not, return to step S5.

[0015] Preferably, the step S5 includes the following sub-steps:

[0016] Step S5.1: Increment N modulo n by 1, where N is the number of tasks deployed in the core;

[0017] Step S5.2: the query counter variable to which task n belongs is incremented by 1;

[0018] Step S5.3: Determine whether the current task query counter is equal to the set value. If so, execute step S5.4; if not, return to step S5.1;

[0019] Step S5.4: Clear the counter variable and read the task n queue information.

[0020] Preferably, it also includes: task execution time monitoring and queue buffer area monitoring;

[0021] The task execution time monitoring includes using the system clock to record and calculate the maximum execution time, the shortest execution time, and the average execution time of each task;

[0022] The queue buffer monitoring includes recording and calculating the maximum utilization of the queue buffer and the average utilization of the queue before and / or after the task execution is started using the queue read pointer.

[0023] Preferably, the large-capacity off-chip memory space is divided into a multi-core shared memory space and a multi-core private memory space;

[0024] The large-capacity off-chip memory includes DDR and HBM.

[0025] Preferably, the multi-core multi-task deployment includes autonomous multi-core load balancing, single image loading and multi-image loading.

[0026] Preferably, the average execution time of all tasks in each core is less than the average generation interval of the core source queue data; the source queue data comes from the CPU external interface or other core task outputs; the queue buffer capacity is greater than the capacity requirement in the case of data bursts; the writing and reading tasks are respectively deployed in the queues of different cores and deployed on the shared memory.

[0027] Preferably, the multi-core load balancing includes deploying load balancing tasks on a certain core, calculating the utilization rate of each core by reading the execution time of tasks in each core, and reallocating the tasks executed by each core when the utilization rate difference reaches a set value.

[0028] Preferably, the single image loading method loads the program image into a shared memory, and all cores read the program from the same memory. The program in the program image contains a judgment statement for comparing core ID numbers, and jumps to execute the program that matches the ID number.

[0029] Preferably, the multi-image loading method loads the program image into the private memory of each core respectively, and all cores read the program from their respective private memories.

[0030] Compared with the prior art, the present invention has the following beneficial effects:

[0031] The present invention is specifically designed based on the characteristics of data-driven tasks, does not require operating system support, is directly deeply coupled with multi-core CPU hardware, is simple to implement, and has high resource utilization. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0033] Figure 1 It is a schematic diagram of the working method of the present invention;

[0034] Figure 2 It is a schematic diagram of the queue scanning process in the present invention. DETAILED DESCRIPTION

[0035] The present invention is described in detail below in conjunction with specific embodiments. The following embodiments will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that, for those of ordinary skill in the art, several changes and improvements can also be made without departing from the concept of the present invention. These all belong to the protection scope of the present invention.

[0036] Embodiment 1

[0037] A multi-core CPU data-driven task deployment method provided by the present invention includes: task input and output data structure, multi-task scheduling, multi-core CPU large-capacity memory space configuration, and multi-core multi-task deployment;

[0038] The data input and output of the task are all one or more data objects, and the buffer structures of the data objects are all queues. The multi-task scheduling is used to cyclically execute the tasks that meet the conditions in the task input queue buffer. The multi-core CPU large-capacity off-chip memory space configuration includes configuring a large-capacity off-chip memory space for deploying queue data. The multi-core multi-task deployment includes retrieving queue data from the multi-core CPU large-capacity off-chip memory space and deploying multiple tasks corresponding to each core.

[0039] like Figure 1 and Figure 2 As shown, the multi-task scheduling includes the following steps:

[0040] Step S1: Initialization.

[0041] Step S2: Set the initialization completion flag.

[0042] Step S3: Detect the initialization completion flags of other cores.

[0043] Step S4: Determine whether all other core initializations are completed according to the initialization completion flag. If so, execute step S5; if not, return to step S3.

[0044] Step S5: query the next task input queue buffer according to the set rules. Step S5 includes the following sub-steps:

[0045] Step S5.1: Increment N modulo n by 1, where N is the number of tasks deployed in the core.

[0046] Step S5.2: The query counter variable to which task n belongs is incremented by 1.

[0047] Step S5.3: Determine whether the current task query counter is equal to the set value. If so, execute step S5.4; if not, return to step S5.1.

[0048] Step S5.4: Clear the counter variable and read the task n queue information.

[0049] Step S6: Determine whether the data in the task input queue buffer area meets the conditions for executing the current task. If so, execute the task; if not, return to step S5.

[0050] The large-capacity off-chip memory space is divided into a multi-core shared memory space and a multi-core private memory space, and the large-capacity off-chip memory includes DDR and HBM. The queue data is implemented using an array, and the queue read and write pointers are implemented using array index variables respectively. The queue elements in the queue are aligned with the cache block boundaries. The shared memory cache used to deploy queue data is turned on, and the task does not copy data from other cores, but is processed directly on the shared memory. Before processing, the relevant parts of the local cache are invalidated, and a write-back operation is performed after processing. When the private memory cache is turned on, the task reads data from other cores and copies it to the private memory of this core for processing. When the shared memory cache is closed, the queue pointer is deployed on the shared memory on the CPU chip.

[0051] The multi-core multi-task deployment includes autonomous multi-core load balancing, single image loading and multi-image loading. The multi-core load balancing includes the deployment of load balancing tasks on a core, calculating the utilization rate of each core by reading the execution time of tasks in each core, and reallocating the tasks executed by each core when the utilization rate difference reaches a set value. The single image loading method loads the program image into the shared memory, and all cores read the program from the same memory. The program in the program image contains a judgment statement for comparing the core ID number, and jumps to execute the program that matches the ID number. The multi-image loading method loads the program image into the private memory of each core respectively, and all cores read the program from their respective private memories. The average execution time of all tasks in each core is less than the average generation interval of the core source queue data. The source queue data comes from the CPU external interface or other core task outputs; the queue buffer capacity should be set to be greater than the capacity requirement in the case of data bursts; the writing and reading tasks are respectively deployed in the queues of different cores and deployed on the shared memory.

[0052] The multi-core CPU data-driven task deployment method of the present invention also includes: task execution time monitoring; queue buffer area monitoring; the task execution time monitoring includes using the system clock to record and calculate the maximum execution time, the shortest execution time, and the average execution time of each task. The queue buffer area monitoring includes using the queue read pointer to record and calculate the maximum utilization rate of the queue buffer area, and the average utilization rate of the queue before and / or after the task execution starts.

[0053] Embodiment 2

[0054] The present invention also provides a multi-core CPU data-driven task deployment system. Those skilled in the art can implement the multi-core CPU data-driven task deployment system by executing the step flow of the multi-core CPU data-driven task deployment method, that is, the multi-core CPU data-driven task deployment method can be understood as a preferred implementation of the multi-core CPU data-driven task deployment system.

[0055] A multi-core CPU data-driven task deployment system provided according to the present invention includes: a task input and output data structure module, a multi-task scheduling module, a multi-core CPU large-capacity memory space configuration module and a multi-core multi-task deployment module. The data input and output of the task are one or more data objects, and the buffer structure of the data object is a queue. Multi-task scheduling is used to cyclically trigger qualified tasks in the task input queue buffer. The multi-core CPU large-capacity off-chip memory space configuration includes configuring a large-capacity off-chip memory space for deploying queue data. Multi-core multi-task deployment includes retrieving queue data from the multi-core CPU large-capacity off-chip memory space and deploying multiple tasks corresponding to each core.

[0056] The multi-task scheduling includes the following modules: Module M1: Initialization. Module M2: Set the initialization completion flag. Module M3: Detect the initialization completion flags of other cores. Module M4: Determine whether all other cores have completed initialization according to the initialization completion flag. If so, trigger module M5. If not, return to module M3. Module M5: Query the next task input queue buffer according to the set rules. Module M5 includes the following submodules: Module M5.1: Increment by 1 with N as modulo n, where N is the number of tasks deployed in the core. Module M5.2: Increment the query counter variable to which task n belongs by 1. Module M5.3: Determine whether the query counter of the current task is equal to the set value. If so, trigger module M5.4. If not, return to module M5.1. Module M5.4: Clear the counter variable and read the queue information of task n. Module M6: Determine whether the data in the task input queue buffer meets the conditions for triggering the current task. If so, trigger the task. If not, return to module M5.

[0057] The multi-core CPU data-driven task deployment system of the present invention also includes: task trigger time monitoring. Queue buffer area monitoring. Task trigger time monitoring includes using the system clock to record and calculate the maximum trigger time, the shortest trigger time, and the average trigger time of each task. Queue buffer area monitoring includes using the queue read pointer to record and calculate the maximum utilization rate of the queue buffer area, and the average utilization rate of the queue before and / or after the task triggering starts.

[0058] Those skilled in the art know that, in addition to realizing the system and its various devices, modules, and units provided by the present invention in a purely computer-readable program code, it is entirely possible to realize the same functions in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers by logically programming the method steps. Therefore, the system and its various devices, modules, and units provided by the present invention can be considered as a hardware component, and the devices, modules, and units included therein for realizing various functions can also be regarded as structures within the hardware component; the devices, modules, and units for realizing various functions can also be regarded as both software modules for realizing the method and structures within the hardware component.

[0059] The above describes the specific embodiments of the present invention. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art can make various changes or modifications within the scope of the claims, which does not affect the essence of the present invention. In the absence of conflict, the embodiments of the present application and the features in the embodiments can be combined with each other arbitrarily.

Claims

1. A multi-core CPU data-driven task deployment method, characterized in that: include: Task input and output data structure, multi-task scheduling, multi-core CPU large-capacity memory space configuration and multi-core multi-task deployment; The data input and output of the task are all one or more data objects, and the buffer structures of the data objects are all queues; the multi-task scheduling is used to cyclically execute tasks that meet the conditions in the task input queue buffer; the multi-core CPU large-capacity off-chip memory space configuration includes configuring a large-capacity off-chip memory space for deploying queue data; the multi-core multi-task deployment includes retrieving queue data from the multi-core CPU large-capacity off-chip memory space and deploying multiple tasks corresponding to each core.

2. The multi-core CPU data-driven task deployment method according to claim 1, characterized in that: The multi-task scheduling comprises the following steps: Step S1: initialization; Step S2: Set the initialization completion flag; Step S3: Detecting other core initialization completion flags; Step S4: judging whether all other core initializations are completed according to the initialization completion flag, if so, executing step S5; if not, returning to step S3; Step S5: query the next task input queue buffer according to the set rules; Step S6: Determine whether the data in the task input queue buffer area meets the conditions for executing the current task. If so, execute the task; if not, return to step S5.

3. The multi-core CPU data-driven task deployment method according to claim 2, characterized in that: The step S5 comprises the following sub-steps: Step S5.1: Increment N modulo n by 1, where N is the number of tasks deployed in the core; Step S5.2: the query counter variable to which task n belongs is incremented by 1; Step S5.3: Determine whether the current task query counter is equal to the set value. If so, execute step S5.4; if not, return to step S5.1; Step S5.4: Clear the counter variable and read the task n queue information.

4. The multi-core CPU data-driven task deployment method according to claim 1, characterized in that: Also includes: Task execution time monitoring and queue buffer monitoring; The task execution time monitoring includes using the system clock to record and calculate the maximum execution time, the shortest execution time, and the average execution time of each task; The queue buffer monitoring includes recording and calculating the maximum utilization of the queue buffer and the average utilization of the queue before and / or after the task execution is started using the queue read pointer.

5. The multi-core CPU data-driven task deployment method according to any one of claims 1 to 3, characterized in that: The large-capacity off-chip memory space is divided into a multi-core shared memory space and a multi-core private memory space; The large-capacity off-chip memory includes DDR and HBM.

6. The multi-core CPU data-driven task deployment method according to claim 1, characterized in that: The multi-core multi-task deployment includes autonomous multi-core load balancing, single image loading and multi-image loading.

7. The multi-core CPU data-driven task deployment method according to claim 1, characterized in that: The average execution time of all tasks in each core is less than the average generation interval of the core source queue data; the source queue data comes from the CPU external interface or other core task output; The queue buffer capacity is larger than the capacity required in the case of data bursts; the writing and reading tasks are deployed in queues of different cores and deployed on shared memory.

8. The multi-core CPU data-driven task deployment method according to claim 6, characterized in that: The multi-core load balancing includes deploying load balancing tasks on a certain core, calculating the utilization rate of each core by reading the execution time of tasks in each core, and reallocating the tasks executed by each core when the utilization rate difference reaches a set value.

9. The multi-core CPU data-driven task deployment method according to claim 6, characterized in that: The single image loading method loads the program image into a shared memory, and all cores read the program from the same memory. The program in the program image contains a judgment statement for comparing core ID numbers, and jumps to execute the program that matches the ID number.

10. The multi-core CPU data-driven task deployment method according to claim 6, characterized in that: The multi-image loading method loads the program image into the private memory of each core respectively, and all cores read the program from their own private memory.

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