Memory management method and memory controller

Abstract

The invention provides a memory management method and a controller thereof. The method comprises the following steps: obtaining to-be-stored mapping table data; the size of an array storage group is determined according to the total number of the chip enable pins, and the array storage group comprises a plurality of entity pages corresponding to the chip enable pins with the number smaller than the total number; based on the word string line sequence, the chip enable pin sequence and the plane sequence, setting a plurality of array storage groups which are arranged continuously; and storing the mapping table data into a plurality of array storage groups, wherein respective check pages of two adjacent array storage groups correspond to different chip enabling pins. Through the technical scheme of the invention, the storage distribution uniformity of the mapping table data can be improved, the parallel efficiency of data reading is ensured, and meanwhile, the reliability of data protection is maintained.

Description

Technical Field

[0001] The present disclosure relates to the field of storage technology, and in particular to a memory management method and a controller thereof applied to a storage device configured with a rewritable non-volatile memory module. Background Art

[0002] In modern storage technology, rewritable non-volatile memory (NAND Flash) has been widely used in storage devices such as solid-state drives (SSDs).

[0003] In the existing SSD architecture, the mapping table is responsible for mapping the logical address to the physical address, and it is used to locate the correct data storage location. The correctness of the mapping table is crucial to the data reading of the SSD. In order to enhance the protection capability of the mapping table, in addition to the LDPC (Low Density Parity Check) protection, the Redundant Array of Independent Disks Error Checking and Correcting Code (RAID ECC) mechanism is also required. This mechanism stores the mapping table data in multiple channels in a dispersed manner, and stores the ECC-encoded check code in the last plane corresponding to the last channel. However, this method will store the check code in the last plane of the last channel. When writing the mapping table data, if there is a power outage, a dummy page will be added before the last plane of the last channel, resulting in valid data being stored only in the chip corresponding to the previous channel, thereby affecting the reading speed of the mapping table data. Summary of the invention

[0004] Aiming at the problem that the check code of the mapping table data is stored in the last plane of the last channel in the prior art, which results in the need to supplement virtual pages when the power is off and affects the data reading speed, the present invention provides a memory management method and a controller thereof. By optimizing the storage distribution strategy of the mapping table data, the check pages can be evenly distributed in the enable pins of different chips, thereby improving the reading efficiency of the mapping table data while ensuring the data protection capability.

[0005] One or more embodiments of the present disclosure provide a memory management method applicable to a storage device configured with a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of chips, each of the plurality of chips corresponds to a chip enable pin, and each chip includes P planes. The method comprises: obtaining mapping table data to be stored; determining the size of an array storage group according to the total number N of a plurality of chip enable pins, wherein the array storage group comprises a plurality of physical pages corresponding to M chip enable pins, wherein M is less than N and greater than 1, and M is equal to N minus a predetermined value; setting a plurality of array storage groups arranged in succession based on a string line sequence, a chip enable pin sequence and a plane sequence, wherein the plurality of physical pages of each array storage group respectively correspond to different planes of the M chip enable pins; and storing the mapping table data in the plurality of array storage groups, wherein the plurality of physical pages of each array storage group comprises a plurality of data pages and a check page, wherein the plurality of data pages are used to store a portion of mapping table data corresponding to the array storage group, and the check page is used to store check data corresponding to the portion of mapping table data, wherein the check pages of two adjacent array storage groups respectively correspond to different chip enable pins.

[0006] In one or more embodiments of the present disclosure, the step of setting the multiple array storage groups arranged in succession based on the word string line sequence, the chip enable pin sequence and the plane sequence includes: selecting the first array storage group to be set according to the serial number sequence of the multiple array storage groups; selecting an available first word string line based on the word string line sequence; selecting one or more available first chip enable pins from the multiple chip enable pins corresponding to the first word string line based on the chip enable pin sequence; if the number of the one or more first chip enable pins is equal to M: obtaining multiple first physical pages corresponding to the multiple planes in each first chip enable pin; and setting the multiple first physical pages as the multiple physical pages of the first array storage group.

[0007] In one or more embodiments of the present disclosure, the step of setting the multiple array storage groups arranged in succession based on the word string line sequence, the chip enable pin sequence and the plane sequence also includes: if the number of the one or more first chip enable pins selected in the first word string line is less than M: select an available second word string line sorted after the first word string line; based on the chip enable pin sequence, select one or more available second chip enable pins from the multiple chip enable pins corresponding to the second word string line, wherein the total number of the one or more first chip enable pins and the one or more second chip enable pins is M; obtain multiple first physical pages corresponding to the multiple planes in each first chip enable pin, and obtain multiple second physical pages corresponding to the multiple planes in each second chip enable pin; and set the multiple first physical pages and the multiple second physical pages as the multiple physical pages of the first array storage group.

[0008] In one or more embodiments of the present disclosure, the check page of each array storage group is the last one of the multiple physical pages of the array storage group.

[0009] In one or more embodiments of the present disclosure, if N is an even number, there is a remainder when M is used as a divisor of N.

[0010] In one or more embodiments of the present disclosure, the predetermined value is 1.

[0011] In one or more embodiments of the present disclosure, the chip enable pin following the last chip enable pin of the i-th word string line is the first chip enable pin of the i+1-th word string line, wherein multiple physical pages of each array storage group correspond to multiple chip enable pins of the same word string line or to multiple chip enable pins of adjacent word string lines, wherein each word string line includes N P entity pages.

[0012] In one or more embodiments of the present disclosure, the method further includes: if a target chip fails, rebuilding the target partial mapping table data stored in the target chip based on the partial mapping table data stored in other chips outside the target chip and the corresponding verification data.

[0013] In one or more embodiments of the present disclosure, the plane order is an order from the 0th plane to the P-1th plane within the same chip enable pin.

[0014] One or more embodiments of the present disclosure provide a memory controller for controlling a storage device configured with a rewritable non-volatile memory module. The memory controller includes: a memory interface control circuit for electrically connecting to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of chips, each of the plurality of chips corresponds to a chip enable pin, and each chip includes P planes; and a processor electrically connected to the memory interface control circuit, wherein the processor is further electrically connected to a connection interface circuit of the storage device to electrically connect to a host system. The processor is configured to: obtain mapping table data to be stored; determine the size of an array storage group according to the total number N of multiple chip enable pins, wherein the array storage group includes multiple physical pages corresponding to M chip enable pins, wherein M is less than N and greater than 1, and M is equal to N minus a predetermined value; set multiple array storage groups arranged in succession based on a string line order, a chip enable pin order, and a plane order, wherein the multiple physical pages of each array storage group correspond to different planes of the M chip enable pins; and store the mapping table data in the multiple array storage groups, wherein the multiple physical pages of each array storage group include multiple data pages and a check page, wherein the multiple data pages are used to store part of the mapping table data corresponding to the array storage group, and the check page is used to store check data corresponding to the part of the mapping table data, wherein the check pages of two adjacent array storage groups respectively correspond to different chip enable pins.

[0015] Based on the above, the memory management method and controller provided by the present disclosure optimize the size setting and distribution mode of the array storage group, so that the mapping table data and its check pages can be evenly distributed in different chip enable pins, effectively avoiding the problem of centralized data storage. At the same time, under the premise of maintaining the strength of data protection, the method can ensure the parallel reading efficiency of the mapping table data even in the case of power failure, thereby improving the overall performance of the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0017] Figure 1 is a block diagram of a host system and a storage device according to an embodiment of the present invention;

[0018] Figure 2 is a flowchart of a memory management method according to an embodiment of the present disclosure;

[0019] Figure 3A schematic diagram of setting up an array storage group via a conventional method;

[0020] Figure 4 The diagram is a schematic diagram of setting an array storage group through a provided memory management method according to an embodiment of the present disclosure.

[0021] Description of Figure Numbers

[0022] 10: Host system

[0023] 20: Storage device

[0024] 110: processor (second processor)

[0025] 120: Host memory

[0026] 130: Data transmission interface circuit

[0027] 210: Memory controller

[0028] 211: Processor (first processor)

[0029] 212: Data management circuit

[0030] 213: Memory interface control circuit

[0031] 214: Buffer memory

[0032] 220: Rewritable non-volatile memory module

[0033] 230: Connecting interface circuit

[0034] S210-S240: Steps

[0035] CE0-CE3: Chip enable pins

[0036] PL0, PL1: Flat surface

[0037] PG000-PG231: Entity Page

[0038] SG0-SG2: string line

[0039] REG01-REG03, REG11-REG14: Array storage group DETAILED DESCRIPTION

[0040] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0041] Figure 1FIG. 1 is a block diagram of a host system and a storage device according to an embodiment of the present invention. Figure 1 , the host system 10 is, for example, a personal computer, a notebook computer, or a server. The host system 10 includes a processor 110 (also referred to as a second processor), a host memory 120, and a data transfer interface circuit 130. In the present embodiment, the processor 110 is coupled (also referred to as electrically connected) to the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 are electrically connected to each other using a system bus. In the present embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 may be disposed on a motherboard of the host system 10.

[0042] The storage device 20 includes a memory controller 210, a rewritable non-volatile memory module 220, a connection interface circuit 230, and a random access memory 240. The memory controller 210 includes a processor 211 (also called a first processor), a data management circuit 212, and a memory interface control circuit 213.

[0043] In this embodiment, the host system 10 is electrically connected to the storage device 20 through the data transmission interface circuit 130 and the connection interface circuit 230 of the storage device 20 to perform data access operations. For example, the host system 10 can store data to the storage device 20 or read data from the storage device 20 via the data transmission interface circuit 130.

[0044] In this embodiment, the number of the data transmission interface circuit 130 can be one or more. Through the data transmission interface circuit 130, the motherboard can be electrically connected to the storage device 20 via a wired or wireless manner. The storage device 20 can be, for example, a USB flash drive, a memory card, a solid state drive (SSD) or a wireless memory storage device. The wireless memory storage device can be, for example, a near field communication (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth memory storage device or a low power consumption Bluetooth memory storage device (e.g., iBeacon) and other memory storage devices based on various wireless communication technologies. In addition, the motherboard can also be electrically connected to various I / O devices such as a global positioning system (GPS) module, a network interface card, a wireless transmission device, a keyboard, a screen, a speaker, etc. through a system bus.

[0045] In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the high-speed peripheral component interconnect interface (Peripheral Component Interconnect Express, PCI Express) standard. In addition, the data transmission between the data transmission interface circuit 130 and the connection interface circuit 230 is performed using the fast non-volatile memory interface standard (Non-Volatile Memory express, NVMe) communication protocol.

[0046] Furthermore, in another embodiment, the connection interface circuit 230 and the memory controller 210 may be packaged in one chip, or the connection interface circuit 230 may be disposed outside a chip including the memory controller 210 .

[0047] In the present embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. For example, in the present embodiment, the host memory 120 and the random access memory 240 may be dynamic random access memory (DRAM), static random access memory (SRAM), etc. However, it should be understood that the present invention is not limited thereto, and the host memory 120 and the random access memory 240 may also be other suitable memories.

[0048] The memory controller 210 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 220 according to instructions of the host system 10 .

[0049] In more detail, the processor 211 in the memory controller 210 is hardware with computing capabilities, which is used to control the overall operation of the memory controller 210. Specifically, the processor 211 is programmed by a plurality of control instructions / program codes, and when the storage device 20 is operating, these control instructions / program codes are executed to perform operations such as writing, reading and erasing data. In addition, in this embodiment, the control instructions / program codes can be further executed to perform specific garbage collection operations to implement the memory management method for different working states of the storage device provided by the present invention. The control instructions / program codes corresponding to the memory management method can also be implemented as a circuit unit in the form of hardware to implement the memory management method provided by the present invention.

[0050] It is worth mentioning that in the present embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a microprocessor, or other programmable processing units (Microprocessor), a digital signal processor (DSP), a programmable controller, an application specific integrated circuit (ASIC), a programmable logic device (PLD) or other similar circuit components, but the present invention is not limited thereto.

[0051] In this embodiment, as described above, the memory controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by the various components of the memory controller 210 can also be regarded as the operations performed by the memory controller 210.

[0052] The data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213 and the connection interface circuit 230. The data management circuit 212 is used to receive instructions from the processor 211 to transmit data. For example, data is read from the host system 10 (e.g., the host memory 120) via the connection interface circuit 230, and the read data is written to the rewritable non-volatile memory module 220 via the memory interface control circuit 213 (e.g., the write operation is performed according to the write instruction from the host system 10). For another example, data is read from one or more physical units of the rewritable non-volatile memory module 220 via the memory interface control circuit 213 (the data can be read from one or more storage units in the one or more physical units), and the read data is written to the host system 10 (e.g., the host memory 120) via the connection interface circuit 230 (e.g., the read operation is performed according to the read instruction from the host system 10). In another embodiment, the data management circuit 212 can also be integrated into the processor 211.

[0053] The memory interface control circuit 213 is used to receive instructions from the processor 211 and cooperate with the data management circuit 212 to perform a write (also called programming) operation, a read operation or an erase operation on the rewritable non-volatile memory module 220 .

[0054] In one embodiment, the memory interface control circuit 213 includes a plurality of chip enable pin control circuits. These chip enable pin control circuits correspond to the chip enable pins (also referred to as CE) of the plurality of chips in the rewritable non-volatile memory module 220, respectively, and are used to control the enabling and disabling of the corresponding chips. In this way, the memory interface control circuit 213 can achieve selective access to different chips.

[0055] In addition, the data to be written to the rewritable non-volatile memory module 220 will be converted into a format acceptable to the rewritable non-volatile memory module 220 via the memory interface control circuit 213. Specifically, if the processor 211 wants to access the rewritable non-volatile memory module 220, the processor 211 will transmit a corresponding instruction sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform a corresponding operation. For example, these instruction sequences may include a write instruction sequence indicating writing data, a read instruction sequence indicating reading data, an erase instruction sequence indicating erasing data, and corresponding instruction sequences for indicating various memory operations. These instruction sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or program codes. For example, in the read instruction sequence, information such as the read identification code, memory address, and physical address will be included.

[0056] In addition, the memory controller 210 establishes a logical to physical address mapping table (Logical To Physical address mapping table) and a physical to logical address mapping table (Physical To Logical address mapping table) to record the mapping relationship between the logical address of the logical unit (e.g., logical block, logical page) configured for the rewritable non-volatile memory module 220 and the physical address (physical address) of the physical unit (e.g., physical erase unit / physical block, physical page). In other words, the memory controller 210 can search for the physical unit mapped by a logical unit (e.g., search for the physical page mapped by a logical page; search for the physical address mapped by a logical address) through the logical to physical address mapping table (also called the logical to physical mapping table), and the memory controller 210 can search for the logical unit mapped by a physical unit (e.g., search for the logical page mapped by a physical page; search for the logical address mapped by a physical address) through the physical to logical address mapping table (also called the physical to logical mapping table).

[0057] In one embodiment, the memory controller 210 further includes a buffer memory 214. The buffer memory 214 is electrically connected to the processor 211 and is used to temporarily store data and instructions from the host system 10, data from the rewritable non-volatile memory module 220, or other system data used to manage the storage device 20. In addition, the buffer memory 214 can also be used to store various mapping tables (e.g., a logical to physical address mapping table and a physical to logical address mapping table) so that the processor 211 can quickly access the data, instructions or system data from the buffer memory 214.

[0058] In one embodiment, in order to ensure the reliability of the mapping table data, before the memory controller 210 writes the mapping table data to the rewritable non-volatile memory module 220, the memory controller 210 performs a Redundant Array of Independent Disks Error Checking and Correcting Code (RAID ECC) protection mechanism on the mapping table data. Specifically, the memory controller 210 generates a corresponding check page based on the mapping table data, and stores the mapping table data and the check page in different chips of the rewritable non-volatile memory module 220. In this way, even if a chip fails, the memory controller 210 can still reconstruct the mapping table data stored in the failed chip based on the mapping table data and the corresponding check page stored in other chips.

[0059] In one embodiment, the buffer memory 214 is divided into a plurality of cache areas, including a mapping table cache area specifically used for temporarily storing mapping table data to be encoded, and a verification data cache area for temporarily storing verification data after encoding. Such area division helps to improve the processing efficiency of mapping table data.

[0060] The rewritable non-volatile memory module 220 is electrically connected to the memory controller 210 (memory interface control circuit 213 ) and is used to store user data sent by the host system 10 .

[0061] In the present embodiment, each memory grain (chip) of the multiple memory grains of the rewritable non-volatile memory module 220 has multiple planes (e.g., each chip enable pin corresponds to P planes), and each plane has multiple physical blocks. Each physical block includes multiple physical programming units (also called physical pages). Each physical page has multiple storage cells (also called physical bytes or bytes), and each storage cell corresponds to a physical address. The physical address is used to record the physical location of the data stored in the storage cell. It should be noted that the present invention is not limited to the size of each physical page and logical page.

[0062] Figure 2 The present invention is a flowchart of a memory management method according to an embodiment of the present invention.

[0063] Reference Figure 2 In step S210, the memory controller 210 obtains the mapping table data to be stored. Specifically, the memory controller 210 can obtain the mapping table data to be stored from the buffer memory 214. The mapping table data includes a logical to physical address mapping table and a physical to logical address mapping table. However, the memory management method can also be applied to other types of mapping tables or various system data that need to be properly protected.

[0064] Next, in step S220, the memory controller 210 determines the size of the array storage group according to the total number N of the plurality of chip enable pins (CE). The array storage group includes a plurality of physical pages corresponding to M chip enable pins, wherein M is less than N and greater than 1, and M is equal to N minus a predetermined value. In one embodiment, the predetermined value can be formulated according to demand, for example, 1. The setting of the predetermined value is to allow a plurality of consecutively arranged array storage groups to be staggered so that the check pages of adjacent array storage groups do not belong to the same chip enable pin.

[0065] It should be noted that in order to allow multiple consecutively arranged array storage groups to be staggered, when the total number N of chip enable pins (CE) is an even number, there is a remainder when the number of M chip enable pins corresponding to the array storage group is used as a divisor of N, that is, N cannot be divided by M, so that the array storage groups are staggered as much as possible.

[0066] In step S230, the memory controller 210 sets a plurality of array storage groups arranged in succession based on the word string line order, the chip enable pin order and the plane order. The memory controller 210 makes the plurality of physical pages of each array storage group correspond to different planes of the M chip enable pins respectively. The plane order is the order from the 0th plane to the P-1th plane within the same chip enable pin.

[0067] For example, in one embodiment, the memory controller 210 sets a plurality of array storage groups arranged in succession based on the word string line sequence, the chip enable pin sequence, and the plane sequence. Specifically, the memory controller 210 first selects the first array storage group to be set according to the sequence of the plurality of array storage groups. Such a sequence of sequence numbers can ensure that the setting process of the array storage groups is carried out in an orderly manner.

[0068] In another embodiment, the memory controller 210 selects an available first word string line from the rewritable non-volatile memory module 220 based on the word string line sequence. Subsequently, the memory controller 210 selects one or more available first chip enable pins from a plurality of chip enable pins corresponding to the first word string line based on the chip enable pin sequence. The chip enable pin sequence may be from a smaller number to a larger number.

[0069] In another embodiment, when the memory controller 210 detects that the number of the selected one or more first chip enable pins is equal to M, the memory controller 210 performs the following operations: First, the memory controller 210 obtains a plurality of first physical pages corresponding to the plurality of planes in each first chip enable pin. Then, the memory controller 210 sets the plurality of first physical pages as the plurality of physical pages of the first array storage group. In this way, the memory controller 210 can complete the setting of the array storage group in a single string line.

[0070] In another embodiment, if the memory controller 210 detects that the number of one or more first chip enable pins selected in the first word string line is less than M (e.g., the remaining space corresponding to the current first word string line cannot set a complete array storage group), the memory controller 210 performs the following steps: First, the memory controller 210 selects an available second word string line that is sorted after the first word string line (obtaining other space from the next word string line to make up for the insufficient space of the first word string line). Then, the memory controller 210 selects one or more available second chip enable pins from the multiple chip enable pins corresponding to the second word string line based on the chip enable pin sequence. Among them, the memory controller 210 ensures that the total number of the one or more first chip enable pins and the one or more second chip enable pins is M.

[0071] Next, the memory controller 210 obtains a plurality of first physical pages corresponding to the plurality of planes in each first chip enable pin, and simultaneously obtains a plurality of second physical pages corresponding to the plurality of planes in each second chip enable pin. Finally, the memory controller 210 sets the plurality of first physical pages and the plurality of second physical pages as the plurality of physical pages of the first array storage group. In this way, the memory controller 210 can complete the setting of the array storage group within the range of crossing adjacent string lines.

[0072] Through the above implementations, the memory management method provided by the present disclosure can flexibly set array storage groups within a single string line or across adjacent string lines according to actual conditions.

[0073] In step S240, the memory controller 210 stores the mapping table data in the plurality of array storage groups. Specifically, the plurality of physical pages of each array storage group includes a plurality of data pages and a check page, wherein the plurality of data pages are used to store a portion of the mapping table data corresponding to the array storage group, and the check page is used to store the check data corresponding to the portion of the mapping table data. It is worth noting that the check pages of the two adjacent array storage groups correspond to different chip enable pins.

[0074] The memory management method disclosed in the present invention can realize uniformly distributed storage of mapping table data, effectively avoiding the problem of reduced reading efficiency that may be caused by centralized storage of check pages in the traditional method.

[0075] In one embodiment, the process of the memory controller 210 generating verification data for the mapping table data is as follows.

[0076] Specifically, the memory controller 210 first divides the part of the mapping table data to be stored into a plurality of data units. Then, the memory controller 210 performs an exclusive OR (XOR) operation on these data units based on the error correction code algorithm of the independent disk redundant array, thereby generating corresponding verification data. The size of the verification data is the same as the size of a single data unit, and the verification data includes redundant information for recovering the part of the mapping table data.

[0077] In another embodiment, the memory controller 210 encodes the generated check data before writing it to the check page. Specifically, the memory controller 210 uses error correction code encoding technology, such as low-density parity check code (LDPC), to encode the check data to improve the reliability of the check data itself. Through this dual protection mechanism, even if the check data itself has partial errors, the memory controller 210 can still recover the correct check data through the error correction code, thereby ensuring the reliability of the mapping table data.

[0078] Figure 3 FIG. 1 is a schematic diagram of setting up an array storage group by a conventional method. In one embodiment, please refer to Figure 3 , which shows a traditional array storage group setting method.

[0079] In this embodiment, the configuration of the array storage group by the memory controller 210 has the following characteristics: the total number of chip enable pins is 4 (N=4), and each array storage group corresponds to 4 chip enable pins (M=4=N).

[0080] Specifically, each word string line (e.g., SG0, SG1, SG2) includes 4 chip enable pins (CE0, CE1, CE2, CE3), and each chip enable pin corresponds to 2 planes (PL0, PL1). The memory controller 210 sets the check page of each array storage group (e.g., REG01, REG02, REG03) to the physical page of the last chip enable pin CE3. For example, in the word string line SG0, the check page of the array storage group REG01 is set in the physical page PG031 of the chip enable pin CE3.

[0081] In another embodiment, when this conventional method is used, the memory controller 210 sets the array storage group in the following order: First, the memory controller 210 sets the physical page corresponding to the chip enable pins CE0 to CE2 (from physical page PG000 to PG021, also called data page) as the data page of the array storage group REG01 in the word string line SG0, and sets the physical page PG031 corresponding to the chip enable pin CE3 as the check page of the array storage group REG01. Then, the memory controller 210 sets the array storage group REG02 in the same way in the word string line SG1, and so on.

[0082] However, this traditional setting method has the following technical defects:

[0083] In one embodiment, since the check page is always fixed in the last chip enable pin CE3, when an abnormal situation such as power failure occurs, the memory controller 210 needs to add a virtual page in the position before the chip enable pin CE3. This results in that the valid mapping table data is concentratedly stored in the front chip enable pins (such as CE0, CE1), while the back chip enable pins (such as CE2, CE3) mainly store virtual pages or check pages.

[0084] In another embodiment, such unbalanced data distribution may significantly reduce the reading efficiency because when the memory controller 210 needs to read the mapping table data, it cannot fully utilize the parallel reading capability of multiple chip enable pins, but is forced to concentrate a large number of reading operations on the front few chip enable pins, thereby causing a reading performance bottleneck.

[0085] These technical defects highlight the limitations of traditional array storage group settings in practical applications and also illustrate the necessity of developing new storage management methods.

[0086] Figure 4 FIG. 1 is a schematic diagram of setting an array storage group through a provided memory management method according to an embodiment of the present disclosure. Figure 4 , which shows the improved array storage group configuration method provided by the present disclosure.

[0087] In this embodiment, the memory controller 210 adopts an innovative configuration strategy: the total number of chip enable pins is 4 (N=4), but each array storage group corresponds to only 3 (N minus a predetermined value 1) chip enable pins ( ).

[0088] For example, the memory controller 210 configures the array storage groups REG11 to REG14 as follows:

[0089] The array storage group REG11 is configured as follows: the memory controller 210 sets the physical pages (from PG000 to PG021) corresponding to the chip enable pins CE0, CE1, CE2 in the string line SG0 as components of the array storage group REG11, wherein the physical page PG021 is set as a check page.

[0090] In one embodiment, the memory controller 210 can use two methods to configure the physical page distribution of the array storage group: the first method is to correspond all the multiple physical pages of the array storage group to the multiple chip enable pins of the same word string line; the second method is to distribute the multiple physical pages of the array storage group to the multiple chip enable pins of the adjacent word string lines. The memory controller 210 can select an appropriate method to configure the array storage group according to the actual storage situation.

[0091] Specifically, the memory controller 210 considers the storage capacity of each word string line. Since each chip enable pin corresponds to P planes, and there are N chip enable pins on the word string line, each word string line includes N P physical pages. For example, when N is 4 and P is 2, each string line may contain 8 physical pages. The memory controller 210 will plan the distribution of the array storage groups based on this fixed storage capacity to ensure that the allocation of physical pages does not exceed the capacity limit of the string line.

[0092] Back to the configuration of the array storage group REG12, the configuration of the array storage group REG12 is as follows: the memory controller 210 crosses the string lines SG0 and SG1, and sets the physical pages (from PG030 to PG111) corresponding to the chip enable pin CE3 in the string line SG0 and the chip enable pins CE0 and CE1 in the string line SG1 as components of the array storage group REG12, wherein the physical page PG111 is set as a check page.

[0093] In more detail, the memory controller 210 performs the following detailed steps when setting the array storage group REG12:

[0094] First, the memory controller 210 selects the array storage group REG12 as the array storage group to be set after completing the setting of REG11 according to the serial number sequence of the array storage groups. Next, the memory controller 210 selects the available string line SG0 as the first string line based on the string line sequence.

[0095] Then, the memory controller 210 selects from the multiple chip enable pins corresponding to the word string line SG0 based on the chip enable pin sequence. Since the chip enable pins CE0, CE1, and CE2 are already occupied by the array storage group REG11, the memory controller 210 can only select the chip enable pin CE3 as the first chip enable pin. At this time, the memory controller 210 detects that the number of the first chip enable pins selected in the word string line SG0 (1) is less than M (M=3).

[0096] Therefore, the memory controller 210 selects the word string line SG1 sorted after the word string line SG0 as the second word string line. The memory controller 210 continues to select an available second chip enable pin from the multiple chip enable pins corresponding to the word string line SG1 based on the chip enable pin sequence. Specifically, the memory controller 210 selects the chip enable pins CE0 and CE1 as the second chip enable pin, so that the total number of the first chip enable pin (CE3) and the second chip enable pin (CE0, CE1) is M (M=3).

[0097] Next, the memory controller 210 obtains a plurality of first physical pages (i.e., PG030, PG031) corresponding to a plurality of planes from the first chip enable pin CE3, and obtains a plurality of second physical pages (i.e., PG100, PG101, PG110, PG111) corresponding to a plurality of planes from the second chip enable pins CE0 and CE1. Finally, the memory controller 210 uniformly sets these first physical pages and second physical pages as a plurality of physical pages of the array storage group REG12, and sets the physical page PG111 therein as a check page.

[0098] Similarly, the array storage group REG13 is configured as follows: the memory controller 210 crosses the word string lines SG1 and SG2, and sets the physical pages corresponding to the chip enable pins CE2 and CE3 in the word string line SG1 and the chip enable pin CE0 in SG2 (from physical page PG120 to PG201) as components of the array storage group REG13, wherein the physical page PG201 is set as a check page.

[0099] The configuration of the array storage group REG14 is as follows: the memory controller 210 sets the physical pages corresponding to the chip enable pins CE1, CE2, and CE3 in the string line SG2 (using the remaining available physical pages PG210-PG231) as components of the array storage group REG14, wherein the physical page PG231 is set as a check page.

[0100] It is worth mentioning that this innovative configuration has the following advantages: First, since the check page location of each array storage group is different, even if the virtual page needs to be supplemented in the case of power failure, the valid mapping table data can still be dispersed and stored in different chip enable pins. For example, the check page of array storage group REG11 is located at chip enable pin CE2, the check page of REG12 is located at chip enable pin CE1, the check page of array storage group REG13 is located at chip enable pin CE0, and the check page of array storage group REG14 is located at chip enable pin CE3.

[0101] Secondly, the memory controller 210 limits the range of the array storage group to M (M=3) chip enable pins, so that the data in the same array storage group will not be stored in the same chip enable pins corresponding to different string lines, ensuring that even if a chip fails, too much data in the same array storage group will not be lost, thereby improving data reliability. If the range of the array storage group is 5, the physical pages in SG0 and SG1 corresponding to CE0 will store data belonging to the same array storage group. When the chip corresponding to CE0 is abnormal, more data will be lost, and the data cannot be corrected again.

[0102] Finally, this cross-word string line configuration method enables the memory controller 210 to fully utilize the parallel reading capabilities of multiple chip enable pins, significantly improving the reading efficiency of the mapping table data.

[0103] In one embodiment, the memory controller 210 adopts a continuity configuration across word strings when managing the arrangement order of chip enable pins. Specifically, when the memory controller 210 completes access to the last chip enable pin of the i-th word string line, it will automatically turn to the first chip enable pin of the i+1-th word string line, thereby achieving continuous access to the chip enable pins.

[0104] Through the above configuration, the memory management method provided by the present disclosure can realize flexible distributed storage of mapping table data while ensuring effective use of storage space. Whether within a single string line or across adjacent string lines, the memory controller 210 can effectively manage and allocate physical page resources.

[0105] In one embodiment, the memory controller 210 adopts a specific check page layout strategy when configuring each array storage group. Specifically, the memory controller 210 sets the check page of each array storage group to the last physical page among multiple physical pages of the array storage group.

[0106] In another embodiment, the memory controller 210 performs the following steps when setting the check page position of the array storage group: First, the memory controller 210 confirms the total number of physical pages contained in the array storage group, wherein the physical pages include data pages for storing mapping table data and check pages for storing check data. Then, the memory controller 210 designates the physical page with the largest sequence number as the check page of the array storage group. For example, if an array storage group includes M physical pages, the Mth physical page will be designated as the check page, and the 1st to (M-1)th physical pages will be used as data pages.

[0107] By using this fixed check page layout strategy, the memory controller 210 can quickly locate the location where the check data is stored when performing data recovery. This layout not only simplifies the data management operation of the memory controller 210, but also improves the access efficiency of the check data. In addition, due to the certainty of the check page location, the memory controller 210 can perform the writing and recovery operations of the mapping table data more efficiently.

[0108] In another embodiment, the memory controller 210 may adopt a round-robin check page allocation strategy. Specifically, the memory controller 210 performs a cycle based on the numbering sequence of the chip enable pins, and sequentially designates physical pages in different chip enable pins as check pages.

[0109] For example, the memory controller 210 may perform the following check page allocation steps: for the first array storage group, the memory controller 210 selects the last physical page in the corresponding last chip enable pin as the check page; for the second array storage group, the memory controller 210 selects the last physical page in the corresponding first chip enable pin as the check page; for the third array storage group, the memory controller 210 selects the last physical page in the corresponding second chip enable pin as the check page.

[0110] Through this round-robin check page allocation strategy, the memory controller 210 not only ensures that the check pages of adjacent array storage groups are not located on the same chip enable pin, but also realizes a balanced distribution of the check pages between the chip enable pins. In addition, the regularity of this allocation strategy also facilitates the memory controller 210 to quickly locate and access the check page position.

[0111] In one embodiment, the memory controller 210 has a mapping table data reconstruction function. Specifically, when the memory controller 210 detects that a target chip fails, a mapping table data reconstruction mechanism is triggered.

[0112] In another embodiment, the memory controller 210 performs the following specific steps to rebuild the mapping table data: First, the memory controller 210 identifies the array storage group containing the target chip. Since multiple physical pages of each array storage group correspond to M different chip enable pins, the memory controller 210 can determine which array storage groups are affected by the target chip failure.

[0113] Then, the memory controller 210 performs data reconstruction operations for each affected array storage group. Specifically, the memory controller 210 first reads complete mapping table data from the chips that have not failed in the array storage group. At the same time, the memory controller 210 reads verification data from the corresponding verification page.

[0114] In another embodiment, the memory controller 210 uses the undamaged mapping table data and the check data to perform an exclusive OR (XOR) operation based on the error correction code algorithm of the independent disk redundant array, thereby reconstructing the target portion of the mapping table data stored in the target chip. For example, if the array storage group includes three data pages (D1, D2, D3) and one check page (P), and D2 is stored in the failed target chip, the memory controller 210 can calculate To rebuild D2.

[0115] In another embodiment, the memory controller 210 performs a data verification step after completing the data reconstruction. Specifically, the memory controller 210 recalculates the check code of the reconstructed data and compares it with the original check code to ensure the accuracy of the reconstructed mapping table data. If the verification passes, the memory controller 210 temporarily stores the reconstructed mapping table data in the buffer memory 214 for subsequent use.

[0116] Through the above mapping table data reconstruction mechanism, the memory management method provided by the present disclosure not only realizes reliable data storage, but also ensures data recovery capability in the event of chip failure, thereby improving the reliability and stability of the storage system. Even if a chip fails, the memory controller 210 can still reconstruct and restore key mapping table data through data and verification information in other chips.

[0117] This embodiment also provides a computer program product, including a computer readable code, or a non-volatile computer readable storage medium carrying the computer readable code, when the computer readable code is executed in a processor, the processor executes the steps of the above-mentioned memory management method. The computer program product can be implemented in hardware, firmware, software or a combination thereof. In an optional embodiment, the computer program product is specifically embodied as a computer storage medium, and in another optional embodiment, the computer program product is specifically embodied as a software product, such as a software development kit (SDK) and the like.

[0118] Based on the above, the memory management method and memory controller provided by the present disclosure have the following advantages:

[0119] By determining the size of the array storage group according to the total number of multiple chip enable pins, wherein the array storage group includes multiple physical pages corresponding to chip enable pins whose number is less than the total number, it is possible to effectively avoid storing the check page in the last chip enable pin, thereby improving the storage distribution uniformity of the mapping table data.

[0120] By setting a plurality of array storage groups arranged in succession based on the word string line sequence, the chip enable pin sequence and the plane sequence, so that a plurality of physical pages of each array storage group correspond to different planes of different chip enable pins, the mapping table data can be evenly distributed in the physical storage space, avoiding the reading bottleneck caused by the centralized storage of data sets.

[0121] By corresponding the check pages of the two adjacent array storage groups to different chip enable pins, even if the virtual page needs to be supplemented in the case of power failure, it can ensure that the valid data is dispersedly stored in different chips, thereby maintaining a high parallel reading efficiency without affecting the protection strength of the mapping table data.

[0122] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method, applicable to a storage device equipped with a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of chips, each of the plurality of chips corresponds to a chip enable pin, and each chip comprises P planes, wherein: The method comprises: Obtaining mapping table data to be stored; Determining a size of an array storage group according to a total number N of the plurality of chip enable pins, wherein the array storage group includes a plurality of physical pages corresponding to M chip enable pins, wherein M is less than N and greater than 1, and M is equal to N minus a predetermined value; Based on the word string line order, the chip enable pin order and the plane order, a plurality of array storage groups are set to be arranged in succession, wherein the plurality of physical pages of each array storage group correspond to different planes of the M chip enable pins respectively; and storing the mapping table data in the plurality of array storage groups, wherein the plurality of physical pages of each array storage group comprises a plurality of data pages and a check page, wherein the plurality of data pages are used to store a portion of the mapping table data corresponding to the array storage group, and the check page is used to store check data corresponding to the portion of the mapping table data, The check pages of the two adjacent array storage groups correspond to different chip enable pins.

2. The memory management method according to claim 1, characterized in that: The step of setting the plurality of array storage groups arranged in succession based on the word string line sequence, the chip enable pin sequence and the plane sequence comprises: Selecting a first array storage group to be set according to the sequence number of the plurality of array storage groups; Based on the word string line sequence, selecting a first available word string line; Based on the chip enable pin sequence, selecting one or more available first chip enable pins from a plurality of chip enable pins corresponding to the first string line; If the number of the one or more first chip enable pins is equal to M: Acquire a plurality of first physical pages corresponding to the P planes in each first chip enable pin; and The plurality of first physical pages are set as the plurality of physical pages of the first array storage group.

3. The memory management method according to claim 2, characterized in that: Based on the word string line sequence, the chip enable pin sequence and the plane sequence, the step of setting the plurality of array storage groups arranged in succession further comprises: If the number of the one or more first chip enable pins selected in the first string line is less than M: Selecting an available second string line that is sorted after the first string line; Based on the chip enable pin sequence, select one or more available second chip enable pins from the plurality of chip enable pins corresponding to the second string line, wherein the total number of the one or more first chip enable pins and the one or more second chip enable pins is M; Acquire a plurality of first physical pages corresponding to the P planes in each first chip enable pin, and acquire a plurality of second physical pages corresponding to the P planes in each second chip enable pin; and The plurality of first physical pages and the plurality of second physical pages are set as the plurality of physical pages of the first array storage group.

4. The memory management method according to claim 1, characterized in that: The check page of each array storage group is the last one of the multiple physical pages of the array storage group.

5. The memory management method according to claim 1, characterized in that: If N is an even number, there is a remainder when M is used as a divisor of N.

6. The memory management method according to claim 1, characterized in that: The predetermined value is 1.

7. The memory management method according to claim 1, characterized in that: The chip enable pin following the last chip enable pin of the i-th word string line is the first chip enable pin of the i+1-th word string line, wherein multiple physical pages of each array storage group correspond to multiple chip enable pins of the same word string line or to multiple chip enable pins of adjacent word string lines, Each string line includes N P entity pages.

8. The memory management method according to claim 1, characterized in that: The method further comprises: If a target chip fails, the target portion of the mapping table data stored in the target chip is reconstructed according to the portion of the mapping table data stored in other chips other than the target chip and the corresponding verification data.

9. A memory controller for controlling a storage device equipped with a rewritable non-volatile memory module, characterized in that: The memory controller comprises: A memory interface control circuit, for electrically connecting to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of chips, each of the plurality of chips corresponds to a chip enable pin, and each chip includes P planes; and A processor electrically connected to the memory interface control circuit, wherein the processor is further electrically connected to the connection interface circuit of the storage device to electrically connect to the host system, wherein the processor is configured to: Obtaining mapping table data to be stored; Determining a size of an array storage group according to a total number N of the plurality of chip enable pins, wherein the array storage group includes a plurality of physical pages corresponding to M chip enable pins, wherein M is less than N and greater than 1, and M is equal to N minus a predetermined value; Based on the word string line order, the chip enable pin order and the plane order, a plurality of array storage groups are set to be arranged in succession, wherein the plurality of physical pages of each array storage group correspond to different planes of the M chip enable pins respectively; and storing the mapping table data in the plurality of array storage groups, wherein the plurality of physical pages of each array storage group comprises a plurality of data pages and a check page, wherein the plurality of data pages are used to store a portion of the mapping table data corresponding to the array storage group, and the check page is used to store check data corresponding to the portion of the mapping table data, The check pages of the two adjacent array storage groups correspond to different chip enable pins.

10. The memory controller according to claim 9, characterized in that: The step of setting the plurality of array storage groups arranged in succession based on the word string line sequence, the chip enable pin sequence and the plane sequence comprises: Selecting a first array storage group to be set according to the sequence number of the plurality of array storage groups; Based on the word string line sequence, selecting a first available word string line; Based on the chip enable pin sequence, selecting one or more available first chip enable pins from a plurality of chip enable pins corresponding to the first string line; If the number of the one or more first chip enable pins is equal to M: Acquire a plurality of first physical pages corresponding to the P planes in each first chip enable pin; and The plurality of first physical pages are set as the plurality of physical pages of the first array storage group.

11. The memory controller according to claim 10, characterized in that: Based on the word string line sequence, the chip enable pin sequence and the plane sequence, the step of setting the plurality of array storage groups arranged in succession further comprises: If the number of the one or more first chip enable pins selected in the first string line is less than M: Selecting an available second string line that is sorted after the first string line; Based on the chip enable pin sequence, select one or more available second chip enable pins from the plurality of chip enable pins corresponding to the second string line, wherein the total number of the one or more first chip enable pins and the one or more second chip enable pins is M; Acquire a plurality of first physical pages corresponding to the P planes in each first chip enable pin, and acquire a plurality of second physical pages corresponding to the P planes in each second chip enable pin; and The plurality of first physical pages and the plurality of second physical pages are set as the plurality of physical pages of the first array storage group.

12. The memory controller according to claim 9, wherein: The check page of each array storage group is the last one of the multiple physical pages of the array storage group.

13. The memory controller according to claim 9, wherein: If N is an even number, there is a remainder when M is used as a divisor of N.

14. The memory controller according to claim 9, wherein: The predetermined value is 1.

15. The memory controller according to claim 9, wherein: The chip enable pin following the last chip enable pin of the i-th word string line is the first chip enable pin of the i+1-th word string line, wherein multiple physical pages of each array storage group correspond to multiple chip enable pins of the same word string line or to multiple chip enable pins of adjacent word string lines, Each string line includes N P entity pages.

16. The memory controller according to claim 9, wherein: The processor is also configured to: If a target chip fails, the target portion of the mapping table data stored in the target chip is reconstructed according to the portion of the mapping table data stored in other chips other than the target chip and the corresponding verification data.

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