Data processing method and device and related equipment

Abstract

The invention provides a data processing method and device and related equipment, and the method comprises the steps: responding to a received DMA read-write request, and determining the size of target data and a read-write initial address based on the DMA read-write request; based on the initial address, the size of the target data and the size of each memory block in the memory module, determining the size of a first TLP packet and a first read-write sequence corresponding to the first TLP packet, and the size of a second TLP packet and a second read-write sequence corresponding to the second TLP packet; and reading and writing the target data based on the initial address, the size of the first TLP packet, the first read-write sequence, the size of the second TLP packet, the second read-write sequence and the size of a preset TLP packet. According to the method and the device, the size of the TLP packet can be dynamically adjusted when the size of the critical part of the memory block is less than the size of one preset TLP packet or the size of the tail part of the target data is less than the size of one preset TLP packet, so that the granularity of DMA offset and the size of the TLP packet can be flexibly matched.

Description

Technical Field

[0001] The present application relates to the field of data transmission, and in particular to a data processing method, device and related equipment. Background Art

[0002] In the high-speed serial computer expansion bus (Peripheral Component Interconnect express, PCIe), direct memory access (DMA) is a commonly used data transmission method. In the DMA data transmission method, data is usually transmitted in the form of TLP (Transaction Layer Packet) packets. The size of TLP packets is usually fixed, such as 256 bytes. ， B), that is, data is mostly read or written in TLP packets of 256B. In addition, the memory module is usually divided into multiple memory blocks according to a fixed size, for example, the memory module is divided into multiple memory blocks according to 2M, and the physical address of the data to be written or read is located in each of the above memory blocks.

[0003] In the DMA transmission mode, when reading or writing data, it usually starts from the starting address (DMA offset) and reads data from the memory module or writes data to the memory module according to the size of the TLP packet. In order to prevent the same TLP packet from spanning two memory blocks when reading or writing, the granularity of the DMA offset needs to be set to an integer multiple of the TLP packet size. When the TLP packet is large, the granularity of the DMA offset is also large, and the data transmission is not flexible enough; when the TLP packet is small, the granularity of the DMA offset can be reduced to achieve the purpose of flexible transmission, but it will waste bandwidth. Summary of the invention

[0004] The main purpose of the present application is to propose a data processing method, apparatus and related equipment, aiming to solve the problem in the prior art that the granularity of DMA offset and the size of TLP packet cannot be flexibly adapted.

[0005] To achieve the above object, the present application proposes a data processing method, which is applied to a high-speed serial computer expansion bus. The data processing method comprises:

[0006] In response to receiving a DMA read / write request, determining a size of target data and a start address for reading or writing based on the DMA read / write request;

[0007] Determine the size of the first TLP packet and its corresponding first read-write order, and the size of the second TLP packet and its corresponding second read-write order based on the starting address, the size of the target data, and the size of each memory block in the memory module;

[0008] The size of the first TLP packet is the size of the critical part of the memory block when the target data is sequentially read and written according to the size of the preset TLP packet starting from the starting address in the memory block where the starting address is located, and the size of the critical part is smaller than the size of the preset TLP packet; the first read-write order is the order of reading and writing to the critical part when the target data is sequentially read and written according to the size of the preset TLP packet starting from the starting address;

[0009] The second TLP packet is the remaining part of the target data after sequentially reading and writing the target data according to the size of the preset TLP packet starting from the starting address, reading and writing the critical part according to the size of the first TLP packet when reading and writing to the critical part, and reading and writing the target data according to the size of the preset TLP packet starting from the next memory block, wherein the data size of the remaining part is smaller than the size of the preset TLP packet;

[0010] The second read-write order is to sequentially read and write the target data according to the size of the preset TLP packet starting from the starting address, read and write the critical part according to the size of the first TLP packet when reading and writing to the critical part, and read and write the target data according to the size of the preset TLP packet starting from the next memory block until the remaining part is read and written;

[0011] The target data is read and written based on the starting address, the size of the first TLP packet, the first read and write order, the size of the second TLP packet, the second read and write order, and the size of the preset TLP packet.

[0012] In an embodiment of the present application, the target data is read and written based on the starting address, the size of the first TLP packet, the first read and write order, the size of the second TLP packet, the second read and write order, and the size of the preset TLP packet, including:

[0013] Reading and writing the target data according to the size of the preset TLP packet starting from the starting address, and reading and writing the target data according to the size of the first TLP packet in the first reading and writing order;

[0014] The target data is read and written according to a preset TLP packet size after the first read and write order, and the target data is read and written according to the second TLP packet size in the second read and write order.

[0015] In an embodiment of the present application, the size of the first TLP packet and the first read and write order are determined based on the following method:

[0016] Determine the available memory in the memory block where the starting address is located based on the starting address and the boundary address of the memory block where the starting address is located;

[0017] Based on the available memory and the size of the preset TLP packet, the size of the first TLP packet and the first read and write order are determined.

[0018] In an embodiment of the present application, the size of the second TLP packet and the second read-write order are determined based on the following method:

[0019] Based on the starting address, the boundary address of the memory block where the starting address is located, and the size of the target data, determining the remaining data size of the target data after reading and writing in the memory block where the starting address is located;

[0020] Based on the remaining data size and the size of the preset TLP packet, the size of the second TLP packet and the second reading and writing order are determined.

[0021] The present application also proposes a data processing device, which is used in a high-speed serial computer expansion bus, and the data processing device comprises:

[0022] The transceiver module is configured to: in response to receiving a DMA read / write request, determine the size of the target data and the start address of the read / write based on the DMA read / write request;

[0023] The processing module is configured to: determine the size of the first TLP packet and its corresponding first read-write order, and the size of the second TLP packet and its corresponding second read-write order based on the starting address, the size of the target data, and the size of each memory block in the memory module;

[0024] The size of the first TLP packet is the size of the critical part of the memory block when the target data is sequentially read and written according to the size of the preset TLP packet starting from the starting address in the memory block where the starting address is located, and the size of the critical part is smaller than the size of the preset TLP packet; the first read-write order is the order of reading and writing to the critical part when the target data is sequentially read and written according to the size of the preset TLP packet starting from the starting address;

[0025] The second TLP packet is the remaining part of the target data after sequentially reading and writing the target data according to the size of the preset TLP packet starting from the starting address, reading and writing the critical part according to the size of the first TLP packet when reading and writing to the critical part, and reading and writing the target data according to the size of the preset TLP packet starting from the next memory block, wherein the data size of the remaining part is smaller than the size of the preset TLP packet;

[0026] The second read-write order is to sequentially read and write the target data according to the size of the preset TLP packet starting from the starting address, read and write the critical part according to the size of the first TLP packet when reading and writing to the critical part, and read and write the target data according to the size of the preset TLP packet starting from the next memory block until the remaining part is read and written;

[0027] The target data is read and written based on the starting address, the size of the first TLP packet, the first read and write order, the size of the second TLP packet, the second read and write order, and the size of the preset TLP packet.

[0028] In the embodiment of the present application, the processing module is further configured as follows:

[0029] Reading and writing the target data according to the size of the preset TLP packet starting from the starting address, and reading and writing the target data according to the size of the first TLP packet in the first reading and writing order;

[0030] The target data is read and written according to a preset TLP packet size after the first read and write order, and the target data is read and written according to the second TLP packet size in the second read and write order.

[0031] In an embodiment of the present application, the processing module is configured to determine the size of the first TLP packet and the first read and write order based on the following method:

[0032] Determine the available memory in the memory block where the starting address is located based on the starting address and the boundary address of the memory block where the starting address is located;

[0033] Based on the available memory and the size of the preset TLP packet, the size of the first TLP packet and the first read and write order are determined.

[0034] In an embodiment of the present application, the processing module is configured to determine the size of the second TLP packet and the second read-write order based on the following method:

[0035] Based on the starting address and the boundary address of the memory block where the starting address is located, determining the remaining data size of the target data after reading and writing in the memory block where the starting address is located;

[0036] Based on the remaining data size and the size of the preset TLP packet, the size of the second TLP packet and the second reading and writing order are determined.

[0037] The present application also proposes a computer-readable storage medium, which includes instructions. When the computer-readable storage medium is executed on a computer, the computer executes the method described in any one of the above embodiments.

[0038] The present application also proposes a computing device, which includes a processor, and the processor is used to implement the method described in any of the above embodiments when executing a computer program stored in a memory.

[0039] In the embodiment of the present application, when processing DMA read and write requests, when the critical part of the memory block is less than a preset TLP packet size, the size of the TLP packet can be dynamically adjusted to avoid reading and writing across the memory blocks, thereby avoiding errors caused by data transmission across the memory blocks; when the tail part of the target data is less than a preset TLP packet size, the size of the TLP packet is dynamically adjusted to avoid reading and writing data other than the target data, thereby ensuring the integrity of the data transmission; in addition, since the size of the TLP packet can be dynamically adjusted, the granularity of the DMA offset can be set smaller, so that small-scale data can be processed more accurately without wasting the transmission bandwidth. In addition, the compatibility and extensibility of the high-speed serial computer expansion bus can be enhanced. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0041] Figure 1 A schematic diagram of data transmission of a DMA read / write request in an example of the prior art;

[0042] Figure 2 A schematic diagram of data transmission of a DMA read / write request in another example of the prior art;

[0043] Figure 3 A step diagram of a data processing method in an embodiment of the present application;

[0044] Figure 4A schematic diagram of data transmission of a DMA read / write request in an embodiment of the present application;

[0045] Figure 5 A schematic diagram of data transmission of a DMA read / write request in an embodiment of the present application;

[0046] Figure 6 A schematic diagram of data transmission of a DMA read / write request in an embodiment of the present application;

[0047] Figure 7 A module diagram of a data processing device in an embodiment of the present application;

[0048] Figure 8 A module diagram of a computer-readable storage medium in an embodiment of the present application;

[0049] Fig. 9 A module diagram of a computing device in one embodiment of the present application.

[0050] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0051] The terms "including" and "having" in the specification and claims of the embodiments of the present application and the above-mentioned drawings and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device including a series of steps or modules is not necessarily limited to those steps or modules clearly listed, but may include other steps or modules that are not clearly listed or inherent to these processes, methods, products or devices. The division of modules appearing in the embodiments of the present application is only a logical division. There may be other division methods when implemented in actual applications. For example, multiple modules can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, indirect coupling between modules, and the communication connection can be electrical or other similar forms, which are not limited in the embodiments of the present application. In addition, the modules or submodules described as separate components may or may not be physically separated, may or may not be physical modules, or may be distributed in multiple circuit modules, and some or all of the modules may be selected according to actual needs to achieve the purpose of the embodiment of the present application.

[0052] The principles and spirit of the present application are explained in detail below with reference to several representative implementations of the present application.

[0053] Exemplary Methods

[0054] like Figure 1 As shown, Figure 1The data transmission diagram of DMA read and write request in the high-speed serial computer expansion bus (PCIe) in the prior art is shown in FIG. Figure 1 In the example shown, the memory module is divided into 2 megabyte (MegaByte, M) blocks, 0-2M is a memory block, 2-4M is a memory block, and 4-6M is a memory block. In addition, the DMA read and write request can be a DMA read request or a DMA write request, the write request can be a request to write data to each memory block of the memory module, and the read request can be a request to read data from each memory block of the memory module.

[0055] exist Figure 1 In the high-speed serial computer expansion bus shown, the size of the TLP packet is 256B and the size is fixed, that is, in a DMA read / write request, data can only be written to the memory module or read from the memory module according to the size of 256B.

[0056] Continue to refer to Figure 1 ,exist Figure 1 In the example shown, the size of the TLP packet is 256B. In order to ensure that the same TLP packet does not span two memory blocks when writing data to or reading data from the memory module, Figure 1 The granularity of DMA offset in is 256B, that is, DMA read and write requests can only start from addresses that are multiples of 256, such as 0, 256B, 512B, 768B, 1024B, etc., so as to ensure that when reading and writing to the boundary of the memory block, the entire memory block can be read and written in 256B size without crossing to the next memory block. At this time, due to the large granularity of DMA offset, data can only be read or written from the above-mentioned 0, 256B, 512B, 768B, 1024B, etc., which are multiples of 256, so the flexibility of data transmission is poor.

[0057] like Figure 2 As shown, in Figure 2 In the DMA, the memory module is still divided into 2M blocks, and the size of the TLP packet is still fixed at 256B, but the granularity of the DMA offset is set to 32B, that is, the DMA read and write requests can start data processing from addresses that are multiples of 32, such as 0, 32B, 64B, 96B, 128B, 160B, 192B, 224B, 256B, etc. Although the granularity of the DMA offset is smaller and data reading and writing is more flexible, the last TLP packet read and written in the 0-2M memory block spans the memory block to the 2-4M memory block, and if the read and write data is large, it may continue to span the boundary of the 2-4M memory block to the 4-6M memory block. When a TLP packet spans the boundary of the memory block for reading and writing, it is very easy to make mistakes.

[0058] Therefore, in order to balance the bandwidth utilization and data transmission flexibility during data transmission, the prior art mostly sets the TLP packet size to a fixed 256B, and simultaneously sets the granularity of the DMA offset to 256B, that is, the TLP packet size and the granularity of the DMA offset in the prior art cannot be flexibly matched.

[0059] Based on this, the present application proposes a data processing method, which is applied to a high-speed serial computer expansion bus to solve the problem in the prior art that the size of the TLP packet and the granularity of the DMA offset cannot be flexibly matched.

[0060] like Figure 3 As shown, in the embodiment of the present application, the data processing method includes the following steps S100-S300:

[0061] Step S100: In response to receiving a DMA read / write request, determining the size of target data and the start address of reading / writing based on the DMA read / write request.

[0062] In an embodiment of the present application, the data processing method is applied to a high-speed serial computer expansion bus, and the DMA read / write request can be a DMA read request or a DMA write request. In addition, the DMA read / write request can be a DMA read / write request sent by a PCIe terminal device mounted on the high-speed serial computer expansion bus to a host end, or a read / write request sent by the host end to a PCIe terminal device.

[0063] In addition, in an embodiment of the present application, the DMA read / write request includes the size of the target data requested to be read / written by the PCIe terminal device or host, as well as the starting address when it is read / written. For example, assuming that the DMA read / write request is a read request, that is, the target data needs to be read from the memory module, then the DMA read request includes the starting address and length of the storage location of the target data in the memory module. For another example, if the DMA read / write request is a write request, that is, the target data needs to be written to the memory module, then the DMA write request includes the starting address and length of the target data that needs to be written in the memory module.

[0064] Step S200: Based on the starting address, the size of the target data and the size of each memory block in the memory module, determine the size of the first TLP packet and its corresponding first read-write order, and the size of the second TLP packet and its corresponding second read-write order;

[0065] The size of the first TLP packet is the size of the critical part of the memory block when the target data is sequentially read and written according to the size of the preset TLP packet starting from the starting address in the memory block where the starting address is located, and the size of the critical part is smaller than the size of the preset TLP packet; the first read-write order is the order of reading and writing to the critical part when the target data is sequentially read and written according to the size of the preset TLP packet starting from the starting address;

[0066] The second TLP packet sequentially reads and writes the target data according to the size of the preset TLP packet starting from the starting address, reads and writes the critical part according to the size of the first TLP packet when reading and writing to the critical part, and reads and writes the target data from the next memory block according to the size of the preset TLP packet after reading and writing the remaining part of the target data, wherein the data size of the remaining part is smaller than the size of the preset TLP packet;

[0067] The second reading and writing order is to sequentially read and write the target data according to the size of the preset TLP packet starting from the starting address, read and write the critical part according to the size of the first TLP packet when reading and writing to the critical part, and read and write the target data according to the size of the preset TLP packet starting from the next memory block until the remaining part is read and written.

[0068] like Figure 4 As shown, in the embodiment of the present application, it is assumed that the memory module is divided into multiple memory blocks according to the size of 2M. Figure 4 Only the memory blocks of 0-2M and the memory blocks of 2-4M are shown, and other memory blocks are not shown. In addition, in other embodiments, the memory blocks can also be divided according to other storage data amounts.

[0069] Continue to refer to Figure 4 In the embodiment of the present application, the DMA read / write request is taken as an example, that is, the target data is read from the memory module. Assuming that in the embodiment of the present application, the granularity of the high-speed serial computer expansion bus DMA offset is 32B, the preset TLP packet size (TLP len) is 512B, and after step S100, it is determined that the size of the target data requested to be read by the DMA read request (DMA size) is 6012B, and the starting address (DAM offset) is 2091840B, then in step S100, the size of the first TLP packet and the first read / write order, as well as the size of the second TLP packet and the second read / write order are first determined.

[0070] Among them, the starting address 2091840B is located in the memory block of 0-2M, that is, starting from the address 2091840B of the memory block of 0-2M, when reading is started according to the preset TLP packet size 512B, after ten readings, the critical part of the 0-2M memory block is reached. The size of the critical part is smaller than the size of the preset TLP packet. When reading by using a method of fixing the TLP packet size in the prior art, it is inevitable to cross the memory block to the next memory block. The embodiment of the present application determines the size of the critical part and the first read-write order, such as Figure 4 As shown, in the embodiment of the present application, starting from 2091840B, after 10 preset TLP packets of 512B, the critical part of the memory block of 0-2M remains 192B, that is, the size of the first TLP packet is 192B, and the first read-write order is the 11th read after 10 preset TLP packets are read.

[0071] Continue to refer to Figure 1 After reading 10 preset TLP packets and 1 192B packet, the memory blocks from 0 to 2M are all read, and then the memory blocks from 2 to 4M are read. Figure 4 It can be seen that after reading a preset TLP package in the 2-4M memory block, only 188B of the target data remains, which is less than the size of a preset TLP package. The prior art reads according to a fixed-size TLP package, that is, the prior art still reads a complete 512B TLP package, which obviously exceeds the address range of the target data. In the embodiment of the present application, the remaining 188B is used as the size of the second TLP package, and based on Figure 4 It can be seen that after 10 preset TLP packet reads and 1 192B read, after another preset TLP packet read, it is the turn to read the remaining part, that is, the second reading order of the remaining part (the second TLP packet) is 13.

[0072] Step S300: Read and write the target data based on the starting address, the size of the first TLP packet, the first read and write order, the size of the second TLP packet, the second read and write order, and the size of the preset TLP packet.

[0073] by Figure 4For example, after the above step S200, it can be determined that the size of the first TLP packet is 192B, the first read-write order is 11, the size of the second TLP packet is 188B, and the second read-write order is 13. Then in step S300, starting from the starting address 2091840B, the reading is performed according to the preset TLP packet size during the 1st to 10th readings, the reading is performed according to the size of the first TLP packet during the 11th reading, the reading is performed according to the preset TLP packet size during the 12th reading, and the reading is performed according to the size of the second TLP packet during the 13th reading.

[0074] In an embodiment of the present application, when facing a critical part of a memory block, or when facing the end of target data, the size of the TLP packet can be dynamically adjusted, thereby avoiding reading and writing across memory blocks, and avoiding reading and writing other data outside the target data range.

[0075] exist Figure 4 In the illustrated embodiment, taking the preset TLP packet as 512B and the granularity of DMA offset as 32B as an example, the data processing method capable of dynamically adjusting the TLP packet size in the present application is introduced. In other embodiments, the granularity of DMAoffset and the preset TLP packet size may also be other values.

[0076] For example, Figure 5 As shown, in the embodiment of the present application, the granularity of the DMA offset can also be set to 64B, and the size of the preset TLP packet (TLP len) can be set to 1024B; or Figure 6 As shown, the granularity of the DMA offset is set to 32B, and the size of the preset TLP packet (TLP len) is set to 2048B.

[0077] Among them, Figure 5 As shown in the figure, when the granularity of DMA offset is set to 64B and the size of the preset TLP packet (TLPlen) is set to 1024B, the critical part of the 0-2M memory block is reached after 5 preset TLP packets starting from the starting address 2091840B, and the critical part is 192B, that is, the size of the first TLP packet is 192B, and the first read-write order is 6; when the memory is 2-4M, the remaining part of the target data is 700B, which is smaller than the size of the preset TLP packet, so the size of the second TLP packet is 700B, and the second read-write order is 7. At this time, the 1st to 5th reads and writes from the starting address are read and written according to the size of the preset TLP packet, the 6th read and write are read and written according to the size of 192B, and the 7th read and write are read and written according to the size of 700B.

[0078] like Figure 6As shown in the figure, when the granularity of DMA offset is set to 32B and the size of the preset TLP packet (TLP len) is set to 2048B, the critical part of the 0-2M memory block is reached after two preset TLP packets from the starting address 2091840B, and the critical part is 1216B, that is, the size of the first TLP packet is 1216B, and the first read-write order is 3; when the memory is 2-4M, the remaining part of the target data is 700B, which is smaller than the size of the preset TLP packet, so the size of the second TLP packet is 700B, and the second read-write order is 4. At this time, the 1st and 2nd reads and writes from the starting address are read and written according to the size of the preset TLP packet, the 3rd read and write are read and written according to the size of 192B, and the 4th read and write are read and written according to the size of 700B.

[0079] In an embodiment of the present application, when the critical part of the memory block is less than the size of a preset TLP packet, or when the end part of the target data is less than the size of a preset TLP packet, the size of the TLP packet can be dynamically adjusted. Therefore, the granularity of the DMA offset and the size of the TLP packet can be flexibly matched.

[0080] In an embodiment of the present application, the size of the first TLP packet and the first read and write order can be determined based on the following method:

[0081] Determine the available memory in the memory block where the starting address is located based on the starting address and the boundary address of the memory block where the starting address is located;

[0082] Based on the available memory and the size of the preset TLP packet, the size of the first TLP packet and the first read and write order are determined.

[0083] by Figure 4 For example, the starting address is 2091840B, and the boundary address of the memory block 0-2M is the address at 2M (2097152B). It can be seen that the available memory of the memory block 0-2M is 2097152-2091840=5312B. The available memory is divided by the size of the preset TLP packet, and the integer part obtained is the number of times read according to the size of the preset TLP packet. The integer part plus one is the first read and write order of the critical part (the first TLP packet), and the remainder part is the size of the critical part (the first TLP packet).

[0084] 53152B / 512B=10 more than 192B

[0085] The first read-write order is (10+1)=11;

[0086] The size of the first TLP packet is 192B.

[0087] In an embodiment of the present application, the size of the second TLP packet and the second read-write order can be determined based on the following method:

[0088] Based on the starting address, the boundary address of the memory block where the starting address is located, and the size of the target data, determining the remaining data size of the target data after reading and writing in the memory block where the starting address is located;

[0089] Based on the remaining data size and the size of the preset TLP packet, the size of the second TLP packet and the second reading and writing order are determined.

[0090] Still Figure 4 For example, the starting address is 2091840B, and the boundary address of the memory block 0-2M is 2M (2097152B). It can be seen that the available memory of the memory block 0-2M is 2097152-2091840=5312B. That is, the target data can read and write 5312B in the memory block 0-2M. Therefore, the size of the remaining data after the target data is read and written in the memory block where the starting address is located is the size of the target data minus the available space in the memory block 0-2M, that is, 6012-5312=700B.

[0091] After obtaining the size of the remaining data, divide the size of the remaining data by the size of the preset TLP packet. The integer part obtained is the number of preset TLP packets in the subsequent memory block, and the remainder part is the size of the last remaining part (the second TLP packet).

[0092] 700B / 512B=1 remainder 188B;

[0093] That is, the size of the second TLP packet is 188B.

[0094] In addition, the second read-write order is the first read-write order plus the integer part and then plus 1, that is, 11+1+1=13.

[0095] In addition, the addresses of each memory block in the above memory module are calculated in decimal. In the computer field, the starting address and the boundary address can also be expressed in hexadecimal. Therefore, the size of the first TLP packet and the size of the second TLP packet can also be calculated in hexadecimal.

[0096] For example, as shown in Table 1 below:

[0097] Table 1

[0098] Index Addr Len(Byte, B) 0 1f-fe80 100 1 1f-ff80 80 2 20-0000 100 3 20-0100 100 4 20-0200 100 5 20-0300 100 6 20-0400 80

[0099] As shown in Table 1 above, Index represents the read and write order, Addr represents the address, and Len represents the size of the TLP packet. The sizes of Addr and Len are both expressed in hexadecimal. For example, if the size of the TLP packet is 256B, the hexadecimal representation is 100B, and the address 1ffe80 is the hexadecimal representation of 2096768 (decimal).

[0100] As shown in Table 1 above, assuming that the starting address is 1ffe80, the preset TLP packet size is 100B (hexadecimal), and the size of the target data is 660B (hexadecimal). Starting from address 1f-ff80, when reading and writing for the 0th time, the target data of 100B (hexadecimal) is read and written, and the size of the address 1f-ff80 to 20-0000 is only 80B (hexadecimal), that is, less than the size of a preset TLP packet, so the size of the first TLP packet is 80B (hexadecimal), the first read and write order is 1, and the reading and writing continues from address 20-0000 according to the preset TLP packet size 100B (hexadecimal). After the read and write order is 2, 3, 4, and 5, the remaining data of the target data is only 80B (hexadecimal), that is, the size of the second TLP packet is 80B (hexadecimal), and the read and write order is 6.

[0101] In the embodiment of the present application, when processing DMA read and write requests, when the critical part of the memory block is less than a preset TLP packet size, the size of the TLP packet can be dynamically adjusted to avoid reading and writing across the memory blocks, thereby avoiding errors caused by data transmission across the memory blocks; when the tail part of the target data is less than a preset TLP packet size, the size of the TLP packet is dynamically adjusted to avoid reading and writing data other than the target data, thereby ensuring the integrity of the data transmission; in addition, since the size of the TLP packet can be dynamically adjusted, the granularity of the DMA offset can be set smaller, so that small-scale data can be processed more accurately without wasting the transmission bandwidth. In addition, the compatibility and extensibility of the high-speed serial computer expansion bus can be enhanced.

[0102] Exemplary Devices

[0103] like Figure 7 As shown, the present application also proposes a data processing device 100, which is used in a high-speed serial computer expansion bus. The data processing device 100 includes:

[0104] The transceiver module 110 is configured to: in response to receiving a DMA read / write request, determine the size of the target data and the start address of the read / write based on the DMA read / write request;

[0105] The processing module 120 is configured to: determine the size of the first TLP packet and its corresponding first read-write order, and the size of the second TLP packet and its corresponding second read-write order based on the starting address, the size of the target data, and the size of each memory block in the memory module;

[0106] The size of the first TLP packet is the size of the critical part of the memory block when the target data is sequentially read and written according to the size of the preset TLP packet starting from the starting address in the memory block where the starting address is located, and the size of the critical part is smaller than the size of the preset TLP packet; the first read-write order is the order of reading and writing to the critical part when the target data is sequentially read and written according to the size of the preset TLP packet starting from the starting address;

[0107] The second TLP packet sequentially reads and writes the target data according to the size of the preset TLP packet starting from the starting address, reads and writes the critical part according to the size of the first TLP packet when reading and writing to the critical part, and reads and writes the target data from the next memory block according to the size of the preset TLP packet after reading and writing the remaining part of the target data, wherein the data size of the remaining part is smaller than the size of the preset TLP packet;

[0108] The second read-write order is to sequentially read and write the target data according to the size of the preset TLP packet starting from the starting address, read and write the critical part according to the size of the first TLP packet when reading and writing to the critical part, and read and write the target data according to the size of the preset TLP packet starting from the next memory block until the remaining part is read and written;

[0109] The target data is read and written based on the starting address, the size of the first TLP packet, the first read and write order, the size of the second TLP packet, the second read and write order, and the size of the preset TLP packet.

[0110] In the embodiment of the present application, the processing module 120 is further configured to:

[0111] Reading and writing the target data according to the size of the preset TLP packet starting from the starting address, and reading and writing the target data according to the size of the first TLP packet in the first reading and writing order;

[0112] The target data is read and written according to a preset TLP packet size after the first read and write order, and the target data is read and written according to the second TLP packet size in the second read and write order.

[0113] In the embodiment of the present application, the processing module 120 is configured to determine the size of the first TLP packet and the first read and write order based on the following method:

[0114] Determine the available memory in the memory block where the starting address is located based on the starting address and the boundary address of the memory block where the starting address is located;

[0115] Based on the available memory and the size of the preset TLP packet, the size of the first TLP packet and the first read and write order are determined.

[0116] In the embodiment of the present application, the processing module 120 is configured to determine the size of the second TLP packet and the second read-write order based on the following method:

[0117] Based on the starting address and the boundary address of the memory block where the starting address is located, determining the remaining data size of the target data after reading and writing in the memory block where the starting address is located;

[0118] Based on the remaining data size and the size of the preset TLP packet, the size of the second TLP packet and the second reading and writing order are determined.

[0119] The implementation of each module of the data processing device 100 in each of the above embodiments can refer to each embodiment of the data processing method, which will not be described in detail here.

[0120] In the embodiment of the present application, by setting the processing module 120, when processing a DMA read / write request, when the critical part of the memory block is less than the size of a preset TLP packet, the size of the TLP packet can be dynamically adjusted to avoid reading and writing across the memory block, thereby avoiding errors caused by data transmission across the memory block; when the tail part of the opposite target data is less than the size of a preset TLP packet, the size of the TLP packet is dynamically adjusted to avoid reading and writing data other than the target data, thereby ensuring the integrity of the data transmission; in addition, since the size of the TLP packet can be dynamically adjusted, a DMA offset with a smaller granularity can be set, so that small-scale data can be processed more accurately without wasting transmission bandwidth. In addition, the compatibility and extensibility of the high-speed serial computer expansion bus can also be enhanced.

[0121] Exemplary Media

[0122] After introducing the method and device of the exemplary embodiment of the present application, next, refer to Figure 8 For a description of the computer-readable storage medium of the exemplary embodiment of the present application, please refer to Figure 8, the computer-readable storage medium shown is a CD 70, on which a computer program (i.e., a program product) is stored. When the computer program is executed by the processor, the steps described in the above method implementation are implemented, for example, in response to receiving a DMA read / write request, the size of the target data and the starting address of the read / write are determined based on the DMA read / write request; based on the starting address, the size of the target data, and the size of each memory block in the memory module, the size of the first TLP packet and its corresponding first read / write order, as well as the size of the second TLP packet and its corresponding second read / write order are determined; wherein the size of the first TLP packet is the size of the critical part of the memory block when the target data is sequentially read and written from the starting address according to the size of the preset TLP packet in the memory block where the starting address is located, and the size of the critical part is smaller than the size of the preset TLP packet; the first read / write order is the size of the critical part when the target data is sequentially read and written from the starting address according to the size of the preset TLP packet. The second TLP packet is to sequentially read and write the target data according to the size of the preset TLP packet from the starting address, read and write the critical part according to the size of the first TLP packet when reading and writing to the critical part, and read and write the target data according to the size of the preset TLP packet from the next memory block, and read and write the target data according to the size of the preset TLP packet until the remaining part is read and written; based on the starting address, the size of the first TLP packet, the first read and write order, the size of the second TLP packet, the second read and write order, and the size of the preset TLP packet, the target data is read and written. The specific implementation method of each step will not be repeated here. It should be noted that examples of the computer-readable storage medium may also include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other optical or magnetic storage media, which are not listed here one by one.

[0123] Exemplary Computing Devices

[0124] refer to Fig. 9 , the present application also provides a computing device.

[0125] Fig. 9 A block diagram of an exemplary computing device 80 suitable for implementing embodiments of the present application is shown. The computing device 80 may be a computer system or a server. Fig. 9 The computing device 80 shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0126] like Fig. 9 As shown, the components of the computing device 80 may include, but are not limited to: one or more processors or processing units 801, a system memory 802, and a bus 803 connecting different system components (including the system memory 802 and the processing unit 801).

[0127] The computing device 80 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by the computing device 80, including volatile and non-volatile media, removable and non-removable media.

[0128] The system storage 802 may include computer system readable media in the form of volatile storage, such as random access memory (RAM) 8021 and / or cache memory 8022. The computing device 80 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, the ROM 8023 may be used to read and write non-removable, non-volatile magnetic media ( Fig. 9 is not shown in the Fig. 9 As shown in FIG. 8 , a disk drive for reading and writing a removable non-volatile disk (e.g., a “floppy disk”) and an optical disk drive for reading and writing a removable non-volatile optical disk (e.g., a CD-ROM, a DVD-ROM, or other optical media) can be provided. In these cases, each drive can be connected to bus 803 via one or more data medium interfaces. System storage 802 may include at least one program product having a set (e.g., at least one) of program modules that are configured to perform the functions of each embodiment of the present application.

[0129] A program / utility 8025 having a set (at least one) of program modules 8024 may be stored, for example, in system memory 802, and such program modules 8024 include, but are not limited to, an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment. Program modules 8024 generally perform the functions and / or methods of the embodiments described herein.

[0130] The computing device 80 may also communicate with one or more external devices 804 (e.g., a keyboard, a pointing device, a display, etc.). Such communication may be performed via an input / output (I / O) interface. Furthermore, the computing device 80 may also communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) via a network adapter 806. Fig. 9 As shown, the network adapter 806 communicates with other modules (such as the processing unit 801, etc.) of the computing device 80 via the bus 803. It should be understood that although Fig. 9 Not shown, other hardware and / or software modules may be used in conjunction with computing device 80 .

[0131] The processing unit 801 executes various functional applications and data processing by running the program stored in the system memory 802. For example, in response to receiving a DMA read / write request, the processing unit 801 determines the size of the target data and the starting address of the read / write based on the DMA read / write request; based on the starting address, the size of the target data and the size of each memory block in the memory module, determines the size of the first TLP packet and its corresponding first read / write order, as well as the size of the second TLP packet and its corresponding second read / write order; wherein the size of the first TLP packet is the size of the critical part of the memory block when the target data is sequentially read and written from the starting address according to the size of the preset TLP packet in the memory block where the starting address is located, and the size of the critical part is smaller than the size of the preset TLP packet; the first read / write order is the order of reading and writing to the critical part when the target data is sequentially read and written from the starting address according to the size of the preset TLP packet; the second TLP packet is the order of reading and writing to the critical part from the starting address; the second TLP packet is the order of reading and writing to the critical part from the starting address. The target data is sequentially read and written according to the size of the preset TLP packet starting from the starting address, and the critical part is read and written according to the size of the first TLP packet when reading and writing to the critical part, and the remaining part of the target data is read and written according to the size of the preset TLP packet starting from the next memory block, wherein the size of the remaining part is smaller than the size of the preset TLP packet; the second read and write order is to sequentially read and write the target data according to the size of the preset TLP packet starting from the starting address, and the critical part is read and written according to the size of the first TLP packet when reading and writing to the critical part, and the target data is read and written according to the size of the preset TLP packet starting from the next memory block until the remaining part is read and written; based on the starting address, the size of the first TLP packet, the first read and write order, the size of the second TLP packet, the second read and write order and the size of the preset TLP packet, the target data is read and written. The specific implementation method of each step will not be repeated here. It should be noted that, although several units / modules or sub-units / sub-modules of the computing device are mentioned in the above detailed description, this division is merely exemplary and not mandatory. In fact, according to the embodiments of the present application, the features and functions of two or more units / modules described above can be embodied in one unit / module. Conversely, the features and functions of one unit / module described above can be further divided into multiple units / modules to be embodied.

[0132] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The protection scope of the present application is not limited thereto. Although the present application is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed in the present application, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

[0133] In addition, although the operations of the method of the present application are described in a specific order in the drawings, this does not require or imply that the operations must be performed in this specific order, or that all the operations shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.

Claims

1. A data processing method, applied to a high-speed serial computer expansion bus, comprising: In response to receiving a DMA read / write request, determining a size of target data and a start address for reading or writing based on the DMA read / write request; Determine the size of the first TLP packet and its corresponding first read-write order, and the size of the second TLP packet and its corresponding second read-write order based on the starting address, the size of the target data, and the size of each memory block in the memory module; The size of the first TLP packet is the size of the critical part of the memory block when the target data is sequentially read and written according to the size of the preset TLP packet starting from the starting address in the memory block where the starting address is located, and the size of the critical part is smaller than the size of the preset TLP packet; the first read-write order is the order of reading and writing to the critical part when the target data is sequentially read and written according to the size of the preset TLP packet starting from the starting address; The second TLP packet sequentially reads and writes the target data according to the size of the preset TLP packet starting from the starting address, reads and writes the critical part according to the size of the first TLP packet when reading and writing to the critical part, and reads and writes the target data from the next memory block according to the size of the preset TLP packet after reading and writing the remaining part of the target data, wherein the data size of the remaining part is smaller than the size of the preset TLP packet; The second read-write order is to sequentially read and write the target data according to the size of the preset TLP packet starting from the starting address, read and write the critical part according to the size of the first TLP packet when reading and writing to the critical part, and read and write the target data according to the size of the preset TLP packet starting from the next memory block until the remaining part is read and written; The target data is read and written based on the starting address, the size of the first TLP packet, the first read and write order, the size of the second TLP packet, the second read and write order, and the size of the preset TLP packet.

2. The data processing method according to claim 1, wherein the target data is read and written based on the starting address, the size of the first TLP packet, the first read-write order, the size of the second TLP packet, the second read-write order, and the size of the preset TLP packet, comprising: Reading and writing the target data according to the size of the preset TLP packet starting from the starting address, and reading and writing the target data according to the size of the first TLP packet in the first reading and writing order; The target data is read and written according to a preset TLP packet size after the first read and write order, and the target data is read and written according to the second TLP packet size in the second read and write order.

3. data processing method as claimed in claim 1, the size of described first TLP bag and described first read-write order are determined based on the following method: Determine the available memory in the memory block where the starting address is located based on the starting address and the boundary address of the memory block where the starting address is located; Based on the available memory and the size of the preset TLP packet, the size of the first TLP packet and the first read and write order are determined.

4. data processing method as claimed in claim 1, the size of second TLP bag and second read-write order are determined based on the following method: Based on the starting address, the boundary address of the memory block where the starting address is located, and the size of the target data, determining the remaining data size of the target data after reading and writing in the memory block where the starting address is located; Based on the remaining data size and the size of the preset TLP packet, the size of the second TLP packet and the second reading and writing order are determined.

5. A data processing device, used in a high-speed serial computer expansion bus, the data processing device comprising: The transceiver module is configured to: in response to receiving a DMA read / write request, determine the size of the target data and the start address of the read / write based on the DMA read / write request; The processing module is configured to: determine the size of the first TLP packet and its corresponding first read-write order, and the size of the second TLP packet and its corresponding second read-write order based on the starting address, the size of the target data, and the size of each memory block in the memory module; The size of the first TLP packet is the size of the critical part of the memory block when the target data is sequentially read and written according to the size of the preset TLP packet starting from the starting address in the memory block where the starting address is located, and the size of the critical part is smaller than the size of the preset TLP packet; the first read-write order is the order of reading and writing to the critical part when the target data is sequentially read and written according to the size of the preset TLP packet starting from the starting address; The second TLP packet sequentially reads and writes the target data according to the size of the preset TLP packet starting from the starting address, reads and writes the critical part according to the size of the first TLP packet when reading and writing to the critical part, and reads and writes the target data from the next memory block according to the size of the preset TLP packet after reading and writing the remaining part of the target data, wherein the data size of the remaining part is smaller than the size of the preset TLP packet; The second read-write order is to sequentially read and write the target data according to the size of the preset TLP packet starting from the starting address, read and write the critical part according to the size of the first TLP packet when reading and writing to the critical part, and read and write the target data according to the size of the preset TLP packet starting from the next memory block until the remaining part is read and written; The target data is read and written based on the starting address, the size of the first TLP packet, the first read and write order, the size of the second TLP packet, the second read and write order, and the size of the preset TLP packet.

6. The data processing device according to claim 5, wherein the processing module is further configured to: Reading and writing the target data according to the size of the preset TLP packet starting from the starting address, and reading and writing the target data according to the size of the first TLP packet in the first reading and writing order; The target data is read and written according to a preset TLP packet size after the first read and write order, and the target data is read and written according to the second TLP packet size in the second read and write order.

7. The data processing device of claim 5, wherein the processing module is configured to determine the size of the first TLP packet and the first read-write order based on the following method: Determine the available memory in the memory block where the starting address is located based on the starting address and the boundary address of the memory block where the starting address is located; Based on the available memory and the size of the preset TLP packet, the size of the first TLP packet and the first read and write order are determined.

8. The data processing device of claim 5, wherein the processing module is configured to determine the size of the second TLP packet and the second read-write order based on the following method: Based on the starting address and the boundary address of the memory block where the starting address is located, determining the remaining data size of the target data after reading and writing in the memory block where the starting address is located; Based on the remaining data size and the size of the preset TLP packet, the size of the second TLP packet and the second reading and writing order are determined.

9. A computer-readable storage medium comprising instructions, which, when executed on a computer, enables the computer to execute the method according to any one of claims 1 to 4.

10. A computing device, comprising a processor, wherein the processor is configured to implement the method according to any one of claims 1 to 4 when executing a computer program stored in a memory.

Images