Method and device for analyzing coupling failure of integrated circuit

Abstract

The invention particularly relates to an analysis method for coupling failure of an integrated circuit. The analysis method comprises the following steps: constructing a ring oscillator circuit; executing the ring oscillator circuit based on a preset power supply parameter, and obtaining output voltage data in a corresponding initial state; inputting the initial state output voltage data into a coupling failure model, and obtaining output voltage data in a coupling failure state output by the model; wherein the coupling failure model is constructed based on a reaction diffusion model of an NBTI effect and an energy driving model of an HCD effect; and acquiring first oscillation frequency data and second oscillation frequency data corresponding to the output voltage data in the initial state and the output voltage data in the coupling failure state, and determining degradation analysis data of the circuit frequency performance based on the first oscillation frequency data and the second oscillation frequency data. According to the method, joint analysis on failure mechanisms of the NBTI effect and the HCD effect is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an analysis method and device for integrated circuit coupling failure, a storage medium, a computer program product, and an electronic device. Background Art

[0002] In the related art, with the continuous development of integrated circuits, faster, lower power consumption and smaller chips are provided. On the one hand, reliability issues such as negative bias temperature instability (NBTI) and hot-carrier degradation (HCD) have become more serious, which will cause the degradation of key electrical parameters such as transistor threshold voltage, saturation leakage current, and subthreshold swing, seriously affecting the service life of the chip. Integrated circuit design requires compact and accurate modeling of these issues to accurately predict the impact of degradation effects on circuit characteristics, thereby leaving margins for design. In existing technical solutions, NBTI and HCD problems are usually studied separately under idealized conditions.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0004] The present invention provides a method and device for analyzing coupled failure of integrated circuits, a storage medium, a computer program product, and an electronic device, which can jointly analyze the failure mechanisms of NBTI effect and HCD effect, thereby overcoming the defects in the prior art to a certain extent.

[0005] Other features and advantages of the present invention will become apparent from the following detailed description, or may be learned in part by practice of the present invention.

[0006] According to a first aspect of the present invention, a method for analyzing coupling failure of an integrated circuit is provided, the method comprising:

[0007] Build a ring oscillator circuit;

[0008] Execute the ring oscillator circuit based on preset power supply parameters to obtain output voltage data in a corresponding initial state;

[0009] Input the initial state output voltage data into a coupling failure model to obtain output voltage data under a coupling failure state output by the model; wherein the coupling failure model is constructed based on a reaction diffusion model of the NBTI effect and an energy driving model of the HCD effect;

[0010] The first oscillation frequency data and the second oscillation frequency data corresponding to the output voltage data in the initial state and the output voltage data in the coupling failure state are obtained, and degradation analysis data of the circuit frequency performance is determined based on the first oscillation frequency data and the second oscillation frequency data.

[0011] In some exemplary embodiments, the method further includes: pre-training the coupling failure model, including:

[0012] Collect voltage-threshold voltage degradation data, time-threshold voltage degradation data, AC stress duty cycle-threshold voltage degradation data, and AC stress frequency-threshold voltage degradation data corresponding to the target size PMOS transistor to construct a sample data set;

[0013] Based on the reaction-diffusion model of NBTI effect and the energy-driven model of HCD effect, an initial coupling failure model is constructed; the reaction-diffusion model based on NBTI effect is used to describe the threshold voltage degradation of NBTI effect; the energy-driven model based on HCD effect is used to describe the threshold voltage degradation of HCD effect;

[0014] The sample data set is used to perform forward propagation training on the initial coupling failure model, and the model hyperparameters are determined to obtain the trained coupling failure model.

[0015] In some exemplary embodiments, the threshold voltage degradation of the NBTI effect is described according to the relationship between gate voltage, AC stress duty cycle, time, and threshold voltage degradation.

[0016] In some exemplary embodiments, the threshold voltage degradation of the HCD effect is described based on the relationship between gate voltage and drain voltage, frequency of the AC voltage stress, time, and the threshold voltage degradation.

[0017] In some exemplary embodiments, the model hyperparameters include: NBTI effect failure weight, NBTI effect voltage influence factor, NBTI effect AC signal duty cycle influence factor, HCD effect failure weight, HCD voltage influence factor, HCD frequency influence factor, and saturation effect coefficient.

[0018] In some exemplary embodiments, the method further comprises:

[0019] Create a new library;

[0020] Calling an editor tool of the Cadence Virtuoso tool to compile the trained coupling failure model to obtain a corresponding coupling failure model file;

[0021] The source file corresponding to the coupling failure model file is saved in the new library, and the input port of the coupling failure model file is configured as a gate voltage stress port, a source voltage stress port and a drain voltage stress port, and the output port is a threshold voltage degradation amount.

[0022] According to a second aspect of the present invention, there is provided an analysis device for integrated circuit coupling failure, comprising:

[0023] Integrated circuit generation module for building ring oscillator circuits;

[0024] An initial data generating module, configured to execute the ring oscillator circuit based on preset power supply parameters and obtain output voltage data in a corresponding initial state;

[0025] A failure data generation module, used to input the initial state output voltage data into a coupled failure model to obtain output voltage data under a coupled failure state output by the model; wherein the coupled failure model is constructed based on a reaction diffusion model of the NBTI effect and an energy driven model of the HCD effect;

[0026] A data analysis module is used to obtain the first oscillation frequency data and the second oscillation frequency data corresponding to the output voltage data in the initial state and the output voltage data in the coupling failure state, and determine the degradation analysis data of the circuit frequency performance based on the first oscillation frequency data and the second oscillation frequency data.

[0027] According to a third aspect of the present invention, there is provided a storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the analysis method for integrated circuit coupling failure described in the first aspect is implemented.

[0028] According to a fourth aspect of the present invention, there is provided an electronic device, comprising:

[0029] Processor; and

[0030] A memory, configured to store executable instructions of the processor;

[0031] The processor is configured to implement the analysis method for integrated circuit coupling failure described in the first aspect above by executing the executable instructions.

[0032] According to a fifth aspect of the present invention, there is provided a computer program product having a computer program stored thereon, and when the computer program is executed by a processor, the method for analyzing coupling failure of an integrated circuit described in the first aspect is implemented.

[0033] The analysis method for coupled failure of integrated circuits provided by the embodiment of the present invention can reasonably describe the interaction between NBTI and HCD failure mechanisms by constructing a coupled failure model based on the reaction diffusion model of the NBTI effect and the energy driven model of the HCD effect, so that the solution is more consistent with the failures experienced during normal operation of the circuit and has better universality; thus accurately analyzing the degradation of circuit performance. No iteration is required during data analysis, thereby improving data analysis efficiency.

[0034] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present invention, and together with the specification are used to explain the principles of the present invention. Obviously, the accompanying drawings described below are only some embodiments of the present invention, and for those of ordinary skill in the art, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0036] Figure 1 A schematic diagram schematically illustrates an analysis method for integrated circuit coupling failure according to an exemplary embodiment of the present invention;

[0037] Figure 2 A schematic diagram schematically showing data comparison of a trained coupling failure model according to an exemplary embodiment of the present invention;

[0038] Figure 3 A schematic diagram schematically showing a comparison between a model calculation result and experimental data of an exemplary embodiment of the present invention showing the influence of an AC stress duty cycle SF on threshold voltage degradation;

[0039] Figure 4 A schematic diagram schematically showing a comparison between a model calculation result and experimental data showing a power exponential relationship between threshold voltage degradation and frequency according to an exemplary embodiment of the present invention;

[0040] Figure 5 A schematic diagram schematically showing a comparison between a model calculation result of a time power exponent obtained by an energy-driven model according to an exemplary embodiment of the present invention and experimental data;

[0041] Figure 6 A schematic diagram schematically shows the structure of a ring oscillator circuit according to an exemplary embodiment of the present invention;

[0042] Figure 7 A schematic diagram schematically illustrates a structure of adding a voltage-controlled voltage source to the gate of a PMOS transistor according to an exemplary embodiment of the present invention;

[0043] Figure 8 A schematic diagram schematically illustrates an input and output port of an exemplary embodiment of the present invention;

[0044] Fig. 9 A schematic diagram schematically showing data comparison of frequency degradation of a ring oscillator according to an exemplary embodiment of the present invention;

[0045] Fig.10 A schematic diagram schematically shows an exemplary embodiment of the present invention, a motion recognition system based on sensory integration and multi-device collaboration;

[0046] Fig.11 The figure schematically shows the composition of an electronic device in an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0047] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the present invention will be more comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0048] In addition, the accompanying drawings are only schematic illustrations of the present invention and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0049] In the related art, in the actual working circuit, on the one hand, the PMOS transistor is subjected to AC voltage stress, and under different working environments, the AC voltage stress has different duty cycles, which will cause NBTI failure to have different degrees of influence on the PMOS transistor. On the other hand, the PMOS transistor is subjected to AC voltage stress, and under different working environments, the AC voltage stress has different frequencies, which will cause HCD failure to have different degrees of influence on the PMOS transistor. In addition, the performance of the integrated circuit gradually degrades and eventually fails during long-term operation, and the working life is generally measured in years. Under such long-term working conditions, there is a saturation phenomenon in HCD failure. For the PMOS transistor affected by HCD failure, the threshold voltage degradation rate is constant in the initial stage. After a long time, the threshold voltage degradation rate gradually slows down until saturation.

[0050] In existing technical solutions, NBTI and HCD problems are usually studied separately under idealized settings. In NBTI studies, no voltage is applied to the drain, resulting in uniform degradation of the Si / SiO2 interface. As the drain voltage increases, the degradation becomes non-uniform, and the contribution of HCD to the total degradation increases. The existing technology lacks research on the impact of NBTI and HCD coupling failure mechanisms on digital circuit performance.

[0051] In view of the shortcomings and deficiencies of the prior art, this example implementation provides an analysis method for integrated circuit coupling failure, explores the reliability of integrated circuits and estimates circuit life based on the physical mechanism of failure, and establishes a coupling failure analysis method that combines NBTI effect and HCD effect for integrated circuit reliability design.

[0052] In this example implementation, reference Figure 1 As shown, the analysis method for integrated circuit coupling failure may specifically include the following steps:

[0053] Step S11, constructing a ring oscillator circuit;

[0054] Step S12, executing the ring oscillator circuit based on preset power supply parameters to obtain output voltage data in a corresponding initial state;

[0055] Step S13, inputting the output voltage data of the initial state into a coupling failure model, and obtaining the output voltage data of the model output under the coupling failure state; wherein the coupling failure model is constructed based on the reaction diffusion model of the NBTI effect and the energy driving model of the HCD effect;

[0056] Step S14, obtaining first oscillation frequency data and second oscillation frequency data corresponding to the output voltage data in the initial state and the output voltage data in the coupling failure state, and determining degradation analysis data of the circuit frequency performance based on the first oscillation frequency data and the second oscillation frequency data.

[0057] Hereinafter, each step of the analysis method for integrated circuit coupling failure in this exemplary implementation will be described in more detail with reference to the accompanying drawings and embodiments.

[0058] Exemplarily, the above method includes: pre-training the coupling failure model. Specifically, it may include:

[0059] Step S21, collecting voltage-threshold voltage degradation data, time-threshold voltage degradation data, AC stress duty cycle-threshold voltage degradation data, and AC stress frequency-threshold voltage degradation data corresponding to the target size PMOS transistor to construct a sample data set;

[0060] Step S22, constructing an initial coupling failure model based on a reaction-diffusion model of the NBTI effect and an energy-driven model of the HCD effect; wherein the reaction-diffusion model based on the NBTI effect is used to describe the threshold voltage degradation of the NBTI effect; and the energy-driven model based on the HCD effect is used to describe the threshold voltage degradation of the HCD effect;

[0061] Step S23, using the sample data set to perform forward propagation training on the initial coupling failure model, determine the model hyperparameters, and obtain the trained coupling failure model.

[0062] Exemplarily, voltage-threshold voltage degradation data, time-threshold voltage degradation data, AC stress duty cycle-threshold voltage degradation data, and AC stress frequency-threshold voltage degradation data of 28nm HKMG PMOS transistors can be collected in advance from multiple data sources. Each data source can be public experimental data. The existing experimental data is used to construct a sample data set for fitting the model.

[0063] For example, the threshold voltage degradation of the NBTI effect can be described according to the relationship between the gate voltage, the AC stress duty cycle, time and the threshold voltage degradation, and the threshold voltage degradation of the HCD effect can be described according to the relationship between the gate voltage and the drain voltage, the frequency of the AC voltage stress, time and the threshold voltage degradation.

[0064] Specifically, the reaction-diffusion (RD) model corresponding to the NBTI effect includes:

[0065]

[0066] In the RD model, there are two processes, the generation and recovery of the interface, which are respectively expressed as the above two basic formulas. The RD model is solved to obtain the following results:

[0067]

[0068] The model reproduces the classic experimental result of a time exponent of 1 / 4. After the double-interface RD model is introduced, the diffusion of hydrogen is corrected to H2 diffusion, resulting in a time exponent of 1 / 6.

[0069] The energy driving model corresponding to the HCD effect can be expressed as:

[0070]

[0071] Where (Vd – Vdsat) is proportional to the lateral electric field (ELat) in the pinch-off region, and parameter A is a process-dependent constant. g -V TH pThe term is related to the carrier density. In 28nm FDSOI, p≈1.

[0072] For example, a coupled failure model is constructed based on the reaction-diffusion RD model of the NBTI effect and the energy-driven model of the HCD effect. The specific formula can be expressed as follows:

[0073]

[0074] in, The threshold voltage degradation model related to NBTI failure is described in part. gs ) is a voltage model obtained by mathematically deriving the basic formula of RD theory, which describes the effect of gate voltage Vgs on threshold voltage degradation.

[0075] The effect of AC stress duty cycle SF on threshold voltage degradation is described. The model calculation results and experimental data are compared. Figure 3 shown.

[0076] t m It describes the time dependence of threshold voltage degradation. By mathematically approximating and deducing the basic formula of RD theory, it is found that there is a power exponential relationship between threshold voltage degradation and time.

[0077] in, The part is used to describe the threshold voltage degradation model related to HCD failure. is the voltage model obtained from the energy-driven theory, which describes the effect of gate voltage Vgs and drain voltage Vds on threshold voltage degradation; f i The frequency of AC voltage stress is taken into account. A large amount of experimental data shows that the threshold voltage degradation is exponentially related to the frequency, so the frequency is constructed in the form of a power exponent. The model calculation results and experimental data are compared. Figure 4 shown.

[0078] It describes the saturation phenomenon of HCD failure in long-term degradation. The power exponent of time t obtained by the energy-driven model is 0.5. The comparison between the model calculation results and the experimental data is as follows: Figure 5 shown.

[0079] and g are the pre-functions of NBTI and HCD, respectively, and these two parts describe the interaction between the two effects when NBTI and HCD exist simultaneously. The model provided by this method is a long-term compact model that can be used to calculate the long-term degradation of the circuit under different voltage stress conditions.

[0080] Exemplarily, the constructed sample data set can be used to perform forward training on the model to determine the hyperparameters of the model.

[0081] Exemplarily, the model hyperparameters include: NBTI effect failure weight, NBTI effect voltage influence factor, NBTI effect AC signal duty cycle influence factor, HCD effect failure weight, HCD voltage influence factor, HCD frequency influence factor, and saturation effect coefficient.

[0082] Specifically, corresponding to the coupled failure model, formula a is the NBTI failure weight, g is the HCD failure weight; b is the NBTI voltage influence factor, c, d, and e are the NBTI AC signal duty cycle influence factors; h is the HCD voltage influence factor, i is the HCD frequency influence factor, and k is the saturation effect coefficient.

[0083] Comparison of model calculation results and experimental data Figure 2 As shown in the figure, simulationdata is the model calculation result, and extractdata is the experimental data. The experimental condition settings in the reference are kept consistent with the simulation condition settings, where the gate and drain voltage bias is the worst stress condition, and the voltage is set to V gs =V ds = -1.8V, the simulation time remains unchanged and is set to 6×10 4 s. Ignoring data extraction errors, Figure 4 It can be observed that the degradation simulation curve of the coupling failure model and the experimental data curve fit well, indicating that the curve degradation trend of the threshold voltage is consistent with the experimental data in the literature. The model can be applied to the 28nm process node to predict the device degradation caused by the coupling failure effect.

[0084] The model provided by this method reasonably analyzes the NBTI failure mechanism and HCD failure mechanism of the integrated circuit, establishes the voltage dependence and time dependence of NBTI based on the RD theory, and considers the influence of AC stress duty cycle on NBTI failure, and establishes the corresponding duty cycle model. The voltage dependence and time dependence of HCD are established based on the energy-driven model, and the influence of AC stress frequency on HCD failure and the saturation effect of HCD failure under long time scale are considered, and the corresponding frequency model and saturation model are established. The power exponential model of gate voltage is used to describe the interaction between NBTI and HCD, rather than simply superimposing the two; and finally a coupling model including duty cycle effect, frequency effect, and saturation effect is obtained. This model is a long-term DC model for long-term performance prediction. The duty cycle can also be used to simulate AC stress for a long time. This model is a compact model, compatible with SPICE simulation software, and can be easily described in Verilog-A language.

[0085] Exemplarily, the method further comprises:

[0086] Step S31, creating a new library;

[0087] Step S32, calling an editor tool of the Cadence Virtuoso tool to compile the trained coupling failure model to obtain a corresponding coupling failure model file;

[0088] Step S33, constructing a source file corresponding to the coupling failure model file and saving it in the new library, and configuring the input port of the coupling failure model file to be a gate voltage stress port, a source voltage stress port and a drain voltage stress port, and the output port to be a threshold voltage degradation amount.

[0089] Specifically, Cadence Virtuoso simulation software is used to create a new library, the Edit tool of Cadence Virtuoso is called, the coupling failure model is described using Verilog-A language, and the Symbol module is created and saved in the new library.

[0090] The input ports of the Symbol module include a voltage stress port and a ground port. The voltage stress port is divided into a gate voltage stress port V h , Source voltage stress port V s and drain voltage stress port V d , the output port is the threshold voltage degradation amount, such as Figure 8 shown.

[0091] Exemplarily, in step S11 , a ring oscillator circuit is constructed.

[0092] Specifically, the 28nm process library is used in the Cadence Virtuoso Schematic Editor tool to build a ring oscillator circuit. The circuit structure is as follows: Figure 6 As shown. It can be used as a sub-circuit module of the coupling failure model and applied to the gate of the PMOS transistor in the constructed ring oscillator circuit. The circuit includes the typical structure and output drive of the ring oscillator, and adds a voltage-controlled voltage source at the gate of the PMOS. The transistor parameters are set, the channel width-to-length ratio of the NMOS transistor is W / L=400 / 40nm, and the channel width-to-length ratio of the PMOS transistor is W / L=800 / 40nm.

[0093] Among them, the inverter is the basic unit of the ring oscillator. The typical structure of the ring oscillator is composed of an odd number of inverters, and the output and input ends are connected end to end to generate self-excited oscillation. The 1st, 2nd, 3rd, and 4th level drives of the output drive are respectively composed of 1, 2, 4, and 8 inverters in cascade, and each level of drive is cascaded in sequence to form the output drive. It is led out between any two inverters in the typical structure of the ring oscillator and connected to the first level drive B1 in the four-level drive, and the fourth level drive leads to the output. In order to flexibly inject the threshold voltage degradation amount into the gate of the sensitive PMOS transistor, the cascade inverters that make up the ring oscillator are composed of discrete inverters, and an equivalent voltage source model is used. As Figure 7 As shown, a voltage-controlled voltage source is added to the gate of the PMOS transistor to facilitate the loading of the coupling failure model for analysis.

[0094] Exemplarily, in step S12, the ring oscillator circuit is executed based on preset power supply parameters to obtain output voltage data in a corresponding initial state.

[0095] Specifically, the Spectre simulation tool of Cadence Virtuoso is used to perform an initial simulation of the ring oscillator circuit, the power supply voltage is set to 1.2V, and the output voltage curve of the ring oscillator circuit in the initial state is obtained as the input initial output voltage data. A voltage-controlled voltage source is added to the PMOS gate of the ring oscillator circuit to load the symbol module of the coupling failure model for circuit simulation.

[0096] Exemplarily, in step S13, the initial state output voltage data is input into a coupling failure model to obtain output voltage data in a coupling failure state output by the model; wherein the coupling failure model is constructed based on a reaction-diffusion model of the NBTI effect and an energy-driven model of the HCD effect.

[0097] Specifically, the output voltage is input to the voltage stress port of the Symbol module, the ground port is grounded, the simulation time is set, the ring oscillator circuit is post-simulated, and the output voltage curve of the ring oscillator circuit under the coupling failure state is obtained as the output voltage data under the coupling failure state.

[0098] Exemplarily, in step S14, first oscillation frequency data and second oscillation frequency data corresponding to the output voltage data in the initial state and the output voltage data in the coupling failure state are obtained, and degradation analysis data of the circuit frequency performance is determined based on the first oscillation frequency data and the second oscillation frequency data.

[0099] Specifically, the voltage output curves in the initial state and the coupling failure state are converted into the oscillation frequency of the ring oscillator circuit. For example, the frequency of the voltage output curve is calculated according to the period of the voltage output curve, and then the frequency data in the initial state and the frequency data in the coupling failure state are used to analyze the degradation information of the circuit frequency performance.

[0100] Comparison of ring oscillator frequency degradation simulation data and frequency degradation experimental data Fig. 9 As shown. The coordinate system is a double logarithmic coordinate system, simulationdata is the model calculation result, and extractdata is the experimental data. It can be seen from the figure that the frequency degradation predicted by the coupling failure model is roughly the same as the experimental degradation data of the ring oscillator circuit. As the stress time continues to increase, the threshold voltage of the transistor continues to degrade, resulting in the continuous degradation of the frequency of the ring oscillator circuit. There is a positive correlation between frequency degradation and time. The predicted value of the coupling failure model is consistent with the experimental value in amplitude. It shows that the coupling failure model can be applied to the frequency degradation of the ring oscillator circuit built at the 28nm process node to make good predictions.

[0101] The present invention provides a coupled failure model that describes the interaction between NBTI and HCD failure mechanisms. It uses a unified circuit simulation method to study the degradation of circuit performance when two failure mechanisms exist at the same time. This coupled failure model is more consistent with the failures experienced when the circuit is working normally and has better universality. The coupled failure model constructed by the present invention takes into account the duty cycle of AC voltage stress. The model can not only simulate and study DC stress circuits, but also simulate and study AC voltage stress circuits with different duty cycles.

[0102] At the same time, the coupled failure model takes into account the frequency of AC voltage stress, and can simulate circuits with AC voltage stress of different frequencies. The coupled failure model also takes into account the saturation effect of HCD, which makes the model more accurate in long-term prediction.

[0103] The coupling failure model of the present invention is a compact model that can predict long-term degradation. When using SPICE simulation, no iteration is required. On the basis of ensuring good accuracy, the efficiency of data analysis is improved. Such a coupling failure model can study circuits with more different working conditions and has a wider range of applications.

[0104] It should be noted that the above figures are only schematic illustrations of the processes included in the method according to an exemplary embodiment of the present invention, and are not intended to be limiting. It is easy to understand that the processes shown in the above figures do not indicate or limit the time sequence of these processes. In addition, it is also easy to understand that these processes can be performed synchronously or asynchronously, for example, in multiple modules.

[0105] For further reference, Fig.10 As shown, in the embodiment of this example, an analysis device 10 for integrated circuit coupling failure is also provided, comprising:

[0106] An integrated circuit generation module 101 is used to construct a ring oscillator circuit;

[0107] An initial data generating module 102, configured to execute the ring oscillator circuit based on preset power supply parameters to obtain output voltage data in a corresponding initial state;

[0108] The failure data generation module 103 is used to input the initial state output voltage data into a coupling failure model to obtain the output voltage data under the coupling failure state output by the model; wherein the coupling failure model is constructed based on the reaction diffusion model of the NBTI effect and the energy driving model of the HCD effect;

[0109] The data analysis module 104 is used to obtain the first oscillation frequency data and the second oscillation frequency data corresponding to the output voltage data in the initial state and the output voltage data in the coupling failure state, and determine the degradation analysis data of the circuit frequency performance based on the first oscillation frequency data and the second oscillation frequency data.

[0110] It should be noted that, although several modules or units of the equipment for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to an embodiment of the present invention, the features and functions of two or more modules or units described above can be embodied in one module or unit. On the contrary, the features and functions of one module or unit described above can be further divided into being embodied by multiple modules or units.

[0111] Fig.11 A schematic diagram of an electronic device suitable for implementing an embodiment of the present invention is shown.

[0112] It should be noted that Fig.11 The electronic device 1000 shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present invention.

[0113] like Fig.11As shown, the electronic device 1000 includes a central processing unit (CPU) 1001, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 1002 or the program loaded from the storage part 1008 to the random access memory (RAM) 1003. In the RAM 1003, various programs and data required for system operation are also stored. The CPU 1001, ROM 1002 and RAM 1003 are connected to each other through a bus 1004. An input / output (I / O) interface 1005 is also connected to the bus 1004.

[0114] The following components are connected to the I / O interface 1005: an input section 1006 including a keyboard, a mouse, etc.; an output section 1007 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 1008 including a hard disk, etc.; and a communication section 1009 including a network interface card such as a LAN (Local Area Network) card, a modem, etc. The communication section 1009 performs communication processing via a network such as the Internet. A drive 1010 is also connected to the I / O interface 1005 as needed. A removable medium 1011, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 1010 as needed, so that a computer program read therefrom is installed into the storage section 1008 as needed.

[0115] In particular, according to an embodiment of the present invention, the process described below with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present invention includes a computer program product, which includes a computer program carried on a storage medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication part 1009, and / or installed from a removable medium 1011. When the computer program is executed by a central processing unit (CPU) 1001, various functions defined in the system of the present application are executed.

[0116] It should be noted that the storage medium shown in the embodiment of the present invention may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present invention, a computer-readable storage medium may be any tangible medium containing or storing a program, which may be used by or in combination with an instruction execution system, device or device. In the present invention, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries a computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any storage medium other than computer-readable storage media, which may send, propagate, or transmit programs for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the storage medium may be transmitted using any appropriate medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above.

[0117] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present invention. In this regard, each box in the flow chart or block diagram can represent a module, a program segment, or a part of a code, and the above-mentioned module, program segment, or a part of a code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flow chart, and the combination of the boxes in the block diagram or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0118] The units involved in the embodiments of the present invention may be implemented by software or hardware, and the units described may also be arranged in a processor. The names of these units do not, in some cases, limit the units themselves.

[0119] It should be noted that, as another aspect, the present application also provides a storage medium, which can be included in an electronic device; or it can exist independently without being installed in the electronic device. The above storage medium carries one or more programs, and when the above one or more programs are executed by an electronic device, the electronic device implements the method described in the following embodiments. For example, the electronic device can implement the following Figure 1 The individual steps of the method are shown.

[0120] In one embodiment, the present application provides a computer program product, including a computer program, which implements the steps in the above-mentioned method embodiments when executed by a processor.

[0121] In addition, the above-mentioned figures are only schematic illustrations of the processes included in the method according to an exemplary embodiment of the present invention, and are not intended to be limiting. It is easy to understand that the processes shown in the above-mentioned figures do not indicate or limit the time sequence of these processes. In addition, it is also easy to understand that these processes can be performed synchronously or asynchronously, for example, in multiple modules.

[0122] Other embodiments of the invention will readily occur to those skilled in the art after considering the specification and practicing the invention herein. This application is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art that are not disclosed by the present invention. The specification and examples are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the claims.

[0123] It should be understood that the present invention is not limited to the exact construction that has been described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. A method for analyzing coupling failure of integrated circuits, characterized in that: The method comprises: Build a ring oscillator circuit; Execute the ring oscillator circuit based on preset power supply parameters to obtain output voltage data in a corresponding initial state; Input the initial state output voltage data into a coupling failure model to obtain output voltage data under a coupling failure state output by the model; wherein the coupling failure model is constructed based on a reaction diffusion model of the NBTI effect and an energy driving model of the HCD effect; The first oscillation frequency data and the second oscillation frequency data corresponding to the output voltage data in the initial state and the output voltage data in the coupling failure state are obtained, and degradation analysis data of the circuit frequency performance is determined based on the first oscillation frequency data and the second oscillation frequency data.

2. The method according to claim 1, characterized in that The method further includes: pre-training the coupling failure model, including: Collect voltage-threshold voltage degradation data, time-threshold voltage degradation data, AC stress duty cycle-threshold voltage degradation data, and AC stress frequency-threshold voltage degradation data corresponding to the target size PMOS transistor to construct a sample data set; Based on the reaction-diffusion model of NBTI effect and the energy-driven model of HCD effect, an initial coupling failure model is constructed; the reaction-diffusion model based on NBTI effect is used to describe the threshold voltage degradation of NBTI effect; the energy-driven model based on HCD effect is used to describe the threshold voltage degradation of HCD effect; The sample data set is used to perform forward propagation training on the initial coupling failure model, and the model hyperparameters are determined to obtain the trained coupling failure model.

3. The method according to claim 2, characterized in that The threshold voltage degradation of the NBTI effect is described based on the relationship between gate voltage, AC stress duty cycle, time and threshold voltage degradation.

4. The method according to claim 2, characterized in that: The threshold voltage degradation of the HCD effect is described based on the relationship between the gate voltage and drain voltage, the frequency and time of the AC voltage stress and the threshold voltage degradation.

5. The method according to claim 2, characterized in that: The model hyperparameters include: NBTI effect failure weight, NBTI effect voltage influence factor, NBTI effect AC signal duty cycle influence factor, HCD effect failure weight, HCD voltage influence factor, HCD frequency influence factor, and saturation effect coefficient.

6. The method according to claim 2, characterized in that The method further comprises: Create a new library; Calling an editor tool of the Cadence Virtuoso tool to compile the trained coupling failure model to obtain a corresponding coupling failure model file; The source file corresponding to the coupling failure model file is saved in the new library, and the input port of the coupling failure model file is configured as a gate voltage stress port, a source voltage stress port and a drain voltage stress port, and the output port is a threshold voltage degradation amount.

7. An analysis device for integrated circuit coupling failure, characterized in that: The device comprises: Integrated circuit generation module for building ring oscillator circuits; An initial data generating module, configured to execute the ring oscillator circuit based on preset power supply parameters and obtain output voltage data in a corresponding initial state; A failure data generation module, used to input the initial state output voltage data into a coupled failure model to obtain output voltage data under a coupled failure state output by the model; wherein the coupled failure model is constructed based on a reaction diffusion model of the NBTI effect and an energy driven model of the HCD effect; A data analysis module is used to obtain the first oscillation frequency data and the second oscillation frequency data corresponding to the output voltage data in the initial state and the output voltage data in the coupling failure state, and determine the degradation analysis data of the circuit frequency performance based on the first oscillation frequency data and the second oscillation frequency data.

8. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method for analyzing coupling failure of an integrated circuit according to any one of claims 1 to 6 is implemented.

9. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the method for analyzing coupling failure of an integrated circuit according to any one of claims 1 to 6 is implemented.

10. An electronic device, characterized in that: include: processor; as well as A memory, configured to store executable instructions of the processor; The processor is configured to execute the integrated circuit coupling failure analysis method according to any one of claims 1 to 6 by executing the executable instructions.

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