Transistor-level time sequence prediction method and system for critical path standard cell

Abstract

The invention discloses a critical path standard cell-oriented transistor-level time sequence prediction method and system. The method comprises the following steps of: obtaining a transistor-level intrinsic characteristic of a standard cell and a state characteristic of the standard cell; carrying out feature fusion on the transistor-level intrinsic feature and the state feature of the standard unit to obtain a standard unit time sequence feature; analyzing based on the time sequence characteristics of the standard cell, and predicting the time sequence data of the transistor level of the standard cell; and training the time sequence analysis model based on the time sequence data of the transistor level of the standard cell to obtain a trained time sequence analysis model so as to predict the predicted standard cell and obtain a time sequence prediction result. According to the method, the time sequence prediction problem in the super-large-scale circuit design, especially a standard unit in an undefined library, can be efficiently solved; through automation and optimization of time sequence prediction, the design period is shortened, the consumption of computing resources is reduced, and the time sequence optimization process is accelerated.

Description

Technical Field

[0001] The present invention mainly relates to the field of integrated circuit technology, and in particular to a transistor-level timing prediction method and system for critical path standard cells. Background Art

[0002] With the continuous development of integrated circuit technology, the complexity of standard cells used in chip design has gradually increased. Especially in transistor-level design, how to accurately and efficiently perform timing analysis has become an important challenge in integrated circuit design. Standard cell timing analysis is one of the key technologies used to evaluate circuit timing performance in integrated circuit design. It usually involves predicting the timing characteristics of each standard cell in the circuit to ensure that the circuit can work stably at a predetermined clock frequency.

[0003] The current standard cell timing analysis methods are mainly based on traditional physical modeling and simulation technology, such as analog simulation based on SPICE models or static timing analysis tools. Although these methods can provide accurate timing analysis results, when faced with ultra-large-scale circuits, due to the huge amount of calculations, the processing time and resource consumption are often very high, resulting in extended design cycles and increased development costs. In addition, the accuracy of traditional methods is limited by the accuracy of the model and the setting of simulation parameters, and errors are prone to occur when dealing with complex circuit topologies and nonlinear effects.

[0004] With the development of machine learning technology, data-driven timing analysis methods have gradually attracted attention. By utilizing a large amount of historical data, machine learning methods can mine circuit timing features and make predictions, thus providing a new approach to timing analysis. In particular, the emergence of graph neural networks has provided new possibilities for solving the topological dependency problem in transistor-level standard cell timing analysis. By modeling the transistor-level topological structure of standard cells, graph neural networks can effectively capture the relationship between transistors and combine their key features for timing prediction, with good prediction accuracy and efficiency.

[0005] However, the existing timing analysis methods based on graph neural networks still have certain limitations. For example, in semi-custom VLSI design, the standard cells in the standard cell library often cannot achieve the best timing results, so customized special standard cells are required, such as customized standard cells in which the number of fins of transistors in the pull-up network and the pull-down network is not 1:1. However, existing methods are often unable to accurately handle special standard cells that are not defined in the standard cell library, resulting in inaccurate timing prediction results. At the same time, how to quickly extract the intrinsic characteristics and state characteristics of standard cells in complex circuits and perform efficient timing prediction based on these characteristics is still a technical problem that needs to be solved urgently.

[0006] Therefore, how to combine machine learning, especially graph neural networks, to improve the timing analysis accuracy and efficiency of transistor-level standard cells, especially in the face of special standard cells and complex circuits that are not defined in the standard cell library, remains an important research topic in the field of integrated circuit design. Summary of the invention

[0007] In view of the technical problems existing in the prior art, the present invention provides a transistor-level timing prediction method and system for critical path standard cells, which can shorten the design cycle, reduce computing resource consumption, and accelerate timing optimization.

[0008] In order to solve the above technical problems, the technical solution proposed by the present invention is: A transistor-level timing prediction method for critical path standard cells comprises the following steps: Acquire the standard cell transistor-level intrinsic characteristics and the state characteristics of the standard cell; wherein the standard cell transistor-level intrinsic characteristics are the property characteristics inherent in the standard cell that do not change with the state conditions; The standard cell transistor-level intrinsic features and state features are fused to obtain the standard cell timing features; Analyze the timing characteristics of standard cells and predict the timing data of standard cells at the transistor level; The timing analysis model is trained based on the timing data of the standard cell transistor level, and the trained timing analysis model is obtained to predict the predicted standard cell to obtain the timing prediction result.

[0009] Preferably, the specific process of obtaining the standard cell transistor-level intrinsic characteristics is: The circuit topology information of the standard cell transistor level and the key information of the standard cell transistor level in the standard cell netlist are extracted to construct the intrinsic features of the standard cell transistor level.

[0010] Preferably, the specific process of extracting the standard cell transistor-level circuit topology information and the standard cell transistor-level key information in the standard cell netlist is as follows: The standard cell transistor-level circuit topology information is extracted from the standard cell netlist, and a standard cell transistor-level heterogeneous graph is constructed with transistors, input pins, output pins, ground and power supply as nodes and wire nets connecting the nodes as edges; at the same time, the corresponding standard cell transistor-level key information is extracted in combination with the standard cell timing arc information.

[0011] Preferably, the specific process of fusing the standard cell transistor-level intrinsic feature with the state feature to obtain the standard cell timing feature is as follows: Construct a customized graph neural network based on the differentiation of topological node correlation at the standard unit transistor level, realize feature embedding of standard unit transistor level intrinsic features, and convert high-dimensional, discrete or structured standard unit transistor level intrinsic features into low-dimensional continuous vector representation; Construct a feature embedding network of standard cell state features to embed the standard cell state features and convert high-dimensional, discrete or structured standard cell state features into low-dimensional continuous vector representations; A feature fusion network of transistor-level intrinsic features and standard cell state features is constructed to achieve feature fusion of transistor-level intrinsic features and standard cell state features to obtain standard cell timing features.

[0012] Preferably, a customized graph neural network based on the differentiation of topological node correlation at the standard unit transistor level is constructed to achieve feature embedding of the intrinsic features at the standard unit transistor level as follows: Different graph convolution methods are used to transfer information between different nodes; specifically, the transistor node features and the connection edges between transistors are taken, and a graph attention network is used for information transfer; the input pin node and the transistor node features and the connection edges between the input pin and the transistor are taken, and a graph convolution network is used for information transfer; the transistor node and the output pin node features and the connection edges between the transistor and the output pin are taken, and a graph convolution network is used for information transfer; the power node and the transistor node features and the connection edges between the power supply and the transistor are taken, and a graph sampling aggregation network is used for information transfer; the transistor node and the ground node features and the connection edges between the transistor and the ground are taken, and a graph sampling aggregation network is used for information transfer.

[0013] Preferably, the timing analysis model is trained based on the timing data of the standard cell transistor level, and the specific process of obtaining the trained timing analysis model includes: Based on the timing data of standard cells in the existing library, data amplification is performed to obtain an expanded training data set; Based on the expanded training data set, the constructed model is subjected to supervised learning, and the model parameters are optimized through back propagation. At the same time, regularization technology is introduced in the training process to ensure the generalization ability of the model to unseen data. At the same time, the hyperparameters are adjusted and the optimal model configuration is selected to obtain a trained time series analysis model.

[0014] Preferably, the specific process of performing data amplification based on the timing data of the standard cells in the existing library to obtain the expanded training data set is as follows: Parse the standard cell library file and extract the delay lookup table between the input jump time, output load and delay corresponding to different timing arcs of each standard cell; According to the input transition time and output load values ​​in the delay lookup table, multiple interpolation values ​​are generated between each two adjacent values ​​to obtain n×n input transition time and output load interpolation values; According to the interpolation of the generated input transition time and output load, combined with the interpolation algorithm, the corresponding n×n delay result is generated; Based on the generated input transition time and output load interpolation, SPICE simulation is used to generate the corresponding n×n unit delay results.

[0015] Preferably, the specific process of obtaining the standard cell transistor-level intrinsic characteristics is: Parse the standard cell netlist, extract the topological relationship between transistors, input pins, output pins, power supply and ground in the standard cell, and form a heterogeneous graph of different types of nodes; Parse the standard cell netlist to extract information about each transistor; parse the standard cell library file and analyze the current process status information to extract the threshold voltage and channel length information of the current transistor; use each piece of information as the initialization feature of the transistor node in the heterogeneous graph; Analyze the current timing arc state, extract the input pins in the current state, the input pin states, the states of other input pins, the monotonic correlation between the input pins and the output pins, whether the input pins are rising delay or falling delay, whether the output pins are rising delay or falling delay, the states of the output pins, as well as the input jump time and the output load, to obtain the state information; Initialize input pin and output pin node features according to the state information; The standard cell library file is parsed and the process corner status information of the current standard cell is analyzed to obtain the voltage value, and the characteristics of the power node are initialized to the voltage value, and the characteristics of the ground node are initialized to 0.

[0016] Preferably, the specific process of obtaining the state characteristics of the standard unit is: Parsing the standard cell library file and extracting process information as the state characteristics of the current standard cell; the process information includes process angle, temperature, height of the standard cell and area of ​​the standard cell; The state characteristics of the standard unit are normalized to obtain the final state characteristics.

[0017] The present invention also discloses a transistor-level timing prediction system for critical path standard cells, comprising a memory and a processor connected to each other, wherein a computer program is stored on the memory, and when the computer program is executed by the processor, the steps of the method described above are executed.

[0018] Compared with the prior art, the advantages of the present invention are: The transistor-level timing prediction method for critical path standard cells of the present invention first extracts transistor-level circuit topology information from the standard cell netlist, constructs a transistor-level heterogeneous graph, and extracts key information in combination with timing arc information; secondly, a customized graph neural network model is constructed based on the extracted transistor-level features; at the same time, the process information is analyzed to extract the state features of the standard cell, and a state feature embedding network is constructed; then, the timing prediction results are obtained through feature fusion and timing prediction network. This method can efficiently handle timing prediction problems in ultra-large-scale circuit design, especially standard cells in undefined libraries; through the automation and optimization of timing prediction, the design cycle is shortened, the consumption of computing resources is reduced, and the timing optimization and ECO process are accelerated. Compared with traditional timing analysis methods, the present invention has obvious advantages in efficiency and adaptability, and has good industrial application prospects.

[0019] The transistor-level timing prediction method for critical path standard cells of the present invention has the following advantages: 1. Accelerate the timing ECO process: By utilizing the efficient reasoning capability of the graph neural network model, the present invention can quickly perform timing prediction for standard cells in ultra-large-scale circuit design. For standard cells that are not defined in the standard cell library, the present invention can also perform timing prediction, thereby guiding and accelerating the timing ECO (Engineering Change Order) process, reducing the time and computing resources required for manual adjustment and simulation.

[0020] 2. Reduce computing resource consumption: Compared with traditional simulation methods (such as SPICE simulation) that require a large number of physical model calculations, the timing prediction method based on graph neural network can complete timing prediction in a shorter time and with fewer computing resources. This not only improves the efficiency of timing analysis, but also reduces the demand for hardware resources and reduces the computing burden of the system.

[0021] 3. Easy to expand and apply: The timing analysis method of the present invention is based on a data-driven machine learning model and has strong scalability in practical applications. With the accumulation of more training data, the timing prediction accuracy of the model can be continuously improved. In addition, the present invention is compatible with the existing integrated circuit design tool chain and can be easily integrated into the existing electronic design automation (EDA) environment, which has good industrial application prospects.

[0022] In summary, the present invention has obvious advantages over the prior art in terms of accuracy, efficiency, generalization ability and computing resource consumption of time series prediction, and has important practical application value. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a flow chart of an embodiment of the transistor level timing prediction method of the present invention.

[0024] Figure 2 This is a framework diagram of the transistor-level standard cell timing analysis model based on graph neural network of the present invention.

[0025] Figure 3 This is a diagram of the information transmission process of a transistor node in the heterogeneous graph neural network in the present invention. DETAILED DESCRIPTION

[0026] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments.

[0027] like Figure 1 As shown, the transistor-level timing prediction method for critical path standard cells provided by an embodiment of the present invention includes the following steps: S1. Extract the standard cell transistor-level circuit topology information from the standard cell netlist, and construct a standard cell transistor-level heterogeneous graph with transistors, input pins, output pins, ground and power as nodes and wire nets connecting the nodes as edges; at the same time, extract the corresponding standard cell transistor-level key information in combination with the standard cell timing arc information; Based on the extracted standard cell transistor-level heterogeneous graph and key information, standard cell transistor-level intrinsic features are constructed as input data for the customized graph neural network model; the standard cell transistor-level intrinsic features are defined as: the property features inherent to the standard cell that do not change with state conditions (such as voltage, temperature, etc.) (such as the connection relationship of the transistors in the standard cell, the transistor width-to-length ratio, etc.); S2. Extract the state characteristics of the standard cells according to the process information of the standard cells to provide more dimensional data support for subsequent timing analysis; S3. Build a customized graph neural network based on the differentiation of topological node correlation at the standard unit transistor level, realize feature embedding of intrinsic features at the standard unit transistor level, and convert high-dimensional, discrete or structured data into low-dimensional continuous vector representation for subsequent machine learning model processing; S4. Construct a feature embedding network of standard cell state features to embed the standard cell state features and convert high-dimensional, discrete or structured data into low-dimensional continuous vector representations for subsequent machine learning model processing; the newly added state features enhance the accuracy and adaptability of time series prediction; specifically, the feature embedding network includes a multi-layer perceptron with two hidden layers, and uses Relu as the activation function; S5. Construct a feature fusion network of transistor-level intrinsic features and standard cell state features to achieve feature fusion of transistor-level intrinsic features and standard cell state features, and obtain standard cell timing features. Specifically, in the feature fusion network, construct a tensor concatenation layer, followed by a batchnormal layer, to ensure the generalization ability of the network model. S6. Construct a timing prediction network to process the complex nonlinear relationship in the timing analysis of standard cells based on the timing features obtained by the feature fusion network and predict the timing results of the standard cell transistor level. Specifically, the timing prediction network contains a multi-layer perceptron with two hidden layers and uses ReLU as the activation function; S7. Based on the timing data of standard cells in the existing library, data augmentation is performed to expand the training data set to improve the accuracy of timing prediction; S8. Perform supervised learning on the constructed model based on the expanded training data, optimize the model parameters through back propagation, and introduce appropriate regularization techniques during the training process to ensure the generalization ability of the model to unseen data; at the same time, adjust the hyperparameters and select the optimal model configuration to obtain a trained time series analysis model; S9, extracting features of the standard cells to be predicted according to steps S1 and S2, and obtaining transistor-level intrinsic features and state features; S10, inputting the extracted transistor-level intrinsic features and state features into the trained timing analysis model to predict the timing analysis results.

[0028] The transistor-level timing prediction method for critical path standard cells of the present invention first extracts transistor-level circuit topology information from the standard cell netlist, constructs a transistor-level heterogeneous graph, and extracts key information in combination with timing arc information; secondly, a customized graph neural network model is constructed based on the extracted transistor-level features; at the same time, the process information is analyzed to extract the state features of the standard cell, and a state feature embedding network is constructed; then, the timing prediction results are obtained through feature fusion and timing prediction network. This method can efficiently handle timing prediction problems in ultra-large-scale circuit design, especially standard cells in undefined libraries; through the automation and optimization of timing prediction, the design cycle is shortened, the consumption of computing resources is reduced, and the timing optimization and ECO process are accelerated. Compared with traditional timing analysis methods, the present invention has obvious advantages in efficiency and adaptability, and has good industrial application prospects.

[0029] In a specific embodiment, step S1 includes: S101, parsing the standard cell netlist, extracting the topological relationship between transistors, input pins, output pins, power supplies and grounds in the standard cell, and forming a heterogeneous graph including four different types of nodes; S102, parsing the standard cell netlist to extract information of each transistor, such as transistor type, aspect ratio of the transistor, number of gates of the transistor, etc.; parsing the standard cell library file and analyzing the current process status information to extract information such as threshold voltage and channel length of the current transistor; using the above information as initialization features of transistor nodes in the heterogeneous graph; S103, analyzing the current timing arc state, extracting the input pins, input pin states, other input pin states, the monotonic correlation between the input pins and the output pins, whether the input pins are rising delay or falling delay, whether the output pins are rising delay or falling delay, the state of the output pins, and the input jump time and output load in the current state, and obtaining the state information; S104. Initialize the input pin and output pin node features according to the state information and the following rules; wherein each tag is encoded using one-hot encoding.

[0030] When initializing the input pin characteristics, specifically include the following tags 1-4 and input transition time: Mark 1: Marks whether the current timing arc is from this pin to the output pin. There are two states: (1) Yes, (2) No.

[0031] Mark 2: Marks the monotonic correlation between this pin and the output pin. There are four states: (1) positive monotonic correlation, (2) negative monotonic correlation, (3) non-monotonic correlation, (4) non-current timing arc input pin. The monotonic correlation between this pin and the output pin is not taken into account.

[0032] Mark 3: Marks whether the pin is a rising edge or a falling delay. There are three states: (1) rising edge, (2) falling delay, and (3) non-current timing arc input pin. It does not matter whether the current pin is a rising edge or a falling delay.

[0033] Mark 4: Marks the state of this pin. There are three states: (1) low level, (2) high level, and (3) its state does not affect the current timing arc.

[0034] Input transition time: The input transition time under the current timing arc. There are two cases: (1) If it is the input pin of the current timing arc, it is set to the input transition time under the current timing arc; (2) If it is not the input pin of the current timing arc, it is set to 0.

[0035] When initializing the output pin characteristics, the following tags 5-6 and output load are specifically included: Mark 5: Marks the output pin as rising edge or falling edge. There are two states: (1) rising edge and (2) falling edge.

[0036] Mark 6: Marks the state of the output pin. There are two states: (1) low level and (2) high level.

[0037] Output load: The output load value under the current timing arc.

[0038] S105 , parsing the standard cell library file and analyzing the process corner state information of the current standard cell to obtain a voltage value, initializing the characteristics of the power node to the voltage value, and initializing the characteristics of the ground node to 0.

[0039] In the above process, the intrinsic characteristics of the standard unit transistor level include not only the physical parameters of the transistor (such as type, aspect ratio, number of gates, etc.), but also the characteristics of the circuit power supply and ground signals. In digital circuit design, the voltage values ​​of the power supply and ground are key factors affecting the logic state and timing of the circuit. Therefore, initializing the characteristics of the power supply node to the voltage value and initializing the characteristics of the ground node to 0 can ensure that the power supply of the actual circuit can be accurately reflected during circuit simulation.

[0040] In a specific embodiment, step S2 includes: S201, parsing the standard cell library file and extracting process information, such as process angle, temperature, height of the standard cell, area of ​​the standard cell, etc., as the state characteristics of the current standard cell; S202: Perform feature normalization on the state features of the standard unit to improve model performance.

[0041] In a specific embodiment, step S3 includes: Different graph convolution methods are used between different nodes to transfer information more efficiently and reasonably. Specifically, the features of transistor nodes and the connection edges between transistors are taken, and the graph attention network is used for information transfer; the features of input pin nodes and transistor nodes and the connection edges between input pins and transistors are taken, and the graph convolution network is used for information transfer; the features of transistor nodes and output pin nodes and the connection edges between transistors and output pins are taken, and the graph convolution network is used for information transfer; the features of power nodes and transistor nodes and the connection edges between power and transistors are taken, and the graph sampling aggregation network is used for information transfer; the features of transistor nodes and ground nodes and the connection edges between transistors and ground are taken, and the graph sampling aggregation network is used for information transfer.

[0042] In a specific embodiment, step S7 includes: S701, parsing the standard cell library file, extracting an 8×8 delay lookup table between input transition time, output load and delay corresponding to different timing arcs of each standard cell; S702, according to the input transition time and the output load values ​​in the delay lookup table, 100 interpolation values ​​are generated between every two adjacent values ​​to obtain 700×700 input transition time and output load interpolation values; S703, generating a unit delay result corresponding to 700×700 according to the generated input transition time and output load interpolation combined with an interpolation algorithm; S704 , generating a corresponding 700×700 unit delay result by using SPICE simulation according to the generated input transition time and output load interpolation.

[0043] Specifically, the delay result generated by the interpolation algorithm in step S703 is an estimate based on the original data, while the unit delay result generated by SPICE simulation in S704 is closer to the actual behavior of the circuit. In timing prediction, the data generated by these two methods can provide different information: the interpolation result can be used for fast estimation and prediction, while the simulation result can be used for accurate circuit analysis and verification. By combining these two methods, the model can be trained more comprehensively and its prediction accuracy can be improved.

[0044] In a specific embodiment, step S8 includes: Process the training data according to steps S1 and S2 of feature engineering to provide high-quality input data for model training; The input data is passed to each network layer of the model through forward propagation, and the timing prediction results of the standard unit are output; Calculate the mean square error between the predicted result and the actual delay as the loss function; The back-propagation algorithm is used to optimize the weights and parameters of the model by calculating the gradient of the loss function relative to the parameters of each layer and using the Adam optimizer to update the weights of the network; L2 regularization and Dropout methods are introduced during the training process to enhance the generalization ability of the model and avoid overfitting. By adding the square sum of weights to the loss function, the excessive value of the model parameters is limited, thereby preventing the model from being too dependent on the noise in the training data. At the same time, a part of the neurons is randomly "discarded" in each training step, forcing the model to pay more attention to global features during training, rather than relying solely on specific neuron paths.

[0045] By adjusting hyperparameters such as learning rate, regularization strength, number of network layers, etc., multiple model trainings are performed to select the optimal model configuration.

[0046] The transistor-level timing prediction method for critical path standard cells of the present invention has the following advantages: 1. Accelerate the timing ECO process: By utilizing the efficient reasoning capability of the graph neural network model, the present invention can quickly perform timing prediction for standard cells in ultra-large-scale circuit design. For standard cells that are not defined in the standard cell library, the present invention can also perform timing prediction, thereby guiding and accelerating the timing ECO (Engineering Change Order) process, reducing the time and computing resources required for manual adjustment and simulation.

[0047] 2. Reduce computing resource consumption: Compared with traditional simulation methods (such as SPICE simulation) that require a large number of physical model calculations, the timing prediction method based on graph neural network can complete timing prediction in a shorter time and with fewer computing resources. This not only improves the efficiency of timing analysis, but also reduces the demand for hardware resources and reduces the computing burden of the system.

[0048] 3. Easy to expand and apply: The timing analysis method of the present invention is based on a data-driven machine learning model and has strong scalability in practical applications. With the accumulation of more training data, the timing prediction accuracy of the model can be continuously improved. In addition, the present invention is compatible with the existing integrated circuit design tool chain and can be easily integrated into the existing electronic design automation (EDA) environment, which has good industrial application prospects.

[0049] In summary, the present invention has obvious advantages over the prior art in terms of accuracy, efficiency, generalization ability and computing resource consumption of time series prediction, and has important practical application value.

[0050] In order to better understand the above technical solution, the above technical solution will be described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0051] like Figure 2 As shown in the corresponding prediction model framework, the left side is the input of the model ( Figure 2 The upper left corner is the extracted transistor-level heterogeneous graph and the standard cell intrinsic feature embedding module (where A1 and A2 in the transistor-level heterogeneous graph are input pins, P1 and P2 are PMOS transistors, and N1 and N2 are NMOS transistors), the lower left corner MLP network is the state feature embedding module of the standard cell, and the right MLP network is the fusion network and output module of the standard cell state feature and transistor-level intrinsic feature.

[0052] The transistor-level timing prediction method for critical path standard cells provided by the present invention specifically comprises the following steps: Feature Engineering: S1. Extract the standard cell transistor-level circuit topology information from the standard cell netlist, and construct a standard cell transistor-level heterogeneous graph with transistors, input pins, output pins, ground and power as nodes and wire nets connecting the nodes as edges; at the same time, extract the corresponding standard cell transistor-level key information in combination with the standard cell timing arc information; the specific steps are: S101. In this embodiment, the standard cell netlist is parsed using a written python script, which can efficiently and accurately extract the circuit topology information of the unit transistor level, and use the HeteroData class in the torch_geometric library of python to construct a heterogeneous graph data structure containing 5 types of nodes, namely transistors, input pins, output pins, power supplies and grounds.

[0053] S102. Parsing the standard cell library file adopts the written python script, or the python liberty library can be used for parsing, which can be efficient and fast, and the extracted transistor information and process status information, that is, whether the transistor is a Pmos tube or an Nmos tube, the number of transistor gates, the number of fins of the transistor, the channel length of the transistor and the threshold voltage of the transistor are used as the initialization characteristics of the transistor node.

[0054] S103-S104, analyzing the current timing arc state using the written python script, can quickly initialize the node features of the input pins and output pins according to the corresponding rules, where each mark is encoded using one-hot encoding.

[0055] S105, parsing the standard cell library file using a written python script, taking the voltage value of the current standard cell under the process corner state as the initialization characteristic value of the power node, and initializing the characteristic of the ground node to 0.

[0056] S2. Extract the state characteristics of the standard cells according to the process information of the standard cells to provide more dimensional data support for subsequent timing analysis; specifically: S201. Parse the standard cell library file using a written python script, and use the process angle, temperature, height of the standard cell, and area of ​​the standard cell as state features of the current standard cell, wherein the process angle information is encoded using one-hot encoding.

[0057] S202. Use the MinMaxScaler function in the scikit-learn library of Python to normalize the data.

[0058] Model construction: S3. Build a customized graph neural network based on the differentiation of topological node correlation at the standard unit transistor level, realize feature embedding of intrinsic features at the standard unit transistor level, and convert high-dimensional, discrete or structured data into low-dimensional continuous vector representation for subsequent machine learning model processing; like Figure 3 As shown, in step S3, a customized heterogeneous graph neural network is constructed based on the torch_geometric library of Python. Figure 3 The information transmission process of a PMOS transistor node P2 in a heterogeneous graph neural network is described, where A1, A2 and A3 are input pins, P1 is a PMOS transistor, and M1 and M2 are NMOS transistors.

[0059] Specifically, the transistor node features and the connection edges between transistors are taken, and the GATconv in the torch_geometric library is used to build a network layer for convolution calculation, such as Figure 3 As shown in the left figure in the figure, it describes the information transfer between transistor P2 and other transistors, and its feature representation is calculated through network convolution to obtain a new representation .

[0060] Take the input pin node and transistor node features and the connection edge between the input pin and the transistor, and use GCNconv in the torch_geometric library to build a network layer for convolution calculation, such as Figure 3 As shown in the right figure in the figure, it describes the information transfer between transistor P2 and the input pin, and its feature representation is calculated through network convolution to obtain a new representation .

[0061] Take the features of the transistor node and the output pin node and the connection edge between the transistor and the output pin, and use GCNconv in the torch_geometric library to build a network layer for convolution calculation, such as Figure 3 The middle ellipsis part in the figure describes the information transmission between transistor P2 and the output pin. Its feature representation is calculated through network convolution to obtain a new representation. .

[0062] Take the power node and transistor node features and the connection edge between the power supply and the transistor, and use SAGEconv in the torch_geometric library to build a network layer for convolution calculation, such as Figure 3 The middle ellipsis part in the figure describes the information transmission between transistor P2 and the power node. Its feature representation is calculated through network convolution to obtain a new representation. .

[0063] Take the features of the transistor node and the ground node as well as the connection edge between the transistor and the ground, and use SAGEconv in the torch_geometric library to build a network layer for convolution calculation, such as Figure 3 The middle ellipsis part in the figure describes the information transmission between transistor P2 and the ground node. Its feature representation is calculated through network convolution to obtain a new representation. .

[0064] After each graph convolution, the feature representation of the node is calculated to obtain a new node feature representation, such as Figure 3 As shown in the lower part of the characteristic transfer part, the new characteristic representation of the transistor P2 node is obtained .

[0065] S4. Construct a feature embedding network of standard cell state features to embed the standard cell state features and convert high-dimensional, discrete or structured data into low-dimensional continuous vector representations for subsequent machine learning model processing; newly added state features enhance the accuracy and adaptability of time series prediction; Specifically, in step S4, three fully connected layers are constructed using the torch library of python. The first two layers use Relu as the activation function, and the third layer directly outputs tensors.

[0066] S5. Construct a feature fusion network of transistor-level intrinsic features and standard cell state features to achieve feature fusion of transistor-level intrinsic features and standard cell state features, and obtain standard cell timing features; Specifically, in step S5, the global_mean_pool function in the torch_geometric library of python is used to perform global average pooling on the output of the heterogeneous graph neural network, and then the cat function in the torch library of python is used to concatenate the pooled features with the features output by S4 to obtain a temporal feature representation, followed by a Batchnormal layer.

[0067] S6. Build a timing prediction network to process the complex nonlinear relationship in the timing analysis of standard cells based on the timing features obtained by the feature fusion network, and predict the timing results of the standard cell transistor level.

[0068] Specifically, in step S6, the torch library of python is used to construct three fully connected layers, all of which use Relu as the activation function, and the third layer outputs the prediction result.

[0069] Model training: S7. Based on the timing data of standard cells in the existing library, data amplification is performed to expand the training data set to improve the accuracy of timing prediction. Specifically: S701, using a script written in Python to parse the standard cell library file, and extracting an 8×8 delay lookup table between input transition time, output load and delay corresponding to different timing arcs of each standard cell.

[0070] S702 , using a script written in Python to generate 100 interpolation values ​​between every two adjacent values ​​according to the input transition time and the output load value in the delay lookup table, and obtain 700×700 input transition time and output load interpolation values.

[0071] S703, using a script written in Python to generate a unit delay result corresponding to 700×700 based on the interpolation of the generated input transition time and output load and in combination with an interpolation algorithm.

[0072] S704 , write a Tcl script to generate a corresponding 700×700 unit delay result by SPICE simulation according to the generated input transition time and output load interpolation.

[0073] S8. Perform supervised learning on the constructed model based on the expanded training data, optimize the model parameters through back propagation, and introduce appropriate regularization techniques during the training process to ensure the model's generalization ability for unseen data; at the same time, adjust the hyperparameters and select the optimal model configuration to obtain a trained time series analysis model.

[0074] Specifically, in step S8, python is used to combine the state characteristics of the standard unit and the heterogeneous graph to build a new data structure and load it into the Dataloader written in the Dataloader in the torch_geometric library based on python; the constructed time series prediction model is loaded, and the model training mode is set using mode.train() to obtain the standard unit time series prediction results output by the model; the MSEloss in the torch library of python is used as the loss function; the loss.backward() of python is used to perform back propagation to optimize the model weights and parameters, and the Adam optimizer is used to update the weights of the network; the weight_decay parameter of the Adam optimizer is directly passed to the optimizer to achieve L2 regularization. At the same time, a dropout layer in the torch library is added before the last fully connected layer of the model to prevent the model from being too dependent on the noise in the training data and enhance the generalization ability of the model; finally, the hyperparameters of the model are set to a learning rate of 0.0001, a regularization strength of 0.01, and a multi-layer perceptron with two layers.

[0075] Model predictions: S9, extracting features of the standard cells to be predicted according to steps S1 and S2, and obtaining transistor-level intrinsic features and state features. Specifically, a written python script is used to extract features, and a data structure is constructed and loaded into Dataloader.

[0076] S10, input the extracted transistor-level intrinsic features and state features into the trained timing analysis model, and predict the timing analysis results. Specifically, load the optimal model, set the model to test mode through model.test(), do not enable the dropout layer, input the data in the Dataloader, and obtain the timing prediction results.

[0077] The embodiment of the present invention further discloses a transistor-level timing prediction system for critical path standard cells, comprising a memory and a processor connected to each other, wherein a computer program is stored on the memory, and when the computer program is executed by the processor, the steps of the above method are executed. The prediction system of the present invention corresponds to the above prediction method and also has the advantages described in the above prediction method.

[0078] The present invention implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by hardware related to computer program instructions. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor, the steps of the above-mentioned method embodiment can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. Computer-readable storage media include: any entity or device that can carry computer program code, recording medium, U disk, mobile hard disk, disk, optical disk, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electric carrier signal, telecommunication signal and software distribution medium. The memory is used to store computer programs and / or modules. The processor implements various functions by running or executing computer programs and / or modules stored in the memory, and calling data stored in the memory. The memory may include a high-speed random access memory and may also include a non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card (Flash Card), at least one disk storage device, a flash memory device, or other volatile solid-state storage devices.

[0079] The above are only preferred embodiments of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should be regarded as the protection scope of the present invention.

Claims

1. A transistor-level timing prediction method for critical path standard cells, characterized in that: Includes steps: Acquire the standard cell transistor-level intrinsic characteristics and the state characteristics of the standard cell; wherein the standard cell transistor-level intrinsic characteristics are the property characteristics inherent in the standard cell that do not change with the state conditions; The standard cell transistor-level intrinsic features and state features are fused to obtain the standard cell timing features; Analyze the timing characteristics of standard cells and predict the timing data of standard cells at the transistor level; The timing analysis model is trained based on the timing data of the standard cell transistor level, and the trained timing analysis model is obtained to predict the predicted standard cell to obtain the timing prediction result.

2. The transistor-level timing prediction method for critical path standard cells according to claim 1, characterized in that: The specific process of obtaining the intrinsic characteristics of the standard cell transistor level is: The circuit topology information of the standard cell transistor level and the key information of the standard cell transistor level in the standard cell netlist are extracted to construct the intrinsic features of the standard cell transistor level.

3. The transistor-level timing prediction method for critical path standard cells according to claim 2, characterized in that: The specific process of extracting the standard cell transistor-level circuit topology information and the standard cell transistor-level key information in the standard cell netlist is as follows: The standard cell transistor-level circuit topology information is extracted from the standard cell netlist, and a standard cell transistor-level heterogeneous graph is constructed with transistors, input pins, output pins, ground and power supply as nodes and wire nets connecting the nodes as edges; at the same time, the corresponding standard cell transistor-level key information is extracted in combination with the standard cell timing arc information.

4. The transistor-level timing prediction method for critical path standard cells according to claim 1, 2 or 3, characterized in that: The specific process of fusing the standard cell transistor-level intrinsic features with the state features to obtain the standard cell timing features is as follows: Construct a customized graph neural network based on the differentiation of topological node correlation at the standard unit transistor level, realize feature embedding of standard unit transistor level intrinsic features, and convert high-dimensional, discrete or structured standard unit transistor level intrinsic features into low-dimensional continuous vector representation; Construct a feature embedding network of standard cell state features to embed the standard cell state features and convert high-dimensional, discrete or structured standard cell state features into low-dimensional continuous vector representations; A feature fusion network of transistor-level intrinsic features and standard cell state features is constructed to achieve feature fusion of transistor-level intrinsic features and standard cell state features to obtain standard cell timing features.

5. The transistor-level timing prediction method for critical path standard cells according to claim 4, characterized in that: The specific process of building a customized graph neural network based on the differentiation of topological node correlation at the standard unit transistor level and realizing feature embedding of the intrinsic features at the standard unit transistor level is as follows: Different graph convolution methods are used to transfer information between different nodes; specifically, the transistor node features and the connection edges between transistors are taken, and a graph attention network is used for information transfer; the input pin node and the transistor node features and the connection edges between the input pin and the transistor are taken, and a graph convolution network is used for information transfer; the transistor node and the output pin node features and the connection edges between the transistor and the output pin are taken, and a graph convolution network is used for information transfer; the power node and the transistor node features and the connection edges between the power supply and the transistor are taken, and a graph sampling aggregation network is used for information transfer; the transistor node and the ground node features and the connection edges between the transistor and the ground are taken, and a graph sampling aggregation network is used for information transfer.

6. The transistor-level timing prediction method for critical path standard cells according to claim 1, 2 or 3, characterized in that: The specific process of training the timing analysis model based on the timing data of the standard cell transistor level to obtain the trained timing analysis model includes: Based on the timing data of standard cells in the existing library, data amplification is performed to obtain an expanded training data set; Based on the expanded training data set, the constructed model is subjected to supervised learning, and the model parameters are optimized through back propagation. At the same time, regularization technology is introduced in the training process to ensure the generalization ability of the model to unseen data. At the same time, the hyperparameters are adjusted and the optimal model configuration is selected to obtain a trained time series analysis model.

7. The transistor-level timing prediction method for critical path standard cells according to claim 6, characterized in that: Based on the timing data of standard cells in the existing library, data amplification is performed to obtain the expanded training data set. The specific process is as follows: Parse the standard cell library file and extract the delay lookup table between the input jump time, output load and delay corresponding to different timing arcs of each standard cell; According to the input transition time and output load values ​​in the delay lookup table, multiple interpolation values ​​are generated between each two adjacent values ​​to obtain n×n input transition time and output load interpolation values; According to the interpolation of the generated input transition time and output load, combined with the interpolation algorithm, the corresponding n×n delay result is generated; Based on the generated input transition time and output load interpolation, SPICE simulation is used to generate the corresponding n×n unit delay results.

8. The transistor-level timing prediction method for critical path standard cells according to claim 1, 2 or 3, characterized in that: The specific process of obtaining the intrinsic characteristics of the standard cell transistor level is: Parse the standard cell netlist, extract the topological relationship between transistors, input pins, output pins, power supply and ground in the standard cell, and form a heterogeneous graph of different types of nodes; Parse the standard cell netlist to extract information about each transistor; parse the standard cell library file and analyze the current process status information to extract the threshold voltage and channel length information of the current transistor; Using each information as initialization feature of transistor nodes in the heterogeneous graph; Analyze the current timing arc state, extract the input pins in the current state, the input pin states, the states of other input pins, the monotonic correlation between the input pins and the output pins, whether the input pins are rising delay or falling delay, whether the output pins are rising delay or falling delay, the states of the output pins, as well as the input jump time and the output load, to obtain the state information; Initialize input pin and output pin node features according to the state information; The standard cell library file is parsed and the process corner status information of the current standard cell is analyzed to obtain the voltage value, and the characteristics of the power node are initialized to the voltage value, and the characteristics of the ground node are initialized to 0.

9. The transistor-level timing prediction method for critical path standard cells according to claim 1, 2 or 3, characterized in that: The specific process of obtaining the state characteristics of the standard cell is: Parsing the standard cell library file and extracting process information as the state characteristics of the current standard cell; the process information includes process angle, temperature, height of the standard cell and area of ​​the standard cell; The state characteristics of the standard unit are normalized to obtain the final state characteristics.

10. A transistor-level timing prediction system for critical path standard cells, comprising a memory and a processor connected to each other, wherein a computer program is stored in the memory, characterized in that: When the computer program is executed by a processor, the computer program performs the steps of the method according to any one of claims 1 to 9.

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