Method and system for checking symmetrical structure in chip

Abstract

The invention discloses an inspection method and system for a symmetrical structure in a chip, and relates to the technical field of chip structure detection. The method comprises the steps of obtaining a GDS file related to a chip internal symmetric structure in chip design; based on the GDS file, a design rule checking method is adopted for carrying out first checking, an image difference analysis method is adopted for carrying out second checking, a multi-scale analysis method is adopted for carrying out third checking, and a spatial frequency domain analysis method is adopted for carrying out fourth checking; and performing analog simulation on the internal symmetric structure of the chip based on the obtained first check result, second check result, third check result and fourth check result, comprehensively analyzing the symmetry of the internal symmetric structure of the chip, and outputting a final comparison check result. The internal symmetric structure of the chip is comprehensively compared and checked by adopting multiple checking methods, so that the checking accuracy of the internal symmetric structure of the chip is improved, and the quality and the manufacturing efficiency of the chip are further improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip structure detection, and in particular relates to a method and system for detecting the internal symmetrical structure of a chip. Background Art

[0002] The internal symmetric structure of integrated circuit design is a very important module in circuit design, which often plays an important role in the entire chip, such as operational amplifiers, comparators, equalizers, etc. Therefore, the circuit design devices and layouts must be strictly symmetrical, among which the layout symmetry is particularly important. If the symmetric structure is not done well, it will lead to mismatch, thus affecting the final chip quality.

[0003] For general layout symmetry, layout engineers will draw a symmetry axis and plan strictly according to the symmetry axis, but sometimes there will be small differences that cannot be found. Although some differences have little impact, some differences will cause mismatches and cause deviations in the results, resulting in irreconcilable mismatch voltages. In addition, there are cases where the bottom layer is strictly symmetrical, but this problem is omitted in the top-level design, which will also cause deviations. Therefore, it has become an urgent problem to compare and check the symmetrical structure inside the chip to ensure chip performance. Summary of the invention

[0004] The object of the present invention is to provide a method and system for inspecting the internal symmetric structure of a chip, which can be achieved by the following technical solutions: In a first aspect, an embodiment of the present application provides a method for inspecting a symmetrical structure inside a chip, comprising the following steps: Obtain the GDS file related to the internal symmetric structure of the chip in the chip design; Based on the GDS file, a design rule checking method is used to perform a first check on the internal symmetric structure of the chip to obtain a first check result; Based on the GDS file, an image difference analysis method is used to perform a second inspection on the internal symmetric structure of the chip to obtain a second inspection result; Based on the GDS file, a multi-scale analysis method is used to perform a third inspection on the internal symmetric structure of the chip to obtain a third inspection result; Based on the GDS file, a spatial frequency domain analysis method is used to perform a fourth inspection on the internal symmetric structure of the chip to obtain a fourth inspection result; Simulating the internal symmetric structure of the chip based on the first inspection result, the second inspection result, the third inspection result and the fourth inspection result, comprehensively analyzing the symmetry of the internal symmetric structure of the chip, and outputting the final comparison inspection result; The GDS file is used to describe the layout information of the integrated circuit and the geometric data of the internal symmetrical structure of the chip.

[0005] Preferably, the first check of the internal symmetric structure of the chip by using a design rule check method includes: Define the symmetry point and confirm the symmetry range to obtain the symmetry area; Exporting the data to be inspected in the GDS file and adding the data to be inspected to the inspection file; Within the symmetric area, the inspection file is extracted using the first inspection rule, and the extracted data is mapped to the selected area; Use the calibre LVL tool to perform layout comparison in the selected area and obtain the first comparison result; A symmetry analysis is performed based on the first comparison result to obtain a first analysis result.

[0006] Preferably, the first check of the internal symmetric structure of the chip by using a design rule check method further includes: Prepare the GDS file and the second inspection rules; Use DRC tools to check geometric symmetry and inter-layer symmetry; Check the positioning of symmetrical elements and check whether the symmetrical elements meet the symmetry requirements; Summarizing multiple inspection results and performing comparative analysis to obtain a second comparative result; Performing symmetry analysis based on the second comparison result and obtaining a second analysis result; Continuously updating the second inspection rule through iteration based on the second analysis result; The geometric symmetry check includes symmetry element detection, axisymmetry check, point symmetry check and shape symmetry check; the inter-layer symmetry check includes multi-layer symmetry and wiring symmetry; The first analysis result and the second analysis result are combined to form the first inspection result.

[0007] Preferably, the second check of the internal symmetric structure of the chip by using an image difference analysis method comprises: Obtaining an inspection image based on the GDS file and preparing a reference image; Preprocessing the inspection image and the reference image, including image alignment, image scaling, and resolution matching; Use image difference analysis tools to compare the preprocessed inspection image with the reference image and generate a difference map; Performing a difference assessment based on the difference map includes: calculating the size and location of the difference, and quantifying the severity of the difference; The difference areas are located according to the difference evaluation results, and multiple difference areas obtained after multiple evaluations are summarized into a difference data set; A difference analysis is performed based on the difference data set to obtain the second inspection result.

[0008] Preferably, the performing difference comparison comprises: Set the difference deviation threshold; Using an image difference analysis algorithm, the reference image and the inspection image are compared pixel by pixel to obtain image comparison differences; The size of the image comparison difference and the difference deviation threshold is determined. If the image comparison difference is less than the difference deviation threshold, the next round of comparison is performed; otherwise, a difference map is generated by integrating multiple image comparison differences.

[0009] Preferably, the third check of the internal symmetric structure of the chip by using a multi-scale analysis method includes: Acquiring multi-scale data based on the GDS file, including macro-scale data, meso-scale data, and micro-scale data; A multi-scale analysis is performed based on the multi-scale data and a multi-scale analysis result is output.

[0010] Preferably, the performing multi-scale analysis based on the multi-scale data comprises: Macro-scale analysis: Symmetry analysis from the overall layout level, including symmetrical wiring, symmetrical power distribution, and symmetrical heat dissipation design; Mesoscale analysis: Symmetry analysis is performed at the local regional scale to check the spatial symmetry and positional relationship between unit modules; Micro-scale analysis: Symmetry analysis at a detailed level, with precise symmetry checks on metal layers and contact points; The analysis results of macroscale analysis, mesoscale analysis and microscale analysis are integrated into multi-scale analysis results.

[0011] Preferably, the fourth check of the internal symmetric structure of the chip by using a spatial frequency domain analysis method includes: Determining input data for spatial frequency domain analysis based on the GDS file, including spatial domain data and frequency domain data; Converting the spatial domain data into the frequency domain data using Fourier transform; forming a periodic frequency spectrum diagram based on the frequency domain data; Performing symmetry analysis in the frequency domain based on the periodic spectrum diagram and obtaining a frequency domain analysis result; The frequency domain analysis result is output as a fourth inspection result.

[0012] In a second aspect, an embodiment of the present application provides an inspection system for a symmetrical structure inside a chip, applying the inspection method as described above, including: The data acquisition module is used to obtain the GDS file related to the internal symmetric structure of the chip in the chip design; A first inspection module, based on the GDS file, uses a design rule inspection method to perform a first inspection on the internal symmetric structure of the chip to obtain a first inspection result; A second inspection module, based on the GDS file, uses an image difference analysis method to perform a second inspection on the internal symmetric structure of the chip to obtain a second inspection result; A third inspection module, based on the GDS file, uses a multi-scale analysis method to perform a third inspection on the internal symmetric structure of the chip to obtain a third inspection result; A fourth inspection module, based on the GDS file, uses a spatial frequency domain analysis method to perform a fourth inspection on the internal symmetric structure of the chip to obtain a fourth inspection result; A simulation module, which simulates the internal symmetric structure of the chip based on the first inspection result, the second inspection result, the third inspection result and the fourth inspection result, comprehensively analyzes the symmetry of the internal symmetric structure of the chip, and outputs a final comparison inspection result; The GDS file is used to describe the layout information of the integrated circuit and the geometric data of the internal symmetrical structure of the chip.

[0013] The beneficial effects of the present invention are: (1) The present invention performs comparative inspection on the internal symmetric structure of the chip and comprehensively inspects the internal structure by using multiple inspection methods, thereby improving the accuracy of the inspection of the internal symmetric structure of the chip, thereby improving the chip quality and manufacturing efficiency.

[0014] (2) The present invention first obtains a GDS file related to the internal symmetric structure of the chip in the chip design; then, based on the GDS file, a design rule check method is used to perform a first check on the internal symmetric structure of the chip to obtain a first check result; then, based on the GDS file, an image difference analysis method is used to perform a second check on the internal symmetric structure of the chip to obtain a second check result; then, based on the GDS file, a multi-scale analysis method is used to perform a third check on the internal symmetric structure of the chip to obtain a third check result; then, based on the GDS file, a spatial frequency domain analysis method is used to perform a fourth check on the internal symmetric structure of the chip to obtain a fourth check result; finally, based on the above-mentioned first check result, second check result, third check result and fourth check result, the internal symmetric structure of the chip is simulated, the symmetry of the internal symmetric structure of the chip is comprehensively analyzed, and the final comparative check result is output. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] For better understanding and implementation, the technical solution of the present application is described in detail below with reference to the accompanying drawings.

[0016] Figure 1 A flowchart of a method for inspecting the internal symmetric structure of a chip provided in an embodiment of the present application; Figure 2 A flowchart of the first level of inspection provided in an embodiment of the present application; Figure 3 A flowchart of the steps of the second check provided in an embodiment of the present application; Figure 4 A schematic diagram of the structure of a system for inspecting the internal symmetrical structure of a chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0017] In order to further explain the technical means and effects taken by the present invention to achieve the predetermined invention purpose, exemplary embodiments will be described in detail here, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are only examples of methods and systems consistent with some aspects of the present application as detailed in the attached claims.

[0018] The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used in this article refers to any or all possible combinations of one or more associated listed items.

[0019] The specific implementation methods, features and effects of the present invention are described in detail below in conjunction with the accompanying drawings and preferred embodiments.

[0020] Example 1 See also Figure 1 The present application provides a method for inspecting the internal symmetric structure of a chip, comprising the following steps: Obtain the GDS file related to the internal symmetric structure of the chip in the chip design; Based on the GDS file, a design rule checking method is used to perform a first check on the internal symmetric structure of the chip to obtain a first check result; Based on the GDS file, an image difference analysis method is used to perform a second inspection on the internal symmetric structure of the chip to obtain a second inspection result; Based on the GDS file, a multi-scale analysis method is used to perform a third inspection on the internal symmetric structure of the chip to obtain a third inspection result; Based on the GDS file, a spatial frequency domain analysis method is used to perform a fourth inspection on the internal symmetric structure of the chip to obtain a fourth inspection result; Simulating the internal symmetric structure of the chip based on the first inspection result, the second inspection result, the third inspection result and the fourth inspection result, comprehensively analyzing the symmetry of the internal symmetric structure of the chip, and outputting the final comparison inspection result; The GDS file is used to describe the layout information of the integrated circuit and the geometric data of the internal symmetrical structure of the chip.

[0021] Specifically, since the accuracy of the internal symmetric structure of the chip will have a great impact on the chip design and manufacturing, in order to ensure the chip quality, the present application performs a comparative inspection on the internal symmetric structure of the chip, and comprehensively inspects the internal structure by adopting a variety of inspection methods, so as to improve the accuracy of the inspection of the internal symmetric structure of the chip, and then improve the chip quality and manufacturing efficiency, specifically: first, obtain the GDS file related to the internal symmetric structure of the chip in the chip design; then, based on the GDS file, use the design rule inspection method to perform a first inspection on the internal symmetric structure of the chip to obtain a first inspection result; then, based on the GDS file, use the image difference analysis method to perform a second inspection on the internal symmetric structure of the chip to obtain a second inspection result; then, based on the GDS file, use the multi-scale analysis method to perform a third inspection on the internal symmetric structure of the chip to obtain a third inspection result; then, based on the GDS file, use the spatial frequency domain analysis method to perform a fourth inspection on the internal symmetric structure of the chip to obtain a fourth inspection result; finally, based on the above-mentioned first inspection result, second inspection result, third inspection result and fourth inspection result, simulate the internal symmetric structure of the chip, comprehensively analyze the symmetry of the internal symmetric structure of the chip, and output the final comparative inspection result. For symmetrical structures, this application uses the design rule checking method to not only check whether the size and spacing of each element in the layout meet the standards, but also check whether the graphics are symmetrical to avoid structural instability or performance deviations that may be caused by asymmetry; generate a difference map through a graphics processing algorithm (for example, pixel comparison of an image) to highlight any asymmetry, thereby identifying potential design defects or manufacturing errors; finally, through the combined effect of the above-mentioned multiple methods, potential problems in the design can be effectively discovered to ensure the consistency and performance of the chip during the manufacturing process.

[0022] It should be noted that the above-mentioned GDS (Graphic Data System) file is a widely used file format for describing the layout and geometric data of integrated circuits. In the process of checking the symmetric structure of chip design, GDS refers to the GDSII file format, which contains all the geometric data of the chip layout, including structures and areas at different levels. "GDS of the cover area" refers to specific areas related to protection or packaging in chip design. The geometric data of these areas will be extracted and used for tasks such as symmetry analysis and design rule checking. By checking the GDS data, it is possible to verify whether the symmetrical layout of the chip meets expectations and ensure that asymmetric design defects will not occur during the manufacturing process.

[0023] like Figure 2 As shown, in one embodiment provided in the present application, the first check of the internal symmetric structure of the chip using the design rule check method includes: Define the symmetry point and confirm the symmetry range to obtain the symmetry area; Exporting the data to be inspected in the GDS file and adding the data to be inspected to the inspection file; Within the symmetric area, the inspection file is extracted using the first inspection rule, and the extracted data is mapped to the selected area; Use the calibre LVL tool to perform layout comparison in the selected area and obtain the first comparison result; A symmetry analysis is performed based on the first comparison result to obtain a first analysis result.

[0024] Specifically, this embodiment compares the final results to obtain reliable comparison results: first define the symmetry point and confirm the symmetry range; then export the data to be checked; then use the written check rule (rule) to extract the data and extract it into the boxed area; then use calibre LVL to compare to obtain the comparison result; finally, perform symmetry analysis on the comparison result to obtain the analysis result. This embodiment uses the above method to compare the desired symmetric data, which can be processed efficiently and has a high accuracy rate.

[0025] It should be noted that Calibre LVL (Layout Versus Layout) is a function in the Calibre design tool suite of Mentor Graphics (now Siemens EDA), which is used to perform layout and layout comparison (LayoutVersus Layout) checks.

[0026] In an embodiment provided in the present application, the first check of the internal symmetric structure of the chip by using a design rule check method further includes: Prepare the GDS file and the second inspection rules; Use DRC tools to check geometric symmetry and inter-layer symmetry; Check the positioning of symmetrical elements and check whether the symmetrical elements meet the symmetry requirements; Summarizing multiple inspection results and performing comparative analysis to obtain a second comparative result; Performing symmetry analysis based on the second comparison result and obtaining a second analysis result; Continuously updating the second inspection rule through iteration based on the second analysis result; The geometric symmetry check includes symmetry element detection, axisymmetry check, point symmetry check and shape symmetry check; the inter-layer symmetry check includes multi-layer symmetry and wiring symmetry; The first analysis result and the second analysis result are combined to form the first inspection result.

[0027] Specifically, this embodiment ensures that the symmetrical structure inside the chip can be stably and reliably realized during the manufacturing process through the above steps, thereby avoiding manufacturing defects or performance problems.

[0028] It should be noted that the above-mentioned DRC (Design Rule Check) tool is an automated tool used in the integrated circuit design process, which aims to ensure that the design complies with the rules and constraints required by the manufacturing process, especially for the symmetrical structure of the chip.

[0029] like Figure 3 As shown, in one embodiment provided in the present application, the second check of the internal symmetric structure of the chip by using the image difference analysis method includes: Obtaining an inspection image based on the GDS file and preparing a reference image; Preprocessing the inspection image and the reference image, including image alignment, image scaling, and resolution matching; Use image difference analysis tools to compare the preprocessed inspection image with the reference image and generate a difference map; Performing a difference assessment based on the difference map includes: calculating the size and location of the difference, and quantifying the severity of the difference; The difference areas are located according to the difference evaluation results, and multiple difference areas obtained after multiple evaluations are summarized into a difference data set; A difference analysis is performed based on the difference data set to obtain the second inspection result.

[0030] Specifically, this embodiment performs a second check on the symmetrical structure inside the chip. The image difference analysis method can identify whether the symmetry remains consistent and detect whether unsatisfactory deformation or asymmetry is introduced during the design update or modification process.

[0031] In an embodiment provided in the present application, the performing difference comparison includes: Set the difference deviation threshold; Using an image difference analysis algorithm, the reference image and the inspection image are compared pixel by pixel to obtain image comparison differences; The size of the image comparison difference and the difference deviation threshold is determined. If the image comparison difference is less than the difference deviation threshold, the next round of comparison is performed; otherwise, a difference map is generated by integrating multiple image comparison differences.

[0032] In an embodiment provided in the present application, the third check of the internal symmetric structure of the chip by using a multi-scale analysis method includes: Acquiring multi-scale data based on the GDS file, including macro-scale data, meso-scale data, and micro-scale data; A multi-scale analysis is performed based on the multi-scale data and a multi-scale analysis result is output.

[0033] In an embodiment provided in the present application, the performing multi-scale analysis based on the multi-scale data includes: Macro-scale analysis: Symmetry analysis from the overall layout level, including symmetrical wiring, symmetrical power distribution, and symmetrical heat dissipation design; Mesoscale analysis: Symmetry analysis is performed at the local regional scale to check the spatial symmetry and positional relationship between unit modules; Micro-scale analysis: Symmetry analysis at a detailed level, with precise symmetry checks on metal layers and contact points; The analysis results of macroscale analysis, mesoscale analysis and microscale analysis are integrated into multi-scale analysis results.

[0034] In an embodiment provided in the present application, the fourth check of the internal symmetric structure of the chip using a spatial frequency domain analysis method includes: Determining input data for spatial frequency domain analysis based on the GDS file, including spatial domain data and frequency domain data; Converting the spatial domain data into the frequency domain data using Fourier transform; forming a periodic frequency spectrum diagram based on the frequency domain data; Performing symmetry analysis in the frequency domain based on the periodic spectrum diagram and obtaining a frequency domain analysis result; The frequency domain analysis result is output as a fourth inspection result.

[0035] Specifically, this embodiment uses the spatial frequency domain analysis method to perform a fourth check on the internal symmetric structure of the chip, mainly by analyzing the chip design in the frequency domain to identify symmetry problems or design defects at different frequencies. This method can effectively capture the periodicity, symmetry deviation and other details in the design, especially in the chip design of complex multi-layer structures and high-frequency applications.

[0036] Example 2 See also Figure 4 The embodiment of the present application provides an inspection system for the internal symmetrical structure of a chip, which is applied to the inspection method as described above, and includes: The data acquisition module is used to obtain the GDS file related to the internal symmetric structure of the chip in the chip design; A first inspection module, based on the GDS file, uses a design rule inspection method to perform a first inspection on the internal symmetric structure of the chip to obtain a first inspection result; A second inspection module, based on the GDS file, uses an image difference analysis method to perform a second inspection on the internal symmetric structure of the chip to obtain a second inspection result; A third inspection module, based on the GDS file, uses a multi-scale analysis method to perform a third inspection on the internal symmetric structure of the chip to obtain a third inspection result; A fourth inspection module, based on the GDS file, uses a spatial frequency domain analysis method to perform a fourth inspection on the internal symmetric structure of the chip to obtain a fourth inspection result; A simulation module, which simulates the internal symmetric structure of the chip based on the first inspection result, the second inspection result, the third inspection result and the fourth inspection result, comprehensively analyzes the symmetry of the internal symmetric structure of the chip, and outputs a final comparison inspection result; The GDS file is used to describe the layout information of the integrated circuit and the geometric data of the internal symmetrical structure of the chip.

[0037] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0038] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0039] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0040] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technical personnel in this field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A method for inspecting the internal symmetric structure of a chip, characterized in that: The steps include: Obtain the GDS file related to the internal symmetric structure of the chip in the chip design; Based on the GDS file, a design rule checking method is used to perform a first check on the internal symmetric structure of the chip to obtain a first check result; Based on the GDS file, an image difference analysis method is used to perform a second inspection on the internal symmetric structure of the chip to obtain a second inspection result; Based on the GDS file, a multi-scale analysis method is used to perform a third inspection on the internal symmetric structure of the chip to obtain a third inspection result; Based on the GDS file, a spatial frequency domain analysis method is used to perform a fourth inspection on the internal symmetric structure of the chip to obtain a fourth inspection result; Simulating the internal symmetric structure of the chip based on the first inspection result, the second inspection result, the third inspection result and the fourth inspection result, comprehensively analyzing the symmetry of the internal symmetric structure of the chip, and outputting the final comparison inspection result; The GDS file is used to describe the layout information of the integrated circuit and the geometric data of the internal symmetrical structure of the chip.

2. A method for inspecting the internal symmetric structure of a chip according to claim 1, characterized in that: The first check of the internal symmetric structure of the chip by using the design rule check method includes: Define the symmetry point and confirm the symmetry range to obtain the symmetry area; Exporting the data to be inspected in the GDS file and adding the data to be inspected to the inspection file; Within the symmetric area, the inspection file is extracted using the first inspection rule, and the extracted data is mapped to the selected area; Use the calibre LVL tool to perform layout comparison in the selected area and obtain the first comparison result; A symmetry analysis is performed based on the first comparison result to obtain a first analysis result.

3. A method for inspecting the internal symmetric structure of a chip according to claim 2, characterized in that: The first check of the internal symmetric structure of the chip by using the design rule check method also includes: Prepare the GDS file and the second inspection rules; Use DRC tools to check geometric symmetry and inter-layer symmetry; Check the positioning of symmetrical elements and check whether the symmetrical elements meet the symmetry requirements; Summarizing multiple inspection results and performing comparative analysis to obtain a second comparative result; Performing symmetry analysis based on the second comparison result and obtaining a second analysis result; Continuously updating the second inspection rule through iteration based on the second analysis result; The geometric symmetry check includes symmetry element detection, axisymmetry check, point symmetry check and shape symmetry check; the inter-layer symmetry check includes multi-layer symmetry and wiring symmetry; The first analysis result and the second analysis result are combined to form the first inspection result.

4. The method for inspecting the internal symmetric structure of a chip according to claim 1, characterized in that: The second check of the internal symmetric structure of the chip by using the image difference analysis method includes: Obtaining an inspection image based on the GDS file and preparing a reference image; Preprocessing the inspection image and the reference image, including image alignment, image scaling, and resolution matching; Use image difference analysis tools to compare the preprocessed inspection image with the reference image and generate a difference map; Performing a difference assessment based on the difference map includes: calculating the size and location of the difference, and quantifying the severity of the difference; The difference areas are located according to the difference evaluation results, and multiple difference areas obtained after multiple evaluations are summarized into a difference data set; A difference analysis is performed based on the difference data set to obtain the second inspection result.

5. The method for inspecting the internal symmetric structure of a chip according to claim 4, characterized in that: The difference comparison comprises: Set the difference deviation threshold; Using an image difference analysis algorithm, the reference image and the inspection image are compared pixel by pixel to obtain image comparison differences; The size of the image comparison difference and the difference deviation threshold is determined. If the image comparison difference is less than the difference deviation threshold, the next round of comparison is performed; otherwise, a difference map is generated by integrating multiple image comparison differences.

6. The method for inspecting the internal symmetric structure of a chip according to claim 1, characterized in that: The third step of checking the internal symmetric structure of the chip by using a multi-scale analysis method includes: Acquiring multi-scale data based on the GDS file, including macro-scale data, meso-scale data, and micro-scale data; A multi-scale analysis is performed based on the multi-scale data and a multi-scale analysis result is output.

7. The method for inspecting the internal symmetric structure of a chip according to claim 6, characterized in that: The performing multi-scale analysis based on the multi-scale data comprises: Macro-scale analysis: Symmetry analysis from the overall layout level, including symmetrical wiring, symmetrical power distribution, and symmetrical heat dissipation design; Mesoscale analysis: Symmetry analysis is performed at the local regional scale to check the spatial symmetry and positional relationship between unit modules; Micro-scale analysis: Symmetry analysis at a detailed level, with precise symmetry checks on metal layers and contact points; The analysis results of macroscale analysis, mesoscale analysis and microscale analysis are integrated into multi-scale analysis results.

8. The method for inspecting the internal symmetric structure of a chip according to claim 1, characterized in that: The fourth step of checking the internal symmetric structure of the chip by using the spatial frequency domain analysis method includes: Determining input data for spatial frequency domain analysis based on the GDS file, including spatial domain data and frequency domain data; Converting the spatial domain data into the frequency domain data using Fourier transform; forming a periodic frequency spectrum diagram based on the frequency domain data; Performing symmetry analysis in the frequency domain based on the periodic spectrum diagram and obtaining a frequency domain analysis result; The frequency domain analysis result is output as a fourth inspection result.

9. An inspection system for the internal symmetrical structure of a chip, using the inspection method according to any one of claims 1 to 8, characterized in that: include: The data acquisition module is used to obtain the GDS file related to the internal symmetric structure of the chip in the chip design; A first inspection module, based on the GDS file, uses a design rule inspection method to perform a first inspection on the internal symmetric structure of the chip to obtain a first inspection result; A second inspection module, based on the GDS file, uses an image difference analysis method to perform a second inspection on the internal symmetric structure of the chip to obtain a second inspection result; A third inspection module, based on the GDS file, uses a multi-scale analysis method to perform a third inspection on the internal symmetric structure of the chip to obtain a third inspection result; A fourth inspection module, based on the GDS file, uses a spatial frequency domain analysis method to perform a fourth inspection on the internal symmetric structure of the chip to obtain a fourth inspection result; A simulation module, which simulates the internal symmetric structure of the chip based on the first inspection result, the second inspection result, the third inspection result and the fourth inspection result, comprehensively analyzes the symmetry of the internal symmetric structure of the chip, and outputs a final comparison inspection result; The GDS file is used to describe the layout information of the integrated circuit and the geometric data of the internal symmetrical structure of the chip.

Images