Circuit device for FPGA (Field Programmable Gate Array) to quickly configure code stream

Abstract

The invention provides a circuit device for quickly configuring a code stream for an FPGA (Field Programmable Gate Array), which comprises a configuration interface and a configuration controller, and code stream data enters the configuration controller through the configuration interface; the configuration controller comprises a configuration control circuit and a code stream frame distribution circuit; the configuration control circuit analyzes the code stream file to obtain the content of the configuration data area; a plurality of storage areas are arranged in a configuration memory of the FPGA; the configuration control circuit finds a first data frame of each storage area in a configuration data area, combines the data frames at the same position of each storage area into a large-bit-width data frame, and sends the large-bit-width data frame to the code stream frame distribution circuit; and the code stream frame distribution circuit divides the combined large-bit-width data frames and then sends the divided large-bit-width data frames to each storage area in parallel. According to the circuit device for rapidly configuring the code stream by the FPGA, parallel configuration is adopted, the configuration speed can be greatly increased, and the resource utilization rate is increased.

Description

Technical Field

[0001] The present invention belongs to the field of FPGA configuration technology, and in particular relates to a circuit device for quickly configuring a code stream of an FPGA. Background Art

[0002] FPGA (Field Programmable Gate Array) is a semiconductor device that consists of programmable logic units and programmable interconnection resources. Unlike fixed-function ASICs (Application-Specific Integrated Circuits), the hardware functions of FPGAs can be reprogrammed by downloading different configuration data. FPGAs are widely used in digital signal processing, communications, embedded systems, artificial intelligence, and automation due to their high flexibility and rapid prototyping capabilities.

[0003] A bitstream file is a binary file used to configure an FPGA. It contains configuration information for all programmable resources inside the FPGA, including the settings of logic units, wiring methods, and configuration of I / O pins. Bitstream files are generated by FPGA design software, which synthesizes the user's design description (usually a hardware description language such as Verilog or VHDL), places and routes, and generates corresponding bitstream files. Bitstream files configure all transistors in the FPGA chip in the form of binary data. For the same FPGA chip, different circuits correspond to bitstream files of the same size and different contents. The bitstream file can be divided into three parts: register configuration area, configuration data area, and verification information area. The register configuration area contains the register addresses and values ​​related to the FPGA configuration bitstream. This part of the content determines the mode, rate, and bitstream scale of the FPGA configuration bitstream. The configuration data area is the core part of the bitstream file, which contains data used to configure the FPGA logic resources and functional modules. This part of the data determines the specific configuration of the FPGA internal logic units, connection resources, and I / O resources.

[0004] Frame is the basic unit of FPGA configuration data. The data frame corresponding to each row and column of the FPGA circuit is fixed in the bitstream file, so the position of the data frame corresponding to a specific row and column can be located in the bitstream file. Currently, there are many modes for bitstream configuration, such as master mode, slave mode, and JTAG mode. Regardless of the mode, the principle is to import the bitstream file into the FPGA through the configuration interface, and the configuration controller inside the FPGA controls the configuration circuit to write the bitstream into the configuration memory (CRAM).

[0005] However, when the configuration circuit of the configuration controller in the prior art writes the code stream into the configuration memory, it needs to configure row by row, column by column, and frame by frame, so the configuration time is long, especially for application scenarios that require fast startup or frequent reconfiguration, resulting in too long configuration time. Summary of the invention

[0006] The present invention provides a circuit device for quickly configuring code streams of FPGA, which adopts parallel configuration and can greatly improve the configuration speed and resource utilization.

[0007] Other purposes and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0008] To achieve one or part or all of the above purposes or other purposes, a technical solution of the present invention provides a circuit device for quickly configuring a code stream of an FPGA, including a configuration interface and a configuration controller, and the code stream data enters the configuration controller through the configuration interface; the configuration controller includes a configuration control circuit and a code stream frame distribution circuit; the configuration control circuit parses the code stream file to obtain the content of the configuration data area; there are multiple storage areas in the configuration memory of the FPGA; the configuration control circuit finds the data frame file corresponding to each storage area in the configuration data area, and merges the data frames at the same position of each storage area into a large bit width data frame, and sends it to the code stream frame distribution circuit; the code stream frame distribution circuit divides the merged large bit width data frame and sends it to each storage area in parallel.

[0009] The configuration controller also includes a decryption and decompression circuit, which decrypts and decompresses the input code stream data and sends the decrypted and decompressed code stream data to the configuration control circuit.

[0010] The FPGA divides the configuration memory into multiple rows and columns of storage areas equal to the number of rows and columns of the internal logic resources of the FPGA chip according to the physical layout of the rows and columns of the internal logic resources of the chip; and divides each column of storage area into a number of corresponding data frame placement areas according to the number of sub-circuits included in each column of logic resources of the FPGA circuit.

[0011] Columns with the same storage area position in different rows have multiple data frame placement areas of equal number.

[0012] The configuration control circuit searches for the data frame file corresponding to each data frame placement area row by row and column by column in the configuration data area of ​​the code stream file, merges the data frame files corresponding to the data frame placement areas with the same position between different rows into a large bit width data frame, and sends it to the code stream frame distribution circuit for segmentation and restoration. The restored data frame files are sent in parallel to the corresponding data frame placement areas in the data storage device.

[0013] The configuration control circuit merges the data frames according to the row order of the configuration memory storage area; the code stream frame distribution circuit divides the merged data frames according to the row order of the configuration memory storage area; The code stream frame distribution circuit has a plurality of data channels, each row storage area of ​​the configuration memory corresponds to a data channel, and the divided data frames enter the data channels in parallel.

[0014] The code stream frame distribution circuit sends the restored multiple data frames in parallel to the data frame placement area at the same position of each row in the configuration memory within one clock cycle; the code stream frame distribution circuit sequentially configures a data frame file to each data frame placement area for each column of data storage area from top to bottom until all data frame placement areas of a column of data storage area are configured with data frame files; the code stream frame distribution circuit configures the data frame files column by column in sequence until the data frame placement areas of all columns are configured with data frame files.

[0015] A two-level cache device is arranged between the configuration control circuit and the code stream frame distribution circuit; the two-level cache device includes an L1 cache and an L2 cache; the configuration control circuit searches for a data frame file corresponding to a current data frame placement area in the configuration data area, merges the data frame files corresponding to data frame placement areas at the same position between different rows into a large bit width data frame, and caches the large bit width data frame to the L1 cache; the configuration control circuit preloads the data frame file corresponding to the next data frame placement area according to the order of the data frame placement areas in each column, and merges them into a large bit width data frame file and caches them in the L2 cache; after the code stream frame distribution circuit takes the data frame from the L1 cache, the data frame in the L2 cache is sent to the L1 cache, and the configuration control circuit continues to preload the data frame file in the next data frame placement area of ​​the configuration memory.

[0016] The configuration controller is also provided with a verification circuit. When all data frames in the configuration memory are configured, the verification circuit reads back the configuration data in the configuration memory and performs CRC verification on the read-back data. The configuration control circuit parses the content of the verification information area of ​​the code stream file, and feeds back the content of the verification information area to the verification circuit. The verification circuit performs an XOR operation on the read-back data based on a preset generating polynomial to obtain a verification code, compares the verification code with the content of the verification information area, and outputs a verification result.

[0017] If the verification code is the same as the content of the verification information area, the verification is successful, otherwise the verification fails; the verification circuit feeds back the verification result to the configuration control circuit, and if the verification is successful, the configuration control circuit pulls up the DONE signal and INIT_B signal of the FPGA; if the verification fails, the configuration control circuit pulls down the DONE signal and INIT_B signal of the FPGA, resets the FPGA, and re-performs the configuration code stream process.

[0018] Compared with the prior art, the beneficial effects of the present invention mainly include: the present invention is based on the division of the storage area in the FPGA configuration memory, and finds the data frame files in each data frame placement area in the storage area of ​​the same column of different rows at a specific position in the configuration data area of ​​the code stream file through the configuration control circuit, merges the multiple data frame files found into a large bit width data frame file, and divides and inputs them through the code stream frame distribution circuit, which can complete the configuration of multiple rows of data frames at the same time, greatly improving the efficiency of data configuration, and at the same time, high resource utilization.

[0019] In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 This is a schematic diagram of the code stream file structure.

[0022] Figure 2 The schematic diagram of the circuit device for quickly configuring the bit stream of FPGA of the present invention is shown.

[0023] Figure 3 A schematic diagram of a storage area inside a configuration memory of the present invention.

[0024] Figure 4 This is a schematic diagram of writing the first row, first column, and first frame configuration data for the specific implementation scheme in Example 1.

[0025] Figure 5 This is a schematic diagram of writing the last frame of configuration data for the specific implementation scheme in Example 1. DETAILED DESCRIPTION

[0026] The above and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front or back, etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and not to limit the present invention.

[0027] Example 1 Embodiment 1 provides a circuit device for fast configuration of FPGA bitstream, including a configuration interface and a configuration controller, wherein the bitstream data enters the configuration controller through the configuration interface; the configuration controller includes a configuration control circuit and a bitstream frame distribution circuit; the configuration control circuit parses the bitstream file to obtain the content of the configuration data area; the configuration memory of the FPGA has multiple storage areas; the configuration control circuit finds the data frame file corresponding to each storage area in the configuration data area, and merges the data frames at the same position of each storage area into a large bit width data frame, and sends it to the bitstream frame distribution circuit; the bitstream frame distribution circuit divides the merged large bit width data frame and sends it to each storage area in parallel.

[0028] The scheme of the present invention is explained in detail below in conjunction with the accompanying drawings.

[0029] FPGA is generally a programmable logic gate array structure composed of several rows and columns. The row of FPGA is the horizontal arrangement unit in its internal structure, and each row contains multiple columns. The column is the vertical arrangement unit in the internal structure of FPGA, and each column contains several sub-circuits (such as CLB units, DSP units, etc.). The configuration data of FPGA is usually organized and managed in frames. Each frame contains the configuration information of a specific regional circuit (sub-circuit) (such as wiring resources or I / O blocks, etc.). Usually, each column of circuits contains circuits of several regions, so it takes several frames of configuration data to configure a column of circuits in FPGA.

[0030] The configuration memory CRAM of this application is divided into different data storage areas. Figure 3 , there are multiple rows and columns of storage areas in the configuration memory CRAM, and the multiple rows and columns of storage areas constitute a storage array. The number of rows and columns of the configuration memory CRAM storage area is arranged according to the row and column arrangement of the logic resources inside the FPGA. Each column of storage area corresponds to multiple data frame placement areas, each data frame placement area can be placed in a data frame, and each data frame is used to configure a specific sub-circuit of a column of FPGA circuits. The number of columns of storage areas between different rows is the same, and the columns with the same storage area position have an equal number of multiple data frame placement areas. That is, the number of columns of each row of storage areas in the configuration memory CRAM and the number and arrangement of data frame placement areas in each column are the same.

[0031] See also Figure 1 Schematic diagram of the bitstream file, which is a binary file used to configure FPGA. It contains the configuration information of all programmable resources inside the FPGA, including the settings of logic units, wiring methods, and configuration of I / O pins. The bitstream file is generated by FPGA design software, which synthesizes the user's design description (usually hardware description language such as Verilog or VHDL), layouts and routes, and generates the corresponding bitstream file. The bitstream file configures all transistors in the FPGA chip in the form of binary data. For the same FPGA chip, different circuits correspond to bitstream files of the same size and different contents. The bitstream file can be divided into three parts: register configuration area, configuration data area, and verification information area. The register configuration area contains the register addresses and values ​​related to the FPGA configuration bitstream. This part of the content determines the mode, rate, bitstream scale, and other information of the FPGA configuration bitstream. The configuration data area is the core part of the bitstream file, which contains data used to configure the FPGA logic resources and functional modules. This part of the data determines the specific configuration of the internal logic units, connection resources, and I / O resources of the FPGA.

[0032] See also Figure 2 The circuit structure of Example 1 includes a configuration interface, and the configuration interface is used to receive a code stream file. Different FPGA configuration methods have different configuration interfaces, and the configuration controller receives an external code stream file through the configuration interface. The code stream file enters the decryption and decompression circuit in the configuration controller, and the decryption and decompression circuit decrypts and decompresses the code stream file. The decryption and decompression steps are prior art and are not repeated here in this application. The code stream file that has undergone the decryption and decompression operation enters the configuration control circuit, and the configuration control circuit parses the code stream file and merges the code stream file. The specific merging processing steps are: parse the code stream file to obtain the content of the configuration data area, and search for each frame of data in the configuration data area according to the storage area position of the configuration memory that needs to be input for each data frame. At the same time, the data frame files corresponding to the data frame placement areas at the same position in the columns at the same position in each row storage area are merged into a large bit width data frame. The merged large-bit-width data frame is transmitted to the code stream frame distribution circuit for segmentation. After the code stream frame distribution circuit segments and restores the large-bit-width data frame, it is distributed in parallel to the data frame placement area at the same position in the column at the same position in each row storage area within one clock cycle, thereby completing the configuration of a data frame in multiple row storage areas within one clock cycle. After completing the configuration of the current data frame, the configuration of the next data frame continues until the configuration of the data frames of all columns is completed.

[0033] The order of merging and the order of splitting are the same, the configuration control circuit merges the data frames according to the row order of the configuration memory storage area (that is, the data frames at the same position in each row are merged); the code stream frame distribution circuit splits the merged data frames according to the row order of the configuration memory storage area.

[0034] In order to realize parallel transmission, there are multiple data channels in the code stream frame distribution circuit, and each row storage area of ​​the configuration memory corresponds to a data channel. The divided data frames enter the data channels in parallel and are sent to the data memory.

[0035] The distribution order of the data frame by the code stream frame distribution circuit is: the data configuration frame of each column is configured from top to bottom. When the data frame of one column is configured, it is configured column by column until the data frames of all columns are configured. Specifically: first, for the data storage area of ​​the selected column, the data frame file is configured in the data frame placement area from top to bottom until all the data frame placement areas of the selected column are configured with data frame files. After all the data frame placement areas of the selected column are configured with data frame files, the data frame file of the next column is configured according to the order of the columns of the data storage area.

[0036] In order to improve the efficiency of configuration, a two-level cache device is set between the configuration control circuit and the code stream frame distribution circuit; see Figure 2 The two-level cache device includes an L1 cache and an L2 cache; the configuration control circuit searches for a data frame file corresponding to a current data frame placement area in the configuration data area, merges the data frame files corresponding to the data frame placement areas at the same position between different rows into a large bit width data frame, and caches the large bit width data frame to the L1 cache; the configuration control circuit preloads the data frame file corresponding to the next data frame placement area according to the order of the data frame placement areas in each column, and merges them into a large bit width data frame file and caches them in the L2 cache; after the code stream frame distribution circuit takes the data frame from the L1 cache, the data frame in the L2 cache is sent to the L1 cache, and the configuration control circuit continues to preload the data frame file in the next data frame placement area of ​​the configuration memory.

[0037] When the configuration is completed, the verification circuit reads back the configuration data in the configuration memory and performs CRC verification on the read-back data. The verification process is as follows: the verification circuit performs XOR operation on the read-back data based on a specific generating polynomial (such as CRC-16, CRC-32, etc.) to obtain a verification code, and compares the verification code with the content of the verification information area of ​​the code stream file. If the two are the same, it means that the verification is successful, and if they are different, it means that the verification failed. The verification circuit feeds back the verification result to the configuration control circuit. If the verification is successful, the configuration control circuit pulls up the DONE signal and INIT_B signal of the FPGA; if the verification fails, the configuration control circuit pulls down the INIT_B signal of the FPGA.

[0038] Example 1 is explained by taking the configuration of an FPGA circuit with a circuit scale of 6 rows, 128 columns, and 512 frames as an example. After the code stream file enters the configuration controller through the configuration interface, the decryption and decompression circuit decrypts and decompresses the code stream information. The configuration control circuit first configures the corresponding register value according to the register address based on the register configuration area content of the code stream file. Next, the configuration control circuit finds the first frame configuration data of the first column of each row of the FPGA at a specific position in the configuration data area of ​​the code stream file, for a total of 6 frames. The above 6 frames of data are merged into a frame of large-bit-width data and sent to the code stream frame distribution circuit. After receiving the large-bit-width configuration data, the code stream frame distribution circuit divides and restores it into 6 frames of configuration data, and distributes the 6 frames of configuration data in parallel to the configuration storage area circuit corresponding to the first frame of the first column of each row of the FPGA within one clock cycle. At this time, the configuration data is written into the FPGA configuration memory as shown in the following figure. Figure 4 Then the configuration control circuit finds the configuration data of the first column and second frame of each row of the FPGA at a specific location in the configuration data area of ​​the code stream file, merges them after the configuration control circuit, and divides and restores them after the code stream frame distribution circuit distributes them in parallel to the configuration control area circuit corresponding to the first column and second frame of each row of the FPGA within one clock cycle, and so on, until the last column of each row of the FPGA is configured, and writes data frames to the data frame placement area of ​​all columns in the above manner. The schematic diagram of the configuration memory for writing the last frame of configuration data is shown in FIG. Figure 5 As shown. When the configuration is completed, the verification circuit reads back the configuration data in the configuration memory and performs CRC verification on the read-back data. The verification circuit feeds back the verification result to the configuration control circuit. If the verification is successful, the configuration control circuit pulls up the DONE signal and INIT_B signal of the FPGA; if the verification fails, the configuration control circuit pulls down the INIT_B signal of the FPGA.

[0039] The above is a detailed introduction to a circuit device for fast configuration of code streams of an FPGA provided by the present invention. In this article, a specific example is used to illustrate the structure and working principle of the present invention. The description of the above embodiment is only used to help understand the method and core idea of ​​the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made to the present invention without departing from the principle of the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A circuit device for fast configuration of code stream of FPGA, characterized in that: It includes a configuration interface and a configuration controller, and the code stream data enters the configuration controller through the configuration interface; The configuration controller includes a configuration control circuit and a code stream frame distribution circuit; The configuration control circuit parses the code stream file to obtain the content of the configuration data area; There are multiple storage areas in the FPGA’s configuration memory; The configuration control circuit finds the data frame file corresponding to each storage area in the configuration data area, and merges the data frames at the same position of each storage area into a large bit width data frame, and sends it to the code stream frame distribution circuit; The code stream frame distribution circuit divides the combined large bit width data frame and sends it to each storage area in parallel.

2. The circuit device for fast FPGA configuration code stream according to claim 1, characterized in that: The configuration controller also includes a decryption and decompression circuit, which decrypts and decompresses the input code stream data and sends the decrypted and decompressed code stream data to the configuration control circuit.

3. The circuit device for fast FPGA configuration code stream according to claim 1, characterized in that: The FPGA divides the configuration memory into a plurality of rows and columns of storage areas equal in number to the rows and columns of the internal logic resources of the FPGA chip according to the physical layout of the rows and columns of the internal logic resources of the chip; According to the number of sub-circuits included in each column of logic resources of the FPGA circuit, each column of storage area is divided into a number of corresponding data frame placement areas.

4. The circuit device for fast FPGA configuration code stream according to claim 3, characterized in that: Columns with the same storage area position in different rows have multiple data frame placement areas of equal number.

5. The circuit device for fast FPGA configuration code stream according to claim 3, characterized in that: The configuration control circuit searches for the data frame file corresponding to each data frame placement area row by row and column by column in the configuration data area of ​​the code stream file, merges the data frame files corresponding to the data frame placement areas with the same position between different rows into a large bit width data frame, and sends it to the code stream frame distribution circuit for segmentation and restoration. The restored data frame files are sent in parallel to the corresponding data frame placement areas in the data storage device.

6. The circuit device for fast configuration of code stream of FPGA according to claim 5, characterized in that: The configuration control circuit merges data frames according to the row order of the configuration memory storage area; The code stream frame distribution circuit divides the merged data frame according to the row order of the storage area of ​​the configuration memory; The code stream frame distribution circuit has a plurality of data channels, each row storage area of ​​the configuration memory corresponds to a data channel, and the divided data frames enter the data channels in parallel.

7. The circuit device for fast FPGA configuration code stream according to claim 5, characterized in that: The code stream frame distribution circuit sends the restored multiple data frames in parallel to the data frame placement area at the same position of each row in the configuration memory within one clock cycle; The code stream frame distribution circuit sequentially configures a data frame file to each data frame placement area for each column of data storage area from top to bottom until all data frame placement areas of a column of data storage area are configured with data frame files; The code stream frame distribution circuit configures the data frame files in sequence column by column until the data frame placement areas of all columns are configured with data frame files.

8. The circuit device for fast FPGA configuration code stream according to claim 6, characterized in that: A two-level cache device is provided between the configuration control circuit and the code stream frame distribution circuit; The two-level cache device includes an L1 cache and an L2 cache; The configuration control circuit searches for a data frame file corresponding to the current data frame placement area in the configuration data area, merges the data frame files corresponding to the data frame placement areas at the same position between different rows into a large bit width data frame, and caches the large bit width data frame into the L1 cache; The configuration control circuit preloads the data frame file corresponding to the next data frame placement area according to the order of the data frame placement areas in each column, and merges them into a large bit width data frame file and caches them in the L2 cache; After the code stream frame distribution circuit takes the data frame from the L1 cache, the data frame in the L2 cache is sent to the L1 cache, and the configuration control circuit continues to preload the data frame file in the next data frame placement area of ​​the configuration memory.

9. The circuit device for fast configuration of code stream of FPGA according to claim 1, characterized in that: The configuration controller is also provided with a check circuit. When all data frames in the configuration memory are configured, the check circuit reads back the configuration data in the configuration memory and performs a CRC check on the read-back data. The configuration control circuit parses the content of the check information area of ​​the code stream file, and feeds back the content of the check information area to the check circuit. The check circuit performs an XOR operation on the read-back data based on a preset generating polynomial to obtain a check code, compares the check code with the content of the check information area, and outputs a check result.

10. The circuit device for fast configuration of code stream of FPGA according to claim 9, characterized in that: If the verification code is the same as the content of the verification information area, the verification is successful, otherwise the verification fails; The verification circuit feeds back the verification result to the configuration control circuit. If the verification is successful, the configuration control circuit pulls up the DONE signal and INIT_B signal of the FPGA; If the verification fails, the configuration control circuit pulls down the FPGA's DONE signal and INIT_B signal, resets the FPGA, and re-performs the configuration bit stream process.

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