A circuit area optimization method based on AND-XOR majority graphs

Abstract

A circuit area optimization method based on AND-XOR majority graphs is disclosed, relating to a digital logic circuit area optimization approach. This method converts the input integrated circuit into an AIG netlist. Then, based on the AIG equivalent structures of XOR gate nodes and majority logic gate nodes, the AIG netlist is cut and replaced. The AIG netlist is then covered with equivalent gate nodes based on the cutting results. Finally, the AIG netlist is mapped into an AXMIG netlist. This method enables area optimization not limited to two-input AND gates, achieving good optimization results and improving the overall performance of the integrated circuit. Since the circuit area is closely related to the number of mapped gates in the logic netlist, a simpler logic netlist typically corresponds to a smaller circuit area. The goal of circuit area optimization is achieved by simplifying the logic netlist.

Description

Technical Field

[0001] This invention relates to a method for optimizing the area of ​​digital logic circuits, and more particularly to a method for optimizing the area of ​​circuits based on AND-XOR majority graphs. Background Technology

[0002] In integrated circuit design, a crucial step is logic synthesis, which generally consists of three parts: translation, optimization, and mapping. A key performance indicator for logic synthesis optimization is controlling the integrated circuit area. Reducing integrated circuit area has become a critical issue that urgently needs to be addressed in integrated circuit design.

[0003] The performance of integrated circuit area optimization largely depends on electronic design automation (EDA) tools. Existing digital logic circuit synthesis primarily uses Boolean logic with AND, OR, and NOT as its basic operation set, along with derived NAND and NOR logic. These are collectively referred to as traditional Boolean (TB) logic. Most EDA tools are developed from TB logic. Besides TB logic, Boolean functions can also be implemented using Reed-Muller (RM) logic based on AND and XOR. Existing research indicates that RM logic offers better performance in integrated circuit synthesis, significantly improving circuit area, speed, and power consumption for implementing arithmetic circuits such as communication circuits and parity check circuits containing modulo-2 addition and multiplication functions. Furthermore, the synthesized circuit netlist is convenient for testing. In recent years, research on integrated circuit area optimization has mainly focused on TB logic. Methods such as rewriting algorithms based on And Inverter Graphs (AIGs) reduce local graph nodes to decrease overall circuit gate nodes, thus optimizing circuit area. Balancing algorithms treat the AIG as an unoptimized balanced tree and perform balancing optimization, using fundamental properties of logic operations such as associativity, commutativity, and distributivity to compress the number of levels and optimize circuit delay. Refactoring algorithms primarily involve optimizing shared nodes. If a function can be computed using existing nodes in the graph, existing nodes are directly connected and shared without rebuilding new child nodes. Most of these integrated circuit area optimization methods have been integrated into EDA tools (such as MIS and ABC). However, these methods face the problem of limited application scenarios. Tools developed based on TB logic cannot effectively solve the challenge of multi-scenario optimization for various applications, including high performance, low power consumption, and small area requirements.

[0004] Currently, integrated circuit logic synthesis optimization attempts to use TB logic, MR logic, and combinations of multiple logic types for logic synthesis optimization. Among them, AND-XOR-NOT graph (AXIG) logic optimization is a method that combines TB logic and RM logic to optimize circuit area. Most AND-XOR-NOT graphs used are based on Boolean functions. To optimize the circuit area, the two-input XOR gate structure in AIG is represented by a single XOR gate node. One example of a two-input XOR gate structure is shown below. Figure 1 As shown, this structure is a local circuit of the AIG netlist, consisting of three AND gate nodes. The top-level node is called the root node, and the two fan-in nodes below the root node are the left and right child nodes of the root node, respectively. The two inputs of the left and right child nodes are both 'a' and 'b'. Solid lines represent inputs without inverters, and dashed lines represent inputs passing through an inverter. Although this AXIG structure is area-optimized compared to AIG, all nodes in the AIG diagram are limited to two-input AND gates and can only use Boolean functions. The transformation is based on the principle. Even with polarity changes for node fan-in and fan-out, it simply replaces two-input AND gates with two-input NAND, NOR, and OR gates. However, there are limitations in implementing three-input gates and more, resulting in an incomplete representation of XOR gate structures, and the area optimization effect needs further improvement. Furthermore, optimizing the logic functions for AIG requires further research into the representation structure of the logic functions. Summary of the Invention

[0005] This invention addresses the limitations of existing technologies in integrated circuit area optimization by providing a circuit area optimization method based on AND-XOR majority logic gates. By simultaneously introducing two-input nodes (XOR gates) and three-input nodes (MAJ gates), the circuit area is further reduced, thereby improving the overall performance of the integrated circuit. This optimization method can simultaneously achieve area optimization with good results, and when applied to integrated circuits, it can enable the integrated circuits to have higher overall performance.

[0006] To achieve the above-mentioned objectives, the present invention provides the following technical solutions.

[0007] A circuit area optimization method based on AND-XOR majority graphs includes the following steps:

[0008] 1) Convert the digital logic circuit to be processed into a logic netlist structure, that is, use a directed acyclic graph data structure to display it, and convert the integrated circuit into an AIG logic representation.

[0009] 2) Define the XOR structure and majority logic structure in the AIG logic representation. Specifically, propose a two-input node (XOR gate) and a majority logic gate (MAJ) as nodes. The logic function expression of the majority gate is as follows: , can also be expressed as Therefore, it is possible to use Boolean functions simultaneously. as well as The method for Boolean logic optimization in Boolean algebra is to find structural representations in the AIG structure that satisfy both Boolean functions and to use XOR gates and majority logic gates as mapping replacements.

[0010] 3) Cut the AIG graph generated by the integrated circuit into independent AIG substructures, and set appropriate cutting conditions to ensure that all sub-AIG networks satisfy the constraints;

[0011] 4) Replace the AIG logic netlist after cutting, search for AIG structures that are suitable for conversion into sub-XOR gate nodes and MAJ gate nodes, and perform corresponding replacement operations. For sub-AIG structures with more than 3 input variables, perform partial search and replace two-input XOR gates or three-input majority logic gates that meet the conditions.

[0012] 5) Map the converted AXMIG netlist to a circuit and output it. The output circuit is the area-optimized circuit.

[0013] In step 2), the specific steps for defining the XOR structure and majority logic structure in the AIG logical representation can be as follows:

[0014] 2-1) Consider the case of inverted input variables: For an XOR gate where both input and output are the original variables, if there are inverted input variables, the input variables can be the inverted variables of one variable, or the inverted variables of two variables. Four transformation forms can be obtained, and This will result in eight transformation forms. At the same time, the XOR gate corresponds to the AIG structure inside the XOR gate, which corresponds to the case of inverting the input variable of the leaf node of the directed acyclic graph.

[0015] 2-2) Consider the order of input variables: When the order of input variables is different, The input variables can result in two cases, and The input variables can result in six different cases; and finally, when the output variable is inverted, Output variables and The output variables can all produce two different transformation forms;

[0016] 2-3) Consider the case where the output variable is inverted: Under various different input and output conditions, the two-input Boolean logic function... The corresponding AIG graph structure can generate a total of 16 different transformations, and a three-input Boolean logic function The corresponding AIG graph structure can generate a total of 96 different transformations.

[0017] In step 3), the specific steps for cutting the AIG image generated from the integrated circuit can be as follows:

[0018] 3-1) View the AIG diagram as a tree structure, with the top node as the root node and the input nodes of each node as its left and right child nodes. Starting from the root node, the AIG Boolean logic structure is divided into independent AIG substructures. The advantage of this method is that these substructures are independent of each other and do not contain each other.

[0019] 3-2) Reduce the size of the resulting subnets during the cutting process. Set the maximum number of input variables for the resulting sub-AIGs during the cutting process, and ensure that all cuts are made within this feasible range. Once an AIG netlist is cut from top to bottom and all sub-AIG networks satisfy the constraints, the cutting of the entire AIG ends.

[0020] In step 4), the specific steps for replacing the segmented AIG logical netlist can be as follows:

[0021] 4-1) Identification and handling of invalid cuts: After the AIG is cut, the resulting sub-AIG networks are regarded as potential sub-AXMIG candidates; invalid cuts are identified and excluded, that is, sub-AIG networks in which internal nodes are connected not only to the cut's internal nodes but also to external nodes; no further processing is done on invalid cuts.

[0022] 4-2) Perform transformations based on the number of inputs, including:

[0023] 4-2-1) Replacement of two-input and three-input sub-AIGs:

[0024] For a sub-AIG network with two inputs, search its internal structure to determine if it is consistent with the internal structure of the AIG corresponding to the two-input XOR gate node (such as a specific structure composed of AND gates and inverters); if consistent, replace the sub-AIG network with the XOR gate node.

[0025] For a sub-AIG network with 3 inputs, search its internal structure and determine whether it is consistent with the internal structure of the AIG corresponding to the three-input MAJ gate node; if consistent, replace the sub-AIG network with the MAJ gate node.

[0026] 4-2-2) Partial Search and Replace for Multiple Input Sub-AIGs:

[0027] For sub-AIG networks with more than 3 input variables, a partial search is performed to identify whether there is a substructure that satisfies the AIG structure corresponding to a two-input XOR gate or a three-input MAJ gate. If a substructure that satisfies the conditions is found, the corresponding gate is replaced (XOR gate or MAJ gate), and the remaining AND gates are not processed. If no substructure that satisfies the conditions is found in the entire sub-AIG network, the search for that sub-AIG is terminated, and no replacement is performed.

[0028] Compared with existing technologies, the advantages of this invention lie in adding a three-input node type to the AIG diagram, enabling area optimization not limited to two-input AND gates, resulting in good optimization effects and improved overall performance of the integrated circuit. A novel digital logic circuit area optimization method is proposed by using three-input nodes to represent arbitrary logic functions. This involves converting the integrated circuit to be processed into a general AIG netlist, then reorganizing the AIG structure using two-input and three-input nodes, followed by AIG-based area segmentation and replacement of two-input and three-input nodes, successfully transforming the AIG logic netlist into an AXMIG logic netlist. This optimization algorithm utilizes the search for AIG substructures suitable for XOR gate implementation, the equivalent transformation of XOR gates with traditional AND and OR gates, the cutting of AIG, the covering of sub-AIG cuttings, the mapping of XOR gates to suitable covers, and the conversion of AIG into AXMIG suitable for XOR gate mapping. Since the circuit area is closely related to the number of mapping gates in the logic netlist, a simple logic netlist usually corresponds to a smaller circuit area. By simplifying the logic netlist, the purpose of circuit area optimization is achieved, resulting in good optimization effect. When applied to integrated circuits, it can enable integrated circuits to have higher synthesis performance. Experimental results show that the AXMIG obtained by the method of this invention reduces the area by 24.93% and 19.75% compared with existing AIG and AXIG, respectively. Attached Figure Description

[0029] Figure 1 For logical functions The corresponding AIG structure diagram.

[0030] Figure 2 Figure 1 shows a schematic diagram of an AIG structure corresponding to a two-input XOR gate node. Among them, (a) is a schematic diagram of the AIG structure where input a is XORed with input b through a NOT gate; (b) is a schematic diagram of the AIG structure where input a is XORed with input b; and (c) is a schematic diagram of the AIG structure where input a is XORed with input b and then passed through a NOT gate.

[0031] Figure 3Figure 1 shows some AIG structure diagrams corresponding to three-input majority logic gate nodes. Among them, (a) is a schematic diagram of the AIG structure with input a and input b passing through a MAJ gate; (b) is a schematic diagram of the AIG structure with input a passing through a NOT gate and input b passing through a MAJ gate; (c) is a schematic diagram of the AIG structure with input a and input b passing through a MAJ gate and then through a NOT gate.

[0032] Figure 4 These are different replacement methods using the same circuit. Figure (a) shows a schematic diagram of an effective cutting method, Figure (b) shows a schematic diagram of an ineffective cutting method, and Figure (c) shows a schematic diagram of an ineffective cutting method.

[0033] Figure 5 The result shows the area optimization after cutting and covering the circuit using the method proposed in this invention. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of this invention clearer, the following embodiments will be used in conjunction with the accompanying drawings to further illustrate the invention. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. Rather, the invention encompasses any substitutions, modifications, equivalent methods, and solutions made within the spirit and scope of the invention as defined in the claims.

[0035] An embodiment of the present invention provides a circuit area optimization method based on AND-XOR majority graphs, comprising the following steps:

[0036] Step 1: Convert the digital logic circuit to be processed into a logic netlist structure, that is, use a directed acyclic graph data structure to display it, and convert the integrated circuit into an AIG logic representation.

[0037] Step 2: Define the XOR structure and majority logic structure in AIG. Specifically, propose a majority logic gate (MAJ) as a node. The logic function expression of the majority gate is as follows: , can also be expressed as Therefore, it is possible to use Boolean functions simultaneously. as well as The method for Boolean logic optimization in Boolean algebra is to find structural representations in the AIG structure that satisfy both Boolean functions and to use XOR gates and majority logic gates as mapping replacements.

[0038] 2-1: For an XOR gate where both input and output are the original variables, if the input variables include inverted variables, the input variables can be the inverted variables of one variable, the inverted variables of two variables, and so on. Four transformation forms can be obtained, and This will result in eight transformation forms. At the same time, the XOR gate corresponds to the AIG structure inside the XOR gate, which corresponds to the case of inverting the input variable of the leaf node of the directed acyclic graph.

[0039] 2-2: When the order of input variables is different, The input variables can result in two cases, and The input variables can result in six different cases; and finally, when the output variable is inverted, Output variables and The output variables can all produce two different transformation forms.

[0040] 2-3: Two-input Boolean logic functions under various input-output conditions The corresponding AIG graph structure can generate a total of 16 different transformations, and a three-input Boolean logic function The corresponding AIG graph structure can generate a total of 96 different transformations.

[0041] Figure 2 Figure 1 shows a schematic diagram of an AIG structure corresponding to a two-input XOR gate node. Among them, (a) is a schematic diagram of the AIG structure where input a is XORed with input b through a NOT gate; (b) is a schematic diagram of the AIG structure where input a is XORed with input b; and (c) is a schematic diagram of the AIG structure where input a is XORed with input b and then passed through a NOT gate. Figure 3 Figure 1 shows some AIG structure diagrams corresponding to three-input majority logic gate nodes. Among them, (a) is a schematic diagram of the AIG structure with input a and input b passing through a MAJ gate; (b) is a schematic diagram of the AIG structure with input a passing through a NOT gate and input b passing through a MAJ gate; (c) is a schematic diagram of the AIG structure with input a and input b passing through a MAJ gate and then through a NOT gate.

[0042] Step 3: Segment the AIG image generated from the integrated circuit:

[0043] 3-1: View the AIG diagram as a tree structure, with the top node as the root node and the input nodes of each node as its left and right child nodes. Starting from the root node, the AIG Boolean logic structure is divided into independent AIG substructures. The advantage of this method is that these substructures are independent of each other and do not contain each other.

[0044] 3-2: Reduce the size of the resulting subnets during the cutting process. Set the maximum number of input variables for the resulting sub-AIGs during the cutting process, and ensure all cuts are made within this feasible range. The cutting of the entire AIG ends when all sub-AIGs satisfy the constraints after the top-down cutting of an AIG netlist is complete.

[0045] Step 4: Replace the AIG logical netlist:

[0046] 4-1: Identification and Handling of Invalid Cuts: After cutting the AIG, the resulting sub-AIG networks need to be transformed into suitable sub-AXMIGs. In the set of sub-AIGs obtained from the cut, a search is conducted for AIG structures suitable for transformation into sub-XOR gate nodes and MAJ gate nodes. For sub-AIG structures where the fan-out connections exist not only within the cut but also with external nodes, these nodes are considered invalid cuts and are not processed.

[0047] 4-2: Transformation based on the number of inputs: For valid AIG cuts, transformation is performed based on the number of inputs to the sub-AIG netlist.

[0048] 4-2-1: If the number of inputs to the identified sub-AIG netlist is 2, it is necessary to search the internal sub-AIG structure to see if it matches the internal structure of the AIG corresponding to a two-input XOR gate node. The internal structure of this sub-AIG uses AND gates as nodes; dashed lines represent connections through an inverter, while solid lines represent direct connections. If the internal structure of the sub-AIG matches any of the above cases, an XOR gate node is used to directly replace the sub-AIG netlist. Similarly, when the number of inputs to the sub-AIG netlist is 3, it is necessary to search the internal sub-AIG structure to see if it matches the internal structure of the AIG corresponding to a three-input MAJ gate node. If it matches any of the above cases, an MAJ gate node is used to replace it.

[0049] 4-2-2: If the number of input variables in the identified sub-AIG structure that needs to be covered is greater than 3, then an arbitrary search needs to be performed on the sub-AIG structures composed of 2 and 3 input variables. If the AIG structure is found to be the result of a two-input XOR gate or a three-input majority logic gate, then the gate is directly replaced. Other remaining AND gates are not processed. If no internal structure is found that satisfies the requirement of a two-input AND gate or a three-input MAJ gate, then the search for this sub-AIG is terminated.

[0050] Step 5: Map the converted AXMIG netlist to a circuit and output it. The output circuit is the area-optimized circuit.

[0051] Figure 4 These are different replacement methods for using the same circuit.

[0052] A circuit area optimization method based on AND-XOR majority graphs includes the following steps:

[0053] Step 1 Figure 4 The image shows different coverages obtained by different cuts of the AIG netlist for the same circuit. This AIG netlist consists of 10 AND gates, represented by numbers 1 to 10, with five inputs: a, b, c, d, and e. Dashed lines indicate logic inversion, and each square represents a cut. Figure 4 After performing different cuts on node 'a', we can obtain different cuts C1, C2, and C3 for root nodes 1, 5, and 6. First, we determine whether each cut is valid. A valid cut is one whose output is connected to only one internal node or output node. An invalid cut is one whose output is connected to multiple internal nodes. This can be seen in the figure. Figure 4 The cut in figure (a) is a valid cut, but Figure 4 The output of cut C3 in graph (b) is output to two different internal nodes, so Figure 4 The cut in Figure (b) is an invalid cut.

[0054] Step 2: After the cutting is completed, the structure of each valid cut is assessed, and the AIG subgraph is replaced with an AXIMG subgraph. For Figure 4 In Figure (a), the number of input variables for each cut is first determined. For cut C1, there are three input variables. The internal structure of C1 is then searched. If it matches the internal structure of an XOR gate, an XOR gate is used to replace C3. For cuts C2 and C3, there are two inputs each. The internal structure of each cut is searched starting from the root node. If the internal structure matches that of an XOR gate, an XOR gate is used to replace both C2 and C3. This process is repeated for all convertible cuts in the AIG netlist. Each convertible cut in the AIG is replaced with an XOR gate or an XOR gate, transforming the entire AIG netlist into an AXMIG netlist. Figure 5 As shown.

[0055] Step 3: Use AXMIG as a circuit and output it. The output circuit is the optimized circuit.

[0056] To evaluate the performance of the AXMIG structure, it was compared with AIG and AXIG. The implementation was performed in C++ on a PC running CentOS 7.0 with a CPU clock frequency of 3.11 GHz and 4 GB of memory, and tested on a standard MCNC circuit. To ensure consistency of experimental parameters, the input circuit was converted to an AIG network using the ABC tool before implementing the other two structures, ensuring that all structures (AIG, AXIG, AXMIG) started from the same point. The experimental results are shown in Table 1. To simulate signal variations in a real circuit, signal probabilities were randomly generated and assigned to the circuits represented by the three structures, ensuring that the input signal probability remained consistent across all structures. The area of ​​each structure was calculated, and the area optimization values ​​of the AXMIG structure relative to the AIG and AXIG structures were compared.

[0057] Table 1 lists the circuit names and corresponding input / output numbers, the area of ​​the AIG, AXIG, and AXMIG structures, and the area optimization value of AXMIG compared to the AIG and AXIG structures. The last row is the average area improvement of AXMIG compared to the AIG and AXIG structures.

[0058] Table 1. Area comparison of the three structures

[0059]

[0060] Statistical results show that, compared with AIG and AXIG, AXMIG reduces the area by an average of 24.93% and 19.75%, respectively. As shown in Table 1, AXMIG significantly outperforms the AIG and AXIG structures in area improvement, with an average improvement of more than 20%. The average area improvement of AXMIG compared with AXIG is greater than 15%, which is due to the introduction of XOR gates and majority logic gate structures, proving that the method proposed in this invention can achieve a more favorable improvement in circuit area performance.

[0061] Analysis of the data in Table 1 shows that the area of ​​most circuits is significantly reduced, with the area of ​​C5315 circuits being significantly reduced and the average percentage reduction increasing. This indicates that the method of the present invention has advantages in circuit area optimization and can effectively optimize the circuit area.

[0062] Area optimization is crucial in integrated circuit design. This invention significantly reduces circuit area by decreasing the number of logic gates and simplifying the logic netlist, thereby lowering costs and improving production efficiency and reliability. It is suitable for high-performance, low-power integrated circuit designs, particularly in arithmetic circuits such as communication circuits and parity checking circuits, significantly improving circuit area, speed, and power consumption performance. By introducing two-input nodes (XOR gates) and three-input nodes (MAJ gates), this invention expands the functionality of EDA tools, making them more efficient in handling complex logic circuits. This invention can be integrated into existing EDA tools, such as MIS and ABC, to enhance their performance in integrated circuit area optimization, bringing new ideas and technologies to the field of integrated circuit design.

[0063] The above embodiments are merely preferred embodiments of the present invention and should not be considered as limiting the scope of the present invention. All equivalent variations and improvements made within the scope of the present invention should still fall within the patent coverage of the present invention.

Claims

1. A method for circuit area optimization based on XNOR majority graph, characterized in that The method comprises the following steps: 1) converting a digital logic circuit to be processed into a logic netlist structure, that is, using a directed acyclic graph data structure to display, and converting the integrated circuit into an AIG logic representation; 2) defining an exclusive or structure and a majority logic structure in the AIG logic representation, specifically: proposing a majority logic gate MAJ as a node, and the logic function expression of the majority gate is f = a b+b c+a c, or f = a b⊕b c⊕a c; Thus, a method for Boolean logic optimization using both the Boolean functions and f = a b + a c + b c = a b X b c X a c as logical algebra, finding a structural representation in AIG structures that satisfies both Boolean functions, and using XOR gates and majority gates as mapping alternatives; 3) cutting the AIG graph generated by the integrated circuit into independent AIG substructures, and setting a cutting condition to ensure that all sub-AIG networks meet the constraints; The specific steps of cutting the AIG graph generated by the integrated circuit are: 3-1) regarding the AIG graph as a tree structure, the node at the top is the root node, and the input nodes of a node are left and right child nodes, and the AIG Boolean logic structure is cut into independent AIG substructures from the root node; these substructures are independent of each other and do not contain each other; 3-2) reducing the size of the sub-network obtained by cutting during cutting, and setting the maximum number of input variables of the sub-AIG obtained by cutting during cutting, and all cutting is feasible cutting; when the AIG netlist is cut from top to bottom, all sub-AIG networks meet the constraints, and the cutting of the entire AIG is completed; 4) replacing the cut AIG logic netlist, searching for AIG structures suitable for conversion into sub-exclusive or gate nodes and MAJ gate nodes, and performing corresponding replacement operations, and for sub-AIG structures with more than 3 input variables, searching and replacing two-input exclusive or gates or three-input majority logic gates that meet the conditions; 5) mapping the converted AXMIG netlist into a circuit and outputting, and the output circuit is the area-optimized circuit.

2. The method for circuit area optimization based on XNOR majority graph as claimed in claim 1, wherein In step 2), the specific steps of defining an exclusive or structure and a majority logic structure in the AIG logic representation are: 2-1) considering the negation of the input variable: for an exclusive or gate with an input and output of the original variable, in the case of an input variable with a negated variable, the input variable is a negated variable of one variable, two variables, f = a⊕b gets four transformation forms, and f = a b⊕b c⊕a c gets eight transformation forms, at the same time, the exclusive or gate corresponds to the AIG structure inside the exclusive or gate, which is the case of the input variable of the input, that is, the leaf node of the directed acyclic graph; 2-2) considering the order of the input variable: in the case of different input variable orders, the input variable of f = a⊕b gets two cases, and the input variable of f = a b⊕b c⊕a c gets six different cases; and finally in the case of output variable negation, the output variable of f = a⊕b and the output variable of f = a b⊕b c⊕a c produce 2 different transformation forms; 2-3) Consider the negation of the output variable: In various input-output cases, the AIG graph structure corresponding to the two-input Boolean logic function f = a^b generates a total of 16 different transformation cases, while the AIG graph structure corresponding to the three-input Boolean logic function f = a b^b c^a c generates a total of 96 different transformation cases.

3. The method for circuit area optimization based on XNOR majority graph as claimed in claim 1, wherein In step 4), the specific steps for replacing the cut AIG logic netlist are as follows: 4-1) Identification and processing of invalid cuts: After cutting the AIG, the obtained sub-AIG network is regarded as a potential sub-AXMIG candidate; identify and exclude invalid cuts, i.e. those sub-AIG networks whose internal nodes not only have connection relationships within the cut, but also have connection relationships with external nodes; invalid cuts are not processed; 4-2) Conversion according to the number of inputs, including: 4-2-1) Replacement of two-input and three-input sub-AIGs: For a sub-AIG network with 2 inputs, search its internal structure and determine whether it is consistent with the AIG internal structure corresponding to the two-input XOR gate node; if consistent, replace the sub-AIG network with the XOR gate node; For a sub-AIG network with 3 inputs, search its internal structure and determine whether it is consistent with the AIG internal structure corresponding to the three-input MAJ gate node; if consistent, replace the sub-AIG network with the MAJ gate node; 4-2-2) Partial search and replacement of multi-input sub-AIGs: For a sub-AIG network with more than 3 input variables, perform partial search to identify whether there is a substructure that meets the AIG structure corresponding to the two-input XOR gate or the three-input MAJ gate; if a substructure that meets the condition is found, replace the corresponding gate, and the remaining AND gates are not processed; if no substructure that meets the condition is found in the entire sub-AIG network, exit the search of the sub-AIG and do not replace it.

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