Layout optimization method, computer device and storage medium

Abstract

The disclosure provides a layout optimization method, a computer device and a storage medium. The method comprises the following steps: obtaining a chip design layout, determining a target pin of a target module according to the chip design layout; selecting a setting direction of the target pin in the target module, calculating a half perimeter of the target module by using a mixed integer linear programming based on different selection results; and determining the setting direction of the target pin when the half perimeter meets a set condition according to a calculation result, so as to complete layout optimization of the target pin.

Description

Technical Field

[0001] This disclosure relates to the field of chip layout planning technology, and in particular to a layout optimization method, computer equipment, and storage medium. Background Technology

[0002] Electronic Design Automation (EDA) refers to a design method that uses computer-aided design (CAD) software to complete the functional design, synthesis, verification, and physical design (including placement, routing, layout, design rule checking, etc.) of very large-scale integrated circuit (VLSI) chips.

[0003] For large modules, greedy algorithms are generally used to optimize line length layout. However, due to the limitations of greedy algorithms, it is difficult to achieve global optimization in the scenario, which affects the optimization effect and makes it difficult to achieve the expected results.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] In view of this, the present disclosure proposes a layout optimization method, a computer device, and a storage medium to solve or partially solve the above problems.

[0006] In view of the above objectives, firstly, this disclosure provides a layout optimization method, comprising:

[0007] Obtain the chip design layout and determine the target pins of the target module based on the chip design layout;

[0008] The target pin is positioned on the target module, and based on the different selection results, the semi-perimeter of the target module is calculated using mixed integer linear programming.

[0009] Based on the calculation results, the orientation of the target pin is determined when the semi-perimeter meets the set conditions, thereby completing the layout optimization of the target pin.

[0010] In a second aspect, this disclosure provides a computer device including one or more processors, a memory, and one or more programs, wherein the one or more programs are stored in the memory and executed by the one or more processors, the programs including instructions for performing the method according to the first aspect.

[0011] In a third aspect, the present disclosure provides a non-transitory computer-readable storage medium containing a computer program which, when executed by one or more processors, causes the processors to perform the method of the first aspect.

[0012] From the above, it can be seen that the present disclosure provides a layout optimization method, a computer device and a storage medium. The method comprises: obtaining a chip design layout, determining a target pin of a target module according to the chip design layout; selecting a setting direction of the target pin in the target module, and calculating a half perimeter of the target module based on different selection results by using a mixed integer linear programming; and determining the setting direction of the target pin according to a calculation result when the half perimeter meets a set condition, so as to complete layout optimization of the target pin. In the optimization process of the target module, the present disclosure selects the setting position of the target pin of the target module, and calculates the half perimeter of the wiring based on different selections, so that a relationship formula between the setting position of all target pins and the bus length can be obtained in the modeling process. Then, the relationship formula is solved by using a mixed integer linear programming solver, so that the global optimal solution of the layout direction of all modules can be obtained. This algorithm can determine the layout direction of multiple modules with complex interconnection relationship at the same time, so that the wire length optimization can be considered from the global perspective, and finally a layout scheme with better global optimization effect is obtained, thereby improving the overall optimization effect. BRIEF DESCRIPTION OF DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the related art, the drawings needed to be used in the embodiments or the related art description will be briefly introduced. Obviously, the drawings in the following description are only embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor.

[0014] Figure 1 A hardware structure schematic diagram of an exemplary computer device provided by the embodiments of the present disclosure is shown.

[0015] Figure 2 A basic structure schematic diagram of an EDA tool provided by the embodiments of the present disclosure is shown.

[0016] Figure 3 A schematic diagram of a basic execution flow of a computing command of an EDA tool provided by the embodiments of the present disclosure is shown.

[0017] Figure 4 A flow schematic diagram of an exemplary method provided by the embodiments of the present disclosure is shown.

[0018] Figure 5 A schematic diagram of a target module provided by the embodiments of the present disclosure is shown. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this specification clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0020] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element, object, or method step preceding the term covers the element, object, or method step listed after the term and its equivalents, but does not exclude other elements, objects, or method steps. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0021] Figure 1 A schematic diagram of the structure of a computer device 100 provided in an embodiment of this disclosure is shown. The computer device 100 may include: a processor 102, a memory 104, a network interface 106, a peripheral interface 108, and a bus 110. The processor 102, memory 104, network interface 106, and peripheral interface 108 are interconnected internally via the bus 110.

[0022] Processor 102 may be a central processing unit (CPU), image processor, neural network processor (NPU), microcontroller (MCU), programmable logic device, digital signal processor (DSP), application-specific integrated circuit (ASIC), or one or more integrated circuits. Processor 102 can be used to perform functions related to the techniques described in this disclosure. In some embodiments, processor 102 may further include multiple sub-processors integrated as a single logic component, such as... Figure 1 As shown, processor 102 may include sub-processor a102a, sub-processor b102b, and sub-processor c102c, etc.

[0023] Memory 104 can be configured to store data (e.g., instruction sets, computer code, intermediate data, etc.). For example, as... Figure 1As shown, the stored data may include program instructions (e.g., program instructions for implementing the technical solutions of this disclosure) and data to be processed. The processor 102 may also access the stored program instructions and data, and execute the program instructions to operate on the data to be processed. The memory 104 may include a volatile storage device or a non-volatile storage device. In some embodiments, the memory 104 may include random access memory (RAM), read-only memory (ROM), optical disk, magnetic disk, hard disk, solid-state drive (SSD), flash memory, memory stick, etc.

[0024] Network interface 106 can be configured to provide communication with other external devices to computer device 100 via a network. This network can be any wired or wireless network capable of transmitting and receiving data. For example, the network can be a wired network, a local wireless network (e.g., Bluetooth, WiFi, Near Field Communication (NFC), etc.), a cellular network, the Internet, or a combination thereof. It is understood that the type of network is not limited to the specific examples described above. In some embodiments, network interface 106 may include any combination of any number of network interface controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, etc.

[0025] The peripheral interface 108 can be configured to connect the computer device 100 to one or more peripheral devices to enable information input and output. For example, peripheral devices may include input devices such as keyboards, mice, touchpads, touch screens, microphones, and various sensors, as well as output devices such as displays, speakers, vibrators, and indicator lights.

[0026] Bus 110 can be configured to transfer information between various components of computer device 100 (e.g., processor 102, memory 104, network interface 106, and peripheral interface 108), such as internal buses (e.g., processor-memory bus), external buses (USB port, PCI-E bus), etc.

[0027] It should be noted that although the above-described device only shows the processor 102, memory 104, network interface 106, peripheral interface 108, and bus 110, in specific implementations, the device may also include other components necessary for normal operation. Furthermore, those skilled in the art will understand that the above-described device may only include the components necessary for implementing the embodiments of this disclosure, and not necessarily all the components shown in the figures.

[0028] Figure 2 A schematic diagram of the basic structure of an EDA tool 200 according to an embodiment of the present disclosure is shown.

[0029] like Figure 2As shown, the area above the dashed line represents the user interface; the area below the dashed line represents EDA tool 200. EDA tool 200 can be... Figure 1 The computer device 100 shown is implemented. In some embodiments, the EDA tool 200 can be implemented as EDA software. More specifically, the EDA tool 200 can be software for placement and routing based on chip design. The EDA tool 200 may include a Tcl command module 204 (or a graphical / window interface module), various calculation modules (e.g., Place calculation module 206, Route calculation module 208, Optimization calculation module 210, etc.), and a database system 212. The user 202 can operate the EDA tool 200 by entering relevant commands in the Tcl command module 204 (or the graphical / window interface module).

[0030] The Tcl command module 204 primarily functions as a message or command transmission module. It can read instructions input by the user 202 into the EDA tool 200 and, based on the specific content of the instructions, allocate and transmit them to the corresponding computing modules for execution of specific tasks.

[0031] Depending on the computational task, the computational modules can be divided into, for example, Place computation module 206, Route computation module 208, and Optimization computation module 210. Place computation module 206 can calculate a reasonable placement for all components, Route computation module 208 can calculate a reasonable wiring connection method between the components, and Optimization computation module 210 can optimize the placement and wiring connection methods between the components. The computational processes of these modules can be performed, for example, Figure 1 It is carried out in the processor 102.

[0032] Database system 212 can be used to completely and comprehensively record and store all information (such as location, orientation, size, structure, wire connection method, etc.) of the simulated or designed chip. This information, for example, can be stored in... Figure 1 In memory 104.

[0033] Figure 3 The basic execution flow 300 of a computation command of an EDA tool 200 according to an embodiment of this disclosure is shown. For example... Figure 3As shown, in step 302, user 202 can issue a command (e.g., the do_place command) to EDA tool 200 through the command interface or graphical user interface (GUI) provided by Tcl command module 204. Then, in step 304, Tcl command module 204 parses this command and distributes it to the corresponding calculation module (e.g., Place calculation module 206). In step 306, each calculation module performs its specific calculations. During this process, as shown in step 308, each calculation module needs to (frequently and repeatedly) retrieve data from database system 212 for calculations. After the calculations are completed, as shown in step 310, each calculation module can write the calculation results to database system 212 and return the results to Tcl command module 204. In step 312, Tcl command module 204 returns the calculation results to user 202 through the command interface or graphical user interface (GUI), and the processing of a calculation command by EDA tool 200 ends. In step 314, the user can evaluate the calculation results and then determine the next step.

[0034] As described in the background section, some application scenarios in this embodiment require optimization of the module layout direction in the digital backend module layout. In some embodiments, a greedy optimization algorithm is mainly used, with the optimization target being line length. The greedy optimization algorithm first determines a reasonable optimization priority, and then optimizes the module layout direction sequentially according to this priority. The determination method is as follows: based on the initial layout direction, mirror flips are attempted in both the horizontal and vertical directions, with the horizontal and vertical flips considered as two independent actions. During each flip, the total line length of all lines connected to this module is compared before and after the flip; this line length is half the circumference. If the line length after the flip is less than before, the flip is performed; otherwise, the flip is abandoned.

[0035] It can be seen that the greedy algorithm can only evaluate the benefit of the current small step, finding a local optimum, but cannot perform global optimization to find the global optimum. In specific scenarios, modules are often large in size, and the layout orientation of a module greatly affects the length of every line connected to that module. These line lengths are crucial evaluation criteria when other modules are flipped. Different modules may have directly connected lines. When a target module is flipped, the lines connected to that module may connect to modules that have not been flipped, and the layout orientation of these modules is not optimal, or may even be random. Even if all the modules connected by these lines have been flipped by this greedy algorithm, the layout orientation of these modules cannot be guaranteed to be optimal. Therefore, the line length evaluation criterion on which the target module's flip depends is also inaccurate. In addition, the final result obtained by the greedy algorithm is highly dependent on the initial layout orientation.

[0036] Therefore, the greedy algorithm cannot guarantee a globally optimal solution or the optimal wire length, ultimately leading to more severe routing congestion and more timing violations in the design. In the design of a specific netlist, the locally optimal solution obtained by the greedy algorithm may differ significantly from the globally optimal solution.

[0037] In light of the above-mentioned practical situation, this disclosure provides a layout optimization method. During the optimization process of the target module, the method selects the placement positions of the target pins and performs semi-circularity statistics on the traces based on different selections. This allows for the generation of a formula relating all target pin placement positions to the bus length during modeling. Subsequently, a mixed-integer linear programming solver is used to solve this formula, thereby obtaining the globally optimal solution for the layout orientation of all modules. This algorithm simultaneously determines the layout orientation of multiple modules with complex interconnections, enabling global optimization of trace lengths and ultimately resulting in a layout scheme with better global optimization effects, thus improving the overall optimization performance.

[0038] Figure 4 A flowchart illustrating an exemplary method 400 provided in an embodiment of this disclosure is shown. Method 400 can be... Figure 1 The computer device 100 is implemented and can be implemented as Figure 2 This is part of the functionality of EDA tools 200. For example... Figure 4 As shown, the method 400 may further include the following steps.

[0039] Step 402: Obtain the chip design layout and determine the target pins of the target module based on the chip design layout.

[0040] Generally, a chip design layout includes every layer of the chip's structure, specifically the transistor placement, wiring, traces, and inter-layer connections of vias, etc. Based on this chip design layout, chip manufacturing service providers can directly run and mass-produce the chips. Furthermore, the chip design layout itself is drawn step by step, with various optimizations accompanying it, ultimately completing the entire chip design layout. In the early stages of the chip design layout, it may only indicate the functional information of the layers, such as a certain layer being a wiring layer, another layer being an insulating layer, etc.; or it may only set up each functional component, indicating the location, size, and other information of each functional component. Then, using EDA tools, etc., step-by-step design and optimization are carried out, finally forming a complete version of the chip design layout. Here, the component (inst) can be a standard processing unit, module or hard core, input / output terminal, register, etc. in the chip.

[0041] In this embodiment, the target module is a structure within a chip used to implement a specific function. A target module may contain numerous components that work together to perform a specific function. These components are then packaged together to form a large module within the chip, such as a cache or memory module. To achieve the corresponding function, the module needs to connect to other modules, components, and / or structures via pins extending from it. Therefore, the target pins can be these signal transmission pins extending from the module. Target pins are used to establish connections between target modules or between a target module and components (standard cells, etc.). During layout optimization, the connection relationships of the target pins are generally determined, but their placement positions on the target module are not yet determined. Therefore, it is necessary to select the placement positions of the target pins and optimize the layout of relevant attributes (such as line length).

[0042] It should be noted that the optimization in this embodiment can be a holistic optimization process targeting all target modules in the chip design layout; or it can be a local optimization process targeting a portion of target modules in a certain area of ​​the chip design layout, such as dividing the chip design layout into several parts and then performing local layout optimization on each part.

[0043] Step 404: Select the orientation of the target pin in the target module. Based on different selection results, calculate the half-perimeter of the target module using mixed integer linear programming.

[0044] In this scenario, the placement of a target pin is relatively fixed, but there is still some room for choice, which may lead to layout optimization when placing the target module. In one example, the pin placement of the target module is generally fixed in one extension direction, such as... Figure 5As shown, pins can be arranged either along the vertical (top-bottom) direction of the target module, i.e., on sides 501 or 502 of the target module, or along the horizontal (left-right) direction of the target module, i.e., on sides 503 or 504 of the target module. In this optimization, pins located on sides 501 or 502 cannot be adjusted to sides 503 or 504 through optimization, so the selection of the target pin is relatively fixed. However, considering the aforementioned choice between placing the pin on side 501 or side 502, and since pins are generally symmetrically arranged (assuming pins are arranged along side 501, the third pin from the top and the third pin from the bottom are symmetrical, and their functions are similar), the pin's location—whether on the top or bottom of side 501—can also be chosen. This creates two possible choices for the target pin in two directions: whether to place it on the left or right side, and whether to place it on the top or bottom side. For the target module with the pin placed on edge 501 or 502, this means choosing whether to place the target pin on edge 501 or 502, and whether to place it on the top or bottom side of edge 501 or 502. In this embodiment, although there is room for choice in the placement of the target pin, it is relatively fixed. Therefore, when calculating the half-circumference of the line length, one direction is unlikely to affect the choice in the other direction (different choices in the other direction have roughly the same impact on the choice in this direction). Thus, the two directions can be completely decoupled for independent selection and optimization.

[0045] In this step, setting the orientation can be understood as selecting the location in a certain direction mentioned above. Figure 5 Taking the example of setting the pins on either side 501 or side 502 in the target module, the selection of side 501 or side 502 can be defined as the first direction, and the selection of the upper or lower side of side 501 or side 502 can be defined as the second direction. It can be seen that the first and second directions are extensions of the central axes of the target module in two directions, and the selection is a symmetrical mirror selection along the corresponding central axes. That is, in some embodiments, the setting orientation includes at least setting along the first direction and / or setting along the second direction. During optimization, different directions are optimized independently, wherein the first direction and the second direction intersect each other.

[0046] Subsequently, for any direction, since there may only be two options for the target pin's orientation, these two options can be represented by 0 and 1. Finally, for the scenario in the aforementioned embodiment, x can be set as the first direction selection, and y as the second direction selection. Then x(0) can represent setting at edge 501, x(1) can represent setting at edge 502, y(0) can represent setting on the upper side, and y(1) can represent setting on the lower side. This allows for the representation of all target pin orientations, resulting in different selection results. Then, based on the different selection results, the half-circumference of the connection line to the target pin can be calculated, and after integration, the bus length formula can be obtained.

[0047] Finally, mixed-integer linear programming (MILP) can be used to solve the bus length formula. MILP refers to a mathematical programming problem where the objective function and constraints are linear, and some decision variables are restricted to integers. As mentioned earlier, for independent calculations in a certain direction, each target pin has only two choices: 0 or 1. Therefore, MILP can simultaneously determine the layout direction of multiple interconnected modules during the calculation process, thus obtaining an optimal line length solution from a global perspective—something that greedy algorithms cannot achieve with local optima.

[0048] In some embodiments, since a chip may contain a large number of target modules, directly solving the problem using mixed-integer linear programming may result in a large computational load and poor efficiency. Therefore, solution space reduction optimization can be performed before selecting the orientation of the target pins. For different target modules in the chip, they can be screened based on their connection relationships. For example, if a target module is not connected to other target modules but only to standard cell library elements, that is, a trace connects to only one target module that can be optimized, since the standard cell library elements are considered to have fixed positions and orientations, it is possible to directly determine which of the two different choices in the aforementioned two different directions has a better half-perimeter. Combining the two directions directly yields the setting method of the target module, which is the final layout optimization result. That is, in some embodiments, the target module includes a first target module; before selecting the orientation of the target pins in the target module, the method further includes: in response to the first target module not being connected to other target modules, calculating the half-perimeter of the target pins of the first target module in different setting orientations, and determining the layout optimization result of the first target module based on the calculation results. The first target module is the aforementioned target module that is only connected to standard cell library components.

[0049] Correspondingly, if a trace connects more than two target modules, meaning the target modules are connected, they will affect each other when calculating the trace half-perimeter. In this case, for any target module, we can still calculate the longest and shortest trace lengths (half-perimeter) achievable by each of the two choices (in one direction). If the longest trace length of the first choice is shorter than the shortest trace length of the second choice, then the layout optimization result of any target module can be directly considered to be the first choice. That is, in some embodiments, the target module includes at least two second target modules; before selecting the setting orientation of the target pin in the target module, the method further includes: in response to the at least two second target modules being interconnected, selecting any second target module, adjusting the setting orientation of the target pins of the other second target modules, and statistically analyzing the longest and shortest half-circumference of the target pin of any second target module in different setting orientations; in response to the longest half-circumference of the target pin of any second target module in any setting orientation being less than the shortest half-circumference in another setting orientation, determining that any setting orientation is the layout optimization result of the target pin of any second target module. Here, the second target module refers to at least two target modules that influence each other in the aforementioned trace; statistically analyzing the longest and shortest half-circumference of the target pin of any second target module in different setting orientations corresponds to the aforementioned statistical analysis of the longest line length (half-circumference) and shortest line length (half-circumference) achievable for each of the two selections (in one direction), to... Figure 5 Taking the current second target module as an example, its pins are set on edge 501 or edge 502. For the pins set on edge 501, the half-perimeters of the pins of other second target modules in different side scenarios are counted to form the longest and shortest half-perimeters on the edge 501 side. The same applies to the edge 502 side. Then the longest half-perimeter on both sides is compared with the shortest half-perimeter on the other side to determine the length.

[0050] Furthermore, in a scenario where a trace contains multiple target modules, each target module is not initially fixed. Due to mutual influence, some target modules may be undetermined. However, if a target module is fixed as described above, it may also affect other target modules, causing them to be fixed as well. Thus, after a target module is fixed, the longest and shortest half-perimeters of the other target modules on the trace can be recalculated and compared. This allows for iterative processing, ultimately determining all target modules on the entire trace. That is, in some embodiments, after determining that any setting orientation is the layout optimization result of the target pin of any second target module, the method further includes: based on the determined target pin setting orientation of any second target module, re-statistically comparing the longest and shortest half-perimeters of the target pins of other second target modules at different setting orientations.

[0051] By using the above method, the size of the computational solution space can be reduced before performing mixed-integer linear programming, allowing some target modules to directly determine their layout optimization results and not participate in the calculation. This reduces the amount of computation at the input, greatly reduces the solution space, significantly shortens the running time, and improves overall efficiency.

[0052] Subsequently, target modules that cannot be filtered out through the above methods, such as those in the aforementioned scenario where the longest half-perimeter of one selection cannot be less than the shortest half-perimeter of another selection, will be used as input for mixed-integer linear programming (MILM) calculations. However, when using MILM for calculations, its high algorithmic complexity can lead to excessively long runtimes on complex problems, impacting efficiency. Therefore, adjustments can be made to the calculation process or scope to optimize the MILM calculation performance. Specifically, in chips, target modules are typically connected via wires. However, different functions may not be interconnected, resulting in multiple sets of target modules entering the MILM calculation stage without any connection between them. Therefore, the initial calculation task can be considered the overall task. Then, unconnected target modules are separated, breaking the overall task down into sub-tasks. Each sub-task is calculated independently, allowing for parallel and independent computation between different sub-tasks, while also enabling synchronous processing by different processing units, thus improving efficiency. That is, in some embodiments, the chip design layout includes multiple target modules; the calculation of the half-perimeter of the target modules is regarded as the total task; the calculation of the half-perimeter of the target modules using mixed integer linear programming includes: in response to the fact that the multiple target modules include at least two sets of unconnected target modules, the total task is split according to the at least two sets of unconnected target modules to form at least two corresponding independent sub-tasks to calculate the half-perimeter separately.

[0053] Furthermore, to further improve processing efficiency, the amount of data to be calculated for the total task (if not divided into sub-tasks) or any sub-task can be limited. This means limiting the number of target modules corresponding to the task, ensuring that the final amount of data involved in the calculation is at most a set threshold. For example, if the threshold is set to 3, and the current task has 5 target modules, then the number can be reduced to 3 through certain means before calculation. The selection method can draw on the aforementioned process of calculating and comparing the longest and shortest half-perimeters. After this comparison, the longest half-perimeter of one side of the target module will generally be higher than the shortest half-perimeter of the other side. However, the degree of this difference varies among different target modules. For example, if module A's longest half-perimeter on the first side is only 1 unit higher than the shortest half-perimeter on the second side (assuming module A's performance in another set of comparisons is worse than this set, and the same applies to module B), while module B's longest half-perimeter on the first side is 5 units higher than the shortest half-perimeter on the second side, then module A's optimization result on the first side is considered to be more probable than module B's. Based on this, the target modules in the task can be sorted and removed from highest to lowest probabilities until the number of remaining target modules meets a set threshold. For the removed target modules, the setting method with the higher probability can be selected to form the final optimized layout result. That is, in some embodiments, the target module included in the total task or any sub-task is referred to as the third target module; the method further includes: in response to the number of the third target modules being greater than a preset threshold, calculating the longest half-circumference and the shortest half-circumference of the target pin of the third target module in different setting orientations, and statistically analyzing the calculation results; filtering and removing the third target modules according to the statistical results, so that the number of the third target modules is reduced to the preset threshold.

[0054] Furthermore, due to factors such as the mutual influence between connections, the above-mentioned screening and removal methods may not achieve the expected results in some scenarios. Therefore, a more accurate evaluation of the target modules is needed. In some embodiments, the longest and shortest half-perimeters can be compared first, and then the average of the longest and shortest half-perimeters is taken as the expected half-perimeter. The absolute value of the difference between the expected half-perimeters in the two directions is the expected return. The difference between the longest and shortest half-perimeters is the risk factor. The reduction in the number of target modules resulting from fixing the direction of the shorter half-perimeter in the direction of the shorter expected half-perimeter (since fixing a target module, as mentioned above, may also fix other target modules, resulting in different reductions for different target modules) is the simplification return. Finally, the expected return × simplification return ÷ risk factor = simplification factor. Modules with larger simplification factors are selected and fixed direction sequentially until the number of integer variables is reduced to the expected range. That is, in some embodiments, the step of filtering and removing the third target module based on statistical results includes: statistically analyzing the average and difference of the longest and shortest half-perimeters of the target pins of any third target module in different setting orientations; taking the change in the number caused by fixing the target pins of any third target module as the gain; and filtering and removing the third target modules based on the average, the difference, and the gain. Here, the average corresponds to the aforementioned expected half-perimeter, through which the expected gain can be obtained; the difference corresponds to the aforementioned risk factor; and the gain corresponds to the aforementioned simplified gain. Ultimately, to ensure tolerable runtime, a certain amount of solution quality can be sacrificed in the above manner, ultimately achieving a balance between result quality and runtime.

[0055] Step 406: Determine the orientation of the target pin when the semi-perimeter meets the set conditions based on the calculation results, thereby completing the layout optimization of the target pin.

[0056] In this step, the setting condition can be to select the scheme with the shortest half-perimeter. Then, based on the aforementioned results, the setting position of the target pin of the target module with the globally optimal half-perimeter can be obtained. Finally, this setting position can be used as the final layout optimization result.

[0057] Finally, the resulting layout optimization results can be output. These results can be sent to downstream EDA processes for further processing, or the chip design layout can be adjusted directly based on the optimization results. Of course, the output methods for the layout optimization results can also include various methods, such as displaying the results on a corresponding device to provide feedback to the operator. In other embodiments, the output methods for the layout optimization results are not limited to display; they can also be used to store, display, use, or further process the results. The specific output method for the layout optimization results can be flexibly selected according to different application scenarios and implementation needs.

[0058] Specifically, for example, in the application scenario where the method of this embodiment is executed on a single device, the layout optimization result can be directly output on the display component (monitor, projector, etc.) of the current device, so that the operator of the current device can directly see the content of the layout optimization result on the display component.

[0059] For example, in application scenarios where the method of this embodiment is executed on a system composed of multiple devices, the layout optimization results can be sent to other preset devices within the system as receivers, i.e., synchronization terminals, via any data communication method (wired connection, NFC, Bluetooth, Wi-Fi, cellular network, etc.), so that the synchronization terminals can perform subsequent processing. Optionally, the synchronization terminal can be a preset server, which is generally located in the cloud and serves as a data processing and storage center, capable of storing and distributing the layout optimization results; wherein, the receivers of the distribution are terminal devices, and the owners or operators of these terminal devices can be managers, designers, maintenance personnel, etc., at various stages of chip design.

[0060] For example, in the application scenario where the method of this embodiment is executed on a system composed of multiple devices, the layout optimization results can be directly sent to a preset terminal device through any data communication method. The terminal device can be one or more of the devices listed in the preceding paragraphs.

[0061] As can be seen from the above, the embodiments of this disclosure provide a layout optimization method. The method includes: acquiring a chip design layout; determining target pins of a target module based on the chip design layout; selecting the placement orientation of the target pins in the target module; calculating the half-perimeter of the target module using mixed-integer linear programming based on different selection results; and determining the placement orientation of the target pins when the half-perimeter meets set conditions based on the calculation results, thereby completing the layout optimization of the target pins. This disclosure, by selecting the placement position of the target pins of the target module during the optimization process and statistically analyzing the half-perimeter of the traces based on different selections, allows for the generation of a formula relating all target pin placement positions to the bus length during modeling. Then, a mixed-integer linear programming solver is used to solve this formula, thereby obtaining the globally optimal solution for the layout orientation of all modules. This algorithm simultaneously determines the layout orientation of multiple modules with complex interconnections, allowing for global consideration of trace length optimization and ultimately obtaining a layout scheme with better global optimization effect, thus improving the overall optimization effect.

[0062] It should be noted that the method of this disclosure embodiment can be executed by a single device, such as a computer or server. The method of this disclosure embodiment can also be applied in a distributed scenario, where multiple devices cooperate to complete the task. In such a distributed scenario, one of these devices may execute only one or more steps of the method of this disclosure embodiment, and the multiple devices will interact with each other to complete the method described.

[0063] It should be noted that the above description describes specific embodiments of this disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired results. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0064] Based on the same inventive concept, corresponding to any of the above embodiments, this disclosure also provides a non-volatile computer-readable storage medium containing a computer program, wherein the non-volatile computer-readable storage medium containing the computer program stores computer instructions for causing the computer to perform the method 400 as described in any of the above embodiments.

[0065] The computer-readable storage medium of this embodiment includes permanent and non-permanent, removable and non-removable media that can be used to store information by any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic tape / disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device.

[0066] The computer instructions stored in the storage medium of the above embodiments are used to cause the computer to perform the method 400 as described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0067] Based on the same inventive concept, corresponding to the method 400 of any of the above embodiments, this disclosure also provides a computer program product, which includes a computer program. In some embodiments, the computer program is executable by one or more processors to cause the processors to perform the method 400. Corresponding to the execution entity for each step in each embodiment of method 400, the processor executing the corresponding step may belong to the corresponding execution entity.

[0068] The computer program product of the above embodiments is used to cause the processor to execute the method 400 as described in any of the above embodiments, and has the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0069] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this disclosure is limited to these examples; within the framework of this disclosure, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this disclosure as described above, which are not provided in detail for the sake of brevity.

[0070] Additionally, to simplify the description and discussion, and to avoid obscuring the embodiments of this disclosure, the provided drawings may or may not show well-known power / ground connections to integrated circuit (IC) chips and other components. Furthermore, the apparatus may be shown in block diagram form to avoid obscuring the embodiments of this disclosure, and this also takes into account the fact that the details of implementation of these block diagram apparatuses are highly dependent on the platform on which the embodiments of this disclosure will be implemented (i.e., these details should be fully understood by those skilled in the art). While specific details (e.g., circuits) have been set forth to describe exemplary embodiments of this disclosure, it will be apparent to those skilled in the art that the embodiments of this disclosure can be implemented without these specific details or with variations thereof. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0071] Although this disclosure has been described in conjunction with specific embodiments thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0072] This disclosure is intended to cover all such substitutions, modifications, and variations falling within the broad scope of the above embodiments. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A layout optimization method, characterized in that, include: Obtain the chip design layout and determine the target pins of the target module based on the chip design layout; The orientation of the target pin on the target module is selected, and based on different selection results, the semi-perimeter of the target module is calculated using mixed integer linear programming; wherein, the orientation is the position of the target pin on the target module. The orientation of the target pin is determined based on the calculation results when the semi-perimeter meets the set conditions, thereby completing the layout optimization of the target pin; The target module includes at least two second target modules; Before selecting the setting orientation of the target pin in the target module, the method further includes: In response to the interconnection of the at least two second target modules, select any second target module, adjust the setting orientation of the target pins of the other second target modules, and count the longest and shortest half-circumference of the target pins of any second target module in different setting orientations. In response to the fact that the longest half-perimeter of the target pin of any second target module in any setting orientation is less than the shortest half-perimeter in another setting orientation, the setting orientation is determined to be the layout optimization result of the target pin of any second target module.

2. The method according to claim 1, characterized in that, The target module includes a first target module; Before selecting the setting orientation of the target pin in the target module, the method further includes: In response to the first target module not being connected to other target modules, the half-perimeter of the target pin of the first target module in different setting orientations is calculated, and the layout optimization result of the first target module is determined based on the calculation result.

3. The method according to claim 1, characterized in that, After determining that any setting orientation is the layout optimization result of the target pin of any second target module, the method further includes: Based on the determined target pin setting orientation of any of the second target modules, the longest and shortest half-circumferences of the target pins of other second target modules at different setting orientations are re-statistically counted and compared.

4. The method according to claim 1, characterized in that, The chip design layout includes multiple target modules; calculating the half-perimeter of each target module is considered the total task. The calculation of the semi-perimeter of the target module using mixed-integer linear programming includes: In response to the fact that the plurality of target modules includes at least two sets of unconnected target modules, the total task is split into at least two corresponding independent sub-tasks, each of which calculates the half perimeter separately.

5. The method according to claim 4, characterized in that, The target module contained in the overall task or any sub-task is referred to as the third target module; The method further includes: In response to the number of the third target modules being greater than a preset threshold, the longest and shortest half-circumferences of the target pins of the third target modules in different settings are calculated, and the calculation results are statistically analyzed. Based on the statistical results, the third target module is filtered and removed, so that the number of the third target module is reduced to the preset threshold.

6. The method according to claim 5, characterized in that, The step of filtering and removing the third target module based on statistical results includes: The average value and difference of the longest and shortest half-circumference of the target pin of any third target module under different setting orientations are statistically analyzed. The change in the number caused by fixing the target pin of any third target module is taken as the gain. The third target modules are screened and removed based on the average value, the difference and the gain.

7. The method according to claim 1, characterized in that, The setting orientation includes setting along a first direction and / or setting along a second direction. During optimization, different directions are optimized independently, wherein the first direction and the second direction intersect each other.

8. A computer device, characterized in that, It includes one or more processors, memory; and one or more programs, wherein the one or more programs are stored in the memory and executed by the one or more processors, the programs including instructions for performing the method according to any one of claims 1 to 7.

9. A non-volatile computer-readable storage medium containing a computer program, characterized in that, When the computer program is executed by one or more processors, the processors perform the method of any one of claims 1 to 7.

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