Compiling method for brain-like chip

Abstract

The invention discloses a brain-like chip-oriented compiling method, and belongs to the field of brain-like computing chip compiling, and the method comprises the steps: dividing each layer of a spiking neural network into a neuron group, and extracting variable information related to the internal operation state or parameter of a brain-like chip from the spiking neural network through a neuron group data module; generating core configuration of a brain-like chip through a core configuration module according to neuron behaviors and operation parameters of the spiking neural network and variable information; dividing a neuron group of the spiking neural network, mapping the neuron group to a brain-like chip core of the brain-like chip, and taking the neuron group as a physical neuron group; establishing connection information for a physical neuron group in the brain-like chip according to the spiking neural network connection relationship; and serializing the operation core configuration and connection information to generate an executable file, so that systematized and all-around compiling of the brain-like chip is realized.

Description

Technical Field

[0001] The present invention belongs to the technical field of pulse neural network compilation, and in particular relates to a compilation method for brain-like chips. Background Art

[0002] Brain-like computing chips are chips developed based on the working mechanism of the brain. They draw on the structure and information processing methods of biological neural networks to provide hardware support for the development of brain-like intelligence. Traditional computing architectures have limitations such as the separation of storage and computing and lack of adaptability, which leads to low energy efficiency and difficulty in coping with complex and changing environments and tasks. Brain-like computing chips can break through these limitations, achieve storage and computing integration, improve energy efficiency, and have stronger adaptability. In the era of big data and artificial intelligence, a large amount of unstructured data requires more effective processing methods. Brain-like computing chips can draw on brain neural mechanisms and cognitive mechanisms to better process these data, improve the machine's ability to understand data, provide a more suitable operating environment for artificial intelligence algorithms, accelerate the training and reasoning process of neural networks, and improve the performance of artificial intelligence systems.

[0003] Brain-like chips have a multi-core distributed architecture, using neurons and synaptic structures to simulate spiking neural networks, while relying on a time-step mechanism to ensure that there is no deviation in the pulses at each time step. In terms of multi-core distributed architecture, brain-like chips usually integrate a large number of processing cores, which work together and are distributed. This architecture can achieve efficient parallel processing, greatly improving the chip's computing speed and processing capabilities, and can handle complex and diverse data tasks at the same time. Neurons in brain-like computing chips are responsible for information processing and transmission. They have certain thresholds and excitation mechanisms like biological neurons. They use axons and dendrites to simulate the connection relationship between neurons and are responsible for transmitting information between neurons. In terms of the time-step mechanism, brain-like chips have strict requirements, and the pulses of each time step must correspond and cannot deviate. During the operation of the chip, time is divided into discrete time steps. In each time step, neurons will update their status and transmit information based on the received pulse signal. This process must be precisely synchronized to ensure the accuracy of the pulses in each time step in time and logic. Only in this way can the stable operation and correct function realization of the entire chip system be guaranteed.

[0004] Therefore, there are many challenges in deploying the spiking neural network model to hardware platforms such as neuromorphic chips. How to build a general and efficient compilation system that can effectively convert and optimize the spiking neural network model according to the characteristics of the chip architecture has become one of the key factors restricting the development of brain-like computing. Existing compilation technologies often have deficiencies in model adaptability, the degree of automation of the compilation process, and support for user-defined requirements, making it difficult to meet the increasingly complex needs of brain-like computing application scenarios. For example, the spiking neural network model is written by different programming frameworks, and different programming frameworks have different treatments for time steps. Some frameworks have no delayed synapses and will update the entire network within one time step; due to hardware limitations, brain-like chips have delayed synapses and will calculate the pulses arriving at the neurons within one time step. Logically, the pulses are propagated layer by layer along the network. Therefore, it is necessary to design a compilation framework for neuromorphic chips with delayed synapses. This method provides a convenient, easy-to-use, flexible and variable compilation method, and ensures that the behavior of the spiking neuron model before and after compilation is consistent. Summary of the invention

[0005] In view of the above, the purpose of the present invention is to provide an efficient compilation method for a pulse neural network, which solves the technical problems in the prior art such as the lack of systematic integration of the pulse neural network compilation process, the single pulse neuron model library and poor scalability, the insufficient adaptability of the compilation process to the chip architecture, and the difficulty for users to flexibly customize the compilation process.

[0006] To achieve the above-mentioned purpose of the invention, an embodiment provides a compilation method for a brain-like chip, comprising the following steps: Each layer of the spiking neural network is divided into a neuron group, and variable information related to the internal operating state or parameters of the brain-like chip is extracted from the spiking neural network through the neuron group data module; Generate the core configuration of the brain-like chip based on the neuron behavior and operating parameters of the pulse neural network and variable information through the core configuration module; The neuron groups of the spiking neural network are divided and mapped to the brain-like chip core of the brain-like chip as physical neuron groups; Establish connection information for the physical neuron group in the brain-like chip based on the connection relationship of the pulse neural network; Serializes core configuration and connection information to generate executable files.

[0007] Preferably, the variable information related to the internal operating state or parameters of the brain-like chip is extracted from the pulse neural network through the neuron group data module, including: First, the name of the neuron group is registered in the neuron group data, and then the variables required in the current neuron group and their corresponding values ​​form the variable information and are configured in the neuron group data. The neuron group and the corresponding variable information are maintained and managed through a dictionary with the neuron group as the class.

[0008] Preferably, the core configuration module generates the core configuration of the brain-like chip according to the neuron behavior and operating parameters of the pulse neural network and the variable information, including: The core configuration module sets the register and memory types and initial values, the configured numerical values ​​or data form ranges according to the variable information through the provided interface, creates a programmable neuron behavior instruction set based on the neuron behavior of the pulse neural network to simulate the neuron behavior, and introduces the rules followed in the configuration process and the neuron behavior operating parameters to form the core configuration. Among them, the rules followed in the configuration process include synaptic delay mechanism and weight accuracy.

[0009] Preferably, the core configuration module is also provided with a delayed synapse model to achieve a close match with the brain-like chip architecture. The delayed synapse model is implemented as follows: first, the instructions of the instruction memory in the core configuration are traversed to find an unused running register, and then the specific value of the delay is written into the unused running register, and the corresponding instructions are written. The value of the running register is checked at each time step. If its value is greater than 0, no processing is performed at this time step, otherwise, normal neuron behavior is executed.

[0010] Preferably, the method also includes constructing a pulse neuron model library, which contains pulse neuron models of different neuron types. When creating a pulse neuron model, the interface provided by the core configuration module is used to allow the user to automatically write neuron behavior instructions and automatically configure the registers and memory of the brain-like chip according to the incoming operating parameters.

[0011] Preferably, the neuron groups of the pulse neural network are divided and mapped to the brain-like chip core of the brain-like chip as physical neuron groups, including: First, the neuron group is divided according to the function and connection relationship of the neurons, so that each divided neuron group meets the hardware limitations of the brain-like chip, and the divided neuron group is mapped to the brain-like chip. The physical neuron group is used to represent the neuron group obtained after the division and mapping. Each physical neuron group represents a neuron group actually placed on the hardware. The physical neuron group contains the number of neurons, shape, position of the neuromorphic core, axon information and dendrite information; then the physical neuron group is initialized according to the shape of the neuron group and the position of the neuromorphic core.

[0012] Preferably, the axon information indicates the dendrite information connected to the neuron, and the axon is divided into two parts: an axon metadata table and an axon target entry table, wherein the axon metadata table includes the neuron number of each neuron and the target entry number corresponding to the neuron, and the axon target entry table includes the target entry number, the core coordinates of the dendrite connected to the neuron, and the dendrite number; The dendrite information indicates the serial number and weight of the connected post-neuron, including three parts: the dendrite metadata table, the dendrite neuron number table and the weight table. The dendrite metadata table includes the dendrite number, the post-neuron serial number table number corresponding to the current dendrite, and the weight table number. The dendrite neuron number table includes the post-neuron serial number table number and the post-synaptic neuron serial number. The weight table contains the weight table number and the weight corresponding to each post-synaptic neuron.

[0013] Preferably, establishing connection information for the physical neuron group in the brain-like chip according to the pulse neural network connection relationship includes: When establishing connection information for the physical neuron groups in the brain-like chip, multiple neuron connection types are supported, including convolution, full connection, one-to-many standard connection, and one-to-one connection. Each connection type requires specifying the physical neuron groups before and after the connection, and also requires specifying the corresponding weights.

[0014] Preferably, each connection type needs to specify the physical neuron group before and after the connection, and the corresponding weights, including: During the execution of each connection type, axon information is established for the physical neuron group before the connection, and dendrite information is established for the physical neuron group after the connection. Specifically, when creating a connection, according to the connection type, all corresponding post-connection neurons are found for each pre-connection neuron, and then weights are matched for each post-connection neuron according to the given weight information. At this time, the serial number table and corresponding weight table of the post-connection neurons are obtained; Subtract the minimum neuron number in the number table from the number of the connected neuron, and record the minimum neuron number in the corresponding axon of the anterior physical neuron group. Then use the neuron number to match in the neuron number table. If the match is successful, it will be recorded in the dendrite metadata table of the corresponding posterior physical neuron group. Otherwise, a new entry will be created in the neuron number table, and the number of the new entry will be recorded in the dendrite metadata table. The weight information will also be matched in the weight table. If the match is successful, it will be recorded in the dendrite metadata table of the corresponding post-physical neuron group; otherwise, a new entry will be created in the weight table and the serial number of the new entry will be recorded in the dendrite metadata table.

[0015] Preferably, the serialization operation core configuration and connection information generates an executable file, including: Each neuron group is serialized according to the core configuration and the connection information contained in the physical neuron group. Specifically, at the beginning of serialization, the variable information in the corresponding neuron group data is found according to the name of the neuron group, and the data of each variable and its corresponding core configuration are obtained therefrom. Then, the variable information configured to the core configuration is matched, and the matched variable information is expanded into the shape of the corresponding neuron group. Then, the core configuration information in the core configuration module is written into the file in the order of configuration registers, running registers, instruction memory, inference state memory, inference parameter memory, learning state memory and learning parameter memory. In this process, the instructions of the core configuration module are mapped to the instruction set provided by the hardware according to the hardware type, and the instructions are converted into configuration information. Finally, the information in the physical neuron group is written into the file in the order of axon storage area and dendrite storage area.

[0016] Compared with the prior art, the present invention has the following beneficial effects: The compilation method of the present invention constructs a complete and efficient compilation process framework, covering all aspects from loading model data to generating executable files. When loading model data, the variables related to the chip are accurately extracted and managed to ensure the effective organization of the data. The register and memory configuration are flexible with the help of the core configuration module, which can handle various data forms and accurately configure according to the differences in neuron groups. Network division and mapping are based on the characteristics of the chip architecture, and physical neuron groups are used to achieve reasonable splitting and accurate mapping. The connection construction supports multiple types and optimizes storage utilization. The serialization operation integrates information to generate executable files. At the same time, the present invention constructs a pulse neuron model library, which includes classic IF and LIF models, and allows users to customize neuron behavior to meet diverse research needs. The present invention also designs a delayed synapse model that closely matches the chip architecture, ensuring that neuron pulse transmission strictly follows the chip time step logic at a low cost, and effectively solves the deficiencies of existing compilation technology in terms of model adaptability and user customization support. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 is a flowchart of a compilation method for a brain-like chip provided in an embodiment; Figure 2 is a schematic diagram of the relationship between axons and dendrites provided in the embodiment; Figure 3It is the axon information organization method provided by the embodiment; Figure 4 This is the dendrite information organization method provided by the embodiment. DETAILED DESCRIPTION

[0019] To make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific implementation methods described herein are only used to explain the present invention and do not limit the scope of protection of the present invention.

[0020] The compilation method for brain-like chips provided in the embodiment clarifies the complete compilation process from loading model data, register and memory configuration, network partitioning and mapping, connection construction, and serialization and export. Each process cooperates with each other to realize the conversion of the spiking neural network (SNN) model to a hardware executable file suitable for brain-like chip operation. Figure 1 As shown, the specific steps include: S1, divide each layer of the pulse neural network into a neuron group, and extract variable information related to the internal operating state or parameters of the brain-like chip from the pulse neural network through the neuron group data module.

[0021] In an embodiment, each layer of the pulse neural network is divided into a neuron group, and each neuron group will be set with a unique name to facilitate subsequent operations. During the compilation process, the operation of loading model data needs to be performed first. The neuron group data (PopsData) module is specifically designed to load the variable information in the model that is related to the internal operating state or parameters of the brain-like chip, and needs to be configured in the neuromorphic core register or memory in the brain-like chip, where the internal operating state or parameters of the brain-like chip include neuron state variables, including membrane potential, threshold voltage, etc.; and parameters of neuron state changes, such as membrane potential attenuation coefficient, etc.

[0022] When loading model data, the data extraction method is also clarified, which refers to using the neuron group data module and the core configuration module to match the variables in the core configuration with the data in the neuron group data module according to the neuron group name, avoiding multiple creations of core configurations, so as to create as few core configurations as possible. The data types involved are also clarified. The data type will be matched according to the input data type and the current neuron group shape, and automatically converted to the required data type to ensure the generation of correct data. For example, the data type of a matrix is ​​generated from a scalar.

[0023] In the embodiment, the extracted variable information is managed using a specific data structure to ensure efficient reading and processing of data. Specifically, the variable information is maintained in a dictionary with a class name of neuron group. The main operation is to register the name of the neuron group into the neuron group data, and then configure the variable information composed of the variables required in the current neuron group and their corresponding values ​​into the neuron group data.

[0024] S2, generates the core configuration of the brain-like chip according to the neuron behavior and operating parameters of the pulse neural network and variable information through the core configuration module.

[0025] In the embodiment, after obtaining the variable information, the core configuration (CoreConfig) of the brain-like chip is generated, and the configurable register and memory types, the range of the configured values ​​or data forms, and the rules followed or the interfaces used in the configuration process are specifically described. The core configuration includes chip configuration, operating parameters, neuron behavior instructions, reasoning state and parameters, and learning state and parameter information, wherein the operating parameters and neuron behavior instructions constitute neuron behavior information, and the chip configuration, reasoning state and parameters, and learning state and parameter information constitute configuration information that supports chip operation, which is used to indicate the working mode and exception handling of the chip.

[0026] The embodiment designs a core configuration module, which provides a unified and convenient interface. With the help of this interface, all configuration spaces of the brain-like chip can be set, and can be dynamically adjusted according to different brain-like chip architecture parameters to adapt to diverse chip requirements. Specifically, the interface can be used to set the register and memory type and their initial values ​​on the neuromorphic core according to variable information, wherein the register and memory types include configuration registers, run registers, instruction memory, inference state memory, inference parameter memory, learning state memory, and learning parameter memory.

[0027] In order to increase the flexibility of the core configuration module, the range of the configured value or data form is also set, that is, the information configured in the core configuration module can be a specific value, a matrix of values, or a variable. In the subsequent serialization process, the corresponding data will be automatically found in the memory according to the core configuration information in the core configuration module, and the data will be automatically filled according to the shape information of the current neuron group. Since the initial values ​​of different neuron groups may be different, the core configuration module will match the information with the neuron group data and configure the variable values ​​of different neuron groups to the correct neuromorphic core registers and memories.

[0028] In order to adapt to programmable brain-like chips and cope with more neuronal behaviors and complex parameters, the method of the present invention also creates a programmable neuronal behavior instruction set based on the neuronal behavior of the spiking neural network, abstracts the hardware instructions of the brain-like chip, and each brain-like chip can have its own specific implementation. The programmable neuronal behavior instruction set includes general instructions: register addition, register subtraction, register multiplication, immediate addition, shift, comparison, jump, etc., and also includes neuronal instructions exclusive to brain-like chips, such as accessing neuronal general prediction parameters, updating membrane voltage, emitting pulses, etc. Neuronal behavior can be simulated according to the provided neuronal behavior instruction set.

[0029] The embodiment also constructs a pulse neuron model library, which contains pulse neuron models of different neuron types, including an Integrate-and-Fire (IF) model, a Leaky Integrate-and-Fire (LIF) model, etc. It should be noted that the pulse neuron is responsible for absorbing and emitting pulses in the pulse neural network. The pulse neuron model refers to a specific type of neuron behavior, such as IF, LIF. Different behaviors lead to different pulse accumulation processes and pulse emission processes of the pulse neural network, and the results of network operation will also be different. Based on the constructed pulse neuron model library, a pulse neural network with different pulse behaviors can be constructed.

[0030] When creating a pulse neuron model, the interface provided by the core configuration module allows users to specify the type of neuron model, automatically write neuron behavior instructions, and automatically match the incoming neuron operating parameters (such as threshold voltage, current, etc.) according to the selected type, and then automatically generate the core configuration according to the model type and parameters, mainly including the contents of configuration registers, operating registers, and instruction memory. The parameter configuration logic in this process is: after selecting the pulse neuron model, a parameter list will be obtained, which stores the required parameter names and types, and then match the parameter name according to the user input, check the data type, and determine whether it is correct.

[0031] The embodiment of the present invention also provides the ability to expand the brain-like chip. Each instruction can have multiple implementations, and each implementation corresponds to a brain-like chip. During compilation, a specific neuron behavior instruction sequence is generated based on the model type selected from the pulse neuron model library. In the serialization stage, the instruction is converted into the configuration information of the corresponding hardware according to the hardware type.

[0032] The core configuration module also introduces the rules followed during the configuration process, which include synaptic delay mechanism and weight accuracy.

[0033] The pulse neural network in the brain-like chip architecture has a synaptic delay mechanism. In order to achieve a close match with the brain-like chip architecture, the present invention also designs a delayed synaptic model, which is implemented by configuring the neuron behavior and inserting specific instructions in the instruction storage area of ​​the brain-like chip so that the neuron does not perform an update operation within a specific time step. The specific implementation method is: first traverse the instructions of the instruction memory in the core configuration, find an unused running register, then write the specific value of the delay into the unused running register, and write the corresponding instructions to automatically configure the register, memory and other configuration spaces of the brain-like chip, so that at each time step, it is determined whether the normal behavior of the neuron is executed according to the register value to ensure that the pulse transmission between neurons complies with the chip time step logic. Specifically, the value of the running register will be checked at each time step. If its value is greater than 0, no processing will be performed at this time step, otherwise, normal neuron behavior will be executed.

[0034] S3, the neuron groups of the pulse neural network are divided and mapped to the brain-like chip core of the brain-like chip as physical neuron groups.

[0035] In an embodiment, due to hardware limitations, it may be necessary to split the neuron group. Specifically, the neuron group is first divided according to the function and connection relationship of the neuron, so that each divided neuron group meets the hardware limitations of the brain-like chip, mainly the number of neurons, the number of axons and the number of dendrites. Then the divided neuron group is mapped to the brain-like chip core. The present invention provides an interface for division and mapping, which can split each neuron group and assign it to the brain-like chip core. Mapping is specifically performed according to the connection relationship, that is, starting from the first layer of the network, for each neuron group to be mapped, the sum of the Manhattan distances of all neuron groups connected to it is calculated, and the core position with the smallest sum of Manhattan distances is found as the current position mapped to the brain-like chip core.

[0036] A physical neuron group (PhysicalPopulation) is used to represent the neuron group obtained after division and mapping. Each physical neuron group represents a neuron group actually placed on hardware. The physical neuron group contains the number of neurons, shape, neuromorphic core position, axon information and dendrite information. After the division and mapping are completed, the physical neuron group is initialized according to the shape of the neuron group and the position of the neuromorphic core.

[0037] The relationship between axon information and dendrite information included in a physical neuron group is as follows Figure 2 As shown in the figure. The axon information indicates the dendrite information connected to the neuron. The axon is divided into two parts: the axon metadata table and the axon target entry table. The organization is as follows Figure 3, where the axon metadata table contains the neuron number of each neuron and the target entry number corresponding to the neuron, that is, each neuron has an axon metadata information, which is used to indicate the sequence number of the target entry. The axon target entry table contains the target entry number, the coordinates of the dendrite core connected to the neuron, and the dendrite number.

[0038] The dendrite information indicates the sequence number and weight of the connected neuron, including the dendrite metadata table, the dendrite neuron number table and the weight table, which are organized as follows: Figure 4 Among them, the dendrite metadata table includes the dendrite number, the post-neuron sequence table number corresponding to the current dendrite, and the weight table number, indicating the post-neuron sequence number of the current dendrite and the corresponding weight. The dendrite neuron number table includes the post-neuron sequence table number and the post-synaptic neuron sequence number. The weight table includes the weight table number and the weight corresponding to each post-synaptic neuron.

[0039] S4, establishing connection information for the physical neuron group in the brain-like chip based on the connection relationship of the pulse neural network.

[0040] In an embodiment, when establishing connection information for a physical neuron group in a brain-like chip, multiple types of connections between neurons are supported, including convolution, full connection, one-to-many standard connection, and one-to-one connection. Each connection type requires specifying the physical neuron group before and after the connection, and also requires specifying the corresponding weights.

[0041] During the execution of each connection type, different processing will be performed according to the characteristics of the connection, and a connection relationship will be established for the physical neuron groups before and after the connection, that is, axon information will be established for the physical neuron group before the connection, and dendrite information will be established for the physical neuron group after the connection. This information will be stored in the physical neuron group for subsequent use. Specifically, when creating a connection, according to the connection type, all corresponding post-connection neurons are found for each pre-connection neuron, and then the weights are matched for each post-connection neuron according to the given weight information. At this time, the serial number table and corresponding weight table of the post-connection neurons are obtained.

[0042] Then, in order to make the most efficient use of the hardware storage resources, the serial number of the connected neuron is subtracted from the minimum neuron serial number in the serial number table, and the minimum neuron serial number is recorded in the corresponding axon of the front physical neuron group. After that, the neuron serial number is used to match in the neuron serial number table. If the match is successful, it will be recorded in the dendrite metadata table of the corresponding rear physical neuron group; otherwise, a new entry will be created in the neuron serial number table, and the serial number of the new entry will be recorded in the dendrite metadata table.

[0043] The weight information will also be matched in the weight table. If the match is successful, it will be recorded in the dendrite metadata table of the corresponding post-physical neuron group; otherwise, a new entry will be created in the weight table and the serial number of the new entry will be recorded in the dendrite metadata table.

[0044] S5, serializes the core configuration and connection information to generate an executable file.

[0045] At the end of the compilation process, a serialization operation will be performed. The serialization operation of the present invention will use the connection information in the neuron group data, core configuration and physical neuron group to serialize each neuron group. Specifically, at the beginning of serialization, the variable information in the corresponding neuron group data will be found according to the name of the neuron group, and the data of each variable and its corresponding core configuration will be obtained from the variable information. Then, the variable information configured to the core configuration will be matched, and the variable information will be expanded into the shape of the corresponding neuron group. Then, the information in the core configuration module will be written into the file in the order of configuration registers, running registers, instruction memory, inference state memory, inference parameter memory, learning state memory and learning parameter memory. In this process, the instructions of the core configuration module will be mapped to the instruction set provided by the hardware according to the hardware type, and the instructions will be converted into configuration information. Finally, the information in the physical neuron group will be written into the file in the order of axon storage area and dendrite storage area.

[0046] The specific implementation methods described above provide a detailed description of the technical solutions and beneficial effects of the present invention. It should be understood that the above is only the most preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, supplements and equivalent substitutions made within the scope of the principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A compilation method for brain-like chips, characterized in that: The following steps are involved: Each layer of the spiking neural network is divided into a neuron group, and variable information related to the internal operating state or parameters of the brain-like chip is extracted from the spiking neural network through the neuron group data module; Generate the core configuration of the brain-like chip based on the neuron behavior and operating parameters of the pulse neural network and variable information through the core configuration module; The neuron groups of the spiking neural network are divided and mapped to the brain-like chip core of the brain-like chip as physical neuron groups; Establish connection information for the physical neuron group in the brain-like chip based on the connection relationship of the pulse neural network; Serializes core configuration and connection information to generate executable files.

2. The compilation method for brain-like chips according to claim 1, characterized in that: The variable information related to the internal operating state or parameters of the brain-like chip is extracted from the pulse neural network through the neuron group data module, including: First, the name of the neuron group is registered in the neuron group data, and then the variables required in the current neuron group and their corresponding values ​​form the variable information and are configured in the neuron group data. The neuron group and the corresponding variable information are maintained and managed through a dictionary with the neuron group as the class.

3. The compilation method for brain-like chips according to claim 1, characterized in that: The core configuration module generates the core configuration of the brain-like chip based on the neuron behavior and operating parameters of the pulse neural network and variable information, including: The core configuration module sets the register and memory types and initial values, the configured numerical values ​​or data form ranges according to the variable information through the provided interface, creates a programmable neuron behavior instruction set based on the neuron behavior of the pulse neural network to simulate the neuron behavior, and introduces the rules followed in the configuration process and the neuron behavior operating parameters to form the core configuration. Among them, the rules followed in the configuration process include synaptic delay mechanism and weight accuracy.

4. The compilation method for brain-like chips according to claim 3, characterized in that: The core configuration module is also provided with a delayed synapse model to achieve a close match with the brain-like chip architecture. The delayed synapse model is implemented as follows: first, the instructions of the instruction memory in the core configuration are traversed to find an unused running register, and then the specific value of the delay is written into the unused running register, and the corresponding instructions are written. The value of the running register is checked at each time step. If its value is greater than 0, no processing is performed at this time step, otherwise, normal neuronal behavior is executed.

5. The compilation method for brain-like chips according to claim 1, characterized in that: The method also includes constructing a pulse neuron model library, which includes pulse neuron models of different neuron types. When creating a pulse neuron model, an interface provided by a core configuration module is used to allow a user to automatically write neuron behavior instructions and automatically configure registers and memory of the brain-like chip according to the input operating parameters.

6. The compilation method for brain-like chips according to claim 1, characterized in that: The neuron groups of the pulse neural network are divided and mapped to the brain-like chip core of the brain-like chip as physical neuron groups, including: First, the neuron group is divided according to the function and connection relationship of the neurons, so that each divided neuron group meets the hardware limitations of the brain-like chip, and the divided neuron group is mapped to the brain-like chip. The physical neuron group is used to represent the neuron group obtained after the division and mapping. Each physical neuron group represents a neuron group actually placed on the hardware. The physical neuron group contains the number of neurons, shape, position of the neuromorphic core, axon information and dendrite information; then the physical neuron group is initialized according to the shape of the neuron group and the position of the neuromorphic core.

7. The compilation method for brain-like chips according to claim 6, characterized in that: The axon information indicates the dendrite information connected to the neuron. The axon is divided into two parts: the axon metadata table and the axon target entry table. The axon metadata table contains the neuron number of each neuron and the target entry number corresponding to the neuron. The axon target entry table contains the target entry number, the core coordinates of the dendrite connected to the neuron, and the dendrite number. The dendrite information indicates the serial number and weight of the connected post-neuron, including three parts: the dendrite metadata table, the dendrite neuron number table and the weight table. The dendrite metadata table includes the dendrite number, the post-neuron serial number table number corresponding to the current dendrite, and the weight table number. The dendrite neuron number table includes the post-neuron serial number table number and the post-synaptic neuron serial number. The weight table contains the weight table number and the weight corresponding to each post-synaptic neuron.

8. The compilation method for brain-like chips according to claim 1, characterized in that: Establish connection information for the physical neuron group in the brain-like chip based on the connection relationship of the pulse neural network, including: When establishing connection information for the physical neuron groups in the brain-like chip, multiple neuron connection types are supported, including convolution, full connection, one-to-many standard connection, and one-to-one connection. Each connection type requires specifying the physical neuron groups before and after the connection, and also requires specifying the corresponding weights.

9. The compilation method for brain-like chips according to claim 8, characterized in that: Each connection type requires specifying the physical neuron group before and after the connection, and the corresponding weights, including: During the execution of each connection type, axon information is established for the physical neuron group before the connection, and dendrite information is established for the physical neuron group after the connection. Specifically, when creating a connection, according to the connection type, all corresponding post-connection neurons are found for each pre-connection neuron, and then weights are matched for each post-connection neuron according to the given weight information. At this time, the serial number table and corresponding weight table of the post-connection neurons are obtained; Subtract the minimum neuron number in the number table from the number of the connected neuron, and record the minimum neuron number in the corresponding axon of the anterior physical neuron group. Then use the neuron number to match in the neuron number table. If the match is successful, it will be recorded in the dendrite metadata table of the corresponding posterior physical neuron group. Otherwise, a new entry will be created in the neuron number table, and the number of the new entry will be recorded in the dendrite metadata table. The weight information will also be matched in the weight table. If the match is successful, it will be recorded in the dendrite metadata table of the corresponding post-physical neuron group; otherwise, a new entry will be created in the weight table and the serial number of the new entry will be recorded in the dendrite metadata table.

10. The compilation method for brain-like chips according to claim 1, characterized in that: Generates executable files from serialized core configuration and connection information, including: Each neuron group is serialized according to the core configuration and the connection information contained in the physical neuron group. Specifically, at the beginning of serialization, the variable information in the corresponding neuron group data is found according to the name of the neuron group, and the data of each variable and its corresponding core configuration are obtained therefrom. Then, the variable information configured to the core configuration is matched, and the matched variable information is expanded into the shape of the corresponding neuron group. Then, the core configuration information in the core configuration module is written into the file in the order of configuration registers, running registers, instruction memory, inference state memory, inference parameter memory, learning state memory and learning parameter memory. In this process, the instructions of the core configuration module are mapped to the instruction set provided by the hardware according to the hardware type, and the instructions are converted into configuration information. Finally, the information in the physical neuron group is written into the file in the order of axon storage area and dendrite storage area.

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