Driving circuit

Abstract

Provided is a drive circuit which can be configured with a small number of transistors and capacitors to minimize a dead zone, and which can stably output a gate signal. The driving circuit includes a plurality of stages that output a plurality of gate signals to a plurality of pixels. Each of the plurality of stages includes: a first transistor connected between a first terminal and a first node and configured to control a voltage level of the first node, the first terminal receiving a first signal; a second transistor connected between a second terminal and a second node and configured to control a voltage level of the second node, the second terminal receiving a second signal; a third transistor connected between a third terminal and the second node and configured to control a voltage level of the second node, the third terminal receiving a third signal; and an output circuit configured to output a corresponding gate signal having one of a high level voltage and a low level voltage among the plurality of gate signals according to a voltage level of the first node and a voltage level of the second node.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0147150 filed on October 30, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The present disclosure relates to a display device, and more particularly, to a driving circuit that outputs a gate signal and a display device including the driving circuit. Background Art

[0004] The display device includes a pixel region including a plurality of pixels, a gate driving circuit, a data driving circuit and a controller. The gate driving circuit includes stages connected to gate lines, and the stages supply gate signals through the gate lines connected thereto in response to signals from the controller. Summary of the invention

[0005] One or more embodiments include a gate drive circuit having a small size and capable of stably outputting a gate signal and a display device including the gate drive circuit. The technical objectives to be achieved by the present disclosure are not limited thereto, and through the following description, other unmentioned technical objectives will be obvious to a person of ordinary skill in the art to which the present disclosure belongs.

[0006] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments.

[0007] According to aspects of the present disclosure, a driving circuit includes a plurality of stages that output a plurality of gate signals to a plurality of pixels. The plurality of stages include a first stage, a last stage, and a plurality of intermediate stages connected in series with each other. The plurality of intermediate stages are connected in series with each other and are arranged between the first stage and the last stage. Each of the plurality of stages includes: a first transistor connected between a first terminal and a first node and configured to control a voltage level of the first node, wherein the first terminal receives a first signal; a second transistor connected between a second terminal and a second node and configured to control a voltage level of the second node, wherein the second terminal receives a second signal; a third transistor connected between a third terminal and a second node and configured to control a voltage level of the second node, wherein the third terminal receives a third signal; and an output circuit configured to output a corresponding gate signal having one of a high level voltage and a low level voltage among a plurality of gate signals according to the voltage level of the first node and the voltage level of the second node.

[0008] The first stage receives an external signal as a first signal, and each of the last stage and the plurality of intermediate stages receives a corresponding gate signal output from a previous stage among the plurality of stages among the plurality of gate signals.

[0009] A gate of each of the first transistor, the second transistor, and the third transistor is connected to a first clock terminal receiving a first clock signal. The first transistor and the second transistor are P-type transistors, and the third transistor is an N-type transistor.

[0010] The second signal may be a first voltage of a low level, and the third signal may be a second voltage of a high level.

[0011] A gate of each of the first transistor, the second transistor, and the third transistor may be connected to a first clock terminal receiving a first clock signal. The first transistor and the third transistor are P-type transistors, and the second transistor is an N-type transistor.

[0012] The second signal may be the same signal as the first signal, and the third signal may be a first voltage of a low level.

[0013] A gate of each of the first transistor and the second transistor can be connected to a first clock terminal to which a first clock signal is input, a gate of the third transistor can be connected to a second clock terminal to which a second clock signal is input, the first transistor is a P-type transistor, and the second transistor and the third transistor are N-type transistors.

[0014] The second signal may be the same signal as the first signal, and the third signal may be the first clock signal.

[0015] Each of the plurality of stages may further include a fourth transistor connected between the first transistor and the first node and including a gate connected to a terminal to which the first voltage of a low level is input.

[0016] The fourth transistor may include two sub-transistors connected in series.

[0017] Each of the plurality of stages may further include: a capacitor connected between the first node and a terminal to which the first voltage of a low level is supplied.

[0018] The output circuit may include: a pull-down transistor connected between the output terminal and the clock terminal and including a gate connected to the first node; a pull-up transistor connected between a terminal supplied with a second voltage of a high level and the output terminal and including a gate connected to the second node; and a capacitor connected between the first node and the output terminal.

[0019] According to aspects of the present disclosure, a driving circuit includes a plurality of stages that output a plurality of gate signals to a plurality of pixels. Each of the plurality of stages includes: a first transistor connected between a first node and an input terminal to which a start signal is input, and including a gate connected to a first clock terminal to which a first clock signal is input; a second transistor connected between a second node and a first voltage input terminal to which a low-level first voltage is input, and including a gate connected to the first clock terminal; a third transistor connected between a second node and a second voltage input terminal to which a high-level second voltage is input, and including a gate connected to the first clock terminal; and an output circuit connected to the second voltage input terminal and a second clock terminal to which a second clock signal is input, and configured to output a corresponding gate signal having one of a high-level voltage and a low-level voltage among a plurality of gate signals according to a voltage level of the first node and a voltage level of the second node. The first transistor and the second transistor are P-type transistors, and the third transistor is an N-type transistor.

[0020] Each of the plurality of stages may further include a fourth transistor connected between the first transistor and the first node and including a gate connected to the first voltage input terminal.

[0021] The fourth transistor may include two sub-transistors connected in series.

[0022] Each of the plurality of stages may further include a capacitor connected between the first node and the first voltage input terminal.

[0023] According to an embodiment of the present disclosure, a driving circuit includes a plurality of stages that output a plurality of gate signals to a plurality of pixels. Each of the plurality of stages includes: a first transistor connected between a first node and an input terminal to which a start signal is input, and including a gate connected to a first clock terminal to which a first clock signal is input; a second transistor connected between the input terminal and a second node, and including a gate connected to the first clock terminal; a third transistor connected between the first clock terminal and a second node, and including a gate connected to a second clock terminal to which a second clock signal is input; and an output circuit connected between the second clock terminal and a first voltage input terminal to which a high level first voltage is input, and configured to output a corresponding gate signal having one of a high level voltage and a low level voltage among a plurality of gate signals according to a voltage level of the first node and a voltage level of the second node. The first transistor is a P-type transistor, and the second transistor and the third transistor are N-type transistors.

[0024] Each of the plurality of stages may further include a fourth transistor connected between the first transistor and the first node and including a gate connected to a second voltage input terminal to which a second voltage of a low level is input.

[0025] The fourth transistor may include two sub-transistors connected in series.

[0026] Each of the plurality of stages may further include: a capacitor connected between the first node and a second voltage input terminal to which the second voltage of a low level is input.

[0027] According to aspects of the present disclosure, a driving circuit includes a plurality of stages that output a plurality of gate signals to a plurality of pixels. Each of the plurality of stages includes: a first transistor connected between a first node and an input terminal to which a start signal is input, and including a gate connected to a first clock terminal to which a first clock signal is input; a second transistor connected between the input terminal and a second node, and including a gate connected to the first clock terminal; a third transistor connected between a second node and a first voltage input terminal to which a low-level first voltage is input, and including a gate connected to the first clock terminal; and an output circuit connected between a second voltage input terminal to which a high-level second voltage is input and a second clock terminal to which a second clock signal is input, and configured to output a corresponding gate signal having one of a high-level voltage and a low-level voltage among a plurality of gate signals according to a voltage level of the first node and a voltage level of the second node. The first transistor and the third transistor are P-type transistors, and the second transistor is an N-type transistor.

[0028] Each of the plurality of stages may further include a fourth transistor connected between the first transistor and the first node and including a gate connected to the first voltage input terminal.

[0029] The fourth transistor may include two sub-transistors connected in series.

[0030] Each of the plurality of stages may further include: a capacitor connected between the first node and the first voltage input terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other aspects, features and advantages of certain embodiments will become more apparent through the following description in conjunction with the accompanying drawings, in which:

[0032] Figure 1 is a diagram illustrating a display device according to an embodiment of the present disclosure;

[0033] Figure 2 is a diagram illustrating a gate driving circuit according to an embodiment of the present disclosure;

[0034] Figure 3 It is a diagram including an embodiment according to the present disclosure Figure 2 A circuit diagram of an example of a stage in a gate drive circuit;

[0035] Figure 4 It is used to describe the embodiments according to the present disclosure. Figure 3 A timing diagram of the operation of the level;

[0036] Figure 5 and Figure 6 It is a diagram including in an embodiment according to the present disclosure Figure 2 A circuit diagram of an example of a stage in a gate drive circuit;

[0037] Figure 7 It is a diagram including in an embodiment according to the present disclosure Figure 2 A circuit diagram of an example of a stage in a gate drive circuit;

[0038] Figure 8 It is used to describe the embodiments according to the present disclosure. Figure 7 A timing diagram of the operation of the level;

[0039] Fig. 9 and Fig.10 It is a diagram including in an embodiment according to the present disclosure Figure 2 A circuit diagram of an example of a stage in a gate drive circuit;

[0040] Fig.11 It is a diagram including in an embodiment according to the present disclosure Figure 2 A circuit diagram of an example of a stage in a gate drive circuit;

[0041] Fig.12 It is used to describe the embodiments according to the present disclosure. Fig.11 A timing diagram of the operation of the stage; and

[0042] Fig.13 and Fig.14 It is a diagram including in an embodiment according to the present disclosure Figure 2 A circuit diagram of an example of a stage in a gate driver circuit. DETAILED DESCRIPTION

[0043] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings. The same reference numerals refer to the same elements throughout. In this regard, the present embodiment may have different forms and should not be construed as being limited to the description set forth herein. Therefore, the following will only describe the embodiments with reference to the accompanying drawings to explain the various aspects of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression "at least one of a, b, and c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0044] Since the present disclosure allows various changes and numerous embodiments, certain embodiments will be shown in the drawings and described in the detailed description. The effects and features of the present disclosure and methods for achieving them will be explained with reference to the embodiments described in detail below with reference to the drawings. However, the present disclosure is not limited to the following embodiments and can be implemented in various forms.

[0045] Although the terms “first”, “second”, etc. may be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element.

[0046] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0047] It will be understood that the terms “comprising” and “having” are intended to indicate the presence of the features or elements described in the specification, and are not intended to exclude the possibility that one or more other features or elements may be present or may be added.

[0048] It will be further understood that when a layer, region or element is referred to as being “on” another layer, region or element, it can be directly on the other layer, region or element or can be indirectly on the other layer, region or element with intervening layers, regions or elements therebetween.

[0049] For the convenience of explanation, the size of the elements in the drawings may be exaggerated or reduced. For example, because the size and thickness of the elements in the drawings are arbitrarily shown for the convenience of explanation, the present disclosure is not limited thereto.

[0050] “A and / or B” is used herein to select only A, only B, or both A and B. Additionally, “at least one of A and B” is used herein to select only A, only B, or both A and B.

[0051] In the following embodiments, when X and Y are connected to each other, this may include a case where X and Y are electrically connected to each other with or without at least one intervening element, a case where X and Y are functionally connected to each other, and a case where X and Y are physically connected to each other. X and Y may be objects (e.g., devices, equipment, circuits, wiring, electrodes, terminals, conductive films, or layers). Accordingly, the connection relationship is not limited to a specific connection relationship (e.g., a connection relationship as shown in the drawings or described in the detailed description), and may include other connection relationships in addition to the connection relationships shown in the drawings or described in the detailed description.

[0052] For example, when X and Y are electrically connected, X and Y may be directly connected to each other, or one or more elements (e.g., switches, transistors, capacitors, inductors, resistors, or diodes) capable of achieving electrical connection between X and Y may be connected between X and Y.

[0053] In the following embodiments, the term "on" used in association with the state of the device may refer to a state in which the device is activated, and the term "off" may refer to a state in which the device is deactivated. The term "on" used in association with the signal received by the device may refer to a signal for activating the device, and the term "off" may refer to a signal for deactivating the device. The device may be activated by a high level voltage or a low level voltage. For example, a P-type transistor (P-channel transistor) is activated by a low level voltage, and an N-type transistor (N-channel transistor) is activated by a high level voltage. Accordingly, it should be understood that the "on" voltages of the P-type transistor and the N-type transistor have opposite (high and low) voltage levels. In the following, the voltage for activating (conducting) the transistor is referred to as the on voltage, and the voltage for deactivating (cutting off) the transistor is referred to as the off voltage. The period in which the on voltage of the signal is maintained is referred to as the on voltage period, and the period in which the off voltage is maintained is referred to as the off voltage period.

[0054] Figure 1 is a diagram schematically illustrating a display device according to an embodiment.

[0055] The display device 10 according to the embodiment may be a display device such as an organic light emitting display device, an inorganic light emitting display device (or an inorganic electroluminescent (EL) display device), and a quantum dot light emitting display device.

[0056] refer to Figure 1 , the display device 10 according to the embodiment may include a pixel region 110 , a gate driving circuit 130 , a data driving circuit 150 , and a controller 170 .

[0057] In the pixel region 110 , a plurality of pixels PX and signal lines for inputting electrical signals to the plurality of pixels PX may be disposed.

[0058] A plurality of pixels PX may be repeatedly arranged in a first direction (x direction or row direction) and a second direction (y direction or column direction). A plurality of pixels PX may be arranged in any of various forms such as stripe arrangement, pentile arrangement, diamond arrangement, and mosaic arrangement to display an image. Each of the plurality of pixels PX may include an organic light emitting diode as a display element, and the organic light emitting diode may be connected to a pixel circuit. The pixel circuit may include a plurality of transistors and at least one capacitor.

[0059] In an embodiment, the plurality of transistors included in the pixel region 110 may be P-type silicon transistors. The silicon transistor may include a silicon semiconductor, and the silicon semiconductor may include amorphous silicon or polycrystalline silicon. For example, the silicon transistor may be a low temperature polycrystalline silicon (LTPS) thin film transistor.

[0060] In an embodiment, a plurality of transistors included in a pixel circuit may be N-type oxide transistors. The oxide transistor may include an oxide semiconductor, and the oxide semiconductor may include a zinc oxide-based material such as zinc oxide, indium zinc oxide, and gallium indium zinc oxide. In some embodiments, the oxide semiconductor may be an indium gallium zinc oxide (IGZO) semiconductor. In some embodiments, the oxide semiconductor may be an indium tin gallium zinc oxide (ITGZO) semiconductor. For example, the oxide transistor may be a low temperature polycrystalline oxide (LTPO) thin film transistor. In an embodiment, some of the plurality of transistors included in a pixel circuit may be P-type silicon transistors, and other transistors may be N-type oxide transistors.

[0061] The signal line for inputting an electrical signal to a plurality of pixels PX may include a plurality of gate lines GL1 to GLn extending in a first direction and a plurality of data lines DL1 to DLm extending in a second direction. The plurality of gate lines GL1 to GLn may be spaced apart from each other in the second direction, and a gate signal may be transmitted to the pixel PX. The plurality of data lines DL1 to DLm may be spaced apart from each other in the first direction, and a data signal may be transmitted to the pixel PX. Each of the plurality of pixels PX may be connected to at least one corresponding gate line among the plurality of gate lines GL1 to GLn and a corresponding data line among the plurality of data lines DL1 to DLm. Each pixel PX may receive a gate signal applied by a corresponding gate line among the gate lines GL1 to GLn and a data signal from a corresponding data line among the data lines DL1 to DLm.

[0062] The gate driving circuit 130 may be connected to the gate lines GL1 to GLn, may generate a gate signal in response to a gate driving control signal GCS from the controller 170, and may sequentially supply the gate signal to the gate lines GL1 to GLn. The gate lines GL1 to GLn may each be connected to a gate of a transistor included in the pixel PX, and the gate signal may be a gate control signal for controlling the turning on and off of the transistor to which the gate line is connected. The gate signal may include a gate-on voltage that may turn on the transistor and a gate-off voltage that may turn off the transistor.

[0063] The gate driving circuit 130 may include a shift register for sequentially generating and outputting gate signals. In an embodiment, the gate driving circuit 130 may include a plurality of shift registers connected in series and sequentially outputting gate signals so that a current shift register receives an output signal of a previous shift register as a start signal or a reset signal.

[0064] The data driving circuit 150 may be connected to the plurality of data lines DL1 to DLm and may supply data signals to the data lines DL1 to DLm in response to a data driving control signal DCS from the controller 170. The data signals supplied to the data lines DL1 to DLm may be supplied to the pixels PX supplied with gate signals.

[0065] In an embodiment, the display device 10 is an organic light emitting display device. A first power supply voltage ELVDD and a second power supply voltage ELVSS may be supplied to the pixels PX of the pixel area 110. The first power supply voltage ELVDD may be a high level voltage supplied to one terminal of a driving transistor included in each pixel PX. The second power supply voltage ELVSS may be a low level voltage supplied to a second electrode (opposite electrode or cathode) of an organic light emitting diode connected to the other terminal of the driving transistor. The first power supply voltage ELVDD and the second power supply voltage ELVSS may be driving voltages for causing a plurality of pixels PX to emit light.

[0066] The controller 170 may generate a gate driving control signal GCS and a data driving control signal DCS based on a signal input from the outside. The controller 170 may supply the gate driving control signal GCS to the gate driving circuit 130 , and may supply the data driving control signal DCS to the data driving circuit 150 .

[0067] Figure 2 is a diagram illustrating a gate driving circuit according to an embodiment. Figure 3 The diagram is included in Figure 2 A circuit diagram of an example of a stage in a gate driver circuit. Figure 4 Is used to describe Figure 3 A timing diagram of the operation of the stage.

[0068] refer to Figure 2 , the gate driving circuit 130 may include a plurality of stages (e.g., ST1 to STn). The plurality of stages (e.g., ST1 to STn) may sequentially output gate signals GS[1] to GS[n] to gate lines GL1 to GLn. The number of stages provided in the gate driving circuit 130 may vary according to the number of rows (horizontal lines) provided in the pixel region 110.

[0069] Each of the first to n-th stages ST1 to STn may be connected to a gate line located in a corresponding row of the pixel region 110. Each of the first to n-th stages ST1 to STn may receive at least one clock signal and at least one voltage signal, may generate a gate signal GS, and may output the gate signal GS to the connected gate line GL. For example, each of the first to n-th stages ST1 to STn may supply a corresponding gate signal GS to a gate line GL provided in a corresponding row.

[0070] The first stage ST1 to the nth stage STn can output the first to the nth gate signals GS[1], GS[2], GS[3], GS[4], ... and GS[n] respectively in response to the start signal. For example, the nth stage STn can output the nth gate signal GS[n] to the nth gate line. An external signal FLM as a start signal for controlling the timing of the first gate signal GS[1] can be supplied to the first stage ST1. In an embodiment, each of the multiple stages ST1 to STn can be a shift register, and includes a first stage ST1, a last stage STn and a plurality of intermediate stages ST2 to ST(n-1) connected in series with each other. The intermediate stages ST2 to ST(n-1) can be connected in series with each other. The first stage ST1 can start the operation by the external signal FLM acting as the start signal of the first stage ST1. The second stage ST2 in the intermediate stages ST2 to ST(n-1) can be directly connected to the first stage ST1, and can receive the output signal of the first stage ST1 as the start signal of the second stage ST2. The output signal of the first stage ST1 may correspond to the gate signal GS[1] transmitted to the second stage ST2 as the first carry signal CR[1]. The output signal of the second stage ST2 may be transmitted to the third stage ST3 directly connected to the second stage ST2. The output signal of the second stage ST2 may be the second gate signal GS[2] transmitted to the third stage ST3 as the second carry signal CR[2]. In response to the second carry signal CR[2], the third stage ST3 may start operation. This description may be applicable to other stages ST4 to STn. The external signal FLM and the carry signals CR[1] to CR[n-1] may serve as the start signals of the stages ST1 to STn, respectively. The carry signals CR[1] to CR[n-1] will be further described below.

[0071] Each of the first stage ST1 to the nth stage STn may include a plurality of terminals to which a plurality of signals are input. The plurality of signals may include a clock signal and a voltage signal. The plurality of terminals may include an input terminal IN, a first voltage input terminal V1, a second voltage input terminal V2, a first clock terminal CK1, a second clock terminal CK2, and an output terminal OUT.

[0072] The start signal may be input to (supplied to) the input terminal IN. The start signal may be an external signal FLM or any one of the carry signals CR[1], CR[2], CR[3], CR[4], ... and CR[n-1]. In an embodiment, each of the carry signals CR[1], CR[2], CR[3], CR[4], ... and CR[n-1] may be a gate signal output from a previous stage (hereinafter referred to as a "previous gate signal"). The external signal FLM may be input to the input terminal IN of the first stage ST1 as a start signal, and the previous gate signal may be input to the input terminal IN of each of the second stage ST2 to the nth stage STn as a start signal. The previous stage may be a stage located at least one stage before the current stage. In Figure 2 In the example, the previous stage is a stage immediately before the current stage. For example, the third gate signal GS[3] output from the third stage ST3 may be input to the input terminal IN of the fourth stage ST4 as a carry signal.

[0073] The first voltage VGH may be input to the first voltage input terminal V1, and the second voltage VGL may be input to the second voltage input terminal V2. The second voltage VGL may have a voltage level lower than that of the first voltage VGH. The first voltage VGH and the second voltage VGL are global signals and may be input from Figure 1 The first voltage VGH and the second voltage VGL may have voltage levels corresponding to a turn-on voltage or a turn-off voltage of a transistor.

[0074] The first clock signal CLK1 or the second clock signal CLK2 may be input to the first clock terminal CK1 and the second clock terminal CK2. The first clock signal CLK1 and the second clock signal CLK2 may be alternately input to the first clock terminal CK1 of the first stage ST1 to the nth stage STn. The second clock signal CLK2 and the first clock signal CLK1 may be alternately input to the second clock terminal CK2 of the first stage ST1 to the nth stage STn. For example, the first clock signal CLK1 and the second clock signal CLK2 may be input to the first clock terminal CK1 and the second clock terminal CK2 of the odd stage (e.g., ST1, ST3, ...), respectively. The second clock signal CLK2 and the first clock signal CLK1 may be input to the first clock terminal CK1 and the second clock terminal CK2 of the even stage (e.g., ST2, ST4, ...), respectively. For example, the first clock signal CLK1 may be supplied to the first clock terminal CK1 of the odd stage and the second clock terminal CK2 of the even stage. The second clock signal CLK2 may be supplied to the second clock terminal CK2 of the odd stage and the first clock terminal CK1 of the even stage.

[0075] like Figure 4As shown in, the first clock signal CLK1 and the second clock signal CLK2 can be square wave signals in which high level voltage and low level voltage are repeated. The high level voltage can correspond to the on-voltage of an N-type transistor or the cut-off voltage of a P-type transistor. The low level voltage can correspond to the cut-off voltage of an N-type transistor or the on-voltage of a P-type transistor. In an embodiment, the first clock signal CLK1 and the second clock signal CLK2 can be square wave signals in which the first voltage VGH and the second voltage VGL are repeated. The first voltage VGH can correspond to the on-voltage of an N-type transistor or the cut-off voltage of a P-type transistor. The second voltage VGL can correspond to the cut-off voltage of an N-type transistor or the on-voltage of a P-type transistor. The first clock signal CLK1 and the second clock signal CLK2 can have the same waveform and can be a phase shift signal. For example, the second clock signal CLK2 can have the same waveform as the waveform of the first clock signal CLK1, and can be input with its phase shifted (delayed) at a specific interval. The second clock signal CLK2 can be shifted by half a cycle relative to the first clock signal CLK1.

[0076] like Figure 4 As shown in, in the first clock signal CLK1 and the second clock signal CLK2, the period during which the high level voltage is maintained in one cycle can be longer than the period during which the low level voltage is maintained. The embodiment is not limited thereto. For example, in the first clock signal CLK1 and the second clock signal CLK2, the period during which the high level voltage is maintained in one cycle can be the same as the period during which the low level voltage is maintained.

[0077] The gate signal can be output from the output terminal OUT. The first to nth gate signals GS[1], GS[2], GS[3], GS[4], ... and GS[n] outputted from the output terminals OUT of the first stage ST1 to the nth stage STn, respectively, can be sequentially shifted for a specific period of time. Each gate signal can be supplied to the pixel through a corresponding output line (e.g., a gate line).

[0078] Hereinafter, the kth stage STka (where k is a natural number greater than 0) corresponding to the kth row of the pixel region 110 is described as an example. The kth stage STka can receive the k-1th gate signal GS[k-1] (hereinafter, referred to as the previous gate signal GS[k-1]) from the k-1th stage which is the previous stage as a start signal, can output the kth gate signal GS[k] to the gate line of the kth row, and can output the kth gate signal GS[k] as a carry signal to the k+1th stage which is the next stage.

[0079] In an odd-numbered stage, the first clock terminal CK1 can receive the first clock signal CLK1, and the second clock terminal CK2 can receive the second clock signal CLK2. In an even-numbered stage, the first clock terminal CK1 can receive the second clock signal CLK2, and the second clock terminal CK2 can receive the first clock signal CLK1. For ease of explanation, the following will be described assuming that the k-th stage STka (hereinafter, referred to as stage STka) is an odd-numbered stage, the first clock signal CLK1 is input to the first clock terminal CK1, and the second clock signal CLK2 is input to the second clock terminal CK2. When k is 1, that is, the first stage ST1 can receive the external signal FLM as a start signal through the input terminal IN.

[0080] In the following, the first voltage VGH may be represented as a high level voltage, and the second voltage VGL may be represented as a low level voltage. The low level may be represented as the first voltage level, and the high level may be represented as the second voltage level. The first voltage VGH may correspond to the turn-on voltage of an N-type transistor or the turn-off voltage of a P-type transistor. The second voltage VGL may correspond to the turn-off voltage of an N-type transistor or the turn-on voltage of a P-type transistor.

[0081] refer to Figure 3 , the stage STka may include a control circuit 131 and an output circuit 135. Each of the control circuit 131 and the output circuit 135 may include at least one transistor. The at least one transistor may include an N-type transistor and / or a P-type transistor. For example, the first transistor T11, the second transistor T12, the third transistor T13, the fifth transistor T15, and the sixth transistor T16 of the stage STka may be P-type transistors, and the fourth transistor T14 may be an N-type transistor. The gate-on voltage of the P-type transistor may be a low-level voltage, and the gate-off voltage of the P-type transistor may be a high-level voltage. The gate-on voltage of the N-type transistor may be a high-level voltage, and the gate-off voltage of the N-type transistor may be a low-level voltage.

[0082] The control circuit 131 may control the voltages of the first node Q1 and the second node QB1 in response to a signal input to the input terminal IN and the first clock terminal CK1. For example, the control circuit 131 may control the voltages of the first node Q1 and the second node QB1 in response to a start signal (eg, an external signal FLM (see Figure 2 ) or carry signal CR (see Figure 2 )) and the first clock signal CLK1 to control the voltages of the first node Q1 and the second node QB1. In an embodiment, the carry signal CR may be a previous gate signal GS[k-1]. The control circuit 131 may include first to fourth transistors T11 to T14.

[0083] The first transistor T11 may be connected between the input terminal IN and the first node Q1. The first transistor T11 may be connected between the input terminal IN and the second transistor T12. The gate of the first transistor T11 may be connected to the first clock terminal CK1. When the first clock signal CLK1 input to the first clock terminal CK1 is at a low level, the first transistor T11 may be turned on and the start signal input to the input terminal IN may be transmitted to the first node Q1.

[0084] The second transistor T12 may be connected between the input terminal IN and the first node Q1. The second transistor T12 may be connected between the first transistor T11 and the first node Q1. The gate of the second transistor T12 may be connected to the second voltage input terminal V2. The second transistor T12 may be turned on by the second voltage VGL input to the second voltage input terminal V2, and the start signal input by the first transistor T11 may be transmitted to the first node Q1. The second transistor T12 may always be in an on state, and the input terminal IN may be selectively electrically connected to the first node Q1 according to the voltage level of the first clock signal CLK1. Because the second transistor T12 shares the stress caused by the multi-stage voltage variation of the first node Q1 with the first transistor T11, the stress on the first transistor T11 may be relieved compared to the stage in which the second transistor T12 is omitted and the first transistor T11 is provided separately. In addition, when the first transistor T11 is turned off, the second transistor T12 may prevent the line voltage drop between the input terminal IN and the first node Q1.

[0085] The third transistor T13 may be connected between the second voltage input terminal V2 and the second node QB1. The gate of the third transistor T13 may be connected to the first clock terminal CK1. When the first clock signal CLK1 input to the first clock terminal CK1 is at a low level, the third transistor T13 may be turned on, and the second voltage VGL input to the second voltage input terminal V2 may be transmitted to the second node QB1. Because the second voltage VGL, which is a constant voltage, is used as a low-level voltage of the second node QB1 through the third transistor T13 instead of a carry signal, regardless of a carry signal defect, a high-level gate signal output may be reliably ensured.

[0086] The fourth transistor T14 may be connected between the first voltage input terminal V1 and the second node QB1. The gate of the fourth transistor T14 may be connected to the first clock terminal CK1. When the first clock signal CLK1 input to the first clock terminal CK1 is at a high level, the fourth transistor T14 may be turned on and the first voltage VGH input to the first voltage input terminal V1 may be transmitted to the second node QB1.

[0087] The output circuit 135 may be connected between the first voltage input terminal V1 and the second clock terminal CK2. The output circuit 135 may output a gate signal GS[k] having one of a high level voltage and a low level voltage according to the voltage levels of the first node Q1 and the second node QB1. The output circuit 135 may include a fifth transistor T15 and a sixth transistor T16. The output circuit 135 may further include a capacitor C1.

[0088] The fifth transistor T15 may be connected between the output terminal OUT and the second clock terminal CK2. The gate of the fifth transistor T15 may be connected to the first node Q1. The fifth transistor T15 may be a pull-down transistor that transmits a low-level voltage to the output terminal OUT. When the first node Q1 is at a low level, the fifth transistor T15 may be turned on and may transmit the second clock signal CLK2 input to the second clock terminal CK2 to the output terminal OUT.

[0089] The sixth transistor T16 may be connected between the first voltage input terminal V1 and the output terminal OUT. The gate of the sixth transistor T16 may be connected to the second node QB1. The sixth transistor T16 may be a pull-up transistor that transmits a high level voltage to the output terminal OUT. When the second node QB1 is at a low level, the sixth transistor T16 may be turned on and may transmit the first voltage VGH of the high level voltage input to the first voltage input terminal V1 to the output terminal OUT.

[0090] The capacitor C1 may be connected between the first node Q1 and the output terminal OUT. When the first transistor T11 is turned off, the voltage level of the first node Q1 may be maintained by the capacitor C1. When the voltage level at the output terminal OUT changes from a high level to a low level, the low level voltage of the first node Q1 may be changed to a lower low level voltage by the capacitor C1.

[0091] In the following, reference will be made to Figure 4 describe Figure 3 The operation of level STka. Figure 4 , a previous gate signal GS[k-1] as a start signal, a first clock signal CLK1, a second clock signal CLK2, a voltage VQ1 of a first node Q1, a voltage VQB1 of a second node QB1, and a gate signal GS[k] as an output signal are illustrated.

[0092] In the first interval P11, the low-level previous gate signal GS[k-1] can be supplied from the previous stage to the input terminal IN, the low-level first clock signal CLK1 can be supplied to the first clock terminal CK1, and the high-level second clock signal CLK2 can be supplied to the second clock terminal CK2.

[0093] The first transistor T11 and the third transistor T13 may be turned on by the first clock signal CLK1 of a low level. The second transistor T12 may be in a turned-on state due to the second voltage VGL of a low level.

[0094] The previous gate signal GS[k-1] of the low level can be transmitted to the first node Q1 through the turned-on first transistor T11 and second transistor T12, and the voltage VQ1 of the first node Q1 can be a low level voltage. Accordingly, the fifth transistor T15 can be turned on, and the second clock signal CLK2 of the high level can be transmitted to the output terminal OUT.

[0095] The low level second voltage VGL may be transmitted to the second node QB1 through the turned-on third transistor T13, and the voltage VQB1 of the second node QB1 may be a low level voltage. Accordingly, the sixth transistor T16 may be turned on, and the high level first voltage VGH may be transmitted to the output terminal OUT.

[0096] Accordingly, a high-level gate signal GS[k] may be output from the output terminal OUT. The voltage difference between the output terminal OUT and the first node Q1 may be stored in the capacitor C1. In an embodiment, the first clock signal CLK1 and the second clock signal CLK2 may have a high level corresponding to the high-level first voltage VGH and a low level corresponding to the low-level second voltage VGL. The gate signal GS[k] has a high level corresponding to the first voltage VGH in the first interval P11. In the first interval P11, the voltage difference between the output terminal OUT and the first node Q1 may correspond to the value of |VGH-VGL|.

[0097] In the second interval P12 , a high level previous gate signal GS[k−1] may be supplied to the input terminal IN, a high level first clock signal CLK1 may be supplied to the first clock terminal CK1 , and a high level second clock signal CLK2 may be supplied to the second clock terminal CK2 .

[0098] The first transistor T11 and the third transistor T13 may be turned off by the high-level first clock signal CLK1, and the fourth transistor T14 may be turned on. Due to the low-level second voltage VGL, the second transistor T12 may be in a turned-on state.

[0099] The high-level first voltage VGH may be transmitted to the second node QB1 through the turned-on fourth transistor T14 , and the voltage VQB1 of the second node QB1 may be a high-level voltage. Accordingly, the sixth transistor T16 may be turned off.

[0100] Since the first node Q1 maintains a low level voltage in the first interval P11 due to the capacitor C1, the conduction state of the fifth transistor T15 can be maintained, and thus, the high level second clock signal CLK2 can be transmitted to the output terminal OUT. Accordingly, a high level gate signal GS[k] can be output from the output terminal OUT.

[0101] In the third interval P13 , a high level previous gate signal GS[k−1] may be supplied to the input terminal IN, a high level first clock signal CLK1 may be supplied to the first clock terminal CK1 , and a low level second clock signal CLK2 may be supplied to the second clock terminal CK2 .

[0102] Since the first clock signal CLK1 maintains a high level, the first transistor T11 and the third transistor T13 are kept off, and the fourth transistor T14 is kept on. Due to the low level second voltage VGL, the second transistor T12 is turned on.

[0103] The high-level first voltage VGH may be transmitted to the second node QB1 through the turned-on fourth transistor T14 , and the voltage VQB1 of the second node QB1 may be a high-level voltage. Accordingly, the sixth transistor T16 may be turned off.

[0104] The low-level second clock signal CLK2 can be transmitted to the output terminal OUT through the fifth transistor T15 whose conductive state is maintained. Accordingly, a low-level gate signal GS[k] can be output from the output terminal OUT. Since the voltage of the output terminal OUT drops from a high level to a low level, the voltage VQ1 of the first node Q1 can drop to a voltage level lower than the voltage level in the second interval P12 due to the coupling of the capacitor C1. In an embodiment, the first clock signal CLK1 and the second clock signal CLK2 can have a high level corresponding to the high-level first voltage VGH and a low level corresponding to the low-level second voltage VGL. In the second interval P12, due to the first transistor T11 being turned off, charging or discharging of the capacitor C1 by the input terminal IN does not occur, and thus the capacitor C1 maintains a voltage difference of |VGH-VGL|. In the third interval P13, the voltage of the output terminal OUT, which is one electrode of the capacitor C1, drops from the first voltage VGH to the second voltage VGL, and thus the voltage of the other electrode of the capacitor C1 corresponding to the first node Q1 drops from the second voltage VGL to a voltage lower than the second voltage VGL.

[0105] In the fourth interval P14 , a high level previous gate signal GS[k−1] may be supplied to the input terminal IN, a high level first clock signal CLK1 may be supplied to the first clock terminal CK1 , and a high level second clock signal CLK2 may be supplied to the second clock terminal CK2 .

[0106] Since the first clock signal CLK1 maintains a high level, the first transistor T11 and the third transistor T13 are kept off, and the fourth transistor T14 is kept on. Due to the low level second voltage VGL, the second transistor T12 is turned on.

[0107] The high-level first voltage VGH may be transmitted to the second node QB1 through the turned-on fourth transistor T14 , and the voltage VQB1 of the second node QB1 may be a high-level voltage. Accordingly, the sixth transistor T16 may be turned off.

[0108] The high-level second clock signal CLK2 can be transmitted to the output terminal OUT through the fifth transistor T15 whose conductive state is maintained. Accordingly, a high-level gate signal GS[k] can be output from the output terminal OUT. Since the voltage of the output terminal OUT rises from a low level to a high level, the voltage VQ1 of the first node Q1 can rise to a low level higher than the voltage level in the third interval P13 (for example, about the voltage level in the second interval P12) due to the coupling of the capacitor C1. In an embodiment, the first clock signal CLK1 and the second clock signal CLK2 can have a high level corresponding to the first voltage VGH and a low level corresponding to the second voltage VGL. In the third interval P13, due to the first transistor T11 being turned off, charging or discharging of the capacitor C1 by the input terminal IN does not occur, and therefore the capacitor C1 maintains a voltage difference corresponding to the value of |VGH-VGL|. In the fourth interval P14 , the voltage of the output terminal OUT which is one electrode of the capacitor C1 increases from the second voltage VGL to the first voltage VGH, and thus the voltage of the other electrode of the capacitor C1 corresponding to the first node Q1 increases from a voltage lower than the second voltage VGL to the second voltage VGL.

[0109] In the fifth interval P15 , a high level previous gate signal GS[k−1] may be supplied to the input terminal IN, a low level first clock signal CLK1 may be supplied to the first clock terminal CK1 , and a high level second clock signal CLK2 may be supplied to the second clock terminal CK2 .

[0110] The first transistor T11 and the third transistor T13 may be turned on by the low-level first clock signal CLK1, and the fourth transistor T14 may be turned off. The second transistor T12 may be in a turned-on state due to the low-level second voltage VGL.

[0111] The high level previous gate signal GS[k-1] may be transmitted to the first node Q1 through the turned-on first and second transistors T11 and T12, and the voltage VQ1 of the first node Q1 may be a high level voltage. Therefore, the fifth transistor T15 may be turned off.

[0112] The low-level second voltage VGL may be transmitted to the second node QB1 through the turned-on third transistor T13, and the voltage VQB1 of the second node QB1 may be a low-level voltage. Accordingly, the sixth transistor T16 may be turned on, and the high-level first voltage VGH may be transmitted to the output terminal OUT. Accordingly, a high-level gate signal GS[k] may be output from the output terminal OUT. In an embodiment, the first clock signal CLK1 and the second clock signal CLK2 may have a high level corresponding to the first voltage VGH and a low level corresponding to the second voltage VGL. In the fifth interval P15, the discharge of the capacitor C1 from the input terminal IN occurs due to the turned-on first transistor T11, and since the voltage of the output terminal OUT is the same as the voltage VQ1 of the first node Q1, no charge is stored in the capacitor C1 in the fifth interval P15.

[0113] Figure 5 and Figure 6 The diagram is included in Figure 2 The following is a circuit diagram of an example of a gate driver circuit of the stage. Figure 3 The difference between the levels.

[0114] Figure 5 Level and Figure 3 The stage STka of FIG. 1 is different in that the second transistor T12 is omitted and a capacitor C12 is provided, and the other elements and operations are the same as those of FIG. Figure 3 The other elements and operations of the stage STka are the same. The capacitor C12 may be connected between the first node Q1 and the second voltage input terminal V2. The capacitor C12 may relieve stress caused on the first transistor T11 due to multi-level voltage variations of the first node Q1.

[0115] Figure 6 Level and Figure 3 The difference of the stage STka is that the second transistor T12 has a structure in which a plurality of sub-transistors are connected in series to each other, and other elements and operations are the same as those of the Figure 3The other elements and operations of the stage STka are the same. The second transistor T12 may include a plurality of sub-transistors connected in series between the first transistor T11 and the first node Q1. The sub-transistor may include a pair of sub-transistors (i.e., a first sub-transistor T12-1 and a second sub-transistor T12-2). The gates of the first sub-transistor T12-1 and the second sub-transistor T12-2 may be connected to the second voltage input terminal V2. Due to the second voltage VGL input to the second voltage input terminal V2, the first sub-transistor T12-1 and the second sub-transistor T12-2 may always be in a conducting state.

[0116] Figure 7 The diagram is included in Figure 2 A circuit diagram of an example of a stage in a gate driver circuit. Figure 8 Is used to describe Figure 7 A timing diagram of the operation of the stage.

[0117] Figure 7 The level is the kth level STkb (wherein k is a natural number greater than 0) corresponding to the kth row of the pixel area 110, and can receive the k-1th gate signal GS[k-1] as a start signal from the k-1th level which is the previous level, can output the kth gate signal GS[k] to the gate line of the kth row, and can output the kth gate signal GS[k] as a carry signal to the k+1th level which is the next level.

[0118] The stage STkb may include a control circuit 141 and an output circuit 145. Each of the control circuit 141 and the output circuit 145 may include at least one transistor. The at least one transistor may include an N-type transistor and / or a P-type transistor. For example, the first transistor T21, the second transistor T22, the fifth transistor T25, and the sixth transistor T26 of the stage STkb may be P-type transistors, and the third transistor T23 and the fourth transistor T24 may be N-type transistors.

[0119] The control circuit 141 may control the voltages of the first node Q2 and the second node QB2 in response to signals input to the input terminal IN, the first clock terminal CK1, and the second clock terminal CK2. For example, the control circuit 141 may control the voltages of the first node Q2 and the second node QB2 in response to a start signal (eg, an external signal FLM (see Figure 2 ) or carry signal CR (see Figure 2 )), the first clock signal CLK1 and the second clock signal CLK2 to control the voltage of the first node Q2 and the second node QB2. In an embodiment, the carry signal CR may be the previous gate signal GS[k-1]. The control circuit 141 may include first to fourth transistors T21 to T24.

[0120] The first transistor T21 may be connected between the input terminal IN and the first node Q2. The first transistor T21 may be connected between the input terminal IN and the second transistor T22. The gate of the first transistor T21 may be connected to the first clock terminal CK1. When the first clock signal CLK1 input to the first clock terminal CK1 is at a low level, the first transistor T21 may be turned on, and the start signal input to the input terminal IN may be transmitted to the first node Q2.

[0121] The second transistor T22 may be connected between the input terminal IN and the first node Q2. The second transistor T22 may be connected between the first transistor T21 and the first node Q2. The gate of the second transistor T22 may be connected to the second voltage input terminal V2. The second transistor T22 may be turned on by the second voltage VGL input to the second voltage input terminal V2, and the start signal input by the first transistor T21 may be transmitted to the first node Q2. The second transistor T22 may always be in an on state. Because the second transistor T22 shares the stress caused by the multi-stage voltage variation of the first node Q2 with the first transistor T21, the stress on the first transistor T21 may be alleviated compared to the stage in which the second transistor T22 is omitted and the first transistor T21 is provided separately. In addition, when the first transistor T21 is turned off, the second transistor T22 may prevent the line voltage drop between the input terminal IN and the first node Q2.

[0122] The third transistor T23 may be connected between the input terminal IN and the second node QB2. The gate of the third transistor T23 may be connected to the first clock terminal CK1. When the first clock signal CLK1 input to the first clock terminal CK1 is at a high level, the third transistor T23 may be turned on and the start signal input to the input terminal IN may be transmitted to the second node QB2.

[0123] The fourth transistor T24 may be connected between the first clock terminal CK1 and the second node QB2. The gate of the fourth transistor T24 may be connected to the second clock terminal CK2. When the second clock signal CLK2 input to the second clock terminal CK2 is at a high level, the fourth transistor T24 may be turned on and the first clock signal CLK1 input to the first clock terminal CK1 may be transmitted to the second node QB2.

[0124] The output circuit 145 may be connected between the first voltage input terminal V1 and the second clock terminal CK2. The output circuit 145 may output a gate signal GS[k] having one of a high level voltage and a low level voltage according to the voltage levels of the first node Q2 and the second node QB2. The output circuit 145 may include a fifth transistor T25 and a sixth transistor T26. The output circuit 145 may further include a capacitor C2.

[0125] The fifth transistor T25 may be connected between the output terminal OUT and the second clock terminal CK2. The gate of the fifth transistor T25 may be connected to the first node Q2. The fifth transistor T25 may be a pull-down transistor that transmits a low-level voltage to the output terminal OUT. When the first node Q2 is at a low level, the fifth transistor T25 may be turned on and may transmit the second clock signal CLK2 input to the second clock terminal CK2 to the output terminal OUT.

[0126] The sixth transistor T26 may be connected between the first voltage input terminal V1 and the output terminal OUT. The gate of the sixth transistor T26 may be connected to the second node QB2. The sixth transistor T26 may be a pull-up transistor that transmits a high level voltage to the output terminal OUT. When the second node QB2 is at a low level, the sixth transistor T26 may be turned on and may output the first voltage VGH of the high level voltage input to the first voltage input terminal V1 to the output terminal OUT.

[0127] The capacitor C2 may be connected between the output terminal OUT and the first node Q2. When the first transistor T21 is turned off, the voltage level of the first node Q2 may be maintained by the capacitor C2. When the voltage level at the output terminal OUT changes from a high level to a low level, the low level voltage of the first node Q2 may be changed to a lower low level voltage by the capacitor C2.

[0128] In the following, reference will be made to Figure 8 describe Figure 7 The STkb level is used for operation. Figure 8 , the previous gate signal GS[k-1] as a start signal, the first clock signal CLK1, the second clock signal CLK2, the voltage VQ2 of the first node Q2, the voltage VQB2 of the second node QB2, and the gate signal GS[k] as an output signal are illustrated.

[0129] In the first interval P21, the low-level previous gate signal GS[k-1] can be supplied from the previous stage to the input terminal IN, the low-level first clock signal CLK1 can be supplied to the first clock terminal CK1, and the high-level second clock signal CLK2 can be supplied to the second clock terminal CK2.

[0130] The first transistor T21 may be turned on by the low-level first clock signal CLK1, and the third transistor T23 may be turned off. The fourth transistor T24 may be turned on by the high-level second clock signal CLK2. Due to the low-level second voltage VGL, the second transistor T22 may be in a turned-on state.

[0131] The previous gate signal GS[k-1] of the low level can be transmitted to the first node Q2 through the turned-on first transistor T21 and second transistor T22, and the voltage VQ2 of the first node Q2 can be a low level voltage. Accordingly, the fifth transistor T25 can be turned on, and the second clock signal CLK2 of the high level can be transmitted to the output terminal OUT.

[0132] The previous gate signal GS[k-1] of the low level cannot be transmitted to the second node QB2 through the turned-off third transistor T23. The first clock signal CLK1 of the low level can be transmitted to the second node QB2 through the fourth transistor T24 turned on by the second clock signal CLK2 of the high level. Accordingly, the sixth transistor T26 can be turned on, and the first voltage VGH of the high level can be transmitted to the output terminal OUT.

[0133] Accordingly, a high-level gate signal GS[k] may be output from the output terminal OUT. The voltage difference between the output terminal OUT and the first node Q2 may be stored in the capacitor C2. In an embodiment, the first clock signal CLK1 and the second clock signal CLK2 may have a high level corresponding to the high-level first voltage VGH and a low level corresponding to the low-level second voltage VGL. The gate signal GS[k] has a high level corresponding to the first voltage VGH in the first interval P21. In the first interval P21, the voltage difference between the output terminal OUT and the first node Q2 may correspond to the value of |VGH-VGL|.

[0134] In the second interval P22 , a high level previous gate signal GS[k−1] may be supplied to the input terminal IN, a high level first clock signal CLK1 may be supplied to the first clock terminal CK1 , and a high level second clock signal CLK2 may be supplied to the second clock terminal CK2 .

[0135] The first transistor T21 may be turned off by the high-level first clock signal CLK1, and the third transistor T23 may be turned on. The fourth transistor T24 may be turned on by the high-level second clock signal CLK2. Due to the low-level second voltage VGL, the second transistor T22 may be in a turned-on state.

[0136] The high-level previous gate signal GS[k-1] may be transmitted to the second node QB2 through the turned-on third transistor T23, the high-level first clock signal CLK1 may be transmitted to the second node QB2 through the turned-on fourth transistor T24, and the voltage VQB2 of the second node QB2 may be a high-level voltage. Accordingly, the sixth transistor T26 may be turned off.

[0137] Since the first node Q2 maintains a low level voltage in the first interval P21 due to the capacitor C2, the conductive state of the fifth transistor T25 can be maintained, and thus, the high level second clock signal CLK2 can be transmitted to the output terminal OUT. Accordingly, a high level gate signal GS[k] can be output from the output terminal OUT.

[0138] In the third interval P23 , a high level previous gate signal GS[k−1] may be supplied to the input terminal IN, a high level first clock signal CLK1 may be supplied to the first clock terminal CK1 , and a low level second clock signal CLK2 may be supplied to the second clock terminal CK2 .

[0139] Because the first clock signal CLK1 maintains a high level, the off state of the first transistor T21 can be maintained, and the on state of the third transistor T23 can be maintained. The fourth transistor T24 can be turned off by the low-level second clock signal CLK2. Due to the low-level second voltage VGL, the second transistor T22 can be in a conducting state.

[0140] The high level previous gate signal GS[k-1] may be transmitted to the second node QB2 through the turned-on third transistor T23, and the voltage VQB2 of the second node QB2 may be a high level voltage. Accordingly, the sixth transistor T26 may be turned off.

[0141] The second clock signal CLK2 of low level can be transmitted to the output terminal OUT through the fifth transistor T25 whose conductive state is maintained. Accordingly, the gate signal GS[k] of low level can be output from the output terminal OUT. Since the voltage of the output terminal OUT drops from the high level to the low level, the voltage VQ2 of the first node Q2 can drop to a voltage level lower than the voltage level in the second interval P22 due to the coupling of the capacitor C2. In an embodiment, the first clock signal CLK1 and the second clock signal CLK2 can have a high level corresponding to the first voltage VGH of the high level and a low level corresponding to the second voltage VGL of the low level. In the second interval P22, due to the first transistor T21 being turned off, the charging or discharging of the capacitor C2 by the input terminal IN does not occur, and thus the capacitor C2 maintains a voltage difference of |VGH-VGL|. In the third interval P23, the voltage of the output terminal OUT, which is one electrode of the capacitor C2, drops from the first voltage VGH to the second voltage VGL, and thus the voltage of the other electrode of the capacitor C2 corresponding to the first node Q2 drops from the second voltage VGL to a voltage lower than the second voltage VGL.

[0142] In the fourth interval P24 , a high level previous gate signal GS[k−1] may be supplied to the input terminal IN, a high level first clock signal CLK1 may be supplied to the first clock terminal CK1 , and a high level second clock signal CLK2 may be supplied to the second clock terminal CK2 .

[0143] Because the first clock signal CLK1 maintains a high level, the cut-off state of the first transistor T21 can be maintained, and the on state of the third transistor T23 can be maintained. The fourth transistor T24 can be turned on by the high-level second clock signal CLK2. Due to the low-level second voltage VGL, the second transistor T22 can be in a turned-on state.

[0144] The high-level previous gate signal GS[k-1] may be transmitted to the second node QB2 through the turned-on third transistor T23, the high-level first clock signal CLK1 may be transmitted to the second node QB2 through the turned-on fourth transistor T24, and the voltage VQB2 of the second node QB2 may be a high-level voltage. Accordingly, the sixth transistor T26 may be turned off.

[0145] The high-level second clock signal CLK2 can be transmitted to the output terminal OUT through the fifth transistor T25 whose conductive state is maintained. Accordingly, a high-level gate signal GS[k] can be output from the output terminal OUT. Since the voltage of the output terminal OUT rises from a low level to a high level, the voltage VQ2 of the first node Q2 can rise to a low level higher than the voltage level in the third interval P23 (for example, about the voltage level in the second interval P22) due to the coupling of the capacitor C2. In an embodiment, the first clock signal CLK1 and the second clock signal CLK2 can have a high level corresponding to the first voltage VGH and a low level corresponding to the second voltage VGL. In the third interval P23, due to the first transistor T21 being turned off, charging or discharging of the capacitor C2 by the input terminal IN does not occur, and therefore the capacitor C2 maintains a voltage difference corresponding to the value of |VGH-VGL|. In the fourth interval P24, the voltage of the output terminal OUT which is one electrode of the capacitor C2 increases from the second voltage VGL to the first voltage VGH, and thus the voltage of the other electrode of the capacitor C2 corresponding to the first node Q2 increases from a voltage lower than the second voltage VGL to the second voltage VGL.

[0146] In the fifth interval P25 , a high level previous gate signal GS[k−1] may be supplied to the input terminal IN, a low level first clock signal CLK1 may be supplied to the first clock terminal CK1 , and a high level second clock signal CLK2 may be supplied to the second clock terminal CK2 .

[0147] The first transistor T21 may be turned on by the low-level first clock signal CLK1, and the third transistor T23 may be turned off. The fourth transistor T24 may be turned on by the high-level second clock signal CLK2. Due to the low-level second voltage VGL, the second transistor T22 may be in a turned-on state.

[0148] The high level previous gate signal GS[k-1] may be transmitted to the first node Q2 through the turned-on first and second transistors T21 and T22, and the voltage VQ2 of the first node Q2 may be a high level voltage. Therefore, the fifth transistor T25 may be turned off.

[0149] The low-level first clock signal CLK1 can be transmitted to the second node QB2 through the turned-on fourth transistor T24, and the voltage VQB2 of the second node QB2 can be a low-level voltage. Accordingly, the sixth transistor T26 can be turned on, and the high-level first voltage VGH can be transmitted to the output terminal OUT. Accordingly, a high-level gate signal GS[k] can be output from the output terminal OUT. In an embodiment, the first clock signal CLK1 and the second clock signal CLK2 can have a high level corresponding to the first voltage VGH and a low level corresponding to the second voltage VGL. In the fifth interval P25, the discharge of the input terminal IN to the capacitor C2 occurs due to the turned-on first transistor T21, and since the voltage of the output terminal OUT is the same as the voltage VQ2 of the first node Q2, no charge is stored in the capacitor C2 in the fifth interval P25.

[0150] Fig. 9 and Fig.10 The diagram is included in Figure 2 The following is a circuit diagram of an example of a gate driver circuit of the stage. Figure 7 The difference between the levels.

[0151] Fig. 9 Level and Figure 7 The stage STkb is different in that the second transistor T22 is omitted and a capacitor C22 is provided, and the other elements and operations are the same as those of the Figure 7 The other elements and operations of the stage STkb are the same. The capacitor C22 may be connected between the first node Q2 and the second voltage input terminal V2. The capacitor C22 may relieve stress caused on the first transistor T21 due to multi-level voltage variations of the first node Q2.

[0152] Fig.10 Level and Figure 7 The stage STkb is different in that the second transistor T22 has a structure in which a plurality of sub-transistors are connected in series, and other elements and operations are the same as those of the Figure 7The other elements and operations of the stage STkb are the same. The second transistor T22 may include a plurality of sub-transistors connected in series between the first transistor T21 and the first node Q2. The sub-transistor may include a pair of sub-transistors, namely a first sub-transistor T22-1 and a second sub-transistor T22-2. The gates of the first sub-transistor T22-1 and the second sub-transistor T22-2 may be connected to the second voltage input terminal V2. Due to the second voltage VGL input to the second voltage input terminal V2, the first sub-transistor T22-1 and the second sub-transistor T22-2 may always be in a conducting state.

[0153] Fig.11 The diagram is included in Figure 2 A circuit diagram of an example of a stage in a gate driver circuit. Fig.12 Is used to describe Fig.11 A timing diagram of the operation of the stage.

[0154] Fig.11 The level is the kth level STkc (wherein k is a natural number greater than 0) corresponding to the kth row of the pixel area 110, and can receive the k-1th gate signal GS[k-1] as a start signal from the k-1th level which is the previous level, can output the kth gate signal GS[k] to the gate line of the kth row, and can output the kth gate signal GS[k] as a carry signal to the k+1th level which is the next level.

[0155] The stage STkc may include a control circuit 151 and an output circuit 155. Each of the control circuit 151 and the output circuit 155 may include at least one transistor. The at least one transistor may include an N-type transistor and / or a P-type transistor. For example, the first transistor T31, the second transistor T32, the fourth transistor T34, the fifth transistor T35, and the sixth transistor T36 of the stage STkc may be P-type transistors, and the third transistor T33 may be an N-type transistor.

[0156] The control circuit 151 may control the voltages of the first node Q3 and the second node QB3 in response to a signal input to the input terminal IN and the first clock terminal CK1. For example, the control circuit 151 may control the voltages of the first node Q3 and the second node QB3 in response to a start signal (eg, an external signal FLM (see Figure 2 ) or carry signal CR (see Figure 2 )) and the first clock signal CLK1 to control the voltage of the first node Q3 and the second node QB3. In an embodiment, the carry signal CR may be a previous gate signal GS[k-1]. The control circuit 151 may include a first transistor T31 to a fourth transistor T34. For example, the carry signal CR as a start signal of the current stage STkc may correspond to the gate signal GS[k-1] of the previous stage. The start signal of the first stage ST1 may be an external signal FLM.

[0157] The first transistor T31 may be connected between the input terminal IN and the first node Q3. The first transistor T31 may be connected between the input terminal IN and the second transistor T32. The gate of the first transistor T31 may be connected to the first clock terminal CK1. When the first clock signal CLK1 input to the first clock terminal CK1 is at a low level, the first transistor T31 may be turned on, and the start signal input to the input terminal IN may be transmitted to the first node Q3.

[0158] The second transistor T32 may be connected between the input terminal IN and the first node Q3. The second transistor T32 may be connected between the first transistor T31 and the first node Q3. The gate of the second transistor T32 may be connected to the second voltage input terminal V2. The second transistor T32 may be turned on by the second voltage VGL input to the second voltage input terminal V2, and the start signal input by the first transistor T31 may be transmitted to the first node Q3. The second transistor T32 may always be in an on state. Because the second transistor T32 shares the stress caused by the multi-stage voltage variation of the first node Q3 with the first transistor T31, the stress on the first transistor T31 may be alleviated compared to the stage in which the second transistor T32 is omitted and the first transistor T31 is provided separately. In addition, when the first transistor T31 is turned off, the second transistor T32 may prevent the line voltage drop between the input terminal IN and the first node Q3.

[0159] The third transistor T33 may be connected between the input terminal IN and the second node QB3. The gate of the third transistor T33 may be connected to the first clock terminal CK1. When the first clock signal CLK1 input to the first clock terminal CK1 is at a high level, the third transistor T33 may be turned on and the start signal input to the input terminal IN may be transmitted to the second node QB3.

[0160] The fourth transistor T34 may be connected between the second node QB3 and the second voltage input terminal V2. The gate of the fourth transistor T34 may be connected to the first clock terminal CK1. When the first clock signal CLK1 input to the first clock terminal CK1 is at a low level, the fourth transistor T34 may be turned on, and the second voltage VGL input to the second voltage input terminal V2 may be transmitted to the second node QB3. Since the second voltage VGL, which is a constant voltage, is used as a low-level voltage of the second node QB3 through the fourth transistor T34 instead of a clock signal, a high-level gate signal output may be reliably ensured.

[0161] The output circuit 155 may be connected between the first voltage input terminal V1 and the second clock terminal CK2. The output circuit 155 may output a gate signal GS[k] having one of a high level voltage and a low level voltage according to the voltage levels of the first node Q3 and the second node QB3. The output circuit 155 may include a fifth transistor T35 and a sixth transistor T36. The output circuit 155 may further include a capacitor C3.

[0162] The fifth transistor T35 may be connected between the output terminal OUT and the second clock terminal CK2. The gate of the fifth transistor T35 may be connected to the first node Q3. The fifth transistor T35 may be a pull-down transistor that transmits a low-level voltage to the output terminal OUT. When the first node Q3 is at a low level, the fifth transistor T35 may be turned on, and the second clock signal CLK2 input to the second clock terminal CK2 may be transmitted to the output terminal OUT.

[0163] The sixth transistor T36 may be connected between the first voltage input terminal V1 and the output terminal OUT. The gate of the sixth transistor T36 may be connected to the second node QB3. The sixth transistor T36 may be a pull-up transistor that transmits a high level voltage to the output terminal OUT. When the second node QB3 is at a low level, the sixth transistor T36 may be turned on and may output the first voltage VGH of the high level voltage input to the first voltage input terminal V1 to the output terminal OUT.

[0164] The capacitor C3 may be connected between the output terminal OUT and the first node Q3. When the first transistor T31 is turned off, the voltage level of the first node Q3 may be maintained by the capacitor C3. When the voltage level at the output terminal OUT changes from a high level to a low level, the low level voltage of the first node Q3 may be changed to a lower low level voltage by the capacitor C3.

[0165] In the following, reference will be made to Fig.12 describe Fig.11 The operation of the STkc stage. Fig.12 , the previous gate signal GS[k-1] as a start signal, the first clock signal CLK1, the second clock signal CLK2, the voltage VQ3 of the first node Q3, the voltage VQB3 of the second node QB3, and the gate signal GS[k] as an output signal are illustrated.

[0166] In the first interval P31, the low-level previous gate signal GS[k-1] can be supplied from the previous stage to the input terminal IN, the low-level first clock signal CLK1 can be supplied to the first clock terminal CK1, and the high-level second clock signal CLK2 can be supplied to the second clock terminal CK2.

[0167] The first transistor T31 and the fourth transistor T34 may be turned on by the low-level first clock signal CLK1, and the third transistor T33 may be turned off. Due to the low-level second voltage VGL, the second transistor T32 may be in a turned-on state.

[0168] The previous gate signal GS[k-1] of the low level can be transmitted to the first node Q3 through the turned-on first transistor T31 and second transistor T32, and the voltage VQ3 of the first node Q3 can be a low level voltage. Accordingly, the fifth transistor T35 can be turned on, and the second clock signal CLK2 of the high level can be transmitted to the output terminal OUT.

[0169] The low level second voltage VGL may be transmitted to the second node QB3 through the turned-on fourth transistor T34, and the voltage VQB3 of the second node QB3 may be a low level voltage. Accordingly, the sixth transistor T36 may be turned on, and the high level first voltage VGH may be transmitted to the output terminal OUT.

[0170] Accordingly, a high-level gate signal GS[k] may be output from the output terminal OUT. A voltage difference between the output terminal OUT and the first node Q3 may be stored in the capacitor C3. In an embodiment, the first clock signal CLK1 and the second clock signal CLK2 may have a high level corresponding to the high-level first voltage VGH and a low level corresponding to the low-level second voltage VGL. The gate signal GS[k] has a high level corresponding to the first voltage VGH in the first interval P31. The voltage difference between the output terminal OUT and the first node Q3 may correspond to the value of |VGH-VGL|.

[0171] In the second interval P32 , a high level previous gate signal GS[k−1] may be supplied to the input terminal IN, a high level first clock signal CLK1 may be supplied to the first clock terminal CK1 , and a high level second clock signal CLK2 may be supplied to the second clock terminal CK2 .

[0172] The first transistor T31 and the fourth transistor T34 may be turned off by the high-level first clock signal CLK1, and the third transistor T33 may be turned on. Due to the low-level second voltage VGL, the second transistor T32 may be in a turned-on state.

[0173] The high level previous gate signal GS[k-1] may be transmitted to the second node QB3 through the turned-on third transistor T33, and the voltage VQB3 of the second node QB3 may be a high level voltage. Accordingly, the sixth transistor T36 may be turned off.

[0174] Since the first node Q3 maintains a low level voltage in the first interval P31 due to the capacitor C3, the conductive state of the fifth transistor T35 can be maintained, and thus, the high level second clock signal CLK2 can be transmitted to the output terminal OUT. Accordingly, a high level gate signal GS[k] can be output from the output terminal OUT.

[0175] In the third interval P33 , a high level previous gate signal GS[k−1] may be supplied to the input terminal IN, a high level first clock signal CLK1 may be supplied to the first clock terminal CK1 , and a low level second clock signal CLK2 may be supplied to the second clock terminal CK2 .

[0176] Since the first clock signal CLK1 maintains a high level, the off states of the first and fourth transistors T31 and T34 may be maintained, and the on state of the third transistor T33 may be maintained. Due to the low level second voltage VGL, the second transistor T32 may be in an on state.

[0177] The high level previous gate signal GS[k-1] may be transmitted to the second node QB3 through the turned-on third transistor T33, and the voltage VQB3 of the second node QB3 may be a high level voltage. Accordingly, the sixth transistor T36 may be turned off.

[0178] The second clock signal CLK2 of low level can be transmitted to the output terminal OUT through the fifth transistor T35 whose conductive state is maintained. Accordingly, the gate signal GS[k] of low level can be output from the output terminal OUT. Since the voltage of the output terminal OUT drops from the high level to the low level, the voltage VQ3 of the first node Q3 can drop to a voltage level lower than the voltage level in the second interval P32 due to the coupling of the capacitor C3. In an embodiment, the first clock signal CLK1 and the second clock signal CLK2 can have a high level corresponding to the first voltage VGH of the high level and a low level corresponding to the second voltage VGL of the low level. In the second interval P32, due to the first transistor T31 being turned off, the charging or discharging of the capacitor C3 by the input terminal IN does not occur, and thus the capacitor C3 maintains a voltage difference of |VGH-VGL|. In the third interval P33, the voltage of the output terminal OUT, which is one electrode of the capacitor C3, drops from the first voltage VGH to the second voltage VGL, and thus the voltage of the other electrode of the capacitor C3 corresponding to the first node Q3 drops from the second voltage VGL to a voltage lower than the second voltage VGL.

[0179] In the fourth interval P34 , a high level previous gate signal GS[k−1] may be supplied to the input terminal IN, a high level first clock signal CLK1 may be supplied to the first clock terminal CK1 , and a high level second clock signal CLK2 may be supplied to the second clock terminal CK2 .

[0180] Since the first clock signal CLK1 maintains a high level, the off states of the first and fourth transistors T31 and T34 may be maintained, and the on state of the third transistor T33 may be maintained. Due to the low level second voltage VGL, the second transistor T32 may be in an on state.

[0181] The high level previous gate signal GS[k-1] may be transmitted to the second node QB3 through the turned-on third transistor T33, and the voltage VQB3 of the second node QB3 may be a high level voltage. Accordingly, the sixth transistor T36 may be turned off.

[0182] The high-level second clock signal CLK2 can be transmitted to the output terminal OUT through the fifth transistor T35 whose conductive state is maintained. Accordingly, a high-level gate signal GS[k] can be output from the output terminal OUT. Since the voltage of the output terminal OUT rises from a low level to a high level, the voltage VQ3 of the first node Q3 can rise to a low level higher than the voltage level in the third interval P33 (e.g., about the voltage level in the second interval P32) due to the coupling of the capacitor C3. In an embodiment, the first clock signal CLK1 and the second clock signal CLK2 can have a high level corresponding to the first voltage VGH and a low level corresponding to the second voltage VGL. In the third interval P33, due to the first transistor T31 being turned off, charging or discharging of the capacitor C3 by the input terminal IN does not occur, and therefore the capacitor C3 maintains a voltage difference corresponding to the value of |VGH-VGL|. In the fourth interval P34, the voltage of the output terminal OUT which is one electrode of the capacitor C3 increases from the second voltage VGL to the first voltage VGH, and thus the voltage of the other electrode of the capacitor C3 corresponding to the first node Q3 increases from a voltage lower than the second voltage VGL to the second voltage VGL.

[0183] In the fifth interval P35 , a high level previous gate signal GS[k−1] may be supplied to the input terminal IN, a low level first clock signal CLK1 may be supplied to the first clock terminal CK1 , and a high level second clock signal CLK2 may be supplied to the second clock terminal CK2 .

[0184] The first transistor T31 and the fourth transistor T34 may be turned on by the low-level first clock signal CLK1, and the third transistor T33 may be turned off. Due to the low-level second voltage VGL, the second transistor T32 may be in a turned-on state.

[0185] The high level previous gate signal GS[k-1] may be transmitted to the first node Q3 through the turned-on first and second transistors T31 and T32, and the voltage VQ3 of the first node Q3 may be a high level voltage. Accordingly, the fifth transistor T35 may be turned off.

[0186] The low-level second voltage VGL can be transmitted to the second node QB3 through the turned-on fourth transistor T34, and the voltage VQB3 of the second node QB3 can be a low-level voltage. Accordingly, the sixth transistor T36 can be turned on, and the high-level first voltage VGH can be transmitted to the output terminal OUT. Accordingly, a high-level gate signal GS[k] can be output from the output terminal OUT. In an embodiment, the first clock signal CLK1 and the second clock signal CLK2 can have a high level corresponding to the first voltage VGH and a low level corresponding to the second voltage VGL. In the fifth interval P35, the discharge of the input terminal IN to the capacitor C3 occurs due to the turned-on first transistor T31, and since the voltage of the output terminal OUT is the same as the voltage VQ3 of the first node Q3, no charge is stored in the capacitor C3 in the fifth interval P35.

[0187] Fig.13 and Fig.14 The diagram is included in Figure 2 The following is a circuit diagram of an example of a gate driver circuit of the stage. Fig.11 The difference between the levels.

[0188] Fig.13 Level and Fig.11 The stage STkc of FIG. 1 is different in that the second transistor T32 is omitted and a capacitor C32 is provided, and the other elements and operations are the same as those of FIG. 1 . Fig.11 The other elements and operations of the stage STkc are the same. The capacitor C32 may be connected between the first node Q3 and the second voltage input terminal V2. The capacitor C32 may relieve stress caused on the first transistor T31 due to multi-level voltage variations of the first node Q3.

[0189] Fig.14 Level and Fig.11 The stage STkc is different in that the second transistor T32 has a structure in which a plurality of sub-transistors are connected in series, and other elements and operations are the same as those of the Fig.11The other elements and operations of the stage STkc are the same. The second transistor T32 may include a plurality of sub-transistors connected in series between the first transistor T31 and the first node Q3. The sub-transistor may include a pair of sub-transistors, namely a first sub-transistor T32-1 and a second sub-transistor T32-2. The gates of the first sub-transistor T32-1 and the second sub-transistor T32-2 may be connected to the second voltage input terminal V2. Due to the second voltage VGL input to the second voltage input terminal V2, the first sub-transistor T32-1 and the second sub-transistor T32-2 may always be in a conducting state.

[0190] According to an embodiment, the voltage levels of a node connected to the gate of a pull-up transistor and a node connected to the gate of a pull-down transistor can be independently controlled without controlling the voltage level of a node connected to the gate of the pull-down transistor to be inverted according to the voltage level of the node connected to the gate of the pull-up transistor, or without controlling the voltage level of a node connected to the gate of the pull-up transistor to be inverted according to the voltage level of the node connected to the gate of the pull-down transistor.

[0191] According to the embodiment, a driving circuit which can be configured with a small number of transistors and capacitors to minimize a dead zone and can stably output a gate signal, and a display device including the driving circuit can be provided.

[0192] According to the embodiment, a gate driving circuit that can be composed of a small number of circuit devices to reduce the area of ​​a non-display region and stably output a gate signal and a display device including the gate driving circuit can be provided. The effects of the present disclosure are not limited to the above effects and can be changed without departing from the scope of the present disclosure.

[0193] It should be understood that the embodiments described herein should be considered as merely descriptive and not for limiting purposes. The description of features or aspects in each embodiment should typically be considered as other similar features or aspects that can be used in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various modifications in form and detail may be made thereto without departing from the spirit and scope as defined by the claims.

Claims

1. A driving circuit comprising a plurality of stages for outputting a plurality of gate signals to a plurality of pixels, in, Each of the plurality of stages comprises: a first transistor connected between a first terminal and a first node and configured to control a voltage level of the first node, wherein the first terminal receives a first signal; a second transistor connected between a second terminal and a second node and configured to control a voltage level of the second node, wherein the second terminal receives a second signal; a third transistor connected between a third terminal and the second node and configured to control the voltage level of the second node, wherein the third terminal receives a third signal; and An output circuit is configured to output a corresponding gate signal having one of a high level voltage and a low level voltage among the plurality of gate signals according to the voltage level of the first node and the voltage level of the second node.

2. The driving circuit according to claim 1, in, The plurality of stages include a first stage, a final stage, and a plurality of intermediate stages connected in series with each other, wherein the plurality of intermediate stages are connected in series with each other and are arranged between the first stage and the last stage, and wherein the first stage receives an external signal as the first signal, and Wherein, each of the last stage and the plurality of intermediate stages receives a corresponding gate signal among the plurality of gate signals output from a previous stage among the plurality of stages.

3. The driving circuit according to claim 1, in, A gate of each of the first transistor, the second transistor, and the third transistor is connected to a first clock terminal receiving a first clock signal, wherein the first transistor and the second transistor are P-type transistors, and Wherein, the third transistor is an N-type transistor.

4. The driving circuit according to claim 3, wherein: The second signal is a first voltage of a low level, and The third signal is a second voltage of a high level.

5. The driving circuit according to claim 1, in, A gate of each of the first transistor, the second transistor, and the third transistor is connected to a first clock terminal receiving a first clock signal, Wherein, the first transistor and the third transistor are P-type transistors, and Wherein, the second transistor is an N-type transistor.

6. The driving circuit according to claim 5, wherein: The second signal is the same signal as the first signal, and The third signal is a first voltage of a low level.

7. The driving circuit according to claim 1, wherein: A gate of each of the first transistor and the second transistor is connected to a first clock terminal to which a first clock signal is input, The gate of the third transistor is connected to a second clock terminal to which a second clock signal is input, The first transistor is a P-type transistor, and The second transistor and the third transistor are N-type transistors.

8. The driving circuit according to claim 7, wherein: The second signal is the same signal as the first signal, and The third signal is the first clock signal.

9. The driving circuit according to claim 1, in, Each of the plurality of stages further comprises: A fourth transistor is connected between the first transistor and the first node and includes a gate connected to a terminal to which a first voltage of a low level is input.

10. The driving circuit according to claim 9, in, The fourth transistor includes two sub-transistors connected in series.

11. The driving circuit according to claim 1, in, Each of the plurality of stages further comprises: The capacitor is connected between the first node and a terminal to which a first voltage of a low level is supplied.

12. The driving circuit according to claim 1, in, The output circuit comprises: a pull-down transistor connected between the output terminal and the clock terminal and including a gate connected to the first node; a pull-up transistor connected between a terminal supplied with a second voltage of a high level and the output terminal and including a gate connected to the second node; and A capacitor is connected between the first node and the output terminal.

13. A driving circuit comprising a plurality of stages for outputting a plurality of gate signals to a plurality of pixels, in, Each of the plurality of stages comprises: a first transistor connected between the first node and an input terminal to which a start signal is input, and including a gate connected to a first clock terminal to which a first clock signal is input; a second transistor connected between the second node and a first voltage input terminal to which a first voltage of a low level is input, and including a gate connected to the first clock terminal; a third transistor connected between the second node and a second voltage input terminal to which a second voltage of a high level is input, and including a gate connected to the first clock terminal; and an output circuit connected to the second voltage input terminal and a second clock terminal to which a second clock signal is input, and configured to output a corresponding gate signal having one of a high level voltage and a low level voltage among the plurality of gate signals according to a voltage level of the first node and a voltage level of the second node, and The first transistor and the second transistor are P-type transistors, and the third transistor is an N-type transistor.

14. The driving circuit according to claim 13, in, Each of the plurality of stages further comprises: A fourth transistor is connected between the first transistor and the first node and includes a gate connected to the first voltage input terminal.

15. The driving circuit according to claim 14, in, The fourth transistor includes two sub-transistors connected in series.

16. The driving circuit according to claim 13, in, Each of the plurality of stages further includes a capacitor connected between the first node and the first voltage input terminal.

17. A driving circuit comprising a plurality of stages for outputting a plurality of gate signals to a plurality of pixels, in, Each of the plurality of stages comprises: a first transistor connected between the first node and an input terminal to which a start signal is input, and including a gate connected to a first clock terminal to which a first clock signal is input; a second transistor connected between the input terminal and a second node and including a gate connected to the first clock terminal; a third transistor connected between the first clock terminal and the second node and including a gate connected to a second clock terminal to which a second clock signal is input; and an output circuit connected between the second clock terminal and a first voltage input terminal to which a first voltage of a high level is input, and configured to output a corresponding gate signal having one of a high level voltage and a low level voltage among the plurality of gate signals according to a voltage level of the first node and a voltage level of the second node, and The first transistor is a P-type transistor, and the second transistor and the third transistor are N-type transistors.

18. The driving circuit according to claim 17, in, Each of the plurality of stages further comprises: The fourth transistor is connected between the first transistor and the first node and includes a gate connected to a second voltage input terminal to which a second voltage of a low level is input.

19. The driving circuit according to claim 18, in, The fourth transistor includes two sub-transistors connected in series.

20. The driving circuit according to claim 17, in, Each of the plurality of stages further comprises: The capacitor is connected between the first node and a second voltage input terminal to which a second voltage of a low level is input.

21. A driving circuit comprising a plurality of stages for outputting a plurality of gate signals to a plurality of pixels, in, Each of the plurality of stages comprises: a first transistor connected between the first node and an input terminal to which a start signal is input, and including a gate connected to a first clock terminal to which a first clock signal is input; a second transistor connected between the input terminal and a second node and including a gate connected to the first clock terminal; a third transistor connected between the second node and a first voltage input terminal to which the first voltage of a low level is input, and including a gate connected to the first clock terminal; and an output circuit connected between a second voltage input terminal to which a high-level second voltage is input and a second clock terminal to which a second clock signal is input, and configured to output a corresponding gate signal having one of a high-level voltage and a low-level voltage among the plurality of gate signals according to a voltage level of the first node and a voltage level of the second node, and The first transistor and the third transistor are P-type transistors, and the second transistor is an N-type transistor.

22. The driving circuit according to claim 21, in, Each of the plurality of stages further comprises: A fourth transistor is connected between the first transistor and the first node and includes a gate connected to the first voltage input terminal.

23. The driving circuit according to claim 22, in, The fourth transistor includes two sub-transistors connected in series.

24. The driving circuit according to claim 21, in, Each of the plurality of stages further comprises: A capacitor is connected between the first node and the first voltage input terminal.

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