Display panel, preparation method thereof, control method and display device

Abstract

The invention belongs to the technical field of display, and discloses a display panel, a preparation method thereof, a control method and a display device.The display panel comprises a plurality of sub-pixels and a pixel driving circuit, the sub-pixels comprise target sub-pixels, the target sub-pixels form a gamma calibration region, and the target sub-pixels form a gamma calibration region; the pixel driving circuit comprises a first sub-pixel driving circuit arranged in the gamma calibration area and a plurality of second sub-pixel driving circuits arranged outside the gamma calibration area; the first sub-pixel driving circuit comprises a first driving transistor with a first channel region; the second sub-pixel driving circuit comprises second driving transistors with second channel regions, and the width-to-length ratios of the second channel regions corresponding to the second driving transistors are the same; an aspect ratio of the first channel region is greater than an aspect ratio of the second channel region. According to the display panel, the brightness of the target sub-pixel in the gamma calibration area is the brightest of the display panel, the pixel uniformity compensation effect is improved, and the brightness uniformity of the display panel can be improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a manufacturing method, a control method and a display device thereof. Background Art

[0002] After all the hardware production of the display panel is completed, two electrical processes will be carried out: one is the photoelectric curve calibration, called gamma calibration (Gammer tunning), and the other is pixel uniformity compensation (PUC). PUC will use the brightness of the gamma target area as the target brightness. When the brightness of a pixel is lower than the target brightness, the input grayscale will be increased; when the brightness of a pixel is higher than the target brightness, the input grayscale will be reduced. When the picture is at a low grayscale, if there is an area with a brightness higher than the target area, the grayscale of the area will be reduced after compensation, and it may enter the interval where Gamma fitting is inaccurate, resulting in inaccurate brightness after PUC compensation. When the target area is the brightest area of ​​the panel, the grayscale of the remaining areas increases after compensation, and the grayscale is in the accurate interval of Gamma fitting, and the brightness is accurate after compensation. Therefore, if the area with lower screen brightness is used as the gamma calibration area, the effect of PUC will be poor, affecting the uniformity of the brightness of the display panel. Summary of the invention

[0003] In view of the above-mentioned defects or deficiencies in the prior art, it is desirable to provide a display panel and a manufacturing method thereof, a control method thereof, and a display device.

[0004] In a first aspect, a display panel is provided, comprising: a plurality of sub-pixels and a pixel driving circuit, wherein the plurality of sub-pixels include a target sub-pixel, the target sub-pixel forms a gamma calibration area, the pixel driving circuit includes a first sub-pixel driving circuit arranged in the gamma calibration area and a plurality of second sub-pixel driving circuits arranged outside the gamma calibration area; The first sub-pixel driving circuit includes a first driving transistor, the first driving transistor includes a first channel region; the second sub-pixel driving circuit includes a second driving transistor, the second driving transistor includes a second channel region, and the width-to-length ratios of the second channel regions corresponding to the second driving transistors are the same; The width-to-length ratio of the first channel region is greater than the width-to-length ratio of the second channel region; wherein the width-to-length ratio is the ratio of the width and length of the corresponding channel region, the length of the channel region is the length of the path of current flowing in the channel region, and the width of the channel region is the channel dimension perpendicular to the direction of current flow.

[0005] In addition, the display panel of the present invention may also have the following additional technical features: In some embodiments, the width-to-length ratio of the first channel region increases by 10% to 20% relative to the width-to-length ratio of the second channel region.

[0006] In some embodiments, a substrate is disposed on a side of the pixel driving circuit away from the sub-pixel, and projection shapes of the first channel region and the second channel region on the substrate are the same or different.

[0007] In some embodiments, the first channel region and the second channel region each include a first connecting segment, a second connecting segment, and a third connecting segment, and two ends of the second connecting segment are respectively bent and connected to the first connecting segment and the third connecting segment.

[0008] In some embodiments, the projection shapes of the first connecting segment, the second connecting segment, and the third connecting segment on the base substrate are all square.

[0009] In some embodiments, the first connecting segment and the third connecting segment are located on the same side of the second connecting segment, the first connecting segment is perpendicular to the second connecting segment, the third connecting segment is perpendicular to the second connecting segment, and the path lengths of the first connecting segment and the third connecting segment along the current flow direction are equal.

[0010] In some embodiments, a path length of the second connection segment of the first channel region along the current flow direction is smaller than a path length of the second connection segment of the second channel region along the current flow direction; or / and, The path length of the first connection section of the first channel region along the current flow direction is shorter than the path length of the first connection section of the second channel region along the current flow direction; or / and, A channel dimension of the second connecting section of the first channel region along a direction perpendicular to the current flow is greater than a channel dimension of the second connecting section of the second channel region along a direction perpendicular to the current flow.

[0011] In some embodiments, the second connecting segment of the first channel region and the second connecting segment of the second channel region have different projected shapes on the substrate, and the channel size of the second connecting segment of the first channel region along a direction perpendicular to the current flow is larger than the channel size of the second connecting segment of the second channel region along a direction perpendicular to the current flow.

[0012] In some embodiments, the second connecting section of the first channel region includes a first end face and a second end face that are oppositely arranged, at least one of the first end face and the second end face is an arcuate face or a V-shaped face, and the projection shape of the second connecting section of the second channel region on the substrate is a square; the distance between the first end face and the second end face is greater than the channel size of the second connecting section of the second channel region along a direction perpendicular to the current flow.

[0013] In some embodiments, there are one or more target sub-pixels, each of the target sub-pixels is arranged in a one-to-one correspondence with the first sub-pixel driving circuit, and the target sub-pixels are located in a central area of ​​the display panel.

[0014] In a second aspect, a method for preparing a display panel is provided, comprising: A pixel driving circuit is formed on a substrate, wherein the pixel driving circuit includes a first sub-pixel driving circuit and a plurality of second sub-pixel driving circuits, wherein the first sub-pixel driving circuit includes a first driving transistor, wherein the first driving transistor includes a first channel region; the second sub-pixel driving circuit includes a second driving transistor, wherein the second driving transistor includes a second channel region, and the width-to-length ratio of the second channel regions corresponding to the second driving transistors is the same; wherein the width-to-length ratio is a ratio of a width to a length of a corresponding channel region, wherein the length of the channel region is a length of a path for current to flow in the channel region, and the width of the channel region is a channel dimension perpendicular to a current flow direction; A plurality of sub-pixels are formed on a side of the pixel driving circuit away from the base substrate, wherein the sub-pixels corresponding to the first pixel driving circuit are target sub-pixels, and the target sub-pixels form a gamma calibration area.

[0015] In some embodiments, the width of the first channel region is increased or / and the length of the first channel region is decreased so that the width-to-length ratio of the first channel region is greater than the width-to-length ratio of the second channel region.

[0016] In some embodiments, the shape of the first channel region is changed so that the width-to-length ratio of the first channel region is greater than the width-to-length ratio of the second channel region.

[0017] In a third aspect, a method for controlling a display panel is provided, the method for controlling the display panel described in any embodiment of the present application, or the display panel obtained by the method for preparing the display panel described in any embodiment of the present application, the method for controlling the display panel includes: The first sub-pixel driving circuit and the second sub-pixel driving circuit drive corresponding sub-pixels to operate at the same driving voltage, so that the brightness of the sub-pixels in the gamma calibration area is greater than the brightness of the sub-pixels outside the gamma calibration area.

[0018] In a fourth aspect, a display panel is provided, wherein the display device comprises the display panel described in any embodiment of the present application, or comprises a display panel obtained by the method for preparing the display panel described in any embodiment of the present application.

[0019] The present disclosure provides a display panel and a preparation method, a control method and a display device thereof. The display panel has a differentiated pixel driving circuit structure, and the width-to-length ratio of the first channel region of the first sub-pixel driving circuit in the gamma calibration area is greater than the width-to-length ratio of the second channel region of the second sub-pixel driving circuit outside the gamma calibration area, so that the brightness of the target sub-pixel in the gamma calibration area is always the brightest in the display panel. After gamma calibration and pixel uniformity compensation, the brightness uniformity of the display panel can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0021] Figure 1 Gamma grayscale and voltage diagram provided for this application; Figure 2 A diagram showing the location of the gamma calibration area within the display panel provided for this application; Figure 3 An exemplary structural diagram of a first driving transistor provided in an embodiment of the present application; Figure 4 A physical diagram of the arrangement of the second sub-pixel driving circuit in the peripheral area of ​​the display panel provided in an embodiment of the present application; Figure 5 for Figure 4 A circuit structure diagram of a second sub-pixel driving circuit; Figure 6 A physical diagram of the arrangement of a first sub-pixel driving circuit in a gamma calibration area of ​​a display panel provided in an embodiment of the present application; Figure 7 A first exemplary structural diagram of a first sub-pixel driving circuit provided in an embodiment of the present application; Figure 8 A second exemplary structural diagram of a first sub-pixel driving circuit provided in an embodiment of the present application; Fig. 9 A third exemplary structural diagram of the first sub-pixel driving circuit provided in an embodiment of the present application; Fig.10 A fourth exemplary structural diagram of the first sub-pixel driving circuit provided in an embodiment of the present application; Fig.11 A circuit diagram of a sub-pixel driving circuit 7T1C provided in an embodiment of the present application; Fig.12 The driving principle diagram of the sub-pixel driving circuit 7T1C provided in the embodiment of the present application; (a) is the initialization stage; (b) is the data writing and compensation stage; (c) is the light emitting stage; Fig.13 A timing diagram of a sub-pixel driving circuit 7T1C provided in an embodiment of the present application; Fig.14 This is a structural diagram of a display device provided in an embodiment of the present application.

[0022] In the above picture: 10 display panel; 101 gamma calibration area; 11 substrate; 12 first sub-pixel driving circuit; 121 first driving transistor; 1210 active layer; 1211 first channel region; 1212 source region; 1213 drain region; 1220 gate; 1221 source; 1222 drain; 1230 gate insulating layer; 13 second sub-pixel driving circuit; 131 second driving transistor; 1310 second channel region; 100 display device. DETAILED DESCRIPTION

[0023] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0024] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and other forms thereof, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open, inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described may be included in any one or more embodiments or examples in any appropriate manner.

[0025] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0026] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0027] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0028] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0029] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing.

[0030] After all the hardware production is completed, the display panel will undergo two electrical processes: one is photoelectric curve calibration, called gamma calibration (Gammertunning), and the other is pixel uniformity compensation (PixelUniformityCompensation, PUC). Among them, gamma correction, also known as gamma nonlinearization or gamma encoding, is used to perform nonlinear operations or inverse operations on the brightness or tri-color stimulus values ​​of light in movies or imaging systems. In display devices, gamma calibration is a process of feedback adjustment to set different driving voltages for different grayscales. If it is a screen with multiple brightness levels (DBV, DisplayBrightnessvalue), the screen with adjustable DBV, such as mobile phone screens and tablet screens, there will be multiple DBV gamma calibration processes and multiple gamma calibration curves. The basic principle of gamma calibration is that in order to make the display panel reach the specified brightness and chromaticity, the existing process will use an optical probe to perform gamma calibration at the center of the panel (industry default), that is, to find the voltage corresponding to the target brightness and chromaticity of several grayscale binding points of RGB sub-pixels under the specified DBV, and obtain the voltage corresponding to the grayscale outside the binding point through linear interpolation. Due to the limitation of process time, several points are generally selected in the grayscale of 0~255 to find the target brightness, chromaticity and corresponding voltage feedback according to the requirements of the algorithm. These points are called binding points. The target brightness, chromaticity and voltage outside the binding points are defined by the algorithm in the form of interpolation.

[0031] After gamma calibration, the inhomogeneity of each production link in the production process will cause differences in device performance, which can be attributed to the differences in backplane characteristics and electroluminescent (EL) device differences. Backplane characteristics mainly refer to the threshold voltage caused by temperature, film thickness, etc. ( ) and the coefficient K The difference is ultimately reflected as uneven brightness of the entire screen. PUC is a method used to compensate for uneven display brightness between pixels. Its principle is to obtain the brightness of each sub-pixel through an external sensor and calculate the grayscale that needs to be increased or decreased for each sub-pixel to achieve the target brightness.

[0032] The voltage corresponding to 0 grayscale is the black state voltage, that is, the minimum voltage when the display panel is not emitting light. Therefore, the interpolated voltage between 0 grayscale and the lowest binding point grayscale is quite different from the actual required voltage. Figure 1 As shown, the brightness of other grayscales between 0 grayscale and the lowest binding point grayscale will be inaccurate. In addition, when calibrating Gamma, the lower the grayscale, the wider the range of target brightness and chromaticity corresponding to the grayscale will be. The combined effect of the two will lead to inaccurate Gamma fitting at low grayscale.

[0033] PUC uses the brightness of the Gamma target area as the target brightness. When the brightness of a pixel is lower than the target brightness, the input grayscale will be increased; when the brightness of a pixel is higher than the target brightness, the input grayscale will be reduced. When the picture is at low grayscale, if there is an area with brightness higher than the target area, the grayscale of the area will be reduced after compensation, and it may enter the interval where Gamma fitting is inaccurate, resulting in inaccurate brightness after compensation. When the target area is the brightest area of ​​the panel, the grayscale of the remaining areas increases after compensation, and the grayscale is in the interval where Gamma fitting is accurate, and the brightness is accurate after compensation. Therefore, if the gamma calibration is performed in an area with lower screen brightness, that is, when the brightness of the center of the screen is the lowest, the PUC effect will be poor. However, the unevenness of the screen brightness is affected by the position of the display panel on the large panel on the one hand, and is difficult to control due to the uncertainty of the process on the other hand.

[0034] To solve the above technical problems, refer to Figures 2 to 10 In a first aspect, a display panel 10 is provided, comprising: a plurality of sub-pixels and a pixel driving circuit, wherein the plurality of sub-pixels include a target sub-pixel, the target sub-pixel forms a gamma calibration area 101, the pixel driving circuit comprises a first sub-pixel driving circuit 12 arranged in the gamma calibration area 101 and a plurality of second sub-pixel driving circuits 13 arranged outside the gamma calibration area 101; The first sub-pixel driving circuit 12 includes a first driving transistor 121, and the first driving transistor 121 includes a first channel region 1211; the second sub-pixel driving circuit 13 includes a second driving transistor 131, and the second driving transistor 131 includes a second channel region 1310, and the width-to-length ratios of the second channel regions 1310 corresponding to the second driving transistors 131 are the same; The width-to-length ratio of the first channel region 1211 is greater than the width-to-length ratio of the second channel region 1310; wherein the width-to-length ratio is the ratio of the width and length of the corresponding channel region, the length of the channel region is the length of the path of current flowing in the channel region, and the width of the channel region is the channel dimension perpendicular to the direction of current flow.

[0035] Specifically, the display panel 10 includes a pixel driving circuit arranged on a base substrate 11. A pixel definition layer is arranged on a side of the pixel driving circuit away from the base substrate 11. The pixel definition layer has a plurality of opening areas arranged at intervals. A sub-pixel is arranged in each opening area. The sub-pixel in each opening area can be any one of a red sub-pixel (R), a green sub-pixel (G) or a blue sub-pixel (B). A pixel generally includes a plurality of sub-pixels, such as RGB constituting a pixel. The pixels on the display panel 10 are distributed in an array.

[0036] The multiple sub-pixels of the display panel 10 include target sub-pixels, and the target sub-pixels on the display panel 10 form a gamma calibration area 101, wherein the gamma calibration area 101 is a gamma calibration optical probe detection area, and the area on the display panel 10 other than the gamma calibration area 101 is a peripheral area. The driving circuit layer is used to form multiple sub-pixel driving circuits distributed in an array, and the multiple sub-pixel driving circuits include a first sub-pixel driving circuit 12 and a second sub-pixel driving circuit 13, and the first sub-pixel driving circuit 12 is set in a one-to-one correspondence with the target sub-pixels in the gamma calibration area 101 to achieve independent driving control of each target sub-pixel; the second sub-pixel driving circuit 13 is set in a one-to-one correspondence with each sub-pixel in the peripheral area to achieve independent driving control of each sub-pixel in the peripheral area.

[0037] It should be noted that if Figure 3 and Figure 4 As shown, in the sub-pixel driving circuit, there is generally only one driving transistor, and the driving transistor includes an active layer 1210. The active layer 1210 includes a channel region (a first channel region or a second channel region) and a source region 1212 and a drain region 1213 located on both sides of the channel region. The source region 1212, the channel region and the drain region 1213 are arranged in parallel to form the active layer 1210. A gate insulating layer 1230 is stacked on the active layer 1210. A gate 1220 is formed on a side of the gate insulating layer 1230 away from the active layer 1210. A source electrode 1221 (S electrode) is overlapped on the source region 1212, and a drain electrode 1222 (D electrode) is overlapped on the drain region 1213. The gate 1220 is located between the source electrode 1221 and the drain electrode 1222. By controlling the gate voltage (or gate 1220 voltage) of the driving transistor to control the source-drain (SD) current of the driving transistor, the corresponding sub-pixel lighting is controlled. I formula: I=

[0038] in, K is a coefficient, including parameters such as the mobility of the driving transistor; is the length of the channel region of the driving transistor, and the length of the channel region is the length of the path for the current to flow in the channel region; is the width of the channel region of the driving transistor, where the width of the channel region is the channel dimension perpendicular to the direction of current flow; is the voltage from the gate 1220 to the source 1221, is the threshold voltage of the driving transistor.

[0039] From the above current formula, we can see that , , K Under the same conditions, the aspect ratio of the driving transistor Directly affects the magnitude of the current, and thus affects the brightness of the corresponding sub-pixel, that is, The larger it is, the greater the current and the brighter the sub-pixel.

[0040] In the embodiment of the present application, the width-to-length ratio of the first channel region 1211 of the first driving transistor 121 corresponding to the first sub-pixel driving circuit 12 is greater than the width-to-length ratio of the second channel region 1310 of the second driving transistor 131 corresponding to the second sub-pixel driving circuit 13. Under the same driving voltage, the brightness of the target sub-pixel in the gamma calibration area 101 can be greater than the brightness of each sub-pixel in the surrounding area, thereby making the brightness of the target sub-pixel on the display panel 10 the brightest sub-pixel on the display panel 10, and the target sub-pixel formation area is used as the gamma calibration area 101, that is, the area detected by the gamma-calibrated optical probe at least covers the area formed by the target sub-pixel, thereby reducing the probability that the gamma calibration area 101 is less than the brightness of the surrounding area of ​​the display panel 10, improving the PUC effect, and thereby improving the brightness uniformity of the display panel 10.

[0041] In this example, by differentiating the pixel driving circuit structure on the substrate 11, the brightness of the target sub-pixel in the gamma calibration area 101 is always the brightest sub-pixel in the display panel 10, so that the gamma calibration area 101 is the area with the highest brightness in the display panel 10 before PUC. Under the premise of such gamma calibration, the effect of PUC can be far superior to the existing structural design of the display panel 10, and after PUC, the uneven brightness caused by the differentiated backplane structure itself can be eliminated, thereby improving the brightness uniformity of the display panel 10.

[0042] In some embodiments, the width-to-length ratio of the first channel region 1211 increases by 10%-20% relative to the width-to-length ratio of the second channel region 1310 .

[0043] Exemplarily, if the width-to-length ratio of the first channel region 1211 is d1, the width-to-length ratio d2 of the second channel region 1310 is: d1=d2(1+a), where a is 10%~20%. Under the same driving voltage, before PUC, the width-to-length ratio of the first channel region 1211 increases by 10%~20% relative to the width-to-length ratio of the second channel region 1310, such as 10%, 12%, 15%, 18%, 20%, etc. The brightness of the target sub-pixel driven by the first sub-pixel driving circuit 12 is greater than the brightness of the sub-pixel driven by the second sub-pixel driving circuit 13. Even if the brightness of the display panel 10 is not uniform due to the influence of process uniformity, the gamma calibration area 101 will still be the brightest area of ​​the display panel 10, which can reduce the brightness uniformity of different display panels 10 after PUC, so that the brightness uniformity of display panels 10 in different panels or batches tends to be stable, thereby improving the quality of the display panel 10. Among them, as analyzed above, in the backplane characteristics, the threshold voltage caused by temperature, film thickness, etc. ( ) and the coefficient K The difference may also cause uneven brightness of the display panel 10. The increase in the width-to-length ratio of the first channel region 1211 relative to the width-to-length ratio of the second channel region 1310 is less than 10%. Due to the difference in backplane characteristics, the brightness of the target sub-pixel may not be the brightest in the display panel 10. The increase in the width-to-length ratio of the first channel region 1211 relative to the width-to-length ratio of the second channel region 1310 is greater than 20%, which exceeds the compensation capability of the PUC, ultimately resulting in poor uniformity of the display panel 10.

[0044] In some embodiments, a base substrate 11 is disposed on a side of the pixel driving circuit away from the sub-pixel, and the projection shapes of the first channel region 1211 and the second channel region 1310 on the base substrate 11 are the same or different.

[0045] For example, Figures 4 to 9 As shown, the shapes of the first channel region 1211 and the second channel region 1310 can be the same. Relative to the second channel region 1310, the width of the first channel region 1211 is increased or / and the length of the first channel region 1211 is reduced so that the width-to-length ratio of the first channel region 1211 is greater than the width-to-length ratio of the second channel region 1310. If the projections of the first channel region 1211 and the second channel region 1310 on the substrate 11 are both square, then the shortest distance between the opposite edges of the source 1221 and the drain 1222 is the length of the channel region, and the channel dimension perpendicular to the current flow direction of the source 1221 and the drain 1222 is the width of the channel region; for another example, the projections of the first channel region 1211 and the second channel region 1310 on the substrate 11 are in the shape of a "J", etc., which will be described in detail later and will not be described here.

[0046] For example, Fig.10As shown, the shapes of the first channel region 1211 and the second channel region 1310 can be different, and the shape of the first channel region 1211 can be changed so that the width-to-length ratio of the first channel region 1211 is greater than the width-to-length ratio of the second channel region 1310. For example, the projection of the second channel region 1310 on the substrate 11 is a square, and the square structure has a first horizontal end face and a second horizontal end face that are oppositely arranged along the stacking direction of the gate 1220; the projection shape of the first channel region 1211 on the substrate 11 is different from that of the second channel region 1310, and at least one of the first horizontal end face and the second horizontal end face in the second channel region 1310 is changed to an arc end face or a V-shaped face, so that the width of the first channel region 1211 is greater than the width of the second channel region 1310, and the principles of other shape changes are the same, and are not listed in this application.

[0047] In some embodiments, Figures 4 to 10 As shown, the first channel region 1211 and the second channel region 1310 both include a first connecting segment, a second connecting segment and a third connecting segment, and two ends of the second connecting segment are bent and connected to the first connecting segment and the third connecting segment respectively.

[0048] Specifically, the first connecting segment, the second connecting segment and the third connecting segment connected in sequence by bending constitute a "J"-shaped channel region. The change of the width or / and length corresponding to at least one of the first connecting segment, the second connecting segment and the third connecting segment, as well as the change of the shape, can make the width-to-length ratio of the first channel region 1211 greater than the width-to-length ratio of the second channel region 1310. Among them, the angle of the bending connection between the first connecting segment and the second connecting segment and the angle of the bending connection between the second connecting segment and the third connecting segment can be the same or different. The angle of the bending connection can be set according to actual needs, such as the angle can be 35~145°, which can be set by technicians in this field according to actual needs. Among them, the first connecting segment and the third connecting segment are located on the same side of the second connecting segment, and the first connecting segment and the third connecting segment are vertically arranged or inclined relative to the second connecting segment. The first connecting segment and the third connecting segment can be inclined relative to the second connecting segment toward the side away from the second connecting segment.

[0049] Among them, Figure 5 As shown, the length of the channel region is the flow path length of the current in the first connection section , the flow path length of the current in the second connection section and the length of the current flow path in the third connection segment The sum of + The width of the first connecting section, the width of the second connecting section and the width of the third connecting section are all equal and are equal to the length of the channel region. equal, or the width of the first connecting segment, the width of the second connecting segment and the width of the third connecting segment are different, then the length of the channel region The maximum value or the average value of the width of the first connecting segment, the width of the second connecting segment and the width of the third connecting segment may be taken.

[0050] In some embodiments, Figures 4 to 9 As shown, the projection shapes of the first connecting segment, the second connecting segment and the third connecting segment on the base substrate 11 are all square.

[0051] Specifically, the first channel region 1211 and the second channel region 1310 have the same shape, the width of at least one of the first connecting segment, the second connecting segment and the third connecting segment in the first channel region 1211 is increased relative to the width of the corresponding connecting segment in the second channel region 1310, or / and, the length of at least one of the first connecting segment, the second connecting segment and the third connecting segment in the first channel region 1211 is reduced relative to the length of the corresponding connecting segment in the second channel region 1310, or / and, the shape of at least one of the first connecting segment, the second connecting segment and the third connecting segment in the first channel region 1211 is changed relative to the shape of the corresponding connecting segment in the second channel region 1310, all of which can achieve a width-to-length ratio of the first channel region 1211 greater than the width-to-length ratio of the second channel region 1310.

[0052] In some embodiments, Figures 4 to 9 As shown, the first connecting segment and the third connecting segment are located on the same side of the second connecting segment, the first connecting segment is perpendicular to the second connecting segment, the third connecting segment is perpendicular to the second connecting segment, and the path lengths of the first connecting segment and the third connecting segment along the current flow direction are equal.

[0053] Specifically, the first connection segment and the third connection segment are located on the same side of the second connection segment and have the same length, and the lengths of the first connection segment and the third connection segment of the first channel region 1211 can be reduced at the same time (the length reduction ratios of the first connection segment and the third connection segment can be the same or different), or / and, the length of the second connection segment of the first channel region 1211 can be reduced, so that the width-to-length ratio of the first channel region is greater than the width-to-length ratio of the second channel region 1310. Alternatively, the widths of the first connection segment, the third connection segment and the third connection segment of the first channel region 1211 can be increased at the same time (the width increase ratios of the three connection segments can be the same or different), so that the width-to-length ratio of the first channel region is greater than the width-to-length ratio of the second channel region 1310.

[0054] Further, in some embodiments, the path length of the second connection segment of the first channel region 1211 along the current flow direction is smaller than the path length of the second connection segment of the second channel region 1310 along the current flow direction; or / and, The path length of the first connection section of the first channel region 1211 along the current flow direction is smaller than the path length of the first connection section of the second channel region 1310 along the current flow direction; or / and, A channel dimension of the second connection segment of the first channel region 1211 along a direction perpendicular to the current flow is greater than a channel dimension of the second connection segment of the second channel region 1310 along a direction perpendicular to the current flow.

[0055] The embodiment of the present application is exemplified by taking the first sub-pixel driving circuit 12 and the second sub-pixel driving circuit 13 as 7T1C driving circuits, wherein the transistor T3 is a driving transistor, as follows.

[0056] For example, Figure 5 and Figure 7 As shown, the path length (L21) of the second connection segment of the first channel region 1211 of the transistor T3 of the first sub-pixel driving circuit 12 along the current flow direction is smaller than the path length (L22) of the second connection segment of the second channel region 1310 of the transistor T3 of the second sub-pixel driving circuit 13 along the current flow direction, that is, L21<L22, and other parameters of the first channel region 1211 of the transistor T3 of the first sub-pixel driving circuit 12 (such as the length and width of the first connection segment, the width of the second connection segment, the length and width of the third connection segment, etc.) are the same as those of the transistor T3 of the second sub-pixel driving circuit 13, and under the same driving voltage, the brightness of the target sub-pixel in the gamma calibration area 101 can be made greater than the brightness of the sub-pixels in the surrounding area.

[0057] For example, Figure 5 and Figure 8 As shown, the path length (L11) of the first connection segment of the first channel region 1211 of the transistor T3 of the first sub-pixel driving circuit 12 along the current flow direction is smaller than the path length (L12) of the first connection segment of the second channel region 1310 of the transistor T3 of the second sub-pixel driving circuit 13 along the current flow direction, that is, L11<L12, and the path length of the third connection segment of the first channel region 1211 of the transistor T3 of the first sub-pixel driving circuit 12 along the current flow direction is smaller than the path length of the third connection segment of the second channel region 1310 of the transistor T3 of the second sub-pixel driving circuit 13 along the current flow direction. Similarly, other parameters of the first channel region 1211 of the transistor T3 of the first sub-pixel driving circuit 12 (such as the width of the first connection segment, the length and width of the second connection segment, the width of the third connection segment, etc.) are the same as those of the transistor T3 of the second sub-pixel driving circuit 13. Under the same driving voltage, the brightness of the target sub-pixel in the gamma calibration area 101 can be made greater than the brightness of the sub-pixels in the surrounding area.

[0058] For example, Figure 5 and Fig. 9 As shown, the channel size (W2) of the second connection segment of the first channel region 1211 of the transistor T3 of the first sub-pixel driving circuit 12 along the direction perpendicular to the current flow is greater than the channel size (W1) of the second connection segment of the second channel region 1310 of the transistor T3 of the second sub-pixel driving circuit 13 along the direction perpendicular to the current flow, that is, W2>W1. Similarly, other parameters of the first channel region 1211 of the transistor T3 of the first sub-pixel driving circuit 12 (such as the length and width of the first connection segment, the length of the second connection segment, the length and width of the third connection segment, etc.) are the same as those of the transistor T3 of the second sub-pixel driving circuit 13, and under the same driving voltage, the brightness of the target sub-pixel in the gamma calibration area 101 can be greater than the brightness of the sub-pixels in the surrounding area.

[0059] It can be understood that the channel size of the first connecting segment of the first channel region 1211 along the direction perpendicular to the current flow is larger than the channel size of the first connecting segment of the second channel region 1310 along the direction perpendicular to the current flow, or / and the channel size of the third connecting segment of the first channel region 1211 along the direction perpendicular to the current flow is larger than the channel size of the third connecting segment of the second channel region 1310 along the direction perpendicular to the current flow. Similarly, the width-to-length ratio of the first channel region 1211 can be greater than the width-to-length ratio of the second channel region 1310.

[0060] In some embodiments, Figure 5 and Fig.10 As shown, the second connecting section of the first channel region 1211 and the second connecting section of the second channel region 1310 have different projected shapes on the substrate 11, and the channel size of the second connecting section of the first channel region 1211 along the direction perpendicular to the current flow is larger than the channel size of the second connecting section of the second channel region 1310 along the direction perpendicular to the current flow.

[0061] Specifically, by changing the shape of any one of the first connecting segment, the second connecting segment, and the third connecting segment of the first channel region 1211 , the width-to-length ratio of the first channel region 1211 can be made greater than the width-to-length ratio of the second channel region 1310 .

[0062] Furthermore, in some embodiments, the second connecting section of the first channel region 1211 includes a first end face and a second end face that are relatively arranged, at least one of the first end face and the second end face is an arc-shaped surface or a V-shaped surface, and the projection shape of the second connecting section of the second channel region 1310 on the substrate 11 is a square; the distance between the first end face and the second end face is greater than the channel size of the second connecting section of the second channel region 1310 along a direction perpendicular to the current flow.

[0063] For example, Figure 5 and Fig.10 As shown, the second connecting section of the first channel region 1211 is different from the second connecting section of the second channel region 1310 in shape. The projection of the second connecting section of the second channel region 1310 on the substrate 11 is square, that is, the second connecting section has a first horizontal end face and a second horizontal end face that are relatively arranged along the stacking direction of the gate 1220. The first channel region 1211 replaces one of the first horizontal end face and the second horizontal end face with an arc-shaped end face, thereby increasing the distance between the two end faces, so that the width-to-length ratio of the second connecting section of the first channel region 1211 is greater than the width-to-length ratio of the second connecting section of the second channel region 1310.

[0064] It should be noted that if Figure 5 As shown, the channel region further includes a fourth connection segment connected to the first connection segment in a zigzag manner, and a fifth connection segment connected to the third connection segment in a zigzag manner. One of the fourth connection segment and the fifth connection segment is connected to the source 1221, and the other connection segment is connected to the drain 1222. Accordingly, the length of the channel region is the flow path length of the current in the first connection section , the flow path length of the current in the second connection section , the length of the current flow path in the third connection section , the length of the current flow path in the fourth connection segment , and the length of the flow path of the current in the fifth connecting segment The sum of + + + The width of the first connecting segment, the width of the second connecting segment, the width of the third connecting segment, the width of the fourth connecting segment, and the width of the fifth connecting segment are all equal and are equal to the length of the channel region. equal, or the width of the first connecting segment, the width of the second connecting segment, the width of the third connecting segment, the width of the fourth connecting segment, and the width of the fifth connecting segment are different, then the length of the channel region The maximum value or the average value of the width of the first connecting segment, the width of the second connecting segment, the width of the third connecting segment, the width of the fourth connecting segment and the width of the fifth connecting segment can be taken.

[0065] It can be understood that by changing the length and / or width, and the shape, of the fourth connecting segment and / or the fifth connecting segment of the first channel region 1211, it is also possible to achieve a width-to-length ratio of the first channel region 1211 greater than the width-to-length ratio of the second channel region 1310. For example, the length of the fourth connecting segment of the first channel region 1211 is smaller than the length of the fourth connecting segment of the second channel region 1310. For another example, the width of the fourth connecting segment of the first channel region 1211 is greater than the width of the fourth connecting segment of the second channel region 1310.

[0066] In some embodiments, Figure 2 As shown, there are one or more target sub-pixels, each of which is arranged in a one-to-one correspondence with the first sub-pixel driving circuit 12 , and the target sub-pixel is located in the central area of ​​the display panel 10 .

[0067] Specifically, in actual application, due to uncertainty and convenience of production, the optical probe is usually placed in the central area of ​​the display panel 10 for gamma calibration. The detection area of ​​the optical probe is generally a circular area, covering the center position of the display panel 10. The present application sets the target sub-pixel in the central area of ​​the display panel 10, so that the gamma calibration area 101 covers the central area of ​​the display panel 10. Under the same driving voltage, the brightness of the target sub-pixel in the gamma calibration area 101 is the brightest in the display panel 10, that is, the brightest area of ​​the display panel 10 is always located in the central area of ​​the display panel 10. The central area of ​​the display panel 10 is used as the gamma calibration area 101. Under this gamma calibration premise, after PUC, the brightness uniformity of the display panel 10 is improved.

[0068] It is understandable that the sub-pixel driving circuit may include multiple transistors, capacitors, and transistor driving components and other electronic components. For example, the sub-pixel driving circuit may include three transistors and one capacitor, forming a 3T1C (i.e., a driving transistor, two switching transistors, and a capacitor). It may also include more than three transistors and at least one capacitor, such as a 4T1C (i.e., a driving transistor, three switching transistors, and a capacitor), a 5T1C (i.e., a driving transistor, four switching transistors, and a capacitor), or a 7T1C (i.e., a driving transistor, six switching transistors, and a capacitor). Among them, the transistor may be a thin film transistor (Thin Film Transistor, referred to as TFT), a field effect transistor (metal oxide semiconductor, referred to as MOS), or other switching devices with the same characteristics. The thin film transistor may be any one of a low temperature polysilicon (LTPS) TFT, an oxide TFT (Oixde TFT), or a low temperature polycrystalline oxide (LTPO) TFT.

[0069] For example, Fig.11 As shown, the first sub-pixel driving circuit 12 and the second sub-pixel driving circuit 13 are both 7T1C driving circuits, in which the T3 transistor is a driving transistor, and the remaining six transistors are switch transistors. The width-to-length ratio of the channel region of the T3 transistor in the first sub-pixel driving circuit 12 is greater than the width-to-length ratio of the channel region of the T3 transistor in the second sub-pixel driving circuit 13. Under the same driving voltage, the brightness of the target sub-pixel corresponding to the first sub-pixel driving circuit 12 can be greater than the brightness of the sub-pixel corresponding to the second sub-pixel driving circuit 13, so that the brightness in the gamma calibration area 101 formed by the target sub-pixel is the highest brightness area of ​​the display panel 10.

[0070] like Fig.12 and Fig.13 As shown, the working principle of the 7T1C drive circuit is: Initialization stage: the control signal Reset is turned on (EM and Gate are turned off), the Reset signal is low level, the EM and Gate signals are high level, T1 and T3 are turned on, and the other transistors are turned off. The voltage Vint resets the voltage to charge and reset the N1 point and the OLED anode voltage, in order to turn off the OLED and initialize the voltage at the N1 point. Data writing compensation stage: the control signal Gate is turned on (Reset and EM are turned off), Gate is a low-level signal, Reset and EM are high-level signals, T2, T3, T4, and T7 are turned on, and the remaining transistors are turned off. The Data voltage is charged to point N1, and the luminous effect of the OLED is adjusted through the compensation mechanism.

[0071] Light-emitting stage: the control signal EM is turned on (Reset and Gate are closed), EM is a low-level signal, Reset and Gate are high-level signals, T3, T5, and T6 are turned on, and the remaining transistors are turned off. VDD flows to VSS, turning on the OLED to emit light.

[0072] In a second aspect, a method for preparing a display panel 10 is provided, comprising: A pixel driving circuit is formed on a substrate 11, wherein the pixel driving circuit includes a first sub-pixel driving circuit 12 and a plurality of second sub-pixel driving circuits 13, wherein the first sub-pixel driving circuit 12 includes a first driving transistor 121, wherein the first driving transistor 121 includes a first channel region 1211; the second sub-pixel driving circuit 13 includes a second driving transistor 131, wherein the second driving transistor 131 includes a second channel region 1310, and the second channel regions 1310 corresponding to the second driving transistors 131 have the same width-to-length ratio; wherein the width-to-length ratio is a ratio of a width to a length of a corresponding channel region, wherein the length of the channel region is a length of a path for current to flow in the channel region, and the width of the channel region is a channel dimension perpendicular to a current flow direction; A plurality of sub-pixels are formed on a side of the pixel driving circuit away from the base substrate 11 , wherein the sub-pixels corresponding to the first pixel driving circuit are target sub-pixels, and the target sub-pixels form a gamma calibration area 101 .

[0073] Specifically, a pixel driving circuit is formed on the base substrate 11, and the pixel driving circuit includes a plurality of sub-pixel driving circuits distributed in an array, and the plurality of sub-pixel driving circuits include a target sub-pixel driving circuit; a pixel definition layer is formed on the side of the pixel driving circuit away from the base substrate 11, and the pixel definition layer has a plurality of opening areas, and sub-pixels are arranged in the opening areas, and the sub-pixels and the sub-pixel driving circuits are arranged one by one to achieve independent driving control of each sub-pixel. The plurality of sub-pixels include a target sub-pixel, and the target sub-pixel forms a gamma calibration area 101, and the sub-pixel driving circuit corresponding to the target sub-pixel is a first sub-pixel driving circuit 12, and the sub-pixel driving circuit corresponding to the remaining sub-pixels is a second sub-pixel driving circuit 13. Since the width-to-length ratio of the first channel region 1211 of the first driving transistor 121 of the first sub-pixel driving circuit 12 is greater than the width-to-length ratio of the second channel region 1310 of the second driving transistor 131 of the second sub-pixel driving circuit 13, the first sub-pixel driving circuit 12 and the second sub-pixel driving circuit 13 can, under the same driving voltage, make the brightness of the target sub-pixel in the gamma calibration area 101 greater than the brightness of the sub-pixel outside the gamma calibration area 101, so that the brightness in the gamma calibration area 101 formed by the target sub-pixel is the area with the highest brightness of the display panel 10, and after gamma calibration and PUC, the brightness uniformity of the display panel 10 can be improved, wherein gamma calibration and PUC are conventional technical means in this field and will not be elaborated in this application.

[0074] It should be noted that in the embodiment of the present application, although the brightness of the target sub-pixel driven by the first sub-pixel driving circuit 12 on the base substrate 11 and the brightness of the sub-pixel driven by the second sub-pixel driving circuit 13 are different, it does not affect the final display effect of the display panel 10. This is because UC itself is a pixel-level brightness compensation. When all sub-pixels on the final display panel 10 display the same brightness, their driving voltages will also be different. It can be understood that each sub-pixel has an independent gamma calibration curve.

[0075] It is understandable that the first sub-pixel driving circuit 12 and the second sub-pixel circuit can be formed by the same patterning process, without increasing the number of masks and the process flow, wherein the patterning process includes conventional technical means such as coating photoresist, mask exposure, development, etching, and stripping photoresist. In some embodiments, the width of the first channel region 1211 is increased or / and the length of the first channel region 1211 is decreased so that the width-to-length ratio of the first channel region 1211 is greater than the width-to-length ratio of the second channel region 1310 .

[0076] Specifically, Figures 7 to 9 As shown, by changing the width and / or length of the first channel region 1211 , the width-to-length ratio of the first channel region 1211 can be made greater than the width-to-length ratio of the second channel region 1310 .

[0077] In some embodiments, the shape of the first channel region 1211 is changed so that the width-to-length ratio of the first channel region 1211 is greater than the width-to-length ratio of the second channel region 1310 .

[0078] Specifically, Fig.10 As shown, by changing the shape of the first channel region 1211 , the width-to-length ratio of the first channel region 1211 can be made greater than the width-to-length ratio of the second channel region 1310 .

[0079] It can be understood that the method for preparing the display panel 10 provided in the embodiment of the present application is used to obtain the display panel 10 described in any embodiment of the present application, and its specific technical features and technical effects are consistent with the display panel 10, and the embodiment of the present application will not be repeated.

[0080] test Comparative Example 1 The central area of ​​the existing display panel 10 is used as the gamma calibration area 101, and the brightness result of the display panel 10 after PUC is shown in Table 1; the width-to-length ratios of the channel regions of the driving transistors of the pixel driving circuits corresponding to each sub-pixel in the existing display panel 10 are all equal, such as Figure 5 As shown, the width-to-length ratio of the channel region of the driving transistor in the gamma calibration region is equal to the width-to-length ratio of the second channel region of the second sub-pixel driving circuit.

[0081] Example 1 A gamma calibration area 101 is formed with the target sub-pixel of the display panel 10 provided in the present application (the target sub-pixel is located in the central area of ​​the display panel 10), and the brightness result of the display panel 10 after PUC is shown in Table 1, wherein the width-to-length ratio of the first channel region 1211 of the first driving transistor corresponding to the target sub-pixel in the gamma calibration area 101 is greater than the width-to-length ratio of the second channel region 1310 of the second driving transistor corresponding to the sub-pixel outside the gamma calibration area 101.

[0082] Table 1 shows the PUC results after gamma calibration for different display panels.

[0083] Among them, Y represents the brightness value, d Y The brightness DBV of the display panel 10 represents a small change or difference in brightness, which is used to accurately describe the change in brightness under different conditions. u and v are the color coordinates in CIE1976UCS (uniform color space), duv represents the difference between the color coordinates u and v and the target color coordinates, which is used to measure the degree of color deviation from the ideal state, reflecting the accuracy and consistency of the displayed color. A smaller duv value means that the color performance of the panel is more accurate and stable, and can better restore the true color of images and videos.

[0084] As shown in Table 1, in Comparative Example 1, the pixel brightness in the gamma calibration area 101 is lower than the pixel brightness in other areas of the screen, resulting in a poor final PUC effect, affecting the brightness uniformity of the display panel 10. The display panel 10 provided in Example 1 of the present application can improve the optical compensation uniformity of the display panel 10.

[0085] In a third aspect, a control method of a display panel 10 is provided, the control method being used to control the display panel 10 described in any embodiment of the present application, or being used to control the display panel 10 obtained by the method for preparing the display panel 10 described in any embodiment of the present application, the control method comprising: The first sub-pixel driving circuit 12 and the second sub-pixel driving circuit 13 drive corresponding sub-pixels to operate at the same driving voltage, so that the brightness of the sub-pixels in the gamma calibration area 101 is greater than the brightness of the sub-pixels outside the gamma calibration area 101 .

[0086] In a fourth aspect, a display device 100 is provided, wherein the display device 100 includes the display panel 10 described in any embodiment of the present application, or includes the display panel 10 obtained by the method for preparing the display panel 10 described in any embodiment of the present application.

[0087] The display device 100 includes the display panel 10 as described above, and may also include other components, for example, may include a circuit for providing an electrical signal to the display panel 10 to drive the display panel 10 to emit light, which circuit may be called a control circuit, and may include a circuit board and / or an IC (Integrate Circuit) electrically connected to the display panel 10.

[0088] In some embodiments, the display device 100 may be a lighting device, in which case the display device 100 is used as a light source to achieve a lighting function. For example, the display device 100 may be a backlight module in a liquid crystal display device 100, a lamp for internal or external lighting, or various signal lamps.

[0089] In other embodiments, the display device 100 may be a display substrate for realizing the function of displaying an image (i.e., a picture). The display device 100 may include a display or a product including a display. Among them, the display may be a flat panel display (Flat Panel Display, FPD), a micro display, etc. If divided according to whether the user can see the back of the display, the display may be a transparent display or an opaque display. If divided according to whether the display can be bent or curled, the display may be a flexible display or a normal display (which may be called a rigid display).

[0090] Examples of products incorporating a display may include: computer monitors, televisions, billboards, laser printers with display capabilities, telephones, cell phones, personal digital assistants (PDAs), laptop computers, digital cameras, camcorders, viewfinders, vehicles, large-area walls, theater screens or stadium signs, etc.

[0091] The technical features and beneficial effects of the above-mentioned display device 100 are the same as the technical features and beneficial effects of the display panel 1010 provided in the above-mentioned embodiment of the present disclosure, and will not be repeated here.

[0092] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other to form a technical solution.

Claims

1. A display panel, characterized in that: include: a plurality of sub-pixels and a pixel driving circuit, the plurality of sub-pixels including a target sub-pixel, the target sub-pixel forming a gamma calibration area, the pixel driving circuit including a first sub-pixel driving circuit disposed within the gamma calibration area and a plurality of second sub-pixel driving circuits disposed outside the gamma calibration area; The first sub-pixel driving circuit includes a first driving transistor, the first driving transistor includes a first channel region; the second sub-pixel driving circuit includes a second driving transistor, the second driving transistor includes a second channel region, and the width-to-length ratios of the second channel regions corresponding to the second driving transistors are the same; The width-to-length ratio of the first channel region is greater than the width-to-length ratio of the second channel region; wherein the width-to-length ratio is the ratio of the width and length of the corresponding channel region, the length of the channel region is the length of the path of current flowing in the channel region, and the width of the channel region is the channel dimension perpendicular to the direction of current flow.

2. The display panel according to claim 1, characterized in that: The width-to-length ratio of the first channel region is increased by 10%-20% relative to the width-to-length ratio of the second channel region.

3. The display panel according to claim 1, characterized in that: A substrate is disposed on a side of the pixel driving circuit away from the sub-pixel, and projection shapes of the first channel region and the second channel region on the substrate are the same or different.

4. The display panel according to claim 3, characterized in that: The first channel region and the second channel region both include a first connecting segment, a second connecting segment and a third connecting segment, and two ends of the second connecting segment are respectively bent and connected to the first connecting segment and the third connecting segment.

5. The display panel according to claim 4, characterized in that: The projection shapes of the first connecting segment, the second connecting segment and the third connecting segment on the base substrate are all square.

6. The display panel according to claim 4, characterized in that: The first connecting segment and the third connecting segment are located on the same side of the second connecting segment, the first connecting segment is perpendicular to the second connecting segment, the third connecting segment is perpendicular to the second connecting segment, and the path lengths of the first connecting segment and the third connecting segment along the current flow direction are equal.

7. The display panel according to claim 4, characterized in that: The path length of the second connection section of the first channel region along the current flow direction is shorter than the path length of the second connection section of the second channel region along the current flow direction; or / and, The path length of the first connection section of the first channel region along the current flow direction is shorter than the path length of the first connection section of the second channel region along the current flow direction; or / and, A channel dimension of the second connecting section of the first channel region along a direction perpendicular to the current flow is greater than a channel dimension of the second connecting section of the second channel region along a direction perpendicular to the current flow.

8. The display panel according to claim 4, characterized in that: The second connecting section of the first channel region and the second connecting section of the second channel region have different projected shapes on the substrate, and the channel size of the second connecting section of the first channel region along the direction perpendicular to the current flow is larger than the channel size of the second connecting section of the second channel region along the direction perpendicular to the current flow.

9. The display panel according to claim 8, characterized in that: The second connecting section of the first channel region includes a first end face and a second end face that are oppositely arranged, at least one of the first end face and the second end face is an arcuate face or a V-shaped face, and the projection shape of the second connecting section of the second channel region on the substrate is a square; the distance between the first end face and the second end face is greater than the channel size of the second connecting section of the second channel region along a direction perpendicular to the current flow.

10. The display panel according to any one of claims 1 to 9, characterized in that: There are one or more target sub-pixels, each of which is arranged in a one-to-one correspondence with the first sub-pixel driving circuit, and the target sub-pixels are located in a central area of ​​the display panel.

11. A method for preparing a display panel, characterized in that: include: A pixel driving circuit is formed on a substrate, wherein the pixel driving circuit includes a first sub-pixel driving circuit and a plurality of second sub-pixel driving circuits, wherein the first sub-pixel driving circuit includes a first driving transistor, wherein the first driving transistor includes a first channel region; the second sub-pixel driving circuit includes a second driving transistor, wherein the second driving transistor includes a second channel region, and the width-to-length ratio of the second channel regions corresponding to the second driving transistors is the same; wherein the width-to-length ratio is a ratio of a width to a length of a corresponding channel region, wherein the length of the channel region is a length of a path for current to flow in the channel region, and the width of the channel region is a channel dimension perpendicular to a current flow direction; A plurality of sub-pixels are formed on a side of the pixel driving circuit away from the base substrate, wherein the sub-pixels corresponding to the first pixel driving circuit are target sub-pixels, and the target sub-pixels form a gamma calibration area.

12. The method for preparing a display panel according to claim 11, characterized in that: The width of the first channel region is increased or / and the length of the first channel region is decreased so that the width-to-length ratio of the first channel region is greater than the width-to-length ratio of the second channel region.

13. The method for preparing a display panel according to claim 11, characterized in that: The shape of the first channel region is changed so that the width-to-length ratio of the first channel region is greater than the width-to-length ratio of the second channel region.

14. A method for controlling a display panel, characterized in that: The control method is used to control the display panel according to any one of claims 1 to 10, or is used to control the display panel obtained by the method for preparing the display panel according to any one of claims 11 to 13, and the control method comprises: The first sub-pixel driving circuit and the second sub-pixel driving circuit drive corresponding sub-pixels to operate at the same driving voltage, so that the brightness of the sub-pixels in the gamma calibration area is greater than the brightness of the sub-pixels outside the gamma calibration area.

15. A display device, characterized in that: The display device comprises the display panel according to any one of claims 1 to 10, or comprises a display panel obtained by the method for preparing a display panel according to any one of claims 11 to 13.

Images