Display signal control method, driving chip and display screen

Abstract

The embodiment of the invention relates to a display signal control method, a driving chip and a display screen. The control method comprises the following steps: receiving a first signal sent by a time sequence control device; caching the first signal to a frame caching module; extracting the first signal from the frame buffer module, and converting the first signal into a second signal for driving a display circuit; and sending the second signal to the display circuit. According to the invention, the first signal is cached and then extracted and converted, and the original high peak bandwidth is reduced to the average bandwidth of one frame, so that the number of interfaces and the rate do not need to be increased, and the power consumption of a chip is reduced.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the technical field of display signal transmission, and in particular to a display signal control method, a driver chip, and a display screen. Background Art

[0002] The significant difference between passive drive (PM, Passive Matrix) and active drive (AM, Active Matrix) is whether each LED has an independent and controllable drive circuit. PM drive means that all LED lights share a set of drive circuits and use time-sharing multiplexing, so it is impossible to display all images at the same time. AM drive means that each LED has its own independent drive circuit, so the images can be displayed simultaneously without time-sharing multiplexing. In general, the display architectures of PM and AM are very different, and the problems introduced are also different.

[0003] With the continuous advancement of Mini-LED and Micro-LED technology, screen resolution is getting higher and higher, and a variety of pixel circuits have emerged. The driving principle and timing of each pixel circuit are different, which is reflected in the source chip (Source IC). The peak bandwidth required to update the data for screens with different resolutions and different pixel circuits may be different, and the difference in bandwidth may be relatively large. How to make the timing controller (TCON) and Source IC adapt to this change well is related to the cost and display quality of the entire Mini / Micro-LED product.

[0004] In the prior art, the bandwidth requirement is met by increasing the number of interfaces at the transmitting and receiving ends. With the increasing demand for splicing screens, it is difficult to meet the demand simply by increasing the number of interfaces, because each additional interface places higher hardware requirements on the Source IC and TCON. At the same time, the increase in bandwidth is reflected in the splicing screen, which increases exponentially. Therefore, this method will not only increase the hardware complexity, but also the cost.

[0005] Regarding the above technical solution, the inventors found that there are at least the following technical problems: This method of increasing the number of interfaces has the problem that the peak bandwidth of the AM driver chip is too large. There is also the problem that the peak bandwidth of the AM splicing screen TCON is too large, which leads to the cost of increasing the interface.

[0006] Therefore, it is necessary to improve one or more problems existing in the above-mentioned related technical solutions.

[0007] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0008] The purpose of the embodiments of the present disclosure is to provide a display signal control method, a driver chip and a display screen, thereby at least solving the problem of excessive peak bandwidth of the AM driver chip and the problem of increased interface cost caused by excessive peak bandwidth of the AM splicing screen TCON.

[0009] The purpose of the present invention is achieved by the following technical solutions:

[0010] In a first aspect, the present invention provides a method for controlling a display signal, the control method comprising:

[0011] receiving a first signal sent by a timing control device;

[0012] Buffering the first signal into a frame buffer module;

[0013] Extracting the first signal from the frame buffer module, and converting the first signal into a second signal for driving a display circuit;

[0014] The second signal is sent to the display circuit.

[0015] Optionally, the step of caching the first signal in a frame buffer module specifically includes:

[0016] Buffering the first signal to a frame buffer module through a bus interface;

[0017] The first signal is extracted from the frame buffer module through the bus interface.

[0018] Optionally, the step of extracting the first signal from the frame buffer module and converting the first signal into a second signal for driving a display circuit specifically includes:

[0019] Generate the second signal by performing level conversion on the first signal;

[0020] The second signal is sent to a display circuit corresponding to the output channel.

[0021] In a second aspect, the present invention provides a driver chip, the driver chip comprising:

[0022] A signal interface, the signal interface is used to receive a first signal sent by the timing control device;

[0023] A frame buffer module, wherein the frame buffer module is used to buffer the first signal;

[0024] a conversion module, the conversion module being used to extract the first signal from the frame buffer module and convert the first signal into a second signal for driving a display circuit;

[0025] An output channel, wherein the output channel is used to send the second signal to the display circuit.

[0026] Optionally, the frame buffer module includes: a frame buffer unit, which is arranged in the driving chip and directly connected to the signal interface.

[0027] Optionally, the frame buffer module includes: a bus interface, the bus interface is directly connected to a frame buffer unit, the frame buffer unit is arranged outside the driving chip, and the bus interface is used to buffer the first signal to the frame buffer unit.

[0028] Optionally, the conversion module includes: a data latch unit, the data latch unit is connected to the frame buffer module, and the data latch unit is used to extract the first signal.

[0029] Optionally, the conversion module further includes: a level conversion unit, which is connected to the data latch unit and is used to convert the first signal into a second signal for driving a display circuit.

[0030] Optionally, the driving chip is a SourceIC; and the frame buffer unit is a frame buffer RAM.

[0031] In a third aspect, the present invention provides a display screen, which is driven and displayed using a driver chip described in any one of the above embodiments.

[0032] The technical solution provided by the embodiments of the present disclosure may have the following beneficial effects:

[0033] In the embodiment of the present disclosure, by first caching the first signal and then extracting and converting it, the originally high peak bandwidth is reduced to an average bandwidth of one frame, thereby eliminating the need to increase the number and rate of interfaces and reducing chip power consumption.

[0034] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0036] Figure 1 A schematic flow chart showing a method for controlling a display signal in an exemplary embodiment of the present disclosure;

[0037] Figure 2 A schematic diagram showing the internal structure of a Source IC in the related art is shown;

[0038] Figure 3 A schematic diagram showing a process of caching and extracting a first signal through a bus interface in an exemplary embodiment of the present disclosure;

[0039] Figure 4 A schematic diagram showing a process of converting a first signal into a second signal in an exemplary embodiment of the present disclosure;

[0040] Figure 5 A schematic diagram showing a structure in which a frame buffer module is arranged inside a driver chip in an exemplary embodiment of the present disclosure;

[0041] Figure 6 A schematic diagram showing a structure in which a frame buffer module is arranged outside a driving chip in an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0042] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the disclosure will be more comprehensive and complete and to fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0043] In addition, the accompanying drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0044] In this exemplary embodiment, a method for controlling a display signal is first provided. Figure 1 As shown in, including:

[0045] Step S101: receiving a first signal sent by a timing control device.

[0046] Step S102: Buffer the first signal in a frame buffer module.

[0047] Step S103: extracting a first signal from the frame buffer module, and converting the first signal into a second signal for driving the display circuit.

[0048] Step S104: Send the second signal to the display circuit.

[0049] It should be understood that the first signal is a signal sent by TCON, which is different from the video signal. It refers to the specific row and column drive signal required by the display panel, that is, the timing pulse signal. The second signal is the channel signal that lights up the specific LED in the LED array. That is, it is a signal that controls the on and off state of the display channel. The display circuit is an LED array circuit.

[0050] It is also important to understand that reference Figure 2 As shown, Figure 2 The internal structure of Source IC in the related art. As the demand for splicing screens continues to increase, the number of interfaces continues to increase. Therefore, there is a problem of excessive peak bandwidth of AM driver chips. There is also a problem of increasing the cost of interfaces due to excessive peak bandwidth of AM splicing screen TCON.

[0051] It is also necessary to understand that the control method of the present application first caches the first signal sent by TCON in the frame buffer module, then extracts the first signal from it and converts it. The frame buffer module is a frame buffer RAM, and the frame buffer RAM can be placed inside the Source IC or outside the Source IC through a bus connection. In this way, the interface processing capability can reduce the originally high peak bandwidth to an average bandwidth of one frame.

[0052] According to the above display signal control method, by first caching the first signal and then extracting and converting it, the originally high peak bandwidth is reduced to an average bandwidth of one frame, thereby eliminating the need to increase the number and rate of interfaces and reducing chip power consumption.

[0053] Next, we will refer to Figures 1 to 4 Each step of the above-mentioned display signal control method in this exemplary embodiment is described in more detail.

[0054] refer to Figure 3 As shown, step S103 specifically includes:

[0055] Step S301: Buffering a first signal into a frame buffer module via a bus interface.

[0056] Step S302: extracting a first signal from a frame buffer module via a bus interface.

[0057] It should be understood that the frame buffer module is a frame buffer RAM, which is set outside the Source IC through a bus connection. Specifically, the first signal sent by TCON is received, the first signal is buffered to the Display RAM through the Bus Ctrl, and the first signal is extracted from the Display RAM through the Bus Ctrl and converted.

[0058] refer to Figure 4 As shown, step S103 specifically includes:

[0059] Step S401: generating a second signal by performing level conversion on a first signal.

[0060] Step S402: Send the second signal to the display circuit corresponding to the output channel.

[0061] It should be understood that the timing pulse signal sent by TCON is converted into a driving voltage that meets the lighting requirements of the LED through level conversion.

[0062] Furthermore, in this exemplary embodiment, a driver chip is also provided. Figure 5 and Figure 6 As shown, the driver chip includes:

[0063] A signal interface, the signal interface is used to receive a first signal sent by the timing control device;

[0064] A frame buffer module, the frame buffer module is used to buffer the first signal;

[0065] A conversion module, the conversion module is used to extract a first signal from the frame buffer module and convert the first signal into a second signal for driving a display circuit;

[0066] The output channel is used to send the second signal to the display circuit.

[0067] It should be understood that the driver chip is SourceIC and the frame buffer unit is frame buffer RAM.

[0068] It is also necessary to understand that the frame buffer RAM can be set inside the Source IC or outside the Source IC through a bus connection. There is no need to increase the number and rate of interfaces, and the chip power consumption is reduced. This provides a basis for the driver chip to implement algorithms such as IR-Drop.

[0069] Next, we will refer to Figure 5 and Figure 6 The above-mentioned driver chip in this exemplary embodiment is described in more detail.

[0070] refer to Figure 5As shown, the frame buffer module includes: a frame buffer unit, which is arranged in the driver chip and directly connected to the signal interface. It should be understood that the frame buffer RAM is placed inside the Source IC, so that the interface processing capability can reduce the originally high peak bandwidth to the average bandwidth of one frame.

[0071] refer to Figure 6 As shown, the frame buffer module includes: a bus interface, the bus interface is directly connected to the frame buffer unit, the frame buffer unit is arranged outside the driver chip, and the bus interface is used to buffer the first signal to the frame buffer unit. It should be understood that the frame buffer RAM is placed outside the Source IC, and the Source IC and the frame buffer RAM are connected through the on-chip bus. During the display process, the display data received by the Source IC is first sent to the frame buffer RAM outside the chip through the bus interface, and the Source IC reads the display data when displaying.

[0072] refer to Figure 5 and Figure 6 As shown, the conversion module includes: a data latch unit, the data latch unit is connected to the frame buffer module, and the data latch unit is used to extract the first signal. It should be understood that the data latch unit is a level-triggered storage unit, and the data storage action depends on the level value of the input clock (or enable) signal. When in the enabled state, the output will change with the data input.

[0073] refer to Figure 5 and Figure 6 As shown, the conversion module further includes: a level conversion unit, the level conversion unit is connected to the data latch unit, and is used to convert the first signal into a second signal for driving the display circuit. It should be understood that the level conversion unit is a Level Shift, which can boost the DVDD voltage to the AVDD voltage.

[0074] Furthermore, in this exemplary embodiment, a display screen is also provided, including: the display screen is driven and displayed by a driver chip in any one of the above embodiments.

[0075] The specific manner of driving the chip and the display device has been described in detail in the embodiment of the driving method of the display signal, and will not be elaborated here.

[0076] It should be noted that although several modules or units of the device for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiment of the present disclosure, the features and functions of two or more modules or units described above can be concretized in one module or unit. Conversely, the features and functions of a module or unit described above can be further divided into multiple modules or units for concretization. The components displayed as modules or units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the disclosed scheme. Those of ordinary skill in the art can understand and implement it without paying creative work.

[0077] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A method for controlling a display signal, characterized in that: The control method comprises: receiving a first signal sent by a timing control device; Buffering the first signal into a frame buffer module; Extracting the first signal from the frame buffer module, and converting the first signal into a second signal for driving a display circuit; The second signal is sent to the display circuit.

2. The control method according to claim 1, characterized in that: The step of caching the first signal into a frame buffer module specifically includes: Buffering the first signal to a frame buffer module through a bus interface; The first signal is extracted from the frame buffer module through the bus interface.

3. The control method according to claim 1 or 2, characterized in that: The step of extracting the first signal from the frame buffer module and converting the first signal into a second signal for driving a display circuit specifically includes: Generate the second signal by performing level conversion on the first signal; The second signal is sent to a display circuit corresponding to the output channel.

4. A driver chip, characterized in that: The driver chip comprises: A signal interface, the signal interface is used to receive a first signal sent by the timing control device; A frame buffer module, wherein the frame buffer module is used to buffer the first signal; a conversion module, the conversion module being used to extract the first signal from the frame buffer module and convert the first signal into a second signal for driving a display circuit; An output channel is used to send the second signal to the display circuit.

5. The driver chip according to claim 4, characterized in that: The frame buffer module includes: a frame buffer unit, which is arranged in the driving chip and directly connected to the signal interface.

6. The driver chip according to claim 4, characterized in that: The frame buffer module includes: a bus interface, the bus interface is directly connected to a frame buffer unit, the frame buffer unit is arranged outside the driving chip, and the bus interface is used to buffer the first signal to the frame buffer unit.

7. The driver chip according to any one of claims 5 to 6, characterized in that: The conversion module includes: a data latch unit, the data latch unit is connected to the frame buffer module, and the data latch unit is used to extract the first signal.

8. The driver chip according to claim 7, characterized in that: The conversion module further includes: a level conversion unit, which is connected to the data latch unit and is used to convert the first signal into a second signal for driving a display circuit.

9. The driver chip according to claim 8, characterized in that: The driving chip is SourceIC; the frame buffer unit is frame buffer RAM.

10. A display screen, characterized in that: The display screen is driven by the driver chip described in any one of claims 4 to 9.

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