Display driving chip and display device

Abstract

The invention provides a display driving chip and a display device, the display driving chip comprises a data processing unit and a pixel unit, the data processing unit comprises a data latch module, a multi-bit digital comparison module, a counter module and a sampling module; the data latch module converts serial data into multi-bit parallel data and sends a counting enable signal to the counter module; the counter module executes counting operation based on the counting enable signal and outputs a counting value to the multi-bit digital comparison module; the multi-bit digital comparison module compares the multi-bit parallel data with the count value and outputs a sampling signal; the sampling module performs voltage sampling on the ramp signal based on the sampling signal and outputs a sampling voltage; and the pixel unit outputs a corresponding pixel signal under the action of the sampling voltage. High-gray-scale display and high-dynamic-range display are achieved, and meanwhile the requirements of the modern display technology for high-gray-scale precision, high integration level, low power consumption and high color rendition degree are met.

Description

Technical Field

[0001] The present application relates to the field of semiconductor display technology, and in particular to a display driver chip and a display device. Background Art

[0002] With the rapid development of display technology, Light Emitting Diode (LED) display technology has been widely used in various display devices, especially the Micro-LED and Mini-LED technologies that have emerged in recent years. With their advantages of high brightness, high contrast, long life and low power consumption, they have become an important development direction of the new generation of display technology.

[0003] Existing LED driving circuits still have many limitations in grayscale control, integration, and power management. Traditional LED driving technology mainly relies on pulse width modulation (PWM) or current regulation to control brightness, but its grayscale accuracy is often insufficient and it is difficult to meet the needs of high dynamic range (HDR) display. At the same time, the integration is low, resulting in complex circuits and not conducive to miniaturization. In addition to the problems of traditional LED driving technology, Micro-LED display technology has also put forward higher requirements, such as supporting grayscale display of 10 bits and above, higher integration of driving circuits, lower power consumption and high-speed data processing capabilities to adapt to application scenarios such as ultra-high-definition display, AR / VR equipment and flexible display. However, to meet these requirements, the traditional driving circuit structure is no longer applicable.

[0004] Therefore, a new solution for high-integration and high-precision display circuits is urgently needed. Summary of the invention

[0005] The purpose of the present application is to provide a display driver chip and a display device, and to provide a highly integrated and high-precision display circuit, in order to address the deficiencies in the above-mentioned prior art.

[0006] To achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:

[0007] In a first aspect, an embodiment of the present application provides a display driver chip, the display driver chip comprising: a data processing unit and a pixel unit, the data processing unit comprising a data latch module, a multi-bit digital comparison module, a counter module and a sampling module;

[0008] The first input end of the data latch module serves as the first pin of the display driver chip, and is used to receive the serial data input by the user. The second input end of the data latch module serves as the second pin of the display driver chip, and is used to receive the clock signal. The first output end of the data latch module is connected to the first input end of the multi-bit digital comparison module, and the second output end of the data latch module is connected to the first input end of the counter module.

[0009] The second input end of the counter module is connected to the third output end of the data latch module, the output end of the counter module is connected to the second input end of the multi-bit digital comparison module, the output end of the multi-bit digital comparison module is connected to the first input end of the sampling module, the second input end of the sampling module is used to access the ramp signal, the second input end of the sampling module serves as the third pin of the display driver chip, and the output end of the sampling module is connected to the pixel unit;

[0010] The data latch module is used to convert the serial data into multi-bit parallel data and send a counting enable signal to the counter module, wherein the serial data is used to indicate the pixel grayscale data to be displayed input by the user; the counter module is used to perform a counting operation based on the counting enable signal sent by the data latch module, and output a counting value to the multi-bit digital comparison module; the multi-bit digital comparison module is used to compare the multi-bit parallel data with the counting value and output a sampling signal to the sampling module; the sampling module is used to perform voltage sampling on the ramp signal based on the sampling signal, output a sampling voltage, and send the sampling voltage to the pixel unit; the pixel unit is used to output a corresponding pixel signal under the action of the sampling voltage.

[0011] Optionally, the first output terminal of the data latch module includes: a first latch sub-output terminal, a second latch sub-output terminal and a third latch sub-output terminal; the first input terminal of the multi-bit digital comparison module includes: a first comparison sub-input terminal, a second comparison sub-input terminal and a third comparison sub-input terminal;

[0012] The first latch sub-output terminal is connected to the first comparison sub-input terminal, the second latch sub-output terminal is connected to the second comparison sub-input terminal, and the third latch sub-output terminal is connected to the third comparison sub-input terminal;

[0013] The data latch module is specifically used to output R channel parallel grayscale data to the multi-bit digital comparison module through the first latch sub-output end, output G channel parallel grayscale data to the multi-bit digital comparison module through the second latch sub-output end, and output B channel parallel grayscale data to the multi-bit digital comparison module through the third latch sub-output end in accordance with a preset timing sequence, and after sending data to the multi-bit digital comparison module, send the counting enable signal to the counter module.

[0014] Optionally, the second output terminal of the multi-bit digital comparison module includes: a first comparison sub-output terminal, a second comparison sub-output terminal and a third comparison sub-output terminal; the first input terminal of the sampling module includes: a first sampling sub-input terminal, a second sampling sub-input terminal and a third sampling sub-input terminal;

[0015] The first comparison sub-output terminal is connected to the first sampling sub-input terminal, the second comparison sub-output terminal is connected to the second sampling sub-input terminal, and the third comparison sub-output terminal is connected to the third sampling sub-input terminal;

[0016] The multi-bit digital comparison module is specifically used to compare the R channel parallel grayscale data with the count value and output the R channel sampling signal to the sampling module through the first comparison sub-output end, compare the G channel parallel grayscale data with the count value and output the G channel sampling signal to the sampling module through the second comparison sub-output end, and compare the B channel parallel grayscale data with the count value and output the B channel sampling signal to the sampling module through the third comparison sub-output end.

[0017] Optionally, the output end of the sampling module includes: a first voltage sub-output end, a second voltage sub-output end and a third voltage sub-output end;

[0018] The first voltage sub-output terminal, the second voltage sub-output terminal and the third voltage sub-output terminal are respectively connected to the pixel unit;

[0019] The sampling module is specifically used to perform voltage sampling on the ramp signal based on the R channel sampling signal and output the R channel sampling voltage through the first voltage sub-output terminal, perform voltage sampling on the ramp signal based on the G channel sampling signal and output the G channel sampling voltage through the second voltage sub-output terminal, and perform voltage sampling on the ramp signal based on the B channel sampling signal and output the B channel sampling voltage through the third voltage sub-output terminal.

[0020] Optionally, the pixel unit includes: a first pixel module, a second pixel module and a third pixel module;

[0021] The first voltage sub-output terminal of the data processing unit is connected to the first input terminal of the first pixel module, the second voltage sub-output terminal of the data processing unit is connected to the first input terminal of the second pixel module, and the third voltage sub-output terminal of the data processing unit is connected to the first input terminal of the third pixel module.

[0022] Optionally, the data processing unit further comprises: a chip enable output terminal;

[0023] The chip enable output terminal is respectively connected to the second input terminal of the first pixel module, the second input terminal of the second pixel module, and the second input terminal of the third pixel module.

[0024] Optionally, the data processing unit further comprises: a pixel enable output terminal;

[0025] The pixel enable output terminal is respectively connected to the third input terminal of the first pixel module, the third input terminal of the second pixel module, and the third input terminal of the third pixel module.

[0026] Optionally, the first pixel module includes: a first field effect transistor, a second field effect transistor, a third field effect transistor and a first capacitor;

[0027] The first end of the first field effect transistor is connected to the first voltage sub-output end of the sampling module, the second end of the first field effect transistor is connected to the chip enable output end, and the third end of the first field effect transistor is respectively connected to one end of the first capacitor and the second end of the second field effect transistor;

[0028] The first end of the second field effect tube is connected to the third end of the third field effect tube, and the second end of the second field effect tube is used to connect to a power source;

[0029] The first end of the third field effect transistor is used to connect to the pixel electrode, and the second end of the third field effect transistor is connected to the pixel enable output terminal; the other end of the first capacitor is connected to the ground;

[0030] The first field effect transistor is closed or turned off based on the chip enable signal output by the chip enable output terminal, the second field effect transistor is closed based on connecting the power supply, and the third field effect transistor is closed or turned off based on the pixel enable signal output by the pixel enable output terminal. If the first field effect transistor, the second field effect transistor and the third field effect transistor are all closed, the first pixel module outputs an R pixel signal under the action of the R channel sampling voltage output by the sampling module.

[0031] Optionally, the power terminal of the pixel unit is connected to an external power supply, the ground terminal of the pixel unit is used for grounding, the power terminal serves as the fourth pin of the display driver chip, and the ground terminal serves as the fifth pin of the display driver chip.

[0032] In a second aspect, an embodiment of the present application further provides a display device, comprising the display driver chip described in the first aspect.

[0033] The beneficial effects of this application are:

[0034] The present application provides a display driver chip and a display device, which converts serial data into multi-bit parallel data through a data latch module, and compares the multi-bit parallel data with the count value output by the counting module. When the count value is equal to the multi-bit parallel data, a sampling signal is output, and the timing count in the grayscale display process can be controlled by the counter module, so that an accurate sampling signal is output to ensure the accurate output of the grayscale level, so that the sampling module can perform voltage sampling on the input ramp signal based on the received sampling signal, thereby outputting a sampling voltage to the pixel unit, and the sampling module optimizes the accuracy of the output sampling voltage by combining the RAMP wave control signal, so that the pixel unit can output the corresponding pixel signal under the action of the sampling voltage. The control of high-bit grayscale display is realized, meeting the high dynamic range (HDR) display requirements, and significantly improving the detail expression and brightness uniformity of the picture. Secondly, a highly integrated design is adopted to integrate the data latch module, the multi-bit digital comparison module, the counter module and the sampling module into a packaged chip, which greatly improves the integration and reduces the package size, and is suitable for high-density display applications such as Micro-LED and Mini-LED. The present invention also improves color reproduction and display consistency through precise brightness and grayscale control, meeting the needs of high-end applications such as high-definition display, AR / VR display and medical imaging. At the same time, its modular design and programmable control interface provide high compatibility and flexibility, which can adapt to the needs of different display scenarios and are widely used in fields such as high-definition display screens, vehicle-mounted displays, wearable devices and industrial detection systems. The highly integrated design reduces external wiring and signal interference, improves the stability and anti-interference ability of circuit operation, improves product reliability and consistency, simplifies the production process and reduces costs. It meets the requirements of modern display technology for high grayscale accuracy, high integration, low power consumption and high color reproduction. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0036] Figure 1 A schematic diagram of the pin structure of a display driver chip provided in an embodiment of the present application;

[0037] Figure 2 A schematic diagram of the structure of a display driver chip provided in an embodiment of the present application;

[0038] Figure 3 A schematic diagram of a ramp signal provided in an embodiment of the present application;

[0039] Figure 4 A schematic diagram of the structure of a data processing unit provided in an embodiment of the present application;

[0040] Figure 5 A data conversion schematic diagram provided for an embodiment of the present application;

[0041] Figure 6 A schematic diagram of the structure of another display driver chip provided in an embodiment of the present application;

[0042] Figure 7 A schematic diagram of the structure of a pixel module provided in an embodiment of the present application. DETAILED DESCRIPTION

[0043] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of explanation and description and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn in real proportion. The flowchart used in this application shows the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowchart can be implemented out of sequence, and the steps without logical context can be reversed in order or implemented simultaneously. In addition, those skilled in the art can add one or more other operations to the flowchart under the guidance of the content of the present application, or remove one or more operations from the flowchart.

[0044] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0045] It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the existence of the features declared thereafter, but does not exclude the addition of other features.

[0046] The display driver chip provided in the embodiment of the present application is suitable for grayscale control and drive circuit design in Micro-LED, Mini-LED display devices and other high-precision display systems, and can be widely used in fields with high display accuracy and brightness requirements such as high-resolution display screens, wearable devices, vehicle-mounted displays, AR / VR displays, medical imaging equipment and industrial detection systems. The display driver chip in the present application is obtained by integrating the data processing function, voltage control function and drive function in one package.

[0047] Figure 1 A schematic diagram of the pin structure of a display driver chip provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, the package pins of the display driver chip mainly include an input power pin 1, an input data pin 2, an input ramp signal (RampSignal, RAMP) pin 3, an input clock signal pin 4 and a ground pin 5.

[0048] Figure 2 A schematic diagram of the structure of a display driver chip provided in an embodiment of the present application is shown in FIG. Figure 2 As shown, the display driver chip includes a data processing unit 10 and a pixel unit 11. The data processing unit 10 includes a data latch module 101, a multi-bit digital comparison module 102, a counter module 103 and a sampling module 104.

[0049] like Figure 2 As shown, the first input terminal of the data latch module 101 is used as the first pin of the display driver chip. Figure 1 The input data pin 2 in the display driver chip can be used to receive the serial data input by the user; the second input end of the data latch module 101 is used as the second pin of the display driver chip to receive the clock signal, such as Figure 1The input clock signal pin 4 in the data latch module 101; the first output terminal of the data latch module 101 is connected to the first input terminal of the multi-bit digital comparison module 102, and the second output terminal of the data latch module 101 can be connected to the first input terminal of the counter module 103.

[0050] Continue as Figure 2 As shown, the second input end of the counter module 103 can be connected to the third output end of the data latch module 101. After the data latch module 101 receives the clock signal, the received clock signal is sent to the counter module 103 through the third output end of the data latch module 101. The output end of the counter module 103 can be connected to the second input end of the multi-bit digital comparison module 102. The output end of the multi-bit digital comparison module 102 is connected to the first input end of the sampling module 104. The second input end of the sampling module 104 is used to access the ramp signal. The second input end of the sampling module 104 serves as the third pin of the display driver chip, as shown in FIG. Figure 1 The output end of the sampling module 104 is connected to the pixel unit 11.

[0051] The serial data may indicate the pixel grayscale data to be displayed input by the user, and the serial data includes 32 bits of data information, specifically including pixel enable data, chip enable data and grayscale data of three RGB channels.

[0052] Optionally, the data latch module 101 is used to convert serial data into multi-bit parallel data, and send a counting enable signal to the counter module 103; the counter module 103 is used to perform a counting operation based on the counting enable signal sent by the data latch module 101, and output a counting value to the multi-bit digital comparison module 102; the multi-bit digital comparison module 102 is used to compare the multi-bit parallel data with the counting value, and output a sampling signal to the sampling module 104. Specifically, when the multi-bit parallel data is equal to the counting value, the sampling signal is output to the sampling module 104; the sampling module 104 is used to perform voltage sampling on the ramp signal based on the sampling signal, output the sampling voltage, and send the sampling voltage to the pixel unit 11; the pixel unit 11 is used to output a corresponding pixel signal under the action of the sampling voltage.

[0053] Specifically, after receiving the serial data through the first input end of the data latch module, the data latch module 101 converts the serial data into multi-bit parallel data, and sends the converted multi-bit parallel data to the multi-bit digital comparison module 102 through the first output end of the data latch module 101. While receiving the serial data, the data latch module 101 also receives the clock signal through the second input end of the latch module 101. Specifically, the data latch module 101 receives the serial data bit by bit according to the received clock signal, and the data latch module 101 can also send the received clock signal to the counter module 103 through the third output end of the data latch module 101, so that the counter module 103 starts counting according to the clock signal after receiving the counter enable signal EN_CNT. Specifically, the counting process is based on the received clock signal, and each clock signal can be counted once, and the counter module 103 can also output the count value to the multi-bit digital comparison module 102.

[0054] Optionally, the multi-bit digital comparison module 102 compares the multi-bit parallel data received from the data latch module 101 with the count value received from the counter module 103, and outputs a sampling signal to the sampling module 104 according to the comparison result. The sampling module 104 can perform voltage sampling on the input ramp signal based on the received sampling signal, output the sampling voltage, and send the sampling voltage to the pixel unit 11. The pixel unit 11 can output a corresponding pixel signal under the action of the sampling voltage, wherein the pixel signal may refer to an R channel pixel signal, a G channel pixel signal, and a B channel pixel signal.

[0055] Among them, the start input of RAMP wave and the start counting of counter start at the same time, such as Figure 3 As shown, when the counter module 103 receives the counting enable signal, it starts counting, for example, counting from 0 to 1023 and then returning to zero. At this time, the RAMP wave also starts to be input. When the count reaches 1023 and returns to zero, the RAMP wave also returns to zero. When the counter module 103 counts from 0 to 1023, the RAMP wave also increases from 0 to 1023. The increase of the RAMP wave represents the increase of the grayscale value. Each grayscale value corresponds to a voltage value. For example, when the RAMP wave is 0, it corresponds to a grayscale voltage of 0, and when it is 1023, it corresponds to a grayscale voltage of 1023.

[0056] In this embodiment, the serial data is converted into multi-bit parallel data by the data latch module, and the multi-bit digital comparison module compares the multi-bit parallel data with the count value output by the counting module. When the count value is equal to the multi-bit parallel data, the sampling signal is output. Then, the timing count in the grayscale display process can be controlled by the counter module, so that an accurate sampling signal is output to ensure the accurate output of the grayscale level, so that the sampling module can perform voltage sampling on the input ramp signal based on the received sampling signal, thereby outputting the sampling voltage to the pixel unit. The sampling module optimizes the accuracy of the output sampling voltage by combining the RAMP wave control signal, so that the pixel unit can output the corresponding pixel signal under the action of the sampling voltage. The control of high-bit grayscale display is realized, meeting the requirements of high dynamic range (HDR) display, and significantly improving the detail expression and brightness uniformity of the picture. Secondly, a highly integrated design is adopted to integrate the data latch module, the multi-bit digital comparison module, the counter module and the sampling module into a packaged chip, which greatly improves the integration and reduces the package size, and is suitable for high-density display applications such as Micro-LED and Mini-LED. The present invention also improves color reproduction and display consistency through precise brightness and grayscale control, meeting the needs of high-end applications such as high-definition display, AR / VR display and medical imaging. At the same time, its modular design and programmable control interface provide high compatibility and flexibility, which can adapt to the needs of different display scenarios and are widely used in fields such as high-definition display screens, vehicle-mounted displays, wearable devices and industrial detection systems. The highly integrated design reduces external wiring and signal interference, improves the stability and anti-interference ability of circuit operation, improves product reliability and consistency, simplifies the production process and reduces costs. It meets the requirements of modern display technology for high grayscale accuracy, high integration, low power consumption and high color reproduction.

[0057] Figure 4 A structural diagram of a data processing unit provided in an embodiment of the present application is shown in FIG. Figure 4 As shown, the first output terminal of the data latch module 101 may include: a first latch sub-output terminal, a second latch sub-output terminal and a third latch sub-output terminal, and the first input terminal of the multi-bit digital comparison module 102 includes: a first comparison sub-input terminal, a second comparison sub-input terminal and a third comparison sub-input terminal;

[0058] Continue as Figure 4 As shown, the first latch sub-output terminal is connected to the first comparison sub-input terminal, the second latch sub-output terminal is connected to the second comparison sub-input terminal, and the third latch sub-output terminal is connected to the third comparison sub-input terminal.

[0059] Optionally, the data latch module 101 can output R channel parallel grayscale data to the multi-bit digital comparison module 102 through the first latch sub-output terminal, output G channel parallel grayscale data to the multi-bit digital comparison module 102 through the second latch sub-output terminal, and output B channel parallel grayscale data to the multi-bit digital comparison module 102 through the third latch sub-output terminal in a preset timing sequence, and after completing sending the data to the multi-bit digital comparison module 102, send a counting enable signal to the counter module 103.

[0060] Optionally, the serial data is 32 bits of serial data transmitted bit by bit through a single data line, wherein the first bit is the data of the chip enable EN, the second bit is the data of the pixel enable PIXEL_En, the third to the twelfth bits are the grayscale data of the red pixel PIXEL_R, the thirteenth to the twenty-second bits are the grayscale information of the green pixel PIXEL_G, and the twenty-third to the thirty-second bits are the grayscale information of the blue pixel PIXEL_B. The serial data is transmitted synchronously through a clock signal, and the data latch module 101 can receive the serial data bit by bit according to the clock signal, convert the received serial data into multi-bit parallel data, latch the converted multi-bit parallel data, and send it to the multi-bit digital comparison module 102.

[0061] Optionally, the converted multi-bit parallel data is as follows Figure 5 As shown, it may include: grayscale data R<9:0> of red pixels, i.e. parallel grayscale data of R channel; grayscale data G<9:0> of green pixels, i.e. parallel grayscale data of G channel; grayscale data B<9:0> of blue pixels, i.e. parallel grayscale data of B channel, and may also include data of chip enable EN and data of pixel enable PIXEL_EN. Among them, the parallel grayscale data R<9:0> of R channel is output to the multi-bit digital comparison module 102 through the first latch sub-output terminal, the parallel grayscale data G<9:0> of G channel is output to the multi-bit digital comparison module 102 through the second latch sub-output terminal, and the parallel grayscale data B<9:0> of B channel is output to the multi-bit digital comparison module 102 through the third latch sub-output terminal.

[0062] In this embodiment, serial data is converted into parallel data through a data latch module, which is convenient for the subsequent multi-bit digital comparison module to compare the data, and when the serial data conversion is completed, a counting enable signal is sent to the counter module, so that the counter module starts counting after receiving the counting enable signal and sends the count value to the multi-bit digital comparison module, so that the multi-bit digital comparison module can compare the parallel data with the count value bit by bit and output an accurate sampling signal, thereby controlling the timing count in the grayscale display process through the counter module to ensure the accurate output of the grayscale level.

[0063] Continue as Figure 4 As shown, the second output terminal of the multi-bit digital comparison module 102 includes: a first comparison sub-output terminal, a second comparison sub-output terminal, and a third comparison sub-output terminal; the first input terminal of the sampling module 104 includes: a first sampling sub-input terminal, a second sampling sub-input terminal, and a third sampling sub-input terminal. Among them, the first comparison sub-output terminal is connected to the first sampling sub-input terminal, the second comparison sub-output terminal is connected to the second sampling sub-input terminal, and the third comparison sub-output terminal is connected to the third sampling sub-input terminal.

[0064] Optionally, the multi-bit digital comparison module 102 can compare the R channel parallel grayscale data with the count value and output the R channel sampling signal to the sampling module 104 through the first comparison sub-output terminal, compare the G channel parallel grayscale data with the count value and output the G channel sampling signal to the sampling module 104 through the second comparison sub-output terminal, and compare the B channel parallel grayscale data with the count value and output the B channel sampling signal to the sampling module 104 through the third comparison sub-output terminal.

[0065] Specifically, after the data latch module 101 completes sending data to the multi-bit digital comparison module 102 , that is, after the data latch module 101 receives the 32 bits of serial data and sends the converted multi-bit parallel data to the multi-bit digital comparison module 102 , it also sends a counting enable signal EN_CNT to the counter module 103 . When the counter module 103 receives the count enable signal EN_CNT, it starts counting, specifically counting from 0 to 1023, and sends the count value obtained by each count to the multi-bit digital comparison module 102. When the multi-bit digital comparison module 102 receives the count value each time, it compares the received count value with the R channel parallel grayscale data R<9:0>, and when the count value is equal to the R channel parallel grayscale data R<9:0>, it outputs the R channel sampling signal S_R; compares the received count value with the G channel parallel grayscale data G<9:0>, and when the count value is equal to the G channel parallel grayscale data G<9:0>, it outputs the G channel sampling signal S_G; compares the received count value with the B channel parallel grayscale data B<9:0>, and when the count value is equal to the B channel parallel grayscale data B<9:0>, it outputs the B channel sampling signal S_B. The count value is also in the form of parallel data, such as CNT<9:0>.

[0066] Exemplarily, if R<9:0> is 256, when the count value sent by the counter module 103 received by the multi-bit digital comparison module 102 is also 256, the multi-bit digital comparison module 102 outputs the R channel sampling signal S_R, and the S_R signal is high level.

[0067] In this embodiment, the multi-bit digital comparison module can realize high-bit grayscale display control by comparing the parallel grayscale data of each channel with the count value sent by the counter module bit by bit.

[0068] Continue as Figure 4 As shown, the output end of the sampling module 104 may include: a first voltage sub-output end, a second voltage sub-output end and a third voltage sub-output end; the first voltage sub-output end, the second voltage sub-output end and the third voltage sub-output end are respectively connected to the pixel unit.

[0069] Optionally, the sampling module can perform voltage sampling on the ramp signal based on the R channel sampling signal and output the R channel sampling voltage DATA_R through the first voltage sub-output terminal, perform voltage sampling on the ramp signal based on the G channel sampling signal and output the G channel sampling voltage DATA_G through the second voltage sub-output terminal, and perform voltage sampling on the ramp signal based on the B channel sampling signal and output the B channel sampling voltage DATA_B through the third voltage sub-output terminal.

[0070] Exemplarily, if the multi-bit digital comparison module 102 sends an R channel sampling signal S_R when the count value is 256, the sampling module 104 samples the RAMP wave when receiving the R channel sampling signal S_R. Since the start input of the RAMP wave and the start counting of the counter module are simultaneous, when the sampling module 104 starts sampling based on the R channel sampling signal S_R, the sampling voltage obtained is also the voltage at 256 gray levels, and the sampling module 104 outputs the R channel sampling voltage DATA_R.

[0071] Figure 6 A schematic diagram of the structure of another display driver chip provided in an embodiment of the present application is shown in FIG. Figure 6 As shown, the pixel unit 11 may include: a first pixel module 110 , a second pixel module 111 and a third pixel module 112 .

[0072] like Figure 6 As shown, the first voltage sub-output terminal of the data processing unit 10 is connected to the first input terminal of the first pixel module 110, the second voltage sub-output terminal of the data processing unit 10 is connected to the first input terminal of the second pixel module 111, and the third voltage sub-output terminal of the data processing unit 10 is connected to the first input terminal of the third pixel module 112. Among them, the first voltage sub-output terminal of the data processing unit 10 is the first voltage sub-output terminal of the sampling module 104, the second voltage sub-output terminal of the data processing unit 10 is the second voltage sub-output terminal of the sampling module 104, and the third voltage sub-output terminal of the data processing unit 10 is the third voltage sub-output terminal of the sampling module 104.

[0073] Optionally, the sampling module 104 in the data processing unit 10 can output the R channel sampling voltage DATA_R to the first pixel module 110 through the first voltage sub-output terminal, output the G channel sampling voltage DATA_G to the second pixel module 111 through the second voltage sub-output terminal, and output the B channel sampling voltage DATA_B to the third pixel module 112 through the third voltage sub-output terminal.

[0074] Continue as Figure 6 As shown, the data processing unit 10 also includes: a chip enable output terminal, wherein the chip enable output terminal is also the chip enable output terminal of the data latch module 101. The chip enable output terminal EN of the data processing unit chip is respectively connected to the second input terminal of the first pixel module 110, the second input terminal of the second pixel module 111, and the second input terminal of the third pixel module 111.

[0075] Optionally, when the data latch module 101 converts serial data into parallel data, the first bit of the 32-bit serial data is used as chip enable data and sent to the first pixel module 110, the second pixel module 111 and the third pixel module 112 respectively through the chip enable output terminal.

[0076] Continue as Figure 6 As shown, the data processing unit 10 may also include a pixel enable output terminal, which is also the pixel enable output terminal of the data latch module 101, and the pixel enable output terminal is respectively connected to the third input terminal of the first pixel module 110, the third input terminal of the second pixel module 111, and the third input terminal of the third pixel module 112.

[0077] Optionally, when the data latch module 101 converts the serial data into parallel data, the second bit of the 32-bit serial data is used as the pixel enable data PIXEL_EN and is sent to the first pixel module 110, the second pixel module 111 and the third pixel module 112 through the pixel enable output terminal. Figure 5 The pixel enable data in Figure 5 The pixel enable data 201 indicates that the pixel circuit is turned on for data writing, and 202 indicates that the pixel circuit is turned off for data clearing.

[0078] Figure 7 A schematic diagram of the structure of a pixel module provided in an embodiment of the present application is shown in FIG. Figure 7 As shown, the first pixel module 110 may include: a first field effect transistor M0, a second field effect transistor M1, a third field effect transistor M2 and a first capacitor C1.

[0079] like Figure 7As shown, the first end of the first field effect transistor M0 is connected to the first voltage sub-output end in the sampling module 104, the second end of the first field effect transistor M0 is connected to the chip enable output end, and the third end of the first field effect transistor M0 is respectively connected to one end of the first capacitor C1 and the second end of the second field effect transistor M1.

[0080] Optionally, the first end of the second field effect tube M1 is connected to the third end of the third field effect tube, and the second end of the second field effect tube M1 is used to connect to the power supply. The first end of the third field effect tube M2 is used to connect to the pixel electrode, and the second end of the third field effect tube M2 is connected to the pixel enable output end; the other end of the first capacitor C1 is grounded. Among them, the first end of the first field effect tube M0 can be a source, the second end of the first field effect tube M0 is a gate, and the third end of the first field effect tube M0 is a drain. The first end, the second end and the third end of the second field effect tube M1 and the third field effect tube M2 are the same as those of the first field effect tube.

[0081] Optionally, the first field effect transistor M0 can be closed or turned off based on the chip enable signal output from the chip enable output terminal, the second field effect transistor M1 can be closed based on the connection to the power supply, and the third field effect transistor M2 can be closed or turned off based on the pixel enable signal output from the pixel enable output terminal. If the first field effect transistor M0, the second field effect transistor M1, and the third field effect transistor M2 are all closed, the first pixel module 110 outputs an R pixel signal under the action of the R channel sampling voltage output by the sampling module 104, and the R pixel signal can be input into the display screen, so that the R pixel signal is displayed on the display screen.

[0082] Optionally, the structure of the second pixel module 111 and the structure of the third pixel module 112 are similar to the structure of the first pixel module 110 .

[0083] Specifically, the second pixel module 111 includes: a fourth field effect tube, a fifth field effect tube, a sixth field effect tube and a second capacitor. Among them, the first end of the fourth field effect tube is connected to the first voltage output terminal in the sampling module 104, the second end of the fourth field effect tube is connected to the chip enable output terminal, and the third end of the fourth field effect tube is respectively connected to one end of the second capacitor and the second end of the second field effect tube; the first end of the fifth field effect tube is connected to the third end of the sixth field effect tube, the second end of the fifth field effect tube is used to connect to the power supply, the first end of the sixth field effect tube is used to connect the pixel electrode, and the second end of the sixth field effect tube is connected to the pixel enable output terminal; the other end of the second capacitor is grounded. If the fourth field effect tube, the fifth field effect tube, and the sixth field effect tube are all closed, the second pixel module 111 outputs a G pixel signal under the action of the G channel sampling voltage output by the sampling module 104.

[0084] Specifically, the third pixel module 112 includes: a seventh field effect tube, an eighth field effect tube, a ninth field effect tube and a third capacitor. Among them, the first end of the seventh field effect tube is connected to the first voltage sub-output terminal in the sampling module 104, the second end of the seventh field effect tube is connected to the chip enable output terminal, and the third end of the seventh field effect tube is respectively connected to one end of the third capacitor and the second end of the second field effect tube; the first end of the eighth field effect tube is connected to the third end of the ninth field effect tube, the second end of the eighth field effect tube is used to connect to the power supply, the first end of the ninth field effect tube is used to connect to the pixel electrode, and the second end of the ninth field effect tube is connected to the pixel enable output terminal; the other end of the third capacitor is grounded. If the seventh field effect tube, the eighth field effect tube, and the ninth field effect tube are all closed, the second pixel module 112 outputs a B pixel signal under the action of the B channel sampling voltage output by the sampling module 104.

[0085] like Figure 2 As shown, the power supply terminal of the pixel unit 11 is connected to the external power supply, the ground terminal of the pixel unit is used for grounding, the power supply terminal of the pixel unit 11 serves as the fourth pin of the display driver chip, and the ground terminal of the pixel unit 11 serves as the fifth pin of the display driver chip. Among them, the second end of the second field effect transistor in the first pixel module 110, the second end of the fifth field effect transistor in the second pixel module 111, and the second end of the eighth field effect transistor in the third pixel module 111 are all connected to the power supply terminal of the pixel unit. The other end of the first capacitor in the first pixel module 110, the other end of the second capacitor in the second pixel module 111, and the other end of the third capacitor in the third pixel module 111 are all connected to the ground terminal of the pixel unit.

[0086] An embodiment of the present application further provides a display device, which may include the display driver chip and a display screen in the aforementioned specific embodiment. The display screen may display pixels corresponding to pixel signals based on pixel signals output by the display driver chip.

[0087] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, the specific working process of the system and device described above can refer to the corresponding process in the method embodiment, and will not be repeated in this application. In the several embodiments provided in this application, it should be understood that the disclosed system, device and method can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation. For example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0088] In addition, each functional unit in each embodiment of the present application can be integrated into a processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, RandomAccess Memory), disk or optical disk and other media that can store program code.

[0089] The above are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be covered by the protection scope of the present application.

Claims

1. A display driver chip, characterized in that: The display driver chip comprises: a data processing unit and a pixel unit, wherein the data processing unit comprises a data latch module, a multi-bit digital comparison module, a counter module and a sampling module; The first input end of the data latch module serves as the first pin of the display driver chip, and is used to receive the serial data input by the user. The second input end of the data latch module serves as the second pin of the display driver chip, and is used to receive the clock signal. The first output end of the data latch module is connected to the first input end of the multi-bit digital comparison module, and the second output end of the data latch module is connected to the first input end of the counter module. The second input end of the counter module is connected to the third output end of the data latch module, the output end of the counter module is connected to the second input end of the multi-bit digital comparison module, the output end of the multi-bit digital comparison module is connected to the first input end of the sampling module, the second input end of the sampling module is used to access the ramp signal, the second input end of the sampling module serves as the third pin of the display driver chip, and the output end of the sampling module is connected to the pixel unit; The data latch module is used to convert the serial data into multi-bit parallel data and send a counting enable signal to the counter module, wherein the serial data is used to indicate the pixel grayscale data to be displayed input by the user; the counter module is used to perform a counting operation based on the counting enable signal sent by the data latch module, and output a counting value to the multi-bit digital comparison module; the multi-bit digital comparison module is used to compare the multi-bit parallel data with the counting value and output a sampling signal to the sampling module; the sampling module is used to perform voltage sampling on the ramp signal based on the sampling signal, output a sampling voltage, and send the sampling voltage to the pixel unit; the pixel unit is used to output a corresponding pixel signal under the action of the sampling voltage.

2. The display driver chip according to claim 1, characterized in that: The first output terminal of the data latch module includes: a first latch sub-output terminal, a second latch sub-output terminal and a third latch sub-output terminal; the first input terminal of the multi-bit digital comparison module includes: a first comparison sub-input terminal, a second comparison sub-input terminal and a third comparison sub-input terminal; The first latch sub-output terminal is connected to the first comparison sub-input terminal, the second latch sub-output terminal is connected to the second comparison sub-input terminal, and the third latch sub-output terminal is connected to the third comparison sub-input terminal; The data latch module is specifically used to output R channel parallel grayscale data to the multi-bit digital comparison module through the first latch sub-output end, output G channel parallel grayscale data to the multi-bit digital comparison module through the second latch sub-output end, and output B channel parallel grayscale data to the multi-bit digital comparison module through the third latch sub-output end in accordance with a preset timing sequence, and after sending data to the multi-bit digital comparison module, send the counting enable signal to the counter module.

3. The display driver chip according to claim 1, characterized in that: The second output terminal of the multi-bit digital comparison module includes: a first comparison sub-output terminal, a second comparison sub-output terminal and a third comparison sub-output terminal; the first input terminal of the sampling module includes: a first sampling sub-input terminal, a second sampling sub-input terminal and a third sampling sub-input terminal; The first comparison sub-output terminal is connected to the first sampling sub-input terminal, the second comparison sub-output terminal is connected to the second sampling sub-input terminal, and the third comparison sub-output terminal is connected to the third sampling sub-input terminal; The multi-bit digital comparison module is specifically used to compare the R channel parallel grayscale data with the count value and output the R channel sampling signal to the sampling module through the first comparison sub-output end, compare the G channel parallel grayscale data with the count value and output the G channel sampling signal to the sampling module through the second comparison sub-output end, and compare the B channel parallel grayscale data with the count value and output the B channel sampling signal to the sampling module through the third comparison sub-output end.

4. The display driver chip according to claim 1, characterized in that: The output end of the sampling module includes: a first voltage sub-output end, a second voltage sub-output end and a third voltage sub-output end; The first voltage sub-output terminal, the second voltage sub-output terminal and the third voltage sub-output terminal are respectively connected to the pixel unit; The sampling module is specifically used to perform voltage sampling on the ramp signal based on the R channel sampling signal and output the R channel sampling voltage through the first voltage sub-output terminal, perform voltage sampling on the ramp signal based on the G channel sampling signal and output the G channel sampling voltage through the second voltage sub-output terminal, and perform voltage sampling on the ramp signal based on the B channel sampling signal and output the B channel sampling voltage through the third voltage sub-output terminal.

5. The display driver chip according to claim 1, characterized in that: The pixel unit includes: a first pixel module, a second pixel module and a third pixel module; The first voltage sub-output terminal of the data processing unit is connected to the first input terminal of the first pixel module, the second voltage sub-output terminal of the data processing unit is connected to the first input terminal of the second pixel module, and the third voltage sub-output terminal of the data processing unit is connected to the first input terminal of the third pixel module.

6. The display driver chip according to claim 5, characterized in that: The data processing unit further includes: a chip enable output terminal; The chip enable output terminal is respectively connected to the second input terminal of the first pixel module, the second input terminal of the second pixel module, and the second input terminal of the third pixel module.

7. The display driver chip according to claim 5, characterized in that: The data processing unit further comprises: a pixel enable output terminal; The pixel enable output terminal is respectively connected to the third input terminal of the first pixel module, the third input terminal of the second pixel module, and the third input terminal of the third pixel module.

8. The display driver chip according to claim 5, characterized in that: The first pixel module includes: a first field effect transistor, a second field effect transistor, a third field effect transistor and a first capacitor; The first end of the first field effect transistor is connected to the first voltage sub-output end of the sampling module, the second end of the first field effect transistor is connected to the chip enable output end, and the third end of the first field effect transistor is respectively connected to one end of the first capacitor and the second end of the second field effect transistor; The first end of the second field effect tube is connected to the third end of the third field effect tube, and the second end of the second field effect tube is used to connect to a power source; The first end of the third field effect transistor is used to connect to the pixel electrode, and the second end of the third field effect transistor is connected to the pixel enable output terminal; the other end of the first capacitor is connected to the ground; The first field effect transistor is closed or turned off based on the chip enable signal output by the chip enable output terminal, the second field effect transistor is closed based on connecting the power supply, and the third field effect transistor is closed or turned off based on the pixel enable signal output by the pixel enable output terminal. If the first field effect transistor, the second field effect transistor and the third field effect transistor are all closed, the first pixel module outputs an R pixel signal under the action of the R channel sampling voltage output by the sampling module.

9. The display driver chip according to claim 5, characterized in that: The power supply terminal of the pixel unit is connected to an external power supply, the ground terminal of the pixel unit is used for grounding, the power supply terminal serves as the fourth pin of the display driver chip, and the ground terminal serves as the fifth pin of the display driver chip.

10. A display device, characterized in that: A display driver chip comprising any one of claims 1 to 9.

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