Nonvolatile memory device and method of operating nonvolatile memory device

Abstract

Disclosed are a nonvolatile memory device and a method of operating the nonvolatile memory device. The nonvolatile memory device includes a plurality of latch groups, an address controller, an encoder, and a buffer. The address controller controls the input address and the output address to each indicate a respective one of the plurality of latch groups. The encoder receives sector data from a latch group corresponding to the output address among the plurality of latch groups, and also compresses the received sector data. The buffer stores the compressed sector data. Among the plurality of latch groups, the compressed sector data stored in the buffer is rewritten to the latch group corresponding to the input address.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2023-0147602 filed on October 31, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present application relates to non-volatile memory devices and methods of operating non-volatile memory devices. Background Art

[0003] Typically, NAND flash memory devices are widely used as storage media in electronic products, and over time or with repeated use, accurate reading of data can become challenging. Conventional hard decision technology distinguishes the voltage of a cell as 0 or 1. Summary of the invention

[0004] To address the challenge of accurately reading data, soft decision technology is being introduced. Soft decision technology analyzes the voltage more finely and estimates the probability of its corresponding value. Through such a scheme, the performance of the error correction code can be enhanced and the life of the NAND flash memory device can be extended.

[0005] Example embodiments of the present disclosure relate to a nonvolatile memory device, a storage device including the nonvolatile memory device, and a method of operating the nonvolatile memory device.

[0006] Example embodiments of the present disclosure are to provide a nonvolatile memory device that can compress and output data, a storage device including the nonvolatile memory device, and a method of operating the nonvolatile memory device.

[0007] According to an example embodiment of the present disclosure, a nonvolatile memory device includes: a plurality of latch groups; an address controller configured to control an input address and an output address to indicate one of the plurality of latch groups; an encoder configured to: receive sector data from a latch group corresponding to an output address among the plurality of latch groups, and compress the received sector data; and a buffer configured to store compressed sector data, wherein, among the plurality of latch groups, the compressed sector data stored in the buffer is rewritten into the latch group corresponding to the input address.

[0008] According to an example embodiment of the present disclosure, a nonvolatile memory device includes: a plurality of latches; a plurality of encoding units configured to compress data of a first size according to a predetermined compression ratio; and a plurality of registers configured to store the compressed data, wherein the plurality of latches output data of the same size as the first size to the plurality of encoding units while moving a first address pointer during a read operation, and wherein the plurality of latches overwrite compressed data of a second size corresponding to the compression ratio from the plurality of registers while moving a second address pointer during an input operation.

[0009] According to another example embodiment of the present disclosure, a method of operating a non-volatile memory device includes: outputting soft decision data from a cache latch under a first address control; compressing the soft decision data according to a predetermined compression ratio; and rewriting the compressed data into a portion of the cache latch under a second address control, wherein the first address control and the second address control are separate from each other.

[0010] According to another example embodiment of the present disclosure, a storage device includes: at least one non-volatile memory device, including a compression circuit configured to compress soft decision data; and a controller, including a decompression circuit configured to receive compressed soft decision data from the at least one non-volatile memory device and decompress the received soft decision data, wherein the compression circuit includes: a plurality of latches configured to store the soft decision data; an encoder configured to: read data of a first size from the plurality of latches in response to an output address and compress the read data; a coding buffer configured to: store the read data and rewrite the stored data into corresponding latches from the plurality of latches in response to an input address; a first address controller configured to perform a first address control on an output address of the plurality of latches during an output operation; and a second address controller configured to perform a second address control on an input address of the plurality of latches during an input operation.

[0011] According to an example embodiment of the present disclosure, a method for operating a non-volatile memory device includes: receiving a special command from an external device; in response to the special command, reading first data according to a hard decision method, and reading second data according to a soft decision method; compressing the second data; and outputting the first data and the compressed second data to the external device, wherein the step of compressing the second data includes: storing the second data in a cache latch; outputting data of a sector unit in response to an output address from the cache latch; compressing the output data of the sector unit; and rewriting the compressed data to a portion of the cache latch in response to an input address. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which: Figure 1 is a diagram illustrating an example storage device; Figure 2 is a diagram illustrating an example nonvolatile memory device; Figure 3A is a circuit diagram showing an example memory block; Figure 3B is a diagram showing a connection relationship between a memory cell array and a page buffer circuit; Figure 4A and Figure 4B is a diagram showing the necessity of a read operation and a compression operation of a soft decision; Figure 5 is a diagram illustrating an example compression process of a general nonvolatile memory device; Figure 6 is a diagram illustrating an example compression circuit of a nonvolatile memory device; Figure 7 is a diagram illustrating an example external output method for compression of data in a nonvolatile memory device; Figure 8 is a diagram illustrating example address control of compressed data of a nonvolatile memory device; Fig. 9 is a diagram illustrating example address control of compressed data of a nonvolatile memory device; Fig.10 is a diagram showing independent operations of a first address control for a read address of a C latch and a second address control for a write address of the C latch in a nonvolatile memory device; Fig.11A , Fig. 11B , Fig. 11C is a diagram showing the relationship between a compression circuit and a plane; Fig.12 is a flow chart illustrating the operation of an exemplary non-volatile memory device; Fig.13 is a flow chart illustrating the operation of an exemplary non-volatile memory device; Fig.14 is a flow chart illustrating the operation of an exemplary non-volatile memory device; Fig.15 is a flow chart illustrating the operation of an example controller; Fig.16 is a diagram illustrating an example storage device; Fig.17 is a diagram illustrating an example controller; Fig.18 is a ladder diagram illustrating an example read operation of a storage device; Fig.19 is a ladder diagram illustrating an example read operation of a storage device; and Fig. 20 is a diagram illustrating an exemplary vertical nonvolatile memory device. DETAILED DESCRIPTION

[0013] Hereinafter, embodiments of the present disclosure will be described as follows with reference to the accompanying drawings.

[0014] A nonvolatile memory device, a storage device including the nonvolatile memory device, and a method for operating the nonvolatile memory device may use two separate address controllers to operate two address pointers in one operation to access a C latch (cache latch) in a page buffer. The nonvolatile memory device in one example may include: an address controller used when reading data to be encoded (or compressed), an address controller used when writing encoded data, an encoder (or compression circuit) for encoding data in the C latch, and a register for storing encoded data. The nonvolatile memory device in one example can achieve sequential repetition of read operations and write operations for data by distinguishing "an address controller used when reading data to be encoded" from "an address controller used when writing encoded data". Therefore, the example nonvolatile memory device can significantly reduce the capacity of the register used to store encoded data.

[0015] The example non-volatile memory device can operate two separate address controllers so that sequential repetition of read operations and write operations can be achieved. When compressing data in the C latch, the example non-volatile memory device can achieve sequential repetition of read operations and write operations for data. The size of the register that temporarily stores the encoded data before rewriting the encoded data to the C latch can be greatly reduced. Therefore, the compression operation of the data can be implemented on-chip.

[0016] Figure 1 An example storage device 10 is shown. Figure 1 , the memory device 10 may include at least one nonvolatile memory device 100 ((one or more) NVM) and a controller 200 CTRL. The nonvolatile memory device 100 and the controller 200 may be connected to each other through at least one channel.

[0017] At least one nonvolatile memory device 100 may be implemented as a chip or a die. The nonvolatile memory device 100 may include a memory cell array 110 (MCA), a page buffer circuit 130 , and a compression circuit 170 .

[0018] The memory cell array 110 may include memory cells arranged in an area where a plurality of word lines and a plurality of bit lines are connected to each other. Here, each of the memory cells may include a nonvolatile memory cell. The page buffer circuit 130 may be implemented to program write data into the memory cells respectively connected to the plurality of bit lines, or to read data from the memory cells. The page buffer circuit 130 may include a plurality of page buffers respectively connected to the plurality of bit lines.

[0019] The compression circuit 170 may be implemented to read data (e.g., soft decision data SDu of a sector unit (hereinafter, may also be referred to as soft decision data SDu, data SDu, or sector data SDu)) stored in the page buffer circuit 130 through a first address control corresponding to an output operation. In an example embodiment, the compression circuit 170 may read the soft decision data SDu of a sector unit from a latch in the page buffer circuit 130 under (e.g., according to) the first address control.

[0020] In addition, the compression circuit 170 may be implemented to compress the read data SDu based on a compression algorithm. In an example embodiment, the compression circuit 170 may compress the data SDu of the sector unit into compressed soft decision data CPR_SDu of the sector unit having a size smaller than the sector size (hereinafter, may also be referred to as compressed soft decision data CPR_SDu, compressed data CPR_SDu, compressed data CPR_SDu, or data CPR_SDu) according to the compression ratio. In an example embodiment, the soft decision data SDu of the sector unit may represent the overlapping area between adjacent threshold voltage distributions as "1" and represent other areas as "0". In the overlapping area between the threshold voltage distributions, the reliability of the hard decision data may be relatively low. In other areas, the reliability of the hard decision data may be relatively high. Since the overlapping area between the adjacent threshold voltage distributions is narrower than other areas, the number of "1" in the soft decision data may be less than the number of "0". The compression circuit 170 may generate compressed data CPR_SDu by encoding "1" in the soft decision data SDu of the sector unit as a "1" position.

[0021] In addition, the compression circuit 170 may be implemented to write the compressed data CPR_SDu to the page buffer circuit 130 through a second address control corresponding to the input operation. In an example embodiment, the compression circuit 170 may rewrite the compressed soft decision data CPR_SDu to a portion of the latch in the page buffer circuit 130 under the second address control (e.g., according to the second address control). Here, the first address control and the second address control may be independently operated by different data path circuits. In an example embodiment, the first address control and the second address control may be the same. In another example embodiment, the first address control and the second address control may be different.

[0022] In addition, the compression circuit 170 can distinguish between an "address controller for reading the data SDu to be compressed during an output operation" and an "address controller for writing the compressed data CPR_SDu during an input operation", thereby achieving sequential repetition of the input operation and the output operation of the soft decision data SDu for the sector unit. In an example embodiment, the address pointer corresponding to the output operation and the address pointer corresponding to the input operation can be separated from each other.

[0023] In addition, the nonvolatile memory device 100 may read (or transmit) compressed soft decision data CPR_SD (hereinafter, may also be referred to as compressed soft decision data CPR_SD, compressed data CPR_SD, or compressed data CPR_SD) to the controller 200 through a channel, wherein the compressed soft decision data CPR_SD may be based on compressed soft decision data CPR_SDu of a sector unit. By transmitting the compressed soft decision data CPR_SD to the channel, the performance of the soft decision operation may be improved.

[0024] The controller 200 may be connected to at least one nonvolatile memory device 100 through at least one channel. The controller 200 may be implemented to control the overall operation of the nonvolatile memory device 100. For example, the controller 200 may send commands, addresses, and data to the nonvolatile memory device 100, or may receive data from the nonvolatile memory device 100 through the channel.

[0025] The controller 200 may include an error correction circuit 230 (ECC) and a decompression circuit 270. The error correction circuit 230 may be implemented to perform an error correction operation on the read data. Here, the error correction operation may apply a hard decision method or a soft decision method. Here, the hard decision method may be a technique in which an error in the data is corrected using the read data and an error correction code according to the on / off characteristics of the memory cell when a reference voltage is applied. In addition, the soft decision method may be a technique in which data errors are corrected by additionally using additional information (e.g., soft decision data SD) on the reliability of the hard decision data separately from the hard decision data and the error correction code.

[0026] The decompression circuit 270 may be implemented to restore the soft decision data SD by decompressing the compressed data CPR_SD based on a decompression algorithm. The decompression circuit 270 may read the restored soft decision data SD into the error correction circuit 230. The error correction circuit 230 may correct errors in the hard decision data based on the hard decision data and the soft decision data. For example, the error correction circuit 230 may correct the hard decision data by changing the log likelihood ratio (LLR) based on the soft decision data.

[0027] The memory device 10 according to example embodiments may include a nonvolatile memory device 100 for compressing soft decision data according to column address control of an independent data path circuit and a controller for decompressing the compressed soft decision data CPR_SD, thereby improving overall performance of soft decision operations and reducing chip size.

[0028] Figure 2 An example nonvolatile memory device 100 is shown. Figure 2 , a nonvolatile memory device 100 may include a memory cell array 110 (MCA), a row decoder 120 (X-DEC), a page buffer circuit 130 , an input / output (I / O) circuit 140 , a control logic 150 , a voltage generator 160 , and a compression circuit 170 .

[0029] The memory cell array 110 (MCA) may be connected to the row decoder 120 (X-DEC) through word lines WL, or selection lines SSL and GSL. The memory cell array 110 may be connected to the page buffer circuit 130 through bit lines BL. The memory cell array 110 may include a plurality of cell strings. Each channel of the cell string may be formed vertically or horizontally. Each of the cell strings may include a plurality of memory cells. Here, a plurality of memory cells may be programmed, erased, or read by a voltage provided by a bit line BL or a word line WL. Typically, a programming operation may be performed in units of pages, and an erase operation may be performed in units of blocks. The memory cell is described in more detail in US registered patents US 7,679,133, US 8,553,466, US 8,654,587, US 8,559,235, and US 9,536,970.

[0030] The row decoder 120 (X-DEC) may be implemented to select one of the memory blocks BLK1 to BLKz (z is an integer of 2 or more) of the memory cell array 110 in response to the row address X-ADD among the addresses ADD. The row decoder 120 may select one of the word lines of the selected memory block in response to the row address X-ADD. The row decoder 120 may transmit a word line voltage V corresponding to an operation mode of the word line of the selected memory block. WL During a program operation, the row decoder 120 may apply a program voltage and a verification voltage to a selected word line, and apply a pass voltage to unselected word lines. During a read operation, the row decoder 120 may apply a read voltage to a selected word line, and apply a read pass voltage to unselected word lines.

[0031] The page buffer circuit 130 may be implemented to operate as a write driver or a sense amplifier. During a programming operation, the page buffer circuit 130 may apply a bit line voltage corresponding to the data to be programmed to the bit line BL of the memory cell array 110. During a read operation or a verify read operation, the page buffer circuit 130 may sense the data stored in the selected memory cell through the corresponding bit line. Each of the plurality of page buffers PB1 to PBn (n is an integer of 2 or more) included in the page buffer circuit 130 may be connected to at least one bit line in response to a column address Y-ADD among the addresses ADD. In one example, each of the plurality of page buffers PB1 to PBn may be implemented so that the sensing node and the transmission node are separated from each other.

[0032] The input / output circuit 140 may provide data provided from an external entity to the page buffer circuit 130. The input / output circuit 140 may provide a command CMD provided by an external entity to the control logic 150. The input / output circuit 140 may provide an address ADD provided by an external entity to the control logic 150. In addition, the input / output circuit 140 may externally read data sensed and latched by the page buffer circuit 130. In addition, the input / output circuit 140 may externally read compressed data CPR_SD stored in the code buffer 173.

[0033] The control logic 150 may be implemented to control the row decoder 120, the page buffer circuit 130, the input / output circuit 140, the voltage generator 160, and the compression circuit 170 in response to a command CMD or a control signal sent from an external device. In addition, the control logic 150 may be implemented to perform a dynamic read operation based on a cell count. In addition, the control logic 150 may send an address control signal ADDCS to the compression circuit 170 in a data compression operation. In one example, the address control signal ADDCS may include a first address control signal for reading soft decision data SDu of a sector unit from the page buffers PB1 to PBn and a second address control signal for writing compressed data CPR_SDu to the coding buffer 173.

[0034] The voltage generator 160 may be implemented to generate various types of word line voltages to be applied to each word line, and a well voltage to be supplied to a bulk (e.g., a well region) in which a memory cell is formed, under the control of the control logic 150. The word line voltage applied to the word line WL may include a program voltage, a pass voltage, a read voltage, a read pass voltage, etc. Although not shown, the nonvolatile memory device 100 in one example may include a cell counter. The cell counter may be implemented to count memory cells corresponding to a specific threshold voltage range according to data sensed by the page buffer circuit 130. For example, the cell counter may count the number of memory cells having a threshold voltage within a specific threshold voltage range by processing data sensed by each of the plurality of page buffers PB1 to PBn.

[0035] The compression circuit 170 may include an encoder 171 and a code buffer 173. The compression circuit 170 may read the soft decision data SDu of the sector unit from the page buffers PB1 to PBn in response to the address control signal ADSCS, may compress the read soft decision data SDu in the encoder 171 according to the compression algorithm, and may write the compressed data CPR_SDu into the code buffer 173. At the same time, Figure 2The code buffer 173 shown in FIG. 1 is shown outside the page buffer circuit 130 , but the embodiment is not limited thereto. The code buffer in one embodiment may exist in the page buffer circuit 130 .

[0036] Figure 3A is a diagram showing an example circuit diagram of a memory block BLKi (i is an integer of 2 or more). A plurality of NAND strings included in the memory block BLKi may be formed in a direction perpendicular to a substrate (eg, in a Z direction perpendicular to an X direction and a Y direction). Figure 3A , the memory block BLKi may include a plurality of NAND strings NS11, NS12, NS13, NS21, NS22, NS23, NS31, NS32, and NS33 connected between the bit lines BL1, BL2, and BL3 and the common source line CSL. Each of the plurality of NAND strings NS11, NS12, NS13, NS21, NS22, NS23, NS31, NS32, and NS33 may include a string selection transistor SST, a plurality of memory cells MC1, MC2, ..., MC8, and a ground selection transistor GST. Figure 3A , each of the plurality of NAND strings NS11, NS12, NS13, NS21, NS22, NS23, NS31, NS32, and NS33 may include eight memory cells MC1, MC2, ..., MC8. However, the number of memory cells is not limited thereto.

[0037] The string selection transistor SST may be connected to corresponding string selection lines SSL1, SSL2, and SSL3. A plurality of memory cells MC1, MC2, ..., MC8 may be connected to corresponding gate lines GTL1, GTL2, ..., GTL8, respectively. A portion of the gate lines GTL1, GTL2, ..., GTL8 may correspond to word lines, and the remaining portions of the gate lines GTL1, GTL2, ..., GTL8 may correspond to dummy word lines. The ground selection transistor GST may be connected to corresponding ground selection lines GSL1, GSL2, and GSL3. The string selection transistor SST may be connected to corresponding bit lines BL1, BL2, and BL3, and the ground selection transistor GST may be connected to a common source line CSL. Word lines (e.g., WL1) at the same height may be connected in common, and the ground selection lines GSL1, GSL2, and GSL3 and the string selection lines SSL1, SSL2, and SSL3 may be separated from each other, respectively. At the same time, Figure 3A The memory block BLKi shown in FIG. 4 may be connected to eight gate lines GTL1 , GTL2 , . . . , GTL8 and three bit lines BL1 , BL2 , BL3 , but is not limited thereto.

[0038] Figure 3Bis a diagram showing a connection relationship between a memory cell array 110 and a page buffer circuit 130 according to an embodiment. Figure 3B , the memory cell array 110 may include first to nth NAND strings NS1 to NSn (n is an integer greater than 2). Each of the first to nth NAND strings NS1 to NSn may include a ground selection transistor GST connected to a ground selection line GSL, a plurality of memory cells MC respectively connected to a plurality of word lines WL1 to WLm (m is an integer greater than or equal to 2), and a string selection transistor SST connected to a string selection line SSL, and the ground selection transistor GST, the plurality of memory cells MC, and the string selection transistor SST may be connected in series to each other.

[0039] The page buffer circuit 130 may include a first page buffer PB1 to an nth page buffer PBn. The first page buffer PB1 may be connected to the first NAND string NS1 through the first bit line BL1, and the nth page buffer PBn may be connected to the nth NAND string NSn through the nth bit line BLn. For example, n may be 7, and the page buffer circuit 130 may have a structure in which eight page buffers PB1 to PBn are arranged in a row. For example, the first page buffer PB1 to the nth page buffer PBn may be arranged in a row in an extending direction of the first bit line BL1 to the nth bit line BLn.

[0040] The page buffer circuit 130 may also include first to nth cache latches CL1 to CLn corresponding to the first to nth page buffers PB1 to PBn, respectively. The page buffer circuit 130 may have a structure in which eight cache latches CL1 to CLn are arranged in a row. For example, the first to nth cache latches CL1 to CLn may be arranged in a row in the extending direction of the first bit line BL1 to the Nth bit line BLn. The sensing node of each of the first to nth page buffers PB1 to PBn may be connected in common to the combined sensing node SOC. In addition, the first to nth cache latches CL1 to CLn may be connected in common to the combined sensing node SOC. Therefore, the first to nth page buffers PB1 to PBn may be connected to the first to nth cache latches CL1 to CLn through the combined sensing node SOC.

[0041] Figure 4A and Figure 4B is a diagram showing the necessity of a read operation and a compression operation of a soft decision. Figure 4A In FIG. 1 , the horizontal axis may represent the threshold voltage Vth, and the vertical axis may represent the number of cells. Figure 4AAs shown in , the soft decision read voltages used in the soft decision read operation may be Vsread1 and Vsread2. The soft decision read operation may indicate that a plurality of soft decision read voltages Vsread1 and Vsread2 having a predetermined voltage difference may be applied to the memory cell based on the hard decision read voltage Vhread1, and information that increases the reliability of the hard decision data HD may be formed. When the soft decision read voltage Vsread1 is applied to the memory cell, the determined data "first SRD" may be 1, 0, 0, and 0 according to whether the memory cell is turned on or off. When the soft decision read voltage Vsread2 is applied to the memory cell, the determined data "second SRD" may be 1, 1, 1, and 0 according to whether the memory cell is turned on or off.

[0042] By performing an exclusive OR (XOR) calculation on the read values ​​"first SRD" and "second SRD" obtained through two read operations, soft decision data SD may be formed. As shown, the soft decision data SD may be 0, 1, 1, and 0. The XOR calculation may be performed in the page buffer circuit 130. That is, the XOR calculation may be performed on the read values ​​"first SRD" and "second SRD" obtained through two read operations using a plurality of latches in the page buffer circuit 130. The soft decision data SD may indicate the reliability of the hard decision data HD. When the soft decision data SD is 0, the soft decision data SD may indicate a state in which the reliability of the hard decision data is high (i.e., strong (s)). When the soft decision data SD is 1, the soft decision data SD may indicate a state in which the reliability of the hard decision data is low (i.e., weak (w)). In other words, 10, 11, 01, 00, which are combinations of hard decision data HD "1, 1, 0, 0" and soft decision data SD "0, 1, 1, 0", may respectively indicate hard decision data HD "1" with high reliability, hard decision data HD "1" with low reliability, hard decision data HD "0" with low reliability, and hard decision data HD "0" with high reliability.

[0043] Typically, the soft decision data SD may have a relatively low ratio of 1 (eg, about 2%). Figure 4B As shown in , when the soft decision data SD is compressed according to the soft decision read operation (ESS(tR)), the length of the data read through the input / output pad (IOx[7:0]) may be reduced. The length of the data may be reduced according to the compression ratio.

[0044] Figure 5 FIG. 2 is a diagram showing a compression process of a general nonvolatile memory device. Figure 5 The compression circuit 50 may include an encoder 51, an address controller 52 and a coding buffer 53. Figure 5According to the read operation of the soft decision, the sector data SEC1, SEC2, SEC3, and SEC4 may be stored in C latches whose number corresponds to the number of page buffers PB1 to PBn. In one embodiment, when the size of the page data is 16 kilobytes (KB), each size of the sector data SEC1, SEC2, SEC3, and SEC4 may be 4KB. However, the size of the page data and the number of the sector data are not limited thereto.

[0045] Typically, the C latch operation can only support one output (read) operation Dout and one input (write) operation Din. Thus, the address controller 52 can be shared in the output operation Dout and the input operation Din. When the address controller 52 is used to encode all the data of the C latch (for example, 16KB), after the output operation Dout for all the data is performed, the compression operation can be performed in the encoder 51, and thereafter, the input operation Din (rewrite) for the encoded data can be performed. In this case, at least a coding buffer 53 having a size corresponding to (16KB data) × (compression ratio) may be required. Typically, the encoded data (ie, compressed data) can be stored in the C latch to read the compressed data out of the chip. In order to complete the compression in one cycle (one page), a storage space equal to the size of the C latch multiplied by the compression ratio may be required. When implementing the compression circuit, chip size overhead may be generated.

[0046] The nonvolatile memory device 100 according to the embodiment may reduce the size of a separate storage space (ie, a code buffer) by independently operating address control of an output operation Dout and an input operation Din in a C-latch operation.

[0047] Figure 6 is a diagram illustrating a compression circuit 170 of a nonvolatile memory device 100 according to an example embodiment. Figure 6 , the compression circuit 170 may include an encoder 171, an address controller 172 and a coding buffer 173.

[0048] The C latch 131 may be divided into a plurality of sectors having latch groups. The C latch 131 may read data SDu (Dout data) from a sector corresponding to an address pointer read from the address controller 172 in an output operation Dout. In addition, in an input operation Din, the C latch 131 may receive compressed data CPR_SDu (Din data) from the code buffer 173 in a sector corresponding to an address pointer read from the address controller 172.

[0049] The encoder 171 may receive sector data SDu from the C latch 131 under the control of the first address, may compress the data based on a compression algorithm, and may read the compressed data CPR_SDu to the code buffer 173 .

[0050] The address controller 172 may include a first address controller 172-1, a second address controller 172-2, and a multiplexer (MUX) 172-3. The first address controller 172-1 may read (or output) an output address (Dout address) corresponding to a read operation for the C latch 131 under a first address control. The second address controller 172-2 may read an input address (Din address) corresponding to a write operation to the C latch 131 under a second address control. In an example embodiment, the first address controller 172-1 and the second address controller 172-2 may operate independently of each other. In an example embodiment, the output address (Dout address) and the input address (Din address) may each indicate a corresponding sector. The multiplexer 172-3 may read one of the output address (Dout address) and the input address (Din address) as an address pointer in the output operation Dout / input operation Din.

[0051] At the same time, Figure 6 In the embodiment, the address controller 172 can separate the address control through the multiplexer 171-3. However, the embodiment is not limited thereto. The address controller in one embodiment can directly control the page buffer through the first address controller and the second address controller without a multiplexer.

[0052] At the same time, Figure 6 In the embodiment, the address controller 172 is shown as an internal component of the compression circuit 170, but its implementation is not limited thereto. The address controller in an example embodiment may be implemented as Figure 2 Components of the control logic 150 are shown in FIG.

[0053] The code buffer 173 may be implemented to store the compressed data CPR_SDu from the encoder 171 and rewrite the stored data CPR_SDu to a portion of the C latch 131 under the second address control. In one example, the code buffer 173 may be implemented as a register.

[0054] and Figure 5 Compared to the example shown in FIG. 1 , the compression circuit 170 in one example can reduce the size of the encoding buffer 173 by an amount corresponding to the compression ratio when encoding by sequentially repeating the read operation / write operation. Figure 6As shown in , when page data is divided into four pieces of sector data SEC1 to SEC4 and the compression ratio is 25%, the minimum size of the code buffer 173 may be the sector data size multiplied by the compression ratio.

[0055] Meanwhile, when the compressed data CPR_SD is read out of a chip in the nonvolatile memory device 100 in one example, which address mapping should be supported may vary according to a demand from a user.

[0056] Figure 7 is a diagram showing an external output method of compressed data (CPR_SD) in a nonvolatile memory device 100 according to an example. In a first case (#1), the starting column address for each sector may be the same before and after compression. In one example, the data length may vary. Here, the data length may be fixed in hardware. In a second case (#2), the starting column address for each sector may be different before and after compression. In this case, the first sector data may include all compressed data CPR_SD. The output operation for the first sector data may become an output operation for all compressed data.

[0057] Figure 8 is a diagram showing address control of compressed data of the nonvolatile memory device 100 according to an example. Figure 8 , the first address control and the second address control may be different. The C latch data of the first sector (ie, the first sector data SEC1) may be output (Dout). In this case, the first address control may include (eg, by the first address controller 172-1) moving the first address pointer (ie, address pointer 1) from the start of the first sector to the end of the first sector. The first sector data SEC1 may be compressed by the encoder 171 using a compression / encoding window. After the first sector data SEC1 is compressed, the output operation Dout and the compression operation may be stopped. Thereafter, the compressed data may be stored in a separate storage space (ie, the encoding buffer 173). Thereafter, the data accumulated in the encoding buffer 173 may be rewritten to the C latch of the corresponding sector. In other words, the data in the separate storage space may be reused. In this case, the second address control may include (eg, by the second address controller 172-2) moving the second address pointer (ie, address pointer 2) from the start of the first sector to a point where a predetermined amount (eg, 1KB) is added to the start of the first sector.

[0058] The above process may be repeatedly performed for all sectors. In this case, the address controller 172 may retrieve the end point of the previous output operation, and the separated address pointer may repeat the above process starting from the end point of the previous output operation. That is, the first address pointer may move from the start point of the second sector to the end point of the second sector (second 4KB Dout). The second address pointer may move from the start point of the second sector to a point where a predetermined amount is added to the start point of the second sector (second compressed data rewrite).

[0059] exist Figure 8 In the embodiment, the first address control may be different from the second address control. The address control is not limited thereto, and the first address control and the second address control may be the same.

[0060] Fig. 9 is a diagram showing address control of compressed data of the nonvolatile memory device 100 according to an example. Fig. 9 , the first address control and the second address control may be the same.

[0061] In the first step, C latch data in the first sector (eg, first sector data SEC1) may be output (read) according to the first address controller 172-1. The first address pointer (address pointer 1) may read data while moving from the start point of the first sector to the end point of the first sector.

[0062] In the second step, the data output from the first step may be encoded in the encoder 171. For example, the encoder 171 may perform the encoding operation through a 16B window.

[0063] In the third step, the data (compressed data) encoded by the encoder 171 may be stored in a separate storage space (ie, the coded buffer 173 ).

[0064] In the fourth step, when the read operation and the encoding operation for the first sector data SEC1 are completed, the read operation may be stopped, and the encoded data stored in the encoding buffer 173 may be rewritten to the C latch. In this case, it is not necessary to store the data in a separate storage space. Therefore, when performing the output / encoding of subsequent sectors, the encoding buffer 173 may be reused.

[0065] In one example, the second address pointer (address pointer 2) may need to access the address for rewriting. Therefore, while the second address pointer moves from the start of the first sector to a predetermined point (e.g., the start of the first sector + 1KB), the first address pointer (address pointer 1) may remain at the end of the first sector.

[0066] In the subsequent steps, the above-mentioned first to fourth steps may be repeated in sequence for the subsequent sectors. The repetitive processing may be performed in sequence for the second sector data SEC2, the third sector data SEC3, and the fourth sector data SEC4. In this case, the address controller 172 may retrieve the previous end point, and the separated address pointers (address pointer 1 and address pointer 2) may repeat the above processing starting from the address. That is, the first address pointer (address pointer 1) may be moved from the starting point of the second sector to the end point of the second sector (second sector read operation). The second address pointer (address pointer 2) may be moved from the starting point of the first sector + a predetermined amount (e.g., 1KB) to the starting point of the first sector + 2 times the predetermined amount (e.g., 2KB) (second sector encoded data rewrite operation).

[0067] Fig.10 1 is a diagram showing independent operations of a first address control for a read address of a C latch and a second address control for a write address of a C latch in a nonvolatile memory device 100 according to an embodiment. The read operation may be an M-byte output operation "M-byte Dout", and the write operation may be an N-byte input operation "N-byte Din". Fig.10 , for ease of description, a 128-byte output operation "128-byte Dout" and a 32-byte input operation "32-byte Din" are shown.

[0068] The size of a page may be 16KB (kilobytes), and the size of each sector may be 128B. Therefore, a total of 32 sectors may exist in the C latch. As the first address pointer (i.e., address pointer 1) moves from the start point of each sector to the end point, an output operation Dout may be performed. Each sector may be divided into 8 pieces of 128b data, and a compression operation may be performed on the divided 128b data in a corresponding compression unit (e.g., encoding unit) COMP. Therefore, 32b of compressed data may be stored in a corresponding storage space ACC. 8 pieces of 32b compressed data (i.e., 32B compressed data) may be rewritten into a C latch (Din) commanded by a second address pointer (i.e., address pointer 2).

[0069] The compression time and the required active area may be in a trade-off relationship. By dividing the address controller into two controllers, the size of the unit compression / output sector can be adjusted to fit the target when the clock generation circuit is changed. For example, a TLC (three-level cell) product may be implemented as 128B Dout and 32B Din, and a QLC (quad-level cell) product may be implemented as 64B Dout and 16B Din. A QLC product may have a longer read time (tR) than that of a TLC product, so that the compression time may be increased and the active area may be reduced.

[0070] The nonvolatile memory device 100 according to an example embodiment may include two independent column address control circuits for reading and writing, an output portion for reading divided page data based on the address control for reading, a register for storing encoded data of the read data, and a page buffer input / output circuit including an input portion for rewriting the encoded data based on the address control for writing.

[0071] Fig.11A , Fig. 11B and Fig. 11C is a diagram showing the relationship between compression circuits and planes (eg, PLANE1, PLANE2, PLANE3, and PLANE4). In one example implementation, as Fig.11A As shown in , the compression circuit can be provided on each of the planes (core + page buffer circuit (PB)). In another embodiment, as Fig. 11B As shown in , the compression circuit can be arranged in a structure in which two planes are shared. In another embodiment, as Fig. 11C As shown in , the compression circuit may be provided in a structure in which four planes are shared. However, the embodiment thereof is not limited thereto, and a compression circuit shared by at least two planes may be provided and a clock may be appropriately generated.

[0072] Fig.12 is a flowchart illustrating the operation of the nonvolatile memory device 100 according to an example. Figures 1 to 12 , the nonvolatile memory device 100 may perform a C latch write operation and a C latch read operation as follows. Soft decision data may be output from the C latch under a first address control (S110). The soft decision data may be compressed by an encoder according to a compression ratio (S120). The compressed data may be rewritten into the C latch under a second address control (S130). In one example, the first address control and the second address control may be separated from each other. In another example, the cache latch may be divided into a plurality of sectors. In one example, under a first address control, while moving a first address pointer from a start point of a corresponding sector among a plurality of sectors to an end point of the sector, the soft decision data may be output from the corresponding latch. In another example, the compressed data may be stored in a register. In one example, by moving a second address pointer from a start point of a sector by a predetermined amount under a second address control, the data in the register may be rewritten to a portion of the latch. In another example, the first address control and the second address control may be the same or different from each other.

[0073] Fig.13 is a flowchart illustrating the operation of the nonvolatile memory device 100 according to another example embodiment. Figures 1 to 10 and Fig.13 , the data output operation of the nonvolatile memory device 100 may be performed as follows. The nonvolatile memory device 100 may receive a special command from an external device (S210). Here, the special command may be configured to indicate a reliability read operation. In response to the special command, the nonvolatile memory device 100 may read data using a hard decision method (H / D) and may read data using a soft decision method (S / D) (S220). The nonvolatile memory device 100 may compress the soft decision data SD read by the soft decision method (S230). The nonvolatile memory device 100 may output the hard decision data and the compressed soft decision data to the external device (S240).

[0074] exist Fig.13 In the embodiment, after the soft decision data is compressed, the hard decision data and the compressed soft decision data may be output. However, the order of compression of the soft decision data, output of the hard decision data, and output of the compressed soft decision data is not limited thereto. In one embodiment, the nonvolatile memory device 100 may read the hard decision data / soft decision data, for example, in response to a special command, may compress the soft decision data, may output the compressed soft decision data to an external device, and may output the hard decision data to an external device. In another example, the nonvolatile memory device 100 may read the hard decision data / soft decision data, for example, in response to a special command, may output the hard decision data to an external device, may compress the soft decision data, and may output the compressed soft decision data to an external device.

[0075] Fig.14 is a flowchart showing the operation of the nonvolatile memory device 100 according to another embodiment. Figures 1 to 10 and Fig.14 , the data output operation of the nonvolatile memory device 100 may be performed as follows. The nonvolatile memory device 100 may read data (S310). The nonvolatile memory device 100 may compress the read data (S320). The nonvolatile memory device 100 may output the compressed data to an external device (S330).

[0076] Fig.15 is a flowchart showing the operation of the controller 200 according to an embodiment. Figures 1 to 10 and Fig.15, the operation of the controller 200 may be performed as follows. The controller 200 may send a special command to the nonvolatile memory device 100 (NVM) (S410). For example, when an error when reading data by the first reading method cannot be corrected, the controller 200 may issue a special command corresponding to the second reading method to read the data more accurately. The controller 200 may receive hard decision data HD and compressed soft decision data (compressed SD) from the nonvolatile memory device 100 (S420). The controller 200 may decompress the compressed soft decision data (compressed SD) (S430). The controller 200 may restore data using the decompressed soft decision data (decompressed SD) and the hard decision data HD (S440).

[0077] Fig.16 2 is a diagram showing a storage device 20 according to an embodiment. Fig.16 , the memory device 20 may include a nonvolatile memory package 21 (NVMPKG) and a controller 22 (CTRL) controlling the nonvolatile memory package 21 .

[0078] The non-volatile memory package 21 (NVMPKG) may include an interface chip (a frequency boost interface chip (FBI) or a "buffer chip") and a plurality of non-volatile memory devices connected to an internal channel. In one embodiment, the non-volatile memory package 21 may include Figures 1 to 15 The encoder 21-1 for compressing data based on a compression algorithm described in . In one example, in the encoder 21-1, the address control of the output operation and the address control of the input operation can be operated independently. In another example embodiment, the interface chip can be connected to the controller 22 through a channel. Here, the channel can be connected to the first internal channel or the second internal channel through the interface chip. Here, the interface chip may include a retraining check circuit for internally determining the need for retraining. In addition, the interface chip can implement an interface protocol for communicating with the controller 22 and an interface protocol for communicating with a non-volatile memory device in a compatible manner. Multiple non-volatile memory devices can be connected to the internal channels respectively. In an example embodiment, the non-volatile memory device of the non-volatile memory package 21 can be implemented in a stacked structure.

[0079] The controller 22 (CTRL) may be implemented to control the overall operation of the non-volatile memory package 21 (e.g., through a read enable signal nRE, a data strobe signal DQS, and a data signal DQ, etc.). The controller 22 may perform functions required for data management of the non-volatile memory package 21 (such as address mapping, error correction, garbage collection, wear leveling, bad block management, or data recovery). Here, these functions may be implemented in hardware, software, or firmware. In addition, the controller 22 may include functions for, for example, Figures 1 to 15 A decoder 22-1 decompresses the compressed data as described in .

[0080] Fig.17 is a diagram showing the controller 22 according to an example embodiment. Fig.17 The controller 22 may include a host interface circuit (HIF) 201, a non-volatile memory interface circuit 202 (NIF), a bus 203, at least one processor 210 (CPU), a buffer memory 220, an error correction circuit 230 (ECC), a host direct memory access (DMA) circuit 240 and a non-volatile memory DMA circuit 250.

[0081] The host interface circuit 201 may be implemented to transmit / receive packets with the host. The packets transmitted from the host to the host interface circuit 201 may include commands or write data to the non-volatile memory device. The packets transmitted from the host interface circuit 201 to the host may include responses to commands or read data from the non-volatile memory device.

[0082] The nonvolatile memory interface circuit 202 may send write data to the nonvolatile memory device 100 or may receive read data from the nonvolatile memory device 100. The nonvolatile memory interface circuit 202 may be implemented to comply with a standard protocol such as Joint Electron Device Engineering Council (JEDEC) Toggle or Open NAND Flash Interface (ONFI).

[0083] At least one processor 210 (CPU(s)) may be implemented to control the overall operation of the storage device 20. The processor 210 may perform various managements (such as cache / buffer management, firmware management, garbage collection management, wear leveling management, data deduplication management, read refresh / reclaim management, bad block management, multi-stream management, mapping management between host data and non-volatile memory, quality of service (QoS) management, system resource allocation management, non-volatile memory queue management, read level management, erase / program management, hot / cold data management, power-off protection management, dynamic thermal management, initialization management, and Redundant Array of Inexpensive Disks (RAID) management. These management operations may be implemented in hardware / firmware / software).

[0084] The buffer memory 220 may temporarily store data to be written to or read from the nonvolatile memory device. In one example, the buffer memory 220 may be configured as a component included in the controller 22. In another example, the buffer memory 220 may be provided outside the controller 22. In addition, the buffer memory 220 may be implemented as a volatile memory (e.g., a static random access memory (SRAM), a dynamic RAM (DRAM), a synchronous RAM (SDRAM), etc.) or a nonvolatile memory (a flash memory, a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), a resistive RAM (ReRAM), a ferroelectric RAM (FRAM), etc.).

[0085] The error correction circuit 230 may generate an error correction code (ECC) during a programming operation, and may use the error correction code to recover data during a read operation. That is, the error correction circuit 230 may generate an error correction code ECC for correcting a faulty bit or an error bit of data received from a nonvolatile memory device. In addition, the error correction circuit 230 may form data to which a parity bit is added by performing error correction coding on the data provided to the nonvolatile memory device. The parity bit may be stored in the nonvolatile memory device 100. In addition, the error correction circuit 230 may perform error correction decoding on the data output from the nonvolatile memory device. The error correction circuit 230 may use parity checking to correct errors. The error correction circuit 230 may use low-density parity check (LDPC) codes, Bose-Chadhoury-Hokkingum (BCH) codes, turbo codes, Reed-Solomon codes, convolutional codes, recursive systematic codes (RSC), and coded modulation (such as trellis coded modulation (TCM) and block coded modulation (BCM)) to correct errors. When error correction is not feasible in the error correction circuit 230 , a read retry operation may be performed.

[0086] The package manager may generate a package according to the protocol of the interface negotiated with the host, or parse various data from the package received from the host. The encryption device may perform at least one of an encryption operation and a decryption operation on the data input to the controller 22 using, for example, a symmetric key algorithm. The encryption device may use an advanced encryption standard (AES) algorithm to perform encryption and decryption of data. The encryption device may include an encryption module and a decryption module. In one example, the encryption device may be implemented in hardware / software / firmware. The encryption device may perform a self-encrypting disk (SED) function or a trusted computing group (TCG) security function. The SED function may use an encryption algorithm to store encrypted data in a non-volatile memory device, or decrypt encrypted data from a non-volatile memory device. Encryption / decryption operations may be performed using an internally generated encryption key. The TCG security function may provide a mechanism capable of controlling access to user data of the storage device 20. For example, the TCG security function may perform an authentication process between an external device and the storage device 20. In one example, the SED function or the TCG security function may be selected optionally.

[0087] The host DMA circuit 240 may be implemented to control a DMA operation between the host device and the controller 22. The host DMA circuit 240 may perform an operation of storing data input from the host device through the host interface circuit 201 in the buffer memory 220 during a program operation under the control of the host controller. In addition, the host DMA circuit 240 may perform an operation of outputting data stored in the buffer memory 220 to the host device through the host interface circuit 201 during a read operation. In one example, the host DMA circuit 240 may be included in the host controller as a component of the host controller.

[0088] The nonvolatile memory DMA circuit 250 may be implemented to control DMA operations between the controller 22 and the nonvolatile memory device. The nonvolatile memory DMA circuit 250 may perform an operation of outputting data stored in the buffer memory 220 to the nonvolatile memory device through the nonvolatile memory interface circuit 202 during a program operation under the control of the nonvolatile memory controller. In addition, the nonvolatile memory DMA circuit 250 may perform an operation of reading data stored in the nonvolatile memory device through the nonvolatile memory interface circuit 202 during a read operation.

[0089] Fig.18 is a ladder diagram showing a read operation of a storage device according to an embodiment. Fig.18, the read operation of the storage device SSD may be performed as follows. The controller CTRL may output a special command to the nonvolatile memory device NVM (S10). The nonvolatile memory device NVM may receive the special command, and may read the first data using a hard decision method (H / D) in response to the special command (S11). In addition, the nonvolatile memory device NVM may read the second data using a soft decision method (S / D) in response to the special command (S12). In one example, the read operation may be performed using the hard decision method (H / D), and then the read operation may be performed using the soft decision method (S / D). In another example, the read operation may be performed using the soft decision method (S / D), and then the read operation may be performed using the hard decision method (H / D). That is, the order of S11 and S12 may be interchanged with each other.

[0090] Thereafter, the nonvolatile memory device NVM may compress the second data (S13). In one example, the second data may be stored in a cache latch, data of a sector unit may be output from the cache latch in response to an output address, the output data of the sector unit may be compressed, and the compressed data may be rewritten to a portion of the cache latch in response to an input address. In one example, while moving the first address pointer from the start point of the sector to the end point, data may be output from the corresponding cache latch. In one example, while moving the second address pointer from the start point of the sector to a point where a predetermined amount is added to the start point, rewriting of the cache latch of the corresponding portion may be performed. In one example embodiment, the first address pointer and the second address pointer may be independently controlled. In one example embodiment, the starting column address for each sector may be the same before and after the compression operation. In another example embodiment, the starting column address may be different for each sector before and after the compression operation.

[0091] Thereafter, the nonvolatile memory device NVM may output the first data and the compressed second data using the controller CTRL (S14). The controller CTRL may restore the data using the first data and the compressed second data (S15). The controller CTRL may output a read reclaim request to the nonvolatile memory device NVM using the restored data (S16). The nonvolatile memory device NVM may perform a read reclaim operation using the restored data.

[0092] Fig.19 is a ladder diagram illustrating a read operation of a storage device according to another example embodiment. Fig.19 , a read operation of the storage device SSD may be performed as follows.

[0093] The controller CTRL may output a read command to the nonvolatile memory device NVM (S20). The nonvolatile memory device NVM may read the first data using a hard decision method (H / D) in response to the read command (S21). In addition, the nonvolatile memory device NVM may read the second data using a soft decision method (S / D) in response to the read command (S22). The nonvolatile memory device NVM may compress the second data (S23). The nonvolatile memory device NVM may output the first data using the controller CTRL (S24).

[0094] The controller CTRL may perform a first error correction operation (first ECC) on the first data (S25). When error correction (UECC) is not feasible according to the result of the first error correction operation ("Yes" of S26), the controller CTRL may output a special command to the nonvolatile memory device NVM (S27). The nonvolatile memory device NVM may output the compressed second data using the controller CTRL in response to the special command (S28). Thereafter, the controller CTRL may decompress the compressed second data (S29). Thereafter, the controller CTRL may perform a second error correction operation (second ECC) on the decompressed second data (S30).

[0095] Meanwhile, the nonvolatile memory device may be implemented as a vertical memory device.

[0096] Fig. 20 is a diagram illustrating a vertical nonvolatile memory device according to an example embodiment. Fig. 20 , the non-volatile memory device 2500 may have a chip-to-chip (C2C) structure. Here, the method of manufacturing the C2C structure may include: separately manufacturing at least one upper chip including a cell area CELL and a lower chip including a peripheral circuit area PERI, and connecting at least one upper chip and one lower chip to each other by bonding. In one example, the bonding method may refer to a method of electrically or physically connecting a bonding metal pattern formed on the lowermost metal layer of the upper chip to a bonding metal pattern formed on the uppermost metal layer of the lower chip. For example, when the bonding metal pattern is formed of copper (Cu), the bonding method may be a Cu-Cu bonding method. In another example, the bonding metal pattern may also be formed of aluminum (Al) or tungsten (W).

[0097] The nonvolatile memory device 2500 may include at least one upper chip including a cell region. Fig. 20As shown in , the nonvolatile memory device 2500 may be implemented to include two upper chips. However, this is merely an example, and the number of upper chips is not limited thereto. When the nonvolatile memory device 2500 is implemented to include two upper chips, the nonvolatile memory device 2500 may be manufactured by the following method: a first upper chip including a first cell area CELL1, a second upper chip including a second cell area CELL2, and a lower chip including a peripheral circuit area PERI are manufactured separately, and the first upper chip, the second upper chip, and the lower chip are connected to each other by bonding. The first upper chip may be flipped over and connected to the lower chip by bonding, and the second upper chip may also be flipped over and connected to the first upper chip by bonding. In the following description, the upper and lower portions of the first upper chip and the second upper chip may be defined relative to the state before the first upper chip and the second upper chip are flipped over. That is, in Fig. 20 , the upper portion of the lower chip may refer to the upper portion defined in the +Z axis direction, and the upper portion of each of the first upper chip and the second upper chip may refer to the upper portion defined in the -Z axis direction. However, this is only an example, and only one of the first upper chip and the second upper chip may be flipped, and the first upper chip and the second upper chip may be connected to each other by bonding.

[0098] Each of the peripheral circuit region PERI and the first and second cell regions CELL1 and CELL2 of the nonvolatile memory device 2500 may include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA. The peripheral circuit region PERI may include a first plate 2210, and a plurality of circuit devices 2220a, 2220b, and 2220c formed on the first plate 2210. An interlayer insulating layer 2215 including one or more insulating layers may be disposed on the plurality of circuit devices 2220a, 2220b, and 2220c, and a plurality of metal wirings may be disposed in the interlayer insulating layer 2215 to connect the plurality of circuit devices 2220a, 2220b, and 2220c. For example, the plurality of metal wirings may include first metal wirings 2230a, 2230b, and 2230c connected to the plurality of circuit devices 2220a, 2220b, and 2220c, and second metal wirings 2240a, 2240b, and 2240c formed on the first metal wirings 2230a, 2230b, and 2230c. The plurality of metal wirings may be formed of at least one of various conductive materials. For example, the first metal wirings 2230a, 2230b, and 2230c may be formed of tungsten having a relatively high resistivity, and the second metal wirings 2240a, 2240b, and 2240c may be formed of copper having a relatively low resistivity.

[0099] Here, only the first metal wiring 2230a, 2230b, and 2230c and the second metal wiring 2240a, 2240b, and 2240c are described, but the embodiment thereof is not limited thereto, and at least one additional metal wiring may be further formed on the second metal wiring 2240a, 2240b, and 2240c. In such a case, the second metal wiring 2240a, 2240b, and 2240c may be formed of aluminum. In addition, in such a case, at least a portion of the additional metal wiring formed on the second metal wiring 2240a, 2240b, and 2240c may be formed of copper having a resistivity lower than the resistivity of aluminum of the second metal wiring 2240a, 2240b, and 2240c.

[0100] Each of the first cell region CELL1 and the second cell region CELL2 may include at least one memory block. The first cell region CELL1 may include a second plate 2310 and a common source line 2320. On the second plate 2310, a plurality of word lines 2331 to 2338 (2330) may be stacked in a direction (Z-axis direction) perpendicular to the upper surface of the second plate 2310. A string selection line and a ground selection line may be disposed above and below the word line 2330, and a plurality of word lines 2330 may be disposed between the string selection line and the ground selection line. Similarly, the second cell region CELL2 may include a third plate 2410 and a common source line 2420, and a plurality of word lines 2431 to 2438 (2430) may be stacked in a direction (Z-axis direction) perpendicular to the upper surface of the third plate 2410. The second plate 2310 and the third plate 2410 may be formed of various materials (e.g., a plate having a single crystal epitaxial layer grown on a silicon plate, a silicon germanium plate, a germanium plate, or a single crystal silicon plate). A plurality of channel structures CH may be formed in each of the first cell region CELL1 and the second cell region CELL2 .

[0101] like Fig. 20 As shown in example A1 of an optional embodiment of A, the channel structure CH may be disposed in the bit line bonding area BLBA, may extend in a direction perpendicular to the upper surface of the second plate 2310, and may penetrate the word line 2330, the string selection line, and the ground selection line. The channel structure CH may include a data storage layer, a channel layer, and a buried insulating layer. The channel layer may be electrically connected to the first metal wiring 2350c in the bit line bonding area BLBA, and electrically connected to the second metal wiring 2360c in the bit line bonding area BLBA. For example, the second metal wiring 2360c may be a bit line and may be connected to the channel structure CH through the first metal wiring 2350c. The bit line 2360c may extend in a first direction (Y-axis direction) parallel to the upper surface of the second plate 2310.

[0102] In one example, as shown in A2 as an optional embodiment of A, the channel structure CH may include a lower channel LCH and an upper channel UCH connected to each other. For example, the channel structure CH may be formed by a process for the lower channel LCH and a process for the upper channel UCH. The lower channel LCH may extend in a direction perpendicular to the upper surface of the second plate 2310, and may penetrate the common source line 2320 and the lower word lines 2331 and 2332. The lower channel LCH may include a data storage layer, a channel layer, and a buried insulating layer, and may be connected to the upper channel UCH. The upper channel UCH may penetrate the upper word lines 2333 to 2338. The upper channel UCH may include a data storage layer, a channel layer, and a buried insulating layer, and the channel layer of the upper channel UCH may be electrically connected to the first metal wiring 2350c and the second metal wiring 2360c. As the length of the channel increases, it may be difficult to form a channel with a constant width due to process-related reasons. The example nonvolatile memory device 2500 may include a channel having improved width uniformity through a lower channel LCH and an upper channel UCH formed through sequential processes.

[0103] like Fig. 20 As shown in A2 of , when the channel structure CH is formed to include a lower channel LCH and an upper channel UCH, a word line disposed adjacent to the boundary of the lower channel LCH and the upper channel UCH may be a dummy word line. For example, word line 2332 and word line 2333 forming the boundary between the lower channel LCH and the upper channel UCH may be dummy word lines. In this case, data may not be stored in a memory cell connected to the dummy word line. Optionally, the number of pages corresponding to the memory cell connected to the dummy word line may be less than the number of pages corresponding to the memory cell connected to the general word line. The voltage level applied to the dummy word line may be different from the voltage level applied to the general word line, and therefore, the influence of the inconsistent channel width between the lower channel LCH and the upper channel UCH on the operation of the memory device may be reduced.

[0104] At the same time, in A2, the number of lower word lines 2331 and 2332 penetrated by the lower channel LCH may be smaller than the number of upper word lines 2333 to 2338 penetrated by the upper channel UCH. However, this is merely an example, and its implementation is not limited thereto. In another example, the number of lower word lines penetrated by the lower channel LCH may be equal to or greater than the number of upper word lines penetrated by the upper channel UCH. In addition, the above-mentioned structure and connection relationship of the channel structure CH disposed in the first cell area CELL1 may be applied to the channel structure CH disposed in the second cell area CELL2. For example, the channel structure CH disposed in the second cell area CELL2 may include a data storage layer, a channel layer, and a filling insulating layer, and the channel layer may be electrically connected to the first metal wiring 2450c and the second metal wiring 2460c in the bit line bonding area BLBA.

[0105] In the bit line bonding area BLBA, the first through electrode THV1 may be disposed in the first cell area CELL1, and the second through electrode THV2 may be disposed in the second cell area CELL2. Fig. 20 As shown in , the first through electrode THV1 may penetrate the common source line 2320 and the plurality of word lines 2330. However, this is only an example, and the first through electrode THV1 may also penetrate the second plate 2310. The first through electrode THV1 may include a conductive material. Alternatively, the first through electrode THV1 may include a conductive material surrounded by an insulating material. The second through electrode THV2 may be provided in the same form and structure as the first through electrode THV1.

[0106] In one exemplary embodiment, the first through electrode THV1 and the second through electrode THV2 may be electrically connected by the first through metal pattern 2372d and the second through metal pattern 2472d. The first through metal pattern 2372d may be formed on the lower end of the first upper chip including the first cell area CELL1, and the second through metal pattern 2472d may be formed on the upper end of the second upper chip including the second cell area CELL2. The first through electrode THV1 may be electrically connected to the first metal wiring 2350c and the second metal wiring 2360c. A lower via 2371d may be formed between the first through electrode THV1 and the first through metal pattern 2372d, and an upper via 2471d may be formed between the second through electrode THV2 and the second through metal pattern 2472d. The first through metal pattern 2372d and the second through metal pattern 2472d may be connected to each other by bonding.

[0107] In addition, in the bit line bonding area BLBA, an upper metal pattern 2252 may be formed on the uppermost metal layer of the peripheral circuit area PERI, and an upper metal pattern 2392 having the same shape as that of the upper metal pattern 2252 may be formed on the uppermost metal layer of the first cell area CELL1. The upper metal pattern 2392 of the first cell area CELL1 and the upper metal pattern 2252 of the peripheral circuit area PERI may be electrically connected to each other by bonding. In the bit line bonding area BLBA, the bit line 2360c may be electrically connected to a page buffer included in the peripheral circuit area PERI. For example, a portion of the circuit device 2220c of the peripheral circuit area PERI may provide a page buffer, and the bit line 2360c may be electrically connected to the circuit device 2220c providing the page buffer through the upper bonding metal 2370c of the first cell area CELL1 and the upper bonding metal 2270c of the peripheral circuit area PERI.

[0108] Reference Fig. 20, in the word line bonding area WLBA, the word line 2330 of the first cell region CELL1 may extend in the second direction (X-axis direction) parallel to the upper surface of the second plate 2310, and may be connected to a plurality of cell contact plugs 2341 to 2347 (2340). The first metal wiring 2350b and the second metal wiring 2360b may be sequentially connected to the upper portion of the cell contact plug 2340 connected to the word line 2330. In the word line bonding area WLBA, the cell contact plug 2340 may be connected to the peripheral circuit region PERI through the upper bonding metal 2370b of the first cell region CELL1 and the upper bonding metal 2270b of the peripheral circuit region PERI.

[0109] The cell contact plug 2340 may be electrically connected to a row decoder included in the peripheral circuit region PERI. For example, a portion of the circuit device 2220b of the peripheral circuit region PERI may provide a row decoder, and the cell contact plug 2340 may be electrically connected to the circuit device 2220b providing the row decoder through the upper bonding metal 2370b of the first cell region CELL1 and the upper bonding metal 2270b of the peripheral circuit region PERI. In one example, the operating voltage of the circuit device 2220b providing the row decoder may be different from the operating voltage of the circuit device 2220c providing the page buffer. For example, the operating voltage of the circuit device 2220c providing the page buffer may be higher than the operating voltage of the circuit device 2220b providing the row decoder.

[0110] Similarly, in the word line bonding area WLBA, the word lines 2430 of the second cell area CELL2 may extend in a second direction (X-axis direction) parallel to the upper surface of the third plate 2410, and may be connected to a plurality of cell contact plugs 2440 (2441 to 2447). The cell contact plugs 2440 may be connected to the peripheral circuit area PERI through the upper metal pattern of the second cell area CELL2, the lower and upper metal patterns of the first cell area CELL1, and the cell contact plugs 2348.

[0111] In the word line bonding area WLBA, the upper bonding metal 2370b may be formed in the first cell area CELL1, and the upper bonding metal 2270b may be formed in the peripheral circuit area PERI. The upper bonding metal 2370b of the first cell area CELL1 and the upper bonding metal 2270b of the peripheral circuit area PERI may be electrically connected to each other by bonding. The upper bonding metal 2370b and the upper bonding metal 2270b may be formed of aluminum, copper, or tungsten.

[0112] In the external pad bonding area PA, a lower metal pattern 2371e may be formed in a lower portion of the first cell area CELL1, and an upper metal pattern 2472a may be formed in an upper portion of the second cell area CELL2. The lower metal pattern 2371e of the first cell area CELL1 and the upper metal pattern 2472a of the second cell area CELL2 may be connected to each other by bonding in the external pad bonding area PA. Similarly, an upper metal pattern 2372a may be formed on the first cell area CELL1, and an upper metal pattern 2272a may be formed on the peripheral circuit area PERI. The upper metal pattern 2372a of the first cell area CELL1 and the upper metal pattern 2272a of the peripheral circuit area PERI may be connected to each other by bonding.

[0113] Common source line contact plugs 2380 and 2480 may be disposed in the external pad bonding area PA. The common source line contact plugs 2380 and 2480 may be formed of a conductive material such as a metal, a metal compound, or doped polysilicon. The common source line contact plug 2380 of the first cell area CELL1 may be electrically connected to the common source line 2320, and the common source line contact plug 2480 of the second cell area CELL2 may be electrically connected to the common source line 2420. The first metal wiring 2350a and the second metal wiring 2360a may be sequentially stacked on the common source line contact plug 2380 of the first cell area CELL1, and the first metal wiring 2450a and the second metal wiring 2460a may be sequentially stacked on the common source line contact plug 2480 of the second cell area CELL2.

[0114] The input / output pads 2205, 2405, and 2406 may be disposed in the external pad bonding area PA. Fig. 20 , a lower insulating film 2201 may cover a lower surface of the first board 2210, and a first input / output pad 2205 may be formed on the lower insulating film 2201. The first input / output pad 2205 may be connected to at least one of a plurality of circuit devices 2220a provided in the peripheral circuit region PERI through a first input / output contact plug 2203, and may be isolated from the first board 2210 by the lower insulating film 2201. In addition, a side insulating film may be provided between the first input / output contact plug 2203 and the first board 2210, and may electrically isolate the first input / output contact plug 2203 and the first board 2210 from each other.

[0115] An upper insulating film 2401 covering the upper surface of the third board 2410 may be formed over the third board 2410. A second input / output pad 2405 or a third input / output pad 2406 may be disposed on the upper insulating film 2401. The second input / output pad 2405 may be connected to at least one of the plurality of circuit devices 2220a disposed in the peripheral circuit region PERI through second input / output contact plugs 2403 and 2303, and the third input / output pad 2406 may be connected to at least one of the plurality of circuit devices 2220a disposed in the peripheral circuit region PERI through third input / output contact plugs 2404 and 2304.

[0116] In an example embodiment, the third plate 2410 may not be disposed in a region where the input / output contact plug is disposed. For example, as shown in B, the third input / output contact plug 2404 may be isolated from the third plate 2410 in a direction parallel to the upper surface of the third plate 2410, may penetrate the interlayer insulating layer 2415 of the second cell region CELL2, and may be connected to the third input / output pad 2406. In this case, the third input / output contact plug 2404 may be formed by various processes.

[0117] For example, as shown in B1 as an alternative embodiment of B, the third input / output contact plug 2404 may extend in the third direction (Z-axis direction), and may have a diameter that increases toward the upper insulating film 2401. That is, although the diameter of the channel structure CH described in A1 is formed to decrease toward the upper insulating film 2401, the diameter of the third input / output contact plug 2404 may increase toward the upper insulating film 2401. For example, the third input / output contact plug 2404 may be formed after the second cell region CELL2 and the first cell region CELL1 are combined with each other.

[0118] Furthermore, as an example, as shown in B2 as an alternative embodiment of B, the third input / output contact plug 2404 may extend in the third direction (Z-axis direction) and may have a diameter that decreases toward the upper insulating film 2401. That is, similar to the channel structure CH, the diameter of the third input / output contact plug 2404 may decrease toward the upper insulating film 2401. For example, the third input / output contact plug 2404 may be formed together with the cell contact plug 2440 before the second cell region CELL2 and the first cell region CELL1 are coupled to each other.

[0119] In another example, the input / output contact plug may be disposed to overlap the third board 2410. For example, as shown in C, the second input / output contact plug 2403 may be formed by penetrating the interlayer insulating layer 2415 of the second cell region CELL2 in the third direction (Z-axis direction), and may be electrically connected to the second input / output pad 2405 through the third board 2410. In this case, the connection structure of the second input / output contact plug 2403 and the second input / output pad 2405 may be implemented in various ways.

[0120] For example, as shown in C1 as an alternative embodiment of C, an opening 2408 penetrating the third plate 2410 may be formed, and the second input / output contact plug 2403 may be directly connected to the second input / output pad 2405 through the opening 2408 formed in the third plate 2410. In this case, as shown in C1, the diameter of the second input / output contact plug 2403 may increase toward the second input / output pad 2405. However, this is only an example, and the diameter of the second input / output contact plug 2403 may decrease toward the second input / output pad 2405.

[0121] For example, as shown in C2 as an alternative embodiment of C, an opening 2408 passing through the third plate 2410 may be formed, and a contact 2407 may be formed in the opening 2408. One end of the contact 2407 may be connected to the second input / output pad 2405, and the other end may be connected to the second input / output contact plug 2403. Therefore, the second input / output contact plug 2403 may be electrically connected to the second input / output pad 2405 through the contact 2407 in the opening 2408. In this case, as shown in C2, the diameter of the contact 2407 may increase toward the second input / output pad 2405, and the diameter of the second input / output contact plug 2403 may decrease toward the second input / output pad 2405. For example, the third input / output contact plug 2403 may be formed together with the cell contact plug 2440 before the second cell region CELL2 and the first cell region CELL1 are coupled to each other, and the contact 2407 may be formed after the second cell region CELL2 and the first cell region CELL1 are coupled to each other.

[0122] Furthermore, as an example, as shown in C3 as an alternative embodiment of C, a stopper 2409 may be further formed on the upper surface of the opening 2408 of the third plate 2410 compared to C2. The stopper 2409 may be a metal wiring formed on the same layer as the common source line 2420. However, this is only an example, and the stopper 2409 may be a metal wiring formed on the same layer as at least one of the word lines 2430. The second input / output contact plug 2403 may be electrically connected to the second input / output pad 2405 through the contact 2407 and the stopper 2409.

[0123] Similar to the second and third input / output contact plugs 2403 and 2404 of the second cell region CELL2, the second and third input / output contact plugs 2303 and 2304 of the first cell region CELL1 may have diameters decreasing or increasing toward the lower metal pattern 2371e, respectively.

[0124] In one example, the slit 4111 may be formed on the third plate 2410. For example, the slit 2411 may be formed in any position of the external pad bonding area PA. In one example embodiment, as shown in D, the slit 2411 may be disposed between the second input / output pad 2405 and the cell contact plug 2440 when viewed from a cross section. However, this is merely an example, and the slit 2411 may be formed so that the second input / output pad 2405 may be disposed between the slit 2411 and the cell contact plug 2440 when viewed from a cross section.

[0125] For example, as shown in D1 as an alternative embodiment of D, a slit 2411 may be formed to penetrate the third plate 2410. The slit 2411 may be used to prevent the third plate 2410 from being finely split when the opening 2408 is formed. However, this is only an example, and the slit 2411 may be formed to a depth of about 60% to 70% of the thickness of the third plate 2410.

[0126] In addition, as an example, as shown in D2 as an alternative embodiment of D, a conductive material 2412 may be formed in the slit 2411. The conductive material 2412 may be used, for example, to release leakage current generated during driving of the circuit device in the external pad bonding area PA. In this case, the conductive material 2412 may be connected to an external ground line.

[0127] For example, as shown in D3 as an alternative embodiment of D, an insulating material 2413 may be formed in the slit 2411. For example, the insulating material 2413 may electrically isolate the second input / output pad 2405 and the second input / output contact plug 2403 disposed in the external pad bonding area PA from the word line bonding area WLBA. By forming the insulating material 2413 in the slit 2411, a voltage provided through the second input / output pad 2405 may be prevented from affecting a metal layer on the third plate 2410 disposed in the word line bonding area WLBA.

[0128] In example embodiments, the first to third input / output pads 2205, 2405, and 2406 may be selectively formed. For example, the nonvolatile memory device 2500 may include only the first input / output pad 2205 disposed over the first board 2210, may include only the second input / output pad 2405 disposed over the third board 2410, or may include only the third input / output pad 2406 disposed over the upper insulating film 2401.

[0129] In an example embodiment, at least one of the second plate 2310 of the first cell region CELL1 and the third plate 2410 of the second cell region CELL2 may be used as a sacrificial plate and may be completely or partially removed before or after the bonding process. An additional film may be deposited after the plate is removed. For example, the second plate 2310 of the first cell region CELL1 may be removed before or after the bonding between the peripheral circuit region PERI and the first cell region CELL1, and an insulating film covering the upper surface of the common source line 2320 or a conductive film for connection may be formed. Similarly, the third plate 2410 of the second cell region CELL2 may be removed before or after the bonding between the first cell region CELL1 and the second cell region CELL2, and an upper insulating film 2401 covering the upper surface of the common source line 2420 or a conductive film for connection may be formed.

[0130] The above-mentioned device can be implemented with hardware components, software components, and / or a combination of hardware components and software components. For example, the device and components described in an example embodiment can be implemented using one or more general-purpose computers or special-purpose computers (such as processors, controllers, arithmetic logic units (ALUs), digital signal processors, microcomputers, field programmable gate arrays (FPGAs), programmable logic units (PLUs), microprocessors, or any other device that can execute instructions and respond). The processing device can execute an operating system (OS) and one or more software applications running on the operating system. In addition, the processing device can access, store, manipulate, process, and generate data in response to the execution of the software. For ease of description, a single processing device can be used, but the processing device may include multiple processing elements or multiple types of processing elements. For example, the processing device may include multiple processors, or a processor and a controller. In addition, other processing configurations (such as parallel processors) may be feasible.

[0131] Software may include computer programs, codes, instructions, or a combination of one or more of them, and may configure a processing device to operate as desired or may configure a processing device to instruct the processing device independently or collectively. The software and / or data may be implemented in any type of machine, component, physical device, virtual device, computer storage medium, or computer storage device to be interpreted by the processing device or to provide instructions or data to the processing device. The software may be distributed on networked computer systems and may be stored or executed in a distributed manner. The software and data may be stored on one or more computer readable recording media.

[0132] In one example, a request for data compression (e.g., soft data) operated in a NAND die may be processed. In one example, a non-volatile memory device may reduce the chip size overhead of a data compression circuit. When outputting data before and after compression, the non-volatile memory device may take into account the possibility of a change in the starting column address. In order to output compressed data externally from the chip, the data may need to be stored in a C latch. In order to complete the compression in 1 cycle (1 page), a storage space corresponding to the compression ratio may be necessary in addition to the C latch. The storage space may be a chip size overhead for implementing the compression circuit. When the compressed data is output outside the chip, which address mapping should be supported may depend on the needs from the user. In one example, case 1, the starting column address is the same for each sector (4KB) before and after compression, but the data length is different (and therefore, hardware fixing is feasible). In another example, case 2, the starting column address is different for each sector (4KB) before and after compression, so that the full compressed data output can be read with the first 4KB and is feasible.

[0133] A nonvolatile memory device in an example embodiment may include a data path circuit for independently reading and writing encoded data of divided pages, a sequential repetitive compression device for reading and rewriting C-latch data using independent two address control circuits, independent two address control circuits for read operation / write operation, a register for encoding and storing data of a specific cell after the C-latch Dout, and a circuit for rewriting register data by a write address independent of a read address.

[0134] In an example embodiment, a method for encoding and inputting / outputting C-latch data by independent two address controls is disclosed. In one example, the encoded data can be rewritten in sequence according to the order of the data addresses before encoding. In one example, the encoded data can be rewritten by following the order of the starting addresses of the data before encoding. In one example, two address control circuits can separate the address scrambling methods of the C-latch Dout / Din. Since the pointers of Dout and Din can be separated, Dout and Din can be repeated in sequence for sector data (e.g., C-latch Dout (4KB) => encoding => C-latch Din (rewrite)).

[0135] According to the aforementioned example embodiments, data can be compressed and output. The cache latch can be accessed using at least two separate address controllers. In an example embodiment, the operation of reading the data to be encoded and the operation of writing the encoded data can be performed independently. In an example embodiment, by repeating the operation of reading the data to be encoded and the operation of writing the encoded data in sequence, the buffer capacity for storing the encoded data can be reduced.

[0136] Although the present disclosure contains many specific implementation details, these should not be interpreted as limiting the scope of possible protection. Specific features described in the context of separate embodiments in the present disclosure may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination. In addition, although the above features may be described as working in a specific combination, one or more features from the combination may be deleted from the combination in some cases, and the combination may point to a sub-combination or a variation of the sub-combination.

[0137] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A non-volatile memory device, comprising: multiple latch groups; An address controller configured to control an input address and an output address to respectively indicate a corresponding latch group among the plurality of latch groups; An encoder configured to: receive sector data from a latch group corresponding to an output address among the plurality of latch groups, and compress the received sector data; as well as a buffer configured to store compressed sector data, Among the plurality of latch groups, the compressed sector data stored in the buffer is rewritten into the latch group corresponding to the input address.

2. The nonvolatile memory device according to claim 1, wherein: The address controller includes: A first address controller configured to output an output address under a first address control; and The second address controller is configured to output the input address under the second address control.

3. The nonvolatile memory device according to claim 2, in, The address controller further includes: a multiplexer configured to output an input address or an output address, and The first address control and the second address control are the same.

4. The nonvolatile memory device according to claim 3, in, During the output operation, the first address controller moves the first address pointer corresponding to the output address from the start point of the sector data to the end point of the sector data, and Wherein, during the input operation, the second address controller moves a second address pointer corresponding to the input address from the start point of the sector data to a point where a predetermined amount is added to the start point of the sector data.

5. The nonvolatile memory device according to claim 4, wherein: During a compression operation for subsequent sector data, the address controller retrieves an end point of the first address pointer and an end point of the second address pointer corresponding to the compression operation for the previous sector data.

6. The nonvolatile memory device according to claim 2, in, The address controller further includes: a multiplexer configured to output an input address or an output address, and Among them, the first address control and the second address control are different.

7. The nonvolatile memory device according to claim 6, in, During the output operation, the first address controller moves the first address pointer corresponding to the output address from the start point of the sector data to the end point of the sector data, and Wherein, during the input operation, the second address controller moves a second address pointer corresponding to the input address from the start point of the sector data to a point where a predetermined amount is added to the start point of the sector data.

8. The nonvolatile memory device according to claim 7, in, During a compression operation for subsequent sector data, the first address controller moves the first address pointer to a starting point corresponding to the subsequent sector data, and During the compression operation for the subsequent sector data, the second address controller moves the second address pointer to a starting point corresponding to the subsequent sector data.

9. The nonvolatile memory device according to any one of claims 1 to 8, in, Sector data is divided into multiple data, and The encoder includes: a plurality of encoding units configured to compress the divided data.

10. The nonvolatile memory device according to claim 9, wherein: The buffer includes: a plurality of registers configured to store compressed data from the plurality of encoding units respectively.

11. A non-volatile memory device comprising: Multiple latches; a plurality of encoding units configured to compress data of a first size according to a predetermined compression ratio; as well as Multiple registers are configured to store compressed data. wherein the plurality of latches output data as large as the first size to the plurality of encoding units while the first address pointer is moved during an output operation, and The plurality of latches rewrite compressed data of a second size corresponding to the compression ratio from the plurality of registers while the second address pointer is moved during an input operation.

12. The nonvolatile memory device according to claim 11, in, The first size is 128 bytes, and Among them, the second size is 32 bytes.

13. The nonvolatile memory device according to claim 11, wherein: The first address control corresponding to the output operation and the second address control corresponding to the input operation are the same.

14. The nonvolatile memory device according to claim 11, wherein: The first address control corresponding to the output operation is different from the second address control corresponding to the input operation.

15. The nonvolatile memory device according to any one of claims 11 to 14, wherein: The compressed data stored in the plurality of latches is output in response to a special command.

16. A method of operating a non-volatile memory device, the method comprising: outputting soft decision data from the cache latch under control of a first address; compressing the soft decision data according to a predetermined compression ratio; as well as rewriting the compressed data into a portion of the cache latch under control of a second address, Here, the first address control and the second address control are separated from each other.

17. The method according to claim 16, in, The cache latches are divided into sectors and The step of outputting soft decision data includes: under the control of the first address, while moving the first address pointer from the starting point of the corresponding sector among the multiple sectors to the end point of the sector, outputting the soft decision data from the corresponding cache latch.

18. The method according to claim 16, further comprising: Store the compressed data in registers.

19. The method according to claim 18, wherein: The step of rewriting the compressed data into the portion of the cache latch includes rewriting the compressed data stored in the register into the portion of the cache latch while moving the second address pointer a predetermined amount from the start of the sector under the control of the second address.

20. The method according to any one of claims 16 to 19, wherein: The first address control and the second address control may be the same or different.

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